ON MC33171 Single supply 3.0 v to 44 v, low power operational amplifier Datasheet

MC33171, MC33172,
MC33174, NCV33172
Single Supply 3.0 V to 44 V,
Low Power Operational
Amplifiers
Quality bipolar fabrication with innovative design concepts are
employed for the MC33171/72/74 series of monolithic operational
amplifiers. These devices operate at 180 mA per amplifier and offer 1.8
MHz of gain bandwidth product and 2.1 V/ms slew rate without the use
of JFET device technology. Although this series can be operated from
split supplies, it is particularly suited for single supply operation, since
the common mode input voltage includes ground potential (VEE).
With a Darlington input stage, these devices exhibit high input
resistance, low input offset voltage and high gain. The all NPN output
stage, characterized by no deadband crossover distortion and large
output voltage swing, provides high capacitance drive capability,
excellent phase and gain margins, low open loop high frequency
output impedance and symmetrical source/sink AC frequency
response.
The MC33171/72/74 are specified over the industrial/automotive
temperature ranges. The complete series of single, dual and quad
operational amplifiers are available in plastic as well as the surface
mount packages.
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PDIP−8
P SUFFIX
CASE 626
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8
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PDIP−14
P, VP SUFFIX
CASE 646
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Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Low Supply Current: 180 mA (Per Amplifier)
Wide Supply Operating Range: 3.0 V to 44 V or ±1.5 V to ±22 V
Wide Input Common Mode Range, Including Ground (VEE)
Wide Bandwidth: 1.8 MHz
High Slew Rate: 2.1 V/ms
Low Input Offset Voltage: 2.0 mV
Large Output Voltage Swing: −14.2 V to +14.2 V
(with ±15 V Supplies)
Large Capacitance Drive Capability: 0 pF to 500 pF
Low Total Harmonic Distortion: 0.03%
Excellent Phase Margin: 60°
Excellent Gain Margin: 15 dB
Output Short Circuit Protection
ESD Diodes Provide Input Protection for Dual and Quad
Pb−Free Packages are Available
NCV Prefix for Automotive and Other Applications Requiring Site
and Control Changes
© Semiconductor Components Industries, LLC, 2006
October, 2006 − Rev. 9
1
SO−8
D, VD SUFFIX
CASE 751
SO−14
D, VD SUFFIX
CASE 751A
14
1
14
1
TSSOP−14
DTB SUFFIX
CASE 948G
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 10 of this data sheet.
Publication Order Number:
MC33171/D
MC33171, MC33172, MC33174, NCV33172
PIN CONNECTIONS
SINGLE
QUAD
Output 1
Offset Null
1
8
NC
Inv. Input
2
7
VCC
Noninv. Input
3
6
Output
VEE
4
5
Offset Null
−
+
Inputs 1
1
14
2
13
3
VCC
Inputs 2
6
Output 2
DUAL
1
4
−
+
4
5
(Single, Top View)
−
+
3
7
+
−
Inputs 4
12
11
+
2
−
Output 4
VEE
10
9
8
Inputs 3
Output 3
(Top View)
Output 1
Inputs 1
1
2
3
VEE
−
+
4
1
2 −
+
8
VCC
7
Output 2
6
Inputs 2
5
(Top View)
VCC
Q3
Q4
Q5
Q6
Q7
Q1
Q17
Q2
R1
R2
C1
D2
Bias
−
Q8
Q9
Q10
Q18
R6
Q11
Inputs
R7
Output
R8
+
C2
D3
Q19
Q13
Q14
Q15
Q12
Q16
Current
Limit
D1
R5
R3
R4
VEE/GND
Offset Null
(MC33171)
Figure 1. Representative Schematic Diagram
(Each Amplifier)
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MC33171, MC33172, MC33174, NCV33172
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
VCC/VEE
±22
V
Input Differential Voltage Range
VIDR
(Note 1)
V
Input Voltage Range
VIR
(Note 1)
V
Output Short Circuit Duration (Note 2)
tSC
Indefinite
sec
Operating Ambient Temperature Range
TA
(Note 3)
°C
Supply Voltage
Operating Junction Temperature
TJ
+150
°C
Storage Temperature Range
Tstg
−65 to +150
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
DC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = −15 V, RL connected to ground, TA = +25°C, unless otherwise noted.)
Characteristics
Symbol
Input Offset Voltage (VCM = 0 V)
VCC = +15 V, VEE = −15 V, TA = +25°C
VCC = +5.0 V, VEE = 0 V, TA = +25°C
VCC = +15 V, VEE = −15 V, TA = Tlow to Thigh (Note 3)
VIO
Average Temperature Coefficient of Offset Voltage
DVIO/DT
Input Bias Current (VCM = 0 V)
TA = +25°C
TA = Tlow to Thigh (Note 3)
IIB
Input Offset Current (VCM = 0 V)
TA = +25°C
TA = Tlow to Thigh (Note 3)
IIO
Large Signal Voltage Gain (VO = ±10 V, RL = 10 k)
TA = +25°C
TA = Tlow to Thigh (Note 3)
AVOL
Output Voltage Swing
VCC = +5.0 V, VEE = 0 V, RL = 10 k, TA = +25°C
VCC = +15 V, VEE = −15 V, RL = 10 k, TA = +25°C
VCC = +15 V, VEE = −15 V, RL = 10 k, TA = Tlow to Thigh (Note 3)
VOH
VCC = +5.0 V, VEE = 0 V, RL = 10 k, TA = +25°C
VCC = +15 V, VEE = −15 V, RL = 10 k, TA = +25°C
VCC = +15 V, VEE = −15 V, RL = 10 k, TA = Tlow to Thigh (Note 3)
VOL
Output Short Circuit (TA = +25°C)
Input Overdrive = 1.0 V, Output to Ground
Source
Sink
Min
Typ
Max
−
−
−
2.0
2.5
−
4.5
5.0
6.5
−
10
−
−
−
20
−
100
200
−
−
5.0
−
20
40
50
25
500
−
−
−
3.5
13.6
13.3
4.3
14.2
−
−
−
−
−
−
−
0.05
−14.2
−
0.15
−13.6
−13.3
mV
mV/°C
nA
nA
V/mV
V
ISC
mA
3.0
15
Input Common Mode Voltage Range
TA = +25°C
TA = Tlow to Thigh (Note 3)
Unit
VICR
5.0
27
−
−
V
VEE to (VCC −1.8)
VEE to (VCC −2.2)
Common Mode Rejection Ratio (RS ≤ 10 k), TA = +25°C
CMRR
80
90
−
dB
Power Supply Rejection Ratio (RS = 100 W), TA = +25°C
PSRR
80
100
−
dB
Power Supply Current (Per Amplifier)
VCC = +5.0 V, VEE = 0 V, TA = +25°C
VCC = +15 V, VEE = −15 V, TA = +25°C
VCC = +15 V, VEE = −15 V, TA = Tlow to Thigh (Note 3)
ID
−
−
−
180
220
−
250
250
300
1. Either or both input voltages must not exceed the magnitude of VCC or VEE.
2. Power dissipation must be considered to ensure maximum junction temperature (TJ) is not exceeded.
3. MC3317x
Tlow = −40°C
Thigh = +85°C
MC3317xV, NCV33172
Tlow = −40°C
Thigh = +125°C
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3
mA
MC33171, MC33172, MC33174, NCV33172
AC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = −15 V, RL connected to ground, TA = +25°C, unless otherwise noted.)
Characteristics
Symbol
Slew Rate (Vin = −10 V to +10 V, RL = 10 k, CL = 100 pF)
AV +1
AV −1
Min
Typ
Max
SR
Unit
V/ms
Gain Bandwidth Product (f = 100 kHz)
GBW
Power Bandwidth
AV = +1.0 RL = 10 k, VO = 20 Vpp, THD = 5%
BWp
1.6
−
2.1
2.1
−
−
1.4
1.8
−
−
35
−
−
−
60
45
−
−
−
−
15
5.0
−
−
MHz
kHz
Phase Margin
RL = 10 k
RL = 10 k, CL = 100 pF
fm
Gain Margin
RL = 10 k
RL = 10 k, CL = 100 pF
Am
Equivalent Input Noise Voltage
RS = 100 W, f = 1.0 kHz
en
−
32
−
nV/√Hz
Equivalent Input Noise Current (f = 1.0 kHz)
In
−
0.2
−
pA/√Hz
−
300
−
−
0.8
−
−
0.03
−
Differential Input Resistance
Vcm = 0 V
Deg
dB
Rin
Input Capacitance
MW
Cin
Total Harmonic Distortion
AV = +10, RL = 10 k, 2.0 Vpp ≤ VO ≤ 20 Vpp, f = 10 kHz
THD
pF
%
−
120
−
dB
Open Loop Output Impedance (f = 1.0 MHz)
zo
−
100
−
W
0
V,
sat OUTPUT SATURATION VOLTAGE (V)
CS
V
ICR , INPUT COMMON MODE VOLTAGE RANGE (V)
Channel Separation (f = 10 kHz)
VCC/VEE = ±1.5 V to ± 22 V
DVIO = 5.0 mV
VCC
−0.8
−1.6
−2.4
0.1
VEE
0
−55
−25
0
25
50
75
TA, AMBIENT TEMPERATURE (°C)
100
125
0
VCC/VEE = ± 5.0 V to ± 22 V
TA = 25°C
VCC
−1.0
Source
1.0
Sink
0
VEE
0
Figure 2. Input Common Mode Voltage Range
versus Temperature
1.0
2.0
3.0
IL, LOAD CURRENT (±mA)
Figure 3. Split Supply Output Saturation
versus Load Current
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4.0
70
20
Phase
Margin
= 58°
10
0
−10
−20
2
VCC/VEE = ±15 V
RL = 10 k
Vout = 0 V
TA = 25°C
1 − Phase
2 − Phase, CL = 100 pF
3 − Gain
4 − Gain, CL = 100 pF
−30
100 k
Gain
1 Margin
= 15 dB
4
140
160
180
3
200
φ m, PHASE MARGIN (DEGREES)
120
70
60
60
VCC/VEE = ±15 V
AVOL = +1.0
RL = 10 k
DVO = 20 mVpp
TA = 25°C
fm
50
40
30
%
20
20
10
10
220
1.0 M
f, FREQUENCY (Hz)
0
10 M
10
20
50
100
200
CL, LOAD CAPACITANCE (pF)
500
0
1.0 k
Figure 5. Phase Margin and Percent
Overshoot versus Load Capacitance
5.0 ms/DIV
GBW
1.1
50 mV/DIV
VCC/VEE = ±15 V
RL = 10 k
1.2
0
10 V/DIV
1.3
GBW AND SR (NORMALIZED)
40
30
Figure 4. Open Loop Voltage Gain and
Phase versus Frequency
0
VCC/VEE = ±15 V
VCM = 0 V
VO = 0 V
DIO = ±0.5 mA
TA = 25°C
1.0
SR
0.9
0.8
0.7
−55
−25
0
25
50
75
100
125
5.0 ms/DIV
TA, AMBIENT TEMPERATURE (°C)
Figure 6. Normalized Gain Bandwidth Product
and Slew Rate versus Temperature
Figure 7. Small and Large Signal
Transient Response
120
100
VCC/VEE = ±15 V
AV = +1.0
RL = 10 k
CL = 100 pF
TA = 25°C
80
I,
D I,
CC POWER SUPPLY CURRENT (mA)
140
zo , OUTPUT IMPEDANCE ()
Ω
50
%, PERCENT OVERSHOOT
3
0
φ , EXCESS PAHSE (DEGREES)
A VOL , OPEN LOOP VOLTAGE GAIN (dB)
MC33171, MC33172, MC33174, NCV33172
AV = 1000
AV = 100
60
40
AV = 10
AV = 1.0
20
0
200
2.0 k
20 k
f, FREQUENCY (Hz)
200 k
2.0 M
1.1
1. TA = −55°C
2. TA = 25°C
0.9 3. TA = 125°C
2
3
0.7
Dual
1
2
3
Single
1
2
3
0.5
0.3
0.1
0
Figure 8. Output Impedance and Frequency
1
Quad
5.0
10
15
VCC/VEE, SUPPLY VOLTAGE (±V)
20
Figure 9. Supply Current versus Supply Voltage
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25
MC33171, MC33172, MC33174, NCV33172
APPLICATIONS INFORMATION − CIRCUIT DESCRIPTION/PERFORMANCE FEATURES
Although the bandwidth, slew rate, and settling time of the
MC33171/72/74 amplifier family is similar to low power op
amp products utilizing JFET input devices, these amplifiers
offer additional advantages as a result of the PNP transistor
differential inputs and an all NPN transistor output stage.
Because the input common mode voltage range of this
input stage includes the VEE potential, single supply
operation is feasible to as low as 3.0 V with the common
mode input voltage at ground potential.
The input stage also allows differential input voltages up
to ±44 V, provided the maximum input voltage range is not
exceeded. Specifically, the input voltages must range
between VCC and VEE supply voltages as shown by the
maximum rating table. In practice, although not
recommended, the input voltages can exceed the VCC
voltage by approximately 3.0 V and decrease below the VEE
voltage by 0.3 V without causing product damage, although
output phase reversal may occur. It is also possible to source
up to 5.0 mA of current from VEE through either inputs’
clamping diode without damage or latching, but phase
reversal may again occur. If at least one input is within the
common mode input voltage range and the other input is
within the maximum input voltage range, no phase reversal
will occur. If both inputs exceed the upper common mode
input voltage limit, the output will be forced to its lowest
voltage state.
Since the input capacitance associated with the small
geometry input device is substantially lower (0.8 pF) than
that of a typical JFET (3.0 pF), the frequency response for
a given input source resistance is greatly enhanced. This
becomes evident in D−to−A current to voltage conversion
applications where the feedback resistance can form a pole
with the input capacitance of the op amp. This input pole
creates a 2nd Order system with the single pole op amp and
is therefore detrimental to its settling time. In this context,
lower input capacitance is desirable especially for higher
values of feedback resistances (lower current DACs). This
input pole can be compensated for by creating a feedback
zero with a capacitance across the feedback resistance, if
necessary, to reduce overshoot. For 10 kW of feedback
resistance, the MC33171/72/74 family can typically settle to
within 1/2 LSB of 8 bits in 4.2 ms, and within 1/2 LSB of 12
bits in 4.8 ms for a 10 V step. In a standard inverting unity
gain fast settling configuration, the symmetrical slew rate is
typically ±2.1 V/ms. In the classic noninverting unity gain
configuration the typical output positive slew rate is also
2.1 V/ms, and the corresponding negative slew rate will
usually exceed the positive slew rate as a function of the fall
time of the input waveform.
The all NPN output stage, shown in its basic form on the
equivalent circuit schematic, offers unique advantages over
the more conventional NPN/PNP transistor Class AB output
stage. A 10 kW load resistance can typically swing within
0.8 V of the positive rail (VCC) and negative rail (VEE),
providing a 28.4 Vpp swing from ±15 V supplies. This large
output swing becomes most noticeable at lower supply
voltages.
The positive swing is limited by the saturation voltage of
the current source transistor Q7, the VBE of the NPN pull−up
transistor Q17, and the voltage drop associated with the
short circuit resistance, R5. For sink currents less than
0.4 mA, the negative swing is limited by the saturation
voltage of the pull−down transistor Q15, and the voltage
drop across R4 and R5. For small valued sink currents, the
above voltage drops are negligible, allowing the negative
swing voltage to approach within millivolts of VEE. For sink
currents (> 0.4 mA), diode D3 clamps the voltage across R4.
Thus the negative swing is limited by the saturation voltage
of Q15, plus the forward diode drop of D3 (≈VEE +1.0 V).
Therefore an unprecedented peak−to−peak output voltage
swing is possible for a given supply voltage as indicated by
the output swing specifications.
If the load resistance is referenced to VCC instead of
ground for single supply applications, the maximum
possible output swing can be achieved for a given supply
voltage. For light load currents, the load resistance will pull
the output to VCC during the positive swing and the output
will pull the load resistance near ground during the negative
swing. The load resistance value should be much less than
that of the feedback resistance to maximize pull−up
capability.
Because the PNP output emitter−follower transistor has
been eliminated, the MC33171/72/74 family offers a 15 mA
minimum current sink capability, typically to an output
voltage of (VEE +1.8 V). In single supply applications the
output can directly source or sink base current from a
common emitter NPN transistor for current switching
applications.
In addition, the all NPN transistor output stage is
inherently faster than PNP types, contributing to the bipolar
amplifier’s improved gain bandwidth product. The
associated high frequency low output impedance (200 W typ
@ 1.0 MHz) allows capacitive drive capability from 0 pF to
400 pF without oscillation in the noninverting unity gain
configuration. The 60° phase margin and 15 dB gain margin,
as well as the general gain and phase characteristics, are
virtually independent of the source/sink output swing
conditions. This allows easier system phase compensation,
since output swing will not be a phase consideration. The AC
characteristics of the MC33171/72/74 family also allow
excellent active filter capability, especially for low voltage
single supply applications.
Although the single supply specification is defined at
5.0 V, these amplifiers are functional to at least 3.0 V @
25°C. However slight changes in parametrics such as
bandwidth, slew rate, and DC gain may occur.
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MC33171, MC33172, MC33174, NCV33172
If power to this integrated circuit is applied in reverse
polarity, or if the IC is installed backwards in a socket, large
unlimited current surges will occur through the device that
may result in device destruction.
As usual with most high frequency amplifiers, proper lead
dress, component placement and PC board layout should be
exercised for optimum frequency performance. For
example, long unshielded input or output leads may result in
unwanted input/output coupling. In order to preserve the
relatively low input capacitance associated with these
amplifiers, resistors connected to the inputs should be
immediately adjacent to the input pin to minimize additional
stray input capacitance. This not only minimizes the input
pole for optimum frequency response, but also minimizes
extraneous “pick up” at this node. Supply decoupling with
adequate capacitance immediately adjacent to the supply pin
is also important, particularly over temperature, since many
types of decoupling capacitors exhibit great impedance
changes over temperature.
The output of any one amplifier is current limited and thus
protected from a direct short to ground. However, under
such conditions, it is important not to allow the device to
exceed the maximum junction temperature rating. Typically
for ±15 V supplies, any one output can be shorted
continuously to ground without exceeding the maximum
temperature rating.
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MC33171, MC33172, MC33174, NCV33172
2.2 k
VCC
510 k
VCC
3.8 Vpp
VO 0
CO
+
100 k
VO
−
RL
CO
+
10 k
100 k
Vin
100 k
3.6 Vpp
VO 0
100 k
Cin
VO
−
100 k
10 k
Cin
RL
1.0 k
100 k
Vin
AV = 101
BW ( −3.0 dB) = 20 kHz
AV = 10
BW ( −3.0 dB) = 200 kHz
Figure 10. AC Coupled Noninverting Amplifier
with Single +5.0 V Supply
VCC
100 k
4.7 k
Figure 11. AC Coupled Inverting Amplifier
with Single +5.0 V Supply
VCC
50 k
RL
+
3
2
VO
−
7
+
6
5
−
1
4
10 k
1.0 M
100 k
VEE
4.2 Vpp
V 2.5 V
Vin O
Offset Nulling range is approximately ±80 mV with
a 10 k potentiometer, MC33171 only.
AV = 10
BW ( −3.0 dB) = 200 kHz
Figure 12. DC Coupled Inverting Amplifier
Maximum Output Swing with Single
+5.0 V Supply
Figure 13. Offset Nulling Circuit
VCC
fo = 30 kHz
Q = 10
HO = 1.0
Vin ≥ 0.2 Vdc
16 k
Vin
R
0.01
16 k
−
R1
1.1 k
VO
+
R
2R
32 k
2C
0.02
R3
2.2 k
−
Vin
C
R2
5.6 k
2C
0.02
C
0.047
fo = 1.0 kHz
C
0.047
0.4
VCC
1
fo =
4 p RC
VO
+
Then: R1 =
R3
2 HO
R2 =
R1 R3
4Q2R1 −R3
Qo fo
Q
Given fo = center frequency
R3 =
< 0.1
Ao = Gain at center frequency
p foC
GBW
Choose Value fo, Q, Ao, C
For less than 10% error for operational amplifier, where fo and GBW are expressed in Hz.
Figure 14. Active High−Q Notch Filter
Figure 15. Active Bandpass Filter
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MC33171, MC33172, MC33174, NCV33172
ORDERING INFORMATION
Op Amp
Function
Operating
Device
Temperature Range
MC33171D
SO−8
(Pb−Free)
MC33171DR2
MC33171DR2G
SO−8
(Pb−Free)
Plastic DIP
MC33171PG
Plastic DIP
(Pb−Free)
MC33172D
SO−8
(Pb−Free)
MC33172DR2
SO−8
(Pb−Free)
Plastic DIP
MC33172PG
Plastic DIP
(Pb−Free)
MC33172VD
SO−8
MC33172VDG
TA = −40° to +125°C
2500 / Tape & Reel
SO−8
MC33174D
SO−14
MC33174DG
SO−14
(Pb−Free)
MC33174DR2
SO−14
SO−14
(Pb−Free)
TSSOP−14*
MC33174DTBG
TSSOP−14*
MC33174DTBR2
TSSOP−14*
MC33174DTBR2G
TSSOP−14*
MC33174P
Plastic DIP
MC33174PG
Plastic DIP
(Pb−Free)
MC33174VDR2
2500 / Tape & Reel
55 Units/Rail
2500 / Tape & Reel
96 Units/Rail
2500 / Tape & Reel
25 Units/Rail
SO−14
MC33174VDR2G
MC33174VP
50 Units/Rail
SO−8
NCV33172DR2**
TA = −40° to +85°C
2500 / Tape & Reel
98 Units/Rail
SO−8
(Pb−Free)
MC33174DR2G
Quad
98 Units/Rail
SO−8
(Pb−Free)
MC33172VDR2G
MC33174DTB
50 Units/Rail
SO−8
TA = −40° to +85°C
MC33172P
MC33172VDR2
2500 / Tape & Reel
SO−8
MC33172DG
Dual
98 Units/Rail
SO−8
TA = −40° to +85°C
MC33171P
MC33172DR2G
Shipping †
SO−8
MC33171DG
Single
Package
TA = −40° to +125°C
MC33174VPG
SO−14
(Pb−Free)
2500 / Tape & Reel
Plastic DIP
Plastic DIP
(Pb−Free)
25 Units/Rail
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
**NCV prefix for automotive and other applications requiring site and control changes.
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MC33171, MC33172, MC33174, NCV33172
MARKING DIAGRAMS
8
8
MC3317xP
AWL
YYWWG
3317V
ALYW
1
PDIP−14
P SUFFIX
CASE 646
1
PDIP−14
VP SUFFIX
CASE 646
SO−14
D SUFFIX
CASE 751A
14
MC33174P
AWLYYWWG
1
8
3317x
ALYW
1
14
SO−8
MC33172VD
NCV33172D
CASE 751
SO−8
D SUFFIX
CASE 751
PDIP−8
P SUFFIX
CASE 626
14
MC33174VP
AWLYYWWG
14
MC33174VDG
AWLYWW
MC33174DG
AWLYWW
1
1
TSSOP−14
DTB SUFFIX
CASE 948G
14
MC33
174
ALYW 1
x
A
WL, L
YY, Y
WW, W
G or SO−14
VD SUFFIX
CASE 751A
= 1 or 2
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
http://onsemi.com
10
1
MC33171, MC33172, MC33174, NCV33172
PACKAGE DIMENSIONS
PDIP−8
P SUFFIX
CASE 626−05
ISSUE L
8
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5
−B−
1
4
F
−A−
NOTE 2
L
C
J
−T−
N
SEATING
PLANE
D
H
M
K
G
0.13 (0.005)
M
T A
M
B
M
http://onsemi.com
11
DIM
A
B
C
D
F
G
H
J
K
L
M
N
MILLIMETERS
MIN
MAX
9.40
10.16
6.10
6.60
3.94
4.45
0.38
0.51
1.02
1.78
2.54 BSC
0.76
1.27
0.20
0.30
2.92
3.43
7.62 BSC
−−−
10 0.76
1.01
INCHES
MIN
MAX
0.370
0.400
0.240
0.260
0.155
0.175
0.015
0.020
0.040
0.070
0.100 BSC
0.030
0.050
0.008
0.012
0.115
0.135
0.300 BSC
−−−
10
0.030
0.040
MC33171, MC33172, MC33174, NCV33172
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AH
−X−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
1
0.25 (0.010)
M
Y
M
4
−Y−
K
G
C
N
DIM
A
B
C
D
G
H
J
K
M
N
S
X 45 SEATING
PLANE
−Z−
0.10 (0.004)
H
D
0.25 (0.010)
M
Z Y
S
X
M
J
S
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
12
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0
8 0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 8 0.010
0.020
0.228
0.244
MC33171, MC33172, MC33174, NCV33172
PACKAGE DIMENSIONS
PDIP−14
CASE 646−06
ISSUE P
14
8
1
7
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
B
A
F
L
N
C
−T−
SEATING
PLANE
H
G
D 14 PL
J
K
0.13 (0.005)
M
M
http://onsemi.com
13
DIM
A
B
C
D
F
G
H
J
K
L
M
N
INCHES
MIN
MAX
0.715
0.770
0.240
0.260
0.145
0.185
0.015
0.021
0.040
0.070
0.100 BSC
0.052
0.095
0.008
0.015
0.115
0.135
0.290
0.310
−−−
10 0.015
0.039
MILLIMETERS
MIN
MAX
18.16
19.56
6.10
6.60
3.69
4.69
0.38
0.53
1.02
1.78
2.54 BSC
1.32
2.41
0.20
0.38
2.92
3.43
7.37
7.87
−−−
10 0.38
1.01
MC33171, MC33172, MC33174, NCV33172
PACKAGE DIMENSIONS
SOIC−14
CASE 751A−03
ISSUE H
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
−A−
14
8
−B−
P 7 PL
0.25 (0.010)
M
7
1
G
−T−
D 14 PL
0.25 (0.010)
T B
S
A
DIM
A
B
C
D
F
G
J
K
M
P
R
J
M
K
M
F
R X 45 C
SEATING
PLANE
B
M
S
SOLDERING FOOTPRINT*
7X
7.04
14X
1.52
1
14X
0.58
1.27
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
14
MILLIMETERS
MIN
MAX
8.55
8.75
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0
7
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.337 0.344
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
0.008 0.009
0.004 0.009
0
7
0.228 0.244
0.010 0.019
MC33171, MC33172, MC33174, NCV33172
PACKAGE DIMENSIONS
TSSOP−14
CASE 948G−01
ISSUE B
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
14X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
S
S
N
2X
14
L/2
M
B
−U−
L
PIN 1
IDENT.
N
F
7
1
0.15 (0.006) T U
0.25 (0.010)
8
S
DETAIL E
ÇÇÇ
ÉÉÉ
ÇÇÇ
ÉÉÉ
ÇÇÇ
K
A
−V−
K1
J J1
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
SECTION N−N
−W−
C
0.10 (0.004)
−T− SEATING
PLANE
D
H
G
DETAIL E
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
14X
0.36
14X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
15
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
−−−
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.50
0.60
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0
8
INCHES
MIN MAX
0.193 0.200
0.169 0.177
−−− 0.047
0.002 0.006
0.020 0.030
0.026 BSC
0.020 0.024
0.004 0.008
0.004 0.006
0.007 0.012
0.007 0.010
0.252 BSC
0
8
MC33171, MC33172, MC33174, NCV33172
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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For additional information, please contact your local
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MC33171/D