FTDI CSTCR6M00G15 Dual usb uart / fifo i.c. Datasheet

FT2232L Dual USB UART / FIFO I.C.
1.0
Introduction
The FT2232L is the lead free version of FTDI’s 3rd generation USB UART / FIFO I.C. family. This device features two
Multi-Purpose UART / FIFO controllers which can be conﬁgured individually in several different modes. As well as a
UART interface, FIFO interface and Bit-Bang IO modes of the 2nd generation FT232BM and FT245BM devices, the
FT2232L offers a variety of additional new modes of operation, including a Multi-Protocol Synchronous Serial Engine
interface which is designed speciﬁcally for synchronous serial protocols such as JTAG and SPI bus.
1.1
Features Summary
•
Single Chip USB  Dual Channel Serial / Parallel
Reset input and Reset Output pins
HARDWARE FEATURES
•
level conversion on each channel
Ports with a variety of conﬁgurations
•
•
•
5V and 3.3V logic IO Interfacing with independent
Entire USB protocol handled on the chip...no USB-
•
Integrated 3.3V LDO Regulator for USB IO
speciﬁc ﬁrmware programming required
•
Integrated 6MHz – 48Mhz clock multiplier PLL
FT232BM-style UART interface option with full
•
USB Bulk or Isochronous data transfer modes
Handshaking & Modem interface signals
•
4.35V to 5.25V single supply operating voltage
range
UART Interface supports 7 / 8 bit data, 1 / 2 stop
bits, and Odd / Even / Mark / Space / No Parity
•
UHCI / OHCI / EHCI host controller compatible
•
Transfer Data Rate 300 to 1 Mega Baud (RS232)
•
USB 2.0 Full Speed (12 Mbits / Second)
•
Transfer Data Rate 300 to 3 Mega Baud (TTL and
compatible
Compact 48-LD Lead Free LQFP package
RS422 / RS485)
•
Auto Transmit Enable control for RS485 serial
VIRTUAL COM PORT (VCP) DRIVERS for
applications using TXDEN pin
•
Windows 98 / 98 SE / 2000 / ME / XP
FT245BM-style FIFO interface option with bi-
•
Linux 2.40 and greater
directional data bus and simple 4 wire handshake
•
Windows CE
interface
•
MAC OS-8 and OS-9**
•
Transfer Data Rate up to 1 MegaByte / Second
•
MAC OS-X
•
Enhanced Bit-Bang Mode interface option
D2XX (USB Direct Drivers + DLL S/W Interface)
•
New Synchronous Bit-Bang Mode interface option
•
Windows 98 / 98 SE / 2000 / ME / XP
•
New Multi-Protocol Synchronous Serial Engine
•
Linux 2.4 and Greater
(MPSSE) interface option
APPLICATION AREAS
•
New MCU Host Bus Emulation Mode option
•
USB Dual Port RS232 Converters
•
New Fast Opto-Isolated Serial Interface Mode
•
USB  Dual Port RS422 / RS485 Converters
option
•
Upgrading Legacy Peripheral Designs to USB
Interface mode and USB Description strings
•
USB Instrumentation
conﬁgurable in external EEPROM
•
USB JTAG Programming
•
EEPROM Conﬁgurable on board via USB
•
USB to SPI Bus Interfaces
•
Support for USB Suspend and Resume conditions
•
USB Industrial Control
via PWREN#, and SI / WU pins
•
Field Upgradable USB Products
Support for bus powered, self powered, and high-
•
Galvanically Isolated Products with USB Interface
•
•
•
•
power bus powered USB conﬁgurations
•
Integrated Power-On-Reset circuit, with optional
DS2232L Version 1.4
[ ** = In planning or under development ]
© Future Technology Devices International Ltd. 2005 Page 1 of 51
FT2232L Dual USB UART / FIFO I.C.
1.2
General Description
The FT2232L is a USB interface which incorporates the functionallity of two of FTDI’s second generation BM chips
into a single device. A single downstream USB port is converted to two IO channels which can each be individually
conﬁgured as a FT232BM-style UART interface, or a FT245BM-style FIFO interface, without the need to add a
USB hub. There are also several new special modes which are either enabled in the external EEPROM, or by using
driver commands. These include Synchronous Bit-Bang Mode, a CPU-Style FIFO Interface Mode, a Multi-Protocol
Synchronous Serial Engine Interface Mode, MCU Host Bus Emulation Mode, and Fast Opto-Isolated Serial Interface
Mode. In addition a new high drive level option means that the device UART / FIFO IO pins will drive out at around
three times the normal power level, meaning that the bus can be shared by several devices. Classic BM-style
Asynchronous Bit-Bang Mode is also supported, but has been enhanced to give the user access to the device’s
internal RD# and WR# strobes.
FTDI provide a royalty free Virtual Com Port (V.C.P) driver that makes the peripheral ports look like a standard COM
port to the PC. Most existing software applications should be able interface with the Virtual Com Port simply by
reconﬁguring them to use the new ports created by the driver. Using the VCP drivers an application programmer would
communicate with the device in exactly the same way as they would a regular PC COM port - using the Windows
VCOMM API calls or a COM port library. The FT2232L driver also incorporates the functions deﬁned for FTDI’s D2XX
drivers, allowing applications programmers to interface software directly to the device using a Windows DLL. Details of
the driver and the programming interface can be found on FTDI’s website at www.ftdichip.com.
DS2232L Version 1.4
© Future Technology Devices International Ltd. 2005 Page 2 of 51
FT2232L Dual USB UART / FIFO I.C.
2.0
Features and Enhancements
The FT2232L incorporates all of the enhancements introduced for the second generation FT232BM and FT245BM
chips. These are summarised as follows :•
•
Two Individually Conﬁgurable IO Channels
is also retained. This will make the device gently
Each of the FT2232L’s Channels (A and B) can be
individually conﬁgured as a FT232BM-style UART
interface, or as a FT245BM-style FIFO interface. In
addition these channel can be conﬁgured in a number
pull down on the FIFO / UART IO lines when the
of special IO modes.
circuitry controlled by PWREN# resets reliably when
power is shut off (PWREN# is high). In this mode any
residual voltage on external circuitry is bled to GND
when power is removed, thus ensuring that external
power is restored.
Integrated Power-On-Reset (POR) circuit
The device incorporates an internal POR function.
A RESET# pin is available to allow external logic to
reset the device where required, however for most
applications this pin can simply be hardwired to Vcc.
•
Whilst USB Bulk transfer is usually the best choice
for data transfer, the scheduling time of the data is
not guaranteed. For applications where scheduling
A RSTOUT# pin is provided in order to allow the new
latency takes priority over data integrity such as
POR circuit to provide a stable reset to external MCU
transferring audio and low bandwidth video data,
and other devices.
•
the FT2232L offers the option of USB Isochronous
transfer via conﬁguration of bit in the EEPROM.
Integrated RCCLK circuit
Used to ensure that the oscillator and clock multiplier
PLL frequency are stable prior to USB enumeration.
•
•
There is a Send Immediate / Wake Up (SI/WU) signal
Integrated level converter on UART / FIFO
pins on each of the chips channels. These combine
two functions on one pin. If USB is in suspend mode
Each channel of the FT2232L has its own
(and remote wakeup is enabled in the EEPROM),
independent VCCIO pin that can be supplied by
strobing this pin low will cause the device to request
between 3V to 5V. This allows each channel’s output
a resume from suspend (WakeUp) on the USB Bus.
voltage drive level to be individually conﬁgured. Thus
Normally, this can be used to wake up the Host PC.
allowing, for example 3.3V logic to be interfaced
During normal operation, if this pin is strobed low
to the device without the need for external level
any data in the device RX buffer will be sent out over
converter I.C.’s.
USB on the next Bulk-IN request from the drivers
regardless of the packet size. This can be used to
Improved power management control for high-
optimise USB transfer speed for some applications.
power USB Bus Powered devices
The PWREN# pin will become active when the
device is enumerated by USB, and be deactivated
when the device is in USB suspend. This can be
used to directly drive a transistor or P-Channel
MOSFET in applications where power switching
of external circuitry is required. The BM pull down
enable feature (conﬁgured in the external EEPROM)
DS2232L Version 1.4
Send Immediate / Wake Up Signal Pin on each
channel
interface and control signals
•
Support for Isochronous USB Transfers
•
Low suspend current
The suspend current of the FT2232L is typically
under 100 μA (excluding the 1.5K pull up resistor on
USBDP) in USB suspend mode. This allows greater
margin for peripherals to meet the USB Suspend
current limit of 500uA.
© Future Technology Devices International Ltd. 2005 Page 3 of 51
FT2232L Dual USB UART / FIFO I.C.
•
Programmable Receive Buffer Timeout
•
Extended EEPROM Support
The TX buffer timeout is programmable over USB in
The FT2232L supports 93C46 (64 x 16 bit), 93C56
1ms increments from 1ms to 255ms, thus allowing
(128 x 16 bit), and 93C66 (256 x 16 bit) EEPROMs.
the device to be better optimised for protocols
The extra space is not used by the device, however
requiring faster response times from short data
it is available for use by other external MCU / logic
packets.
whilst the FT2232L is being held in reset. There is
now an adiitional 64 words of space available (128
•
Relaxed VCC Decoupling
The improved level of Vcc decoupling that was
incorporated into BM devices has also been
implemented in the FT2232L device.
bytes total) in the user area when a 93C56 or 93C66
is used.
•
USB 2.0 (full speed option)
An EEPROM based option allows the FT2232L to
•
Baud Rate Pre-Scaler Divisors
return a USB 2.0 device descriptor as opposed to
The FT2232L (UART mode) baud rate pre-scaler
USB 1.1. Note : The device would be a USB 2.0 Full
supports division by (n+0), (n+0.125), (n+0.25),
Speed device (12Mb/s) as opposed to a USB 2.0
(n+0.375), (n+0.5), (n+0.625), (n+0.75) and (n+0.875)
High Speed device (480Mb/s).
where n is an integer between 2 and 16,384 (214).
DS2232L Version 1.4
© Future Technology Devices International Ltd. 2005 Page 4 of 51
FT2232L Dual USB UART / FIFO I.C.
In addition to the BM chip features, the FT2232L incorporates the following new features and interface modes :•
Enhanced Asynchronous Bit-Bang Interface
normally be un-conﬁgured (i.e. have no deﬁned
The FT2232L supports FTDI’s BM chip Bit Bang
function) at power-up. Application software on the PC
mode. In Bit Bang mode, the eight FIFO data lines
could use the MPSSE to download conﬁguration data
can be switched between FIFO interface mode
to the FPGA over USB. This data would deﬁne the
and an 8-bit Parallel IO port. Data packets can be
hardware’s function on power up. The other FT2232
sent to the device and they will be sequentially sent
channel would be available for other devices.
to the interface at a rate controlled by an internal
This approach would allow a customer to create a
timer (equivalent to the baud rate prescaler). With
“generic” USB peripheral, who’s hardware function
the FT2232L device this mode has been enhanced
can be deﬁned under control of the application
so that the internal RD# and WR# strobes are now
brought out of the device which can be used to allow
external logic to be clocked by accesses to the BitBang IO bus.
software. The FPGA based hardware could be easily
upgraded or totally changed simply by changing the
FPGA conﬁguration data ﬁle. (See FTDI’s MORPHIC development module for a practicle example,
www.morph-ic.com)
•
•
•
Synchronous Bit-Bang Interface
Synchronous Bit-Bang Mode differs from
Asynchronous Bit-Bang mode in that the device
is only read when it is written to. Thus making it
easier for the controlling program to measure the
response to an output stimulus as the data returned
is synchronous to the output data.
High Output Drive Level Capabillity
The IO interface pins can be made to drive out at
three times the standard drive level thus allowing
multiple devices, or devices that require a greater
drive strength to be interfaced to the FT2232L. This
option is conﬁgured in the external EEPROM, ad can
be set individually for each channel.
Multi-Protocol Synchronous Serial Engine
Interface (M.P.S.S.E.)
The Multi-Protocol Synchronous Serial Engine
(MPSSE) interface is a new option designed to
interface efﬁciently with synchronous serial protocols
such as JTAG and SPI Bus. It is very ﬂexible in that it
can be conﬁgured for different industry standards, or
•
MCU Host Bus Emulation
This new mode combines the ‘A’ and ‘B’ bus interface
to make the FT2232L interface emulate a standard
8048 / 8051 style MCU bus. This allows peripheral
devices for these MCU families to be directly
attached to the FT2232L with IO being performed
over USB with the help of MPSSE interface
technology.
•
Fast Opto-Isolated Serial Interface
A new proprietary FTDI protocol is designed to
allow galvanically isolated devices to communicate
sychronously with the FT2232L using just 4 signal
wires (over two dual opto-isolators), and two power
lines. The peripheral circuitry controls the data
transfer rate in both directions, whilst maintaining
full data integrity. Maximum USB full speed data
rates can be acheived. Both ‘A’ and ‘B’ channels
can communicate over the same 4 wire interface if
desired.
proprietary bus protocols. For instance, it is possible
to connect one of the FT2232L’s channels to an
SRAM conﬁgurable FPGA as supplied by vendors
such as Altera and Xilinx. The FPGA device would
DS2232L Version 1.4
© Future Technology Devices International Ltd. 2005 Page 5 of 51
FT2232L Dual USB UART / FIFO I.C.
3.0
Simpliﬁed Block Diagram
PWREN#
VCC
48MHz
Baud Rate
Generator
Channel A
ADBUS1
ADBUS2
PWRCTL
3V3OUT
ADBUS0
Dual Port TX
Buffer
128 bytes
3.3 Volt
LDO
Regulator
Dual Port RX
Buffer
384 Bytes
ADBUS3
ADBUS4
MultiPurpose
UART / FIFO
Controller
ADBUS5
ADBUS6
ADBUS7
ACBUS0
ACBUS1
ACBUS2
ACBUS3
USBDP
USB
Transceiver
USBDM
Serial Interface
Engine
( SIE )
SI/WUA
USB
Protocol Engine
Channel B
Dual Port TX
Buffer
128 bytes
USB DPLL
Dual Port RX
Buffer
384 Bytes
XTOUT
x8 Clock
Multiplier
48MHz
XTIN
TEST
GND
BDBUS1
BDBUS2
MultiPurpose
UART / FIFO
Controller
BDBUS3
BDBUS4
BDBUS5
BDBUS6
BDBUS7
BCBUS0
BCBUS1
BCBUS2
48MHz
6MHZ
Oscillator
BDBUS0
12MHz
Baud Rate
Generator
BCBUS3
SI/WUB
3V3OUT
EECS
EEPROM
Interface
EESK
RESET#
EEDATA
RESET
GENERATOR
RSTOUT#
Figure 1 - FT2232L Simpliﬁed Block Diagram
3.1
•
Functional Block Descriptions
3.3V LDO Regulator
The 3.3V LDO Regulator generates the 3.3 volt
reference voltage for driving the USB transceiver
cell output buffers. It requires an external
decoupling capacitor to be attached to the 3V3OUT
regulator output pin. It also provides 3.3V power to
the RSTOUT# pin. The main function of this block
is to power the USB Transceiver and the Reset
Generator Cells rather than to power external logic.
However, external circuitry requiring 3.3V nominal
at a current of not greater than 5mA could also
draw its power from the 3V3OUT pin if required.
DS2232L Version 1.4
•
USB Transceiver
The USB Transceiver Cell provides the USB 1.1 /
USB 2.0 full-speed physical interface to the USB
cable. The output drivers provide 3.3 volt level slew
rate control signalling, whilst a differential receiver
and two single ended receivers provide USB data
in, SEO and USB Reset condition detection.
•
USB DPLL
The USB DPLL cell locks on to the incoming NRZI
USB data and provides separate recovered clock
and data signals to the SIE block.
© Future Technology Devices International Ltd. 2005 Page 6 of 51
FT2232L Dual USB UART / FIFO I.C.
•
6MHz Oscillator
The 6MHz Oscillator cell generates a 6MHz
reference clock input to the x8 Clock multiplier from
an external 6MHz crystal or ceramic resonator.
•
x8 Clock Multiplier
The x8 Clock Multiplier takes the 6MHz input
from the Oscillator cell and generates a 48MHz
reference clock for the USB DPPL and the Baud
Rate Generator blocks.
•
Serial Interface Engine (SIE)
The Serial Interface Engine (SIE) block performs
the Parallel to Serial and Serial to Parallel
conversion of the USB data. In accordance to the
USB 2.0 speciﬁcation, it performs bit stufﬁng / unstufﬁng and CRC5 / CRC16 generation / checking
on the USB data stream.
•
USB Protocol Engine
The USB Protocol Engine manages the data
stream from the device USB control endpoint. It
handles the low level USB protocol (Chapter 9)
requests generated by the USB host controller
and the commands for controlling the functional
parameters of the UART / FIFO controller blocks.
•
Dual Port TX Buffers (128 bytes)
Data from the USB data out endpoint is stored
in the Dual Port TX buffer and removed from the
buffer to the transmit register under control of the
UART FIFO controller.
•
Dual Port RX Buffers (384 bytes)
Data from the UART / FIFO controller receive
register is stored in the Dual Port RX buffer prior
to being removed by the SIE on a USB request for
data from the device data in endpoint.
•
Multi-Purpose UART / FIFO Controllers
The Multi-purpose UART / FIFO controllers handle
the transfer of data between the Dual Port RX
and TX buffers and the UART / FIFO transmit
DS2232L Version 1.4
and receive registers. When conﬁgured as a
UART it performs asynchronous 7 / 8 bit Parallel
to Serial and Serial to Parallel conversion of the
data on the RS232 (RS422 and RS485) interface.
Control signals supported by UART mode include
RTS, CTS, DSR , DTR, DCD and RI. There
are also transmitter enable control signal pins
(TXDEN) provided to assist with interfacing to
RS485 transceivers. RTS/CTS, DSR/DTR and
Xon/Xoff handshaking options are also supported.
Handshaking, where required, is handled in
hardware to ensure fast response times. The
UART’s also supports the RS232 BREAK setting
and detection conditions.
•
Baud Rate Generator
The Baud Rate Generator provides a x16 clock
input to the UART’s from the 48MHz reference
clock and consists of a 14 bit prescaler and 3
register bits which provide ﬁne tuning of the baud
rate (used to divide by a number plus a fraction).
This determines the Baud Rate of the UART which
is programmable from 183 baud to 3 million baud.
•
RESET Generator
The Reset Generator Cell provides a reliable
power-on reset to the device internal circuitry
on power up. An additional RESET# input and
RSTOUT# output are provided to allow other
devices to reset the FT2232L, or the FT2232L
to reset other devices respectively. During reset,
RSTOUT# is driven low, otherwise it drives out
at the 3.3V provided by the onboard regulator.
RSTOUT# can be used to control the 1.5K
pull-up on USBDP directly where delayed USB
enumeration is required. It can also be used to
reset other devices. RSTOUT# will stay highimpedance for approximately 5ms after VCC
has risen above 3.5V AND the device oscillator is
running AND RESET# is high. RESET# should
be tied to VCC unless it is a requirement to reset
the device from external logic or an external reset
generator I.C.
© Future Technology Devices International Ltd. 2005 Page 7 of 51
FT2232L Dual USB UART / FIFO I.C.
•
EEPROM Interface
When used without an external EEPROM the
FT2232L be conﬁgured as a USB to dual serial
port device. Adding an external 93C46 (93C56
or 93C66) EEPROM allows each of the chip’s
channels to be independently conﬁgured as
a serial UART (232 mode), or a parallel FIFO
(245 mode). The external EEPROM is used to
enable the Fast Opto-Isolated Serial interface
mode. The external EEPROM can also be used
to customise the USB VID, PID, Serial Number,
Product Description Strings and Power Descriptor
value of the FT2232L for OEM applications.
Other parameters controlled by the EEPROM
include Remote Wake Up, Isochronous Transfer
Mode, Soft Pull Down on Power-Off and USB 2.0
DS2232L Version 1.4
descriptor modes.
The EEPROM should be a 16 bit wide
conﬁguration such as a MicroChip 93LC46B or
equivalent capable of a 1Mb/s clock rate at VCC =
4.35V to 5.25V. The EEPROM is programmableon board over USB using a utility program available
from FTDI’s web site (www.ftdichip.com). This
allows a blank part to be soldered onto the PCB
and programmed as part of the manufacturing and
test process.
If no EEPROM is connected (or the EEPROM is
blank), the FT2232L will default to dual serial ports.
The device use its built-in default VID, PID Product
Description and Power Descriptor Value. In this
case, the device will not have a serial number as
part of the USB descriptor.
© Future Technology Devices International Ltd. 2005 Page 8 of 51
FT2232L Dual USB UART / FIFO I.C.
4.0
Device Pin-Out
BDBUS3
BDBUS1
BDBUS2
VCC
PWREN#
BDBUS0
XTIN
XTOUT
AVCC
AGND
EECS
TEST
7
1
48
FTDI
RESET#
RSTOUT#
3V3OUT
USBDP
FT2232L
USBDM
XXYY
ADBUS1
ADBUS3
ADBUS2
ADBUS4
GND
ADBUS5
BDBUS7
43
VCCIOB
BCBUS0
BCBUS1
44
BCBUS2
48
BCBUS3
SI/WUB
GND
1
2
47
V
C
C
I
O
B
ADBUS0
ADBUS1
ADBUS2
ADBUS3
ADBUS4
USBDM
ADBUS5
ADBUS6
ADBUS7
USBDP
ACBUS0
ACBUS1
ACBUS2
ACBUS3
SI/WUA
RSTOUT#
RESET#
BDBUS0
BDBUS1
XTIN
BDBUS2
BDBUS3
BDBUS4
BDBUS5
BDBUS6
XTOUT
EECS
BDBUS7
EESK
BCBUS0
EEDATA
TEST
A
G
N
D
45
ADBUS6
4
Figure 2
Pin-Out
(Lead Free LQFP-48 Package )
DS2232L Version 1.4
5
BDBUS5
GND
BDBUS6
V
C
C
I
O
A
BCBUS1
BCBUS2
BCBUS3
G G G G
SI/WUB
N N N N
D D D D PWREN#
24
23
22
21
20
19
17
16
15
13
12
11
10
40
39
38
37
36
35
33
32
30
29
28
27
26
41
34
25
18
9
ADBUS7
BDBUS4
ADBUS0
25
24
12
13
ACBUS1
GND
SI/WUA
ACBUS3
ACBUS2
37
36
VCCIOA
ACBUS0
EESK
EEDATA
VCC
V
C
C
31
14
8
3V3OUT
42
3
46
6
V
C
C
A
V
C
C
Figure 3
Pin-Out
(Schematic Symbol )
© Future Technology Devices International Ltd. 2005 Page 9 of 51
FT2232L Dual USB UART / FIFO I.C.
5.0
Pin Deﬁnitions
This section decribes the operation of the FT2232L pins. Common pins are deﬁned in the ﬁrst section, then the I/O
pins are deﬁned, by chip mode. More detailed descriptions of the operation of the I/O pins are provided in section 9.
5.1
Common Pins
The operation of the following FT2232L pins stay the same, regardless of the chip mode :USB INTERFACE GROUP
Pin#
Signal
Type
Description
7
USBDP
I/O
USB Data Signal Plus ( Requires 1.5K pull-up to 3V3OUT or RSTOUT# )
8
USBDM
I/O
USB Data Signal Minus
EEPROM INTERFACE GROUP
Pin#
Signal
Type
Description
48
EECS
I/O
EEPROM – Chip Select. Tri-State during device reset. **Note 1
1
EESK
OUTPUT Clock signal to EEPROM. Tri-State during device reset, else drives out. **Note 1
2
EEDATA
I/O
EEPROM – Data I/O Connect directly to Data-In of the EEPROM and to DataOut of the EEPROM via a 2.2K resistor. Also, pull Data-Out of the EEPROM
to VCC via a 10K resistor for correct operation. Tri-State during device reset.
**Note 1
MISCELLANEOUS SIGNAL GROUP
Pin#
Signal
Type
Description
4
RESET#
INPUT
Can be used by an external device to reset the FT2232L. If not required, tie to
VCC. **Note 1
5
RSTOUT#
OUTPUT Output of the internal Reset Generator. Drives low for 5.6 ms after VCC > 3.5V
and the internal clock starts up, then clamps it’s output to the 3.3V output of the
internal regulator. Taking RESET# low will also force RSTOUT# to drive low.
RSTOUT# is NOT affected by a USB Bus Reset.
47
TEST
INPUT
41
PWREN#
OUTPUT Goes Low after the device is conﬁgured via USB, then high during USB suspend.
Can be used to control power to external logic using a P-Channel Logic Level
MOSFET switch. Enable the Interface Pull-Down Option in EEPROM when using
the PWREN# pin in this way.
43
XTIN
INPUT
44
XTOUT
OUTPUT Output from 6MHz Crystal Oscillator Cell. XTOUT stops oscillating during USB
suspend, so take care if using this signal to clock external logic.
Puts device into I.C. test mode – must be tied to GND for normal operation.
Input to 6MHz Crystal Oscillator Cell. This pin can also be driven by an external
6MHz clock if required. Note : Switching threshold of this pin is VCC/2, so if
driving from an external source, the source must be driving at 5V CMOS level or
a.c. coupled to centre around VCC/2.
**Note 1 - During device reset, these pins are tri-state but pulled up to VCC via internal 200K resistors.
DS2232L Version 1.4
© Future Technology Devices International Ltd. 2005 Page 10 of 51
FT2232L Dual USB UART / FIFO I.C.
POWER AND GND GROUP
Pin#
Signal
Type
6
3V3OUT
OUTPUT 3.3 volt Output from the integrated L.D.O. regulator This pin should be
decoupled to GND using a 33nF ceramic capacitor in close proximity to the
device pin. It’s prime purpose is to provide the internal 3.3V supply to the
USB transceiver cell and the RSTOUT# pin. A small amount of current (<=
5mA) can be drawn from this pin to power external 3.3V logic if required.
3, 42
VCC
PWR
+4.35 volt to +5.25 volt VCC to the device core, LDO and non-UART / FIFO
controller interface pins.
14
VCCIOA
PWR
+3.0 volt to +5.25 volt VCC to the UART / FIFO A Channel interface pins
10..13, 15..17 and 19..24. When interfacing with 3.3V external logic in a bus
powered design connect VCCIO to a 3.3V supply generated from the USB
bus. When interfacing with 3.3V external logic in a self powered design
connect VCCIO to the 3.3V supply of the external logic. Otherwise connect
to VCC to drive out at 5V CMOS level.
31
VCCIOB
PWR
+3.0 volt to +5.25 volt VCC to the UART / FIFO B Channel interface pins
26..30, 32..33 and 35..40. When interfacing with 3.3V external logic in a bus
powered design connect VCCIO to a 3.3V supply generated from the USB
bus. When interfacing with 3.3V external logic in a self powered design
connect VCCIO to the 3.3V supply of the external logic. Otherwise connect
to VCC to drive out at 5V CMOS level.
PWR
Device - Ground Supply Pins
9,18, 25, 34 GND
Description
46
AVCC
PWR
Device - Analog Power Supply for the internal x8 clock multiplier. A low pass
ﬁlter consisting of a 470 Ohm series resistor and a 100 nF to GND should be
used on the supply to this pin.
45
AGND
PWR
Device - Analog Ground Supply for the internal x8 clock multiplier
DS2232L Version 1.4
© Future Technology Devices International Ltd. 2005 Page 11 of 51
FT2232L Dual USB UART / FIFO I.C.
5.2
IO Pin Deﬁnitions by Chip Mode
The FT2232L will default to dual serial mode (232 UART mode on both channel A and B, if no external EEPROM is
used, or the external EEPROM is blank. The deﬁnition of the following pins vary according to the chip’s mode :-
Channel A
Pin Deﬁnitions by Chip Mode **Note 2
Enhanced
Asynchronous
MPSSE
and
**Note 4
Synchronous
Bit-Bang Modes
Pin#
Generic
Pin
Name
232 UART 245 FIFO
Mode
Mode
24
ADBUS0
TXD
D0
D0
TCK/SK
AD0
23
ADBUS1
RXD
D1
D1
TDI/D0
AD1
22
ADBUS2
RTS#
D2
D2
TDO/DI
AD2
21
ADBUS3
CTS#
D3
D3
TMS/CS
AD3
20
ADBUS4
DTR#
D4
D4
GPIOL0
AD4
19
ADBUS5
DSR#
D5
D5
GPIOL1
AD5
17
ADBUS6
DCD#
D6
D6
GPIOL2
AD6
16
ADBUS7
RI#
D7
D7
GPIOL3
AD7
15
ACBUS0
TXDEN
RXF#
WR# **Note 6
GPIOH0
I/O0
13
ACBUS1
SLEEP#
TXE#
RD# **Note 6
GPIOH1
I/O1
12
ACBUS2
RXLED#
RD#
WR# **Note 7
GPIOH2
IORDY
11
ACBUS3
TXLED#
WR
RD# **Note 7
GPIOH3
OSC
10
SI/WUA
SI/WUA
SI/WUA
SI/WUA
**Note 8
**Note 8
MCU
Host Bus
Emulation
Mode
**Note 5
Fast
OptoIsolated
Serial
Mode
**Note 3
**Note 2 : 232 UART, 245 FIFO, CPU FIFO Interface, and Fast Opto-Isolated modes are enabled in the external
EEPROM. Enhanced Asynchronous and Synchronous Bit-Bang modes, MPSSE, and MCU Host Bus Emulation
modes are enabled using the driver command set bit mode. See Section 5.2 for details.
**Note 3 : Channel A can be conﬁgured in another IO mode if channel B is in Fast Opto-Isolated Serial Mode. If both
Channel A and Channel B are in Fast Opto-Isolated Serial Mode all of the IO will be on Channel B.
**Note 4 : MPSSE is Channel A only.
**Note 5 : MCU Host Bus Emulation requires both Channels.
**Note 6 : The Bit-Bang Mode (synchronous and asynchronous) WR# and RD# strobes are on these pins when the
main Channel mode is 245 FIFO, CPU FIFO interface, or Fast Opto-Isolated Serial Modes.
**Note 7 : The Bit-Bang Mode (synchronous and asynchronous) WR# and RD# strobes are on these pins when the
main Channel mode is 232 UART Mode.
**Note 8 : SI/WU is not available in these modes.
DS2232L Version 1.4
© Future Technology Devices International Ltd. 2005 Page 12 of 51
FT2232L Dual USB UART / FIFO I.C.
Channel B
Pin Deﬁnitions by Chip Mode **Note 2
Enhanced
Asynchronous
MPSSE
and
**Note 4
Synchronous
Bit-Bang Modes
Fast
OptoIsolated
Serial
Mode
Pin#
Generic
Pin
Name
232 UART 245 FIFO
Mode
Mode
40
BDBUS0
TXD
D0
D0
A8
FSDI
39
BDBUS1
RXD
D1
D1
A9
FSCLK
38
BDBUS2
RTS#
D2
D2
A10
FSDO
37
BDBUS3
CTS#
D3
D3
A11
FSCTS
36
BDBUS4
DTR#
D4
D4
A12
**Note 3
35
BDBUS5
DSR#
D5
D5
A13
33
BDBUS6
DCD#
D6
D6
A14
32
BDBUS7
RI#
D7
D7
A15
30
BCBUS0
TXDEN
RXF#
WR# **Note 9
CS#
29
BCBUS1
SLEEP#
TXE#
RD# **Note 9
ALE
28
BCBUS2
RXLED#
RD#
WR# **Note 7
RD#
27
BCBUS3
TXLED#
WR
RD# **Note 7
WR#
26
SI/WUB
SI/WUB
SI/WUB
SI/WUB
**Note 8
MCU
Host Bus
Emulation
Mode
**Note 5
**Note 8
SI/WUB
**Note 2 : 232 UART, 245 FIFO, CPU FIFO Interface, and Fast Opto-Isolated modes are enabled in the external
EEPROM. Enhanced Asynchronous and Synchronous Bit-Bang modes, MPSSE, and MCU Host Bus Emulation
modes are enabled using the driver command set bit mode. See Section 5.2 for details.
**Note 3 : Channel A can be conﬁgured in another IO mode if channel B is in Fast Opto-Isolated Serial Mode. If both
Channel A and Channel B are in Fast Opto-Isolated Serial Mode all of the IO will be on Channel B.
**Note 4 : MPSSE is Channel A only.
**Note 5 : MCU Host Bus Emulation requires both Channels.
**Note 6 : The Bit-Bang Mode (synchronous and asynchronous) WR# and RD# strobes are on these pins when the
main Channel mode is 245 FIFO, CPU FIFO interface, or Fast Opto-Isolated Serial Modes.
**Note 7 : The Bit-Bang Mode (synchronous and asynchronous) WR# and RD# strobes are on these pins when the
main Channel mode is 232 UART Mode.
**Note 8 : SI/WU is not available in these modes.
**Note 9 : The Bit-Bang Mode (synchronous and asynchronous) WR# and RD# strobes are on these pins when the
main Channel mode is 245 FIFO, CPU FIFO interface. Bit-Bang mode is not available on Channel B when Fast OptoIsolated Serial Mode is enabled.
DS2232L Version 1.4
© Future Technology Devices International Ltd. 2005 Page 13 of 51
FT2232L Dual USB UART / FIFO I.C.
5.3
IO Mode Command Hex Values
Enhanced Asynchronous and Synchronous Bit-Bang modes, MPSSE, and MCU Host Bus Emulation modes are
enabled using the D2XX driver command FT_SetBitMode. The hex values used with this command to enable these
modes are as followsMode
Value (hex)
Reset the IO bit Mode
0
Asynchronous Bit Bang Mode
1
MPSSE
2
Synchronous Bit bang Mode
4
MCU Host bus Emulation
8
Fast Opto-Isolated Serial Mode
10
See application note AN2232L-02 “Bit Mode Functions for the FT2232L” for more details and examples.
Note that all other device modes can be enabled in the external EEPROM, and do not require these values to be
conﬁgured.
In the case of Fast Opto-Isolated Serial mode sending a value of 10 will hold this device mode in reset, and sending a
value of 0 will release this mode from reset.
DS2232L Version 1.4
© Future Technology Devices International Ltd. 2005 Page 14 of 51
FT2232L Dual USB UART / FIFO I.C.
6.0
Package Outline
Figure 4 - 48 LD Lead Free LQFP Package Dimensions
9
7
PIN# 48
Pin# 1
FTDI
FT2232L
XXYY
0.22+/- 0.05
7 9
0.5
1.0
0.24 +/- 0.07
1.4 +/- 0.05
1.60
MAX
1o
+/- 1o
2
0.05 Min
0.15 Max
0.09 Min
0.16 Max
0.09 Min
0.2 Max
0.25
0.22 +/- 0.05
0.2 Min
0.6 +/- 0.15
The FT2232L is supplied in a 48 pin lead (Pb) free LQFP package. This package has a 7mm x 7mm body (9mm x
9mm including leads) with leads on a 0.5mm pitch. The FT2232L is fully compliant with the European Union RoHS
directive.
The above drawing shows the LQFP-48 package – all dimensions are in millimetres.
.
XXYY = Date Code ( XX = 2 digit week number, YY = 1 or 2 digit year number.
DS2232L Version 1.4
© Future Technology Devices International Ltd. 2005 Page 15 of 51
FT2232L Dual USB UART / FIFO I.C.
7.0
Absolute Maximum Ratings
These are the absolute maximum ratings for the FT2232L device in accordance with the Absolute Maximum Rating System
(IEC 60134). Exceeding these may cause permanent damage to the device.
•
•
•
•
•
•
•
•
•
•
•
Storage Temperature …………………………………………………….............................. –65oC to + 150oC
Floor Life (Out of Bag) at Factory Ambient (30oC/60% Relative Humidity)........................192 Hours **Note 10
(Level 3 Compliant)
Ambient Temperature (Power Applied)……………………….............................................. 0oC to + 70oC
VCC Supply Voltage ……………………………………………….................................….... -0.5V to +6.00V
DC Input Voltage - Inputs ………………………………………………................................. -0.5V to VCC + 0.5V
DC Input Voltage - High Impedance Bidirectionals …………………….............................. -0.5V to VCC + 0.5V
DC Output Current – Outputs ……………………………………………............................... 24mA
DC Output Current – Low Impedance Bidirectionals …………………................................ 24mA
Power Dissipation (VCC = 5.25V) .……………………………………...............................… 500mW
Electrostatic Discharge Voltage (Human Body Model) (I < 1μA) …………......................… +/- 3000V
Latch Up Current (Vi = +/- 10V maximum, for 10 ms) ……………………........................... +/-200mA
**Note 10 – If devices are stored out of the packaging beyond this time limit the devices should be baked before use.
The devices should be ramped up to a temperature of 110oC and baked for 8 to 10 hours.
DS2232L Version 1.4
© Future Technology Devices International Ltd. 2005 Page 16 of 51
FT2232L Dual USB UART / FIFO I.C.
7.1
D.C. Characteristics
DC Characteristics ( Ambient Temperature = 0 to 70oC )
Operating Voltage and Current
Parameter
Description
Min
Typ
Max
Units
Conditions
Vcc1
VCC Operating Supply Voltage
4.35
5.0
5.25
V
Vcc2
VCCIO Operating Supply Voltage
3.0
-
5.25
V
Icc1
Operating Supply Current
-
30
-
mA
Normal Operation
Icc2
Operating Supply Current
-
100
200
μA
USB Suspend **Note 11
**Note 11 – Supply current excludes the 200μA nominal drawn by the external pull-up resistor on USBDP.
IO Pin Characteristics ( VCCIO = 5.0V, Standard Drive Level ) **Note 12
Parameter
Description
Min
Typ
Max
Units
Conditions
Voh
Output Voltage High
3.2
4.1
4.9
V
I source = 2mA
Vol
Output Voltage Low
0.3
0.4
0.6
V
I sink = 2mA
Vin
Input Switching Threshold
1.3
1.6
1.9
V
VHys
Input Switching Hysteresis
50
55
60
mV
IO Pin Characteristics ( VCCIO = 3.0 - 3.6V, Standard Drive Level ) **Note 12
Parameter
Description
Min
Typ
Max
Units
Conditions
Voh
Output Voltage High
2.2
2.7
3.2
V
I source = 1 mA
Vol
Output Voltage Low
0.3
0.4
0.5
V
I sink = 2 mA
Vin
Input Switching Threshold
1.0
1.2
1.5
V
VHys
Input Switching Hysteresis
20
25
30
mV
IO Pin Characteristics ( VCCIO = 5.0V, High Drive Level ) **Note 12, **Note 13
Parameter
Description
Min
Typ
Max
Units
Voh
Output Voltage High
3.2
4.1
4.9
V
Conditions
I source = 6 mA
Vol
Output Voltage Low
0.3
0.4
0.6
V
I sink = 6 mA
Vin
Input Switching Threshold
1.3
1.6
1.9
V
VHys
Input Switching Hysteresis
50
55
60
mV
IO Pin Characteristics ( VCCIO = 3.0 - 3.6V, High Drive Level ) **Note 12, **Note 13
Parameter
Description
Min
Typ
Max
Units
Conditions
Voh
Output Voltage High
2.2
2.8
3.2
V
I source = 3mA
Vol
Output Voltage Low
0.3
0.4
0.6
V
I sink = 8 mA
Vin
Input Switching Threshold
1.0
1.2
1.5
V
VHys
Input Switching Hysteresis
20
25
30
mV
**Note 12 : Inputs have an internal 200K pull-up resistor to VCCIO, which can alternativly be programmed to pull
down using a conﬁguration bit in the external EEPROM.
**Note 12 : The high output drive level is conﬁgured in the external EEPROM. Each channel can be conﬁgured
individually.
DS2232L Version 1.4
© Future Technology Devices International Ltd. 2005 Page 17 of 51
FT2232L Dual USB UART / FIFO I.C.
XTIN / XTOUT Pin Characteristics
Parameter
Description
Min
Typ
Max
Units
Conditions
Voh
Output Voltage High
4.0
-
5.0
V
Fosc = 6MHz
Vol
Output Voltage Low
0.1
-
1.0
V
Fosc = 6MHz
Vin
Input Switching Threshold
1.8
2.5
3.2
V
RESET#, TEST, EECS, EESK, EEDATA Pin Characteristics **Note 14
Parameter
Description
Min
Typ
Max
Units
Conditions
Voh
Output Voltage High
3.2
4.1
4.9
V
I source = 2mA
Vol
Output Voltage Low
0.3
0.4
0.6
V
I sink = 2 mA
Vin
Input Switching Threshold
1.3
1.6
1.9
V
VHys
Input Switching Hysteresis
50
55
60
mV
**Note 14 – EECS, EESK, EEDATA and RESET# pins have an internal 200K pull-up resistor to VCC
RSTOUT# Pin Characteristics
Parameter
Description
Min
Typ
Max
Units
Conditions
Voh
Output Voltage High
3.0
-
3.6
V
I source = 2mA
Vol
Output Voltage Low
0.3
-
0.6
V
I sink = 2mA
USB IO Pin Characteristics **Note 15
Parameter
Description
Min
Typ
Max
Units
Conditions
UVoh
IO Pins Static Output ( High)
2.8
-
3.6
V
RI = 1.5K to 3V3Out ( D+ )
RI = 15K to GND ( D- )
UVol
IO Pins Static Output ( Low )
0
-
0.3
V
RI = 1.5K to 3V3Out ( D+ )
RI = 15K to GND ( D- )
UVse
Single Ended Rx Threshold
0.8
2.0
V
UCom
Differential Common Mode
0.8
2.5
V
UVDif
Differential Input Sensitivity
0.2
-
V
UDrvZ
Driver Output Impedance
29
-
44
Ohm
**Note 15 – Driver Output Impedance includes the external 27R series resistors on USBDP and USBDM pins.
DS2232L Version 1.4
© Future Technology Devices International Ltd. 2005 Page 18 of 51
8.0
Standard Device Conﬁguration Examples
8.1
Oscillator Conﬁgurations
FT2232L Dual USB UART / FIFO I.C.
FT2232C
FT2232L
43
3-Pin Resonator
6MHz
FT2232C
FT2232L
27pF
43
XTIN
XTIN
2 - Pin Resonator
or Crystal
6MHz
1M
27pF
44
XTOUT
Figure 5
3-Pin Ceramic Resonator Conﬁguration
44
XTOUT
Figure 6
Crystal or 2-Pin Ceramic Resonator
Conﬁguration
Figure 5 illustrates how to use the FT2232L with a 3-Pin Ceramic Resonator. A suitable part would be a ceramic
resonator from Murata’s CERALOCK range. (Murata Part Number CSTCR6M00G15), or equivalent. 3-Pin ceramic
resonators have the load capacitors built into the resonator so no external loading capacitors are required. This makes
for an economical conﬁguration. The accuracy of this Murata ceramic resonator is +/- 0.25% and it is speciﬁcally
designed for USB full speed applications. A 1 MegaOhm loading resistor across XTIN and XTOUT is recommended in
order to guarantee this level of accuracy.
Other ceramic resonators with a lesser degree of accuracy (typically +/- 0.5%) are technically out-with the USB
speciﬁcation, but it has been calculated that using such a device will work satisfactorily in practice with a FT2232L
design. An example of such a device is Murata’s CSTLSM00G53.
Figure 6 illustrates how to use the FT2232L with a 6MHz Crystal or 2-Pin Ceramic Resonator. In this case, these
devices do not have in-built loading capacitors so these have to be added between XTIN, XTOUT and GND as
shown. A value of 27pF is shown as the capacitor in the example – this will be good for many crystals and some
resonators but do select the value based on the manufacturers recommendations wherever possible. If using a crystal,
use a parallel cut type. If using a resonator, see the previous note on frequency accuracy.
It is also possible to use a 6 MHz Oscillator with the FT2232L. In this case the output of the oscillator would be
connected to XTIN, and XTOUT should be left unconnected. The oscillator must have a CMOS output.
DS2232L Version 1.4
© Future Technology Devices International Ltd. 2005 Page 19 of 51
8.2
FT2232L Dual USB UART / FIFO I.C.
EEPROM Conﬁguration
Figure 7 illustrates how to connect the FT2232L to the 93C46
(93C56 or 93C66) EEPROM. EECS (pin 48) is directly
connected to the chip select (CS) pin of the EEPROM. EESK
(pin 1) is directly connected to the clock (SK) pin of the
EEPROM. EEDATA (pin 2) is directly connected to the Data
In (Din) pin of the EEPROM. There is a potential condition
whereby both the Data Output (Dout) of the EEPROM can drive
out at the same time as the EEDATA pin of the FT2232L. To
prevent potential data clash in this situation, the Dout of the
EEPROM is connected to EEDATA of the FT2232L via a 2.2K
resistor.
FT2232C
FT2232L
48
EECS
1
EESK
2
EEDATA
VCC
EEPROM - 93C46 / 56 / 66
1
2
2.2K
3
4
CS
VCC
SK
NC
DIN
NC
DOUT
GND
8
7
6
5
Following a power-on reset or a USB reset, the FT2232L will
scan the EEPROM to ﬁnd out (a) if an EEPROM is attached to
the Device and (b) if the data in the device is valid. If both of
these are the case, then the FT2232L will use the data in the
EEPROM, otherwise it will use its built-in default values and
conﬁguration. The default port conﬁguration of the FT2232L
puts both Channel A and Channel B into serial UART mode.
When a valid command is issued to the EEPROM from the
FT2232L, the EEPROM will acknowledge the command by
VCC
10K
pulling its Dout pin low. In order to check for this condition,
it is necessary to pull Dout high using a 10K resistor. If the
Figure 7
command acknowledge doesn’t happen then EEDATA will be
EEPROM Conﬁguration
pulled high by the 10K resistor during this part of the cycle
and the device will detect an invalid command or no EEPROM
present.
There are two varieties of 93C46/56/66 EEPROM’s on the market – one is conﬁgured as being 16 bits wide, the other
is conﬁgured as being 8 bits wide. These are available from many sources such as Microchip, STMicro, ISSI etc. The
FT2232L requires EEPROM’s with a 16-bit wide conﬁguration such as the Microchip 93LC46B device. The EEPROM
must be capable of reading data at a 1Mb clock rate at a supply voltage of 4.35V to 5.25V. Most available parts are
capable of this. Check the manufacturers data sheet to ﬁnd out how to connect pins 6 and 7 of the EEPROM. Some
devices specify these as no-connect, others use them for selecting 8 / 16 bit mode or for test functions. Some other
parts have their pinout rotated by 90o so please select the required part and its options carefully.
It is possible to “share” the EEPROM between the FT2232L and another external device such as an MCU. However,
this can only be done when the FT2232L is in its reset condition as it tri-states its EEPROM interface at that time. A
typical conﬁguration would use four bits of an MCU IO Port. One bit would be used to hold the FT2232L reset (using
RESET#) on power-up, the other three would connect to the EECS, EESK and EEDATA pins of the FT2232L in
order to read / write data to the EEPROM at this time. Once the MCU has read / written the EEPROM, it would take
RESET# high to allow the FT2232L to conﬁgure itself and enumerate over USB.
The external EEPROM can be programmed over USB using utility software provided by FTDI. The external EEPROM
is used to enable 245 FIFO, and Fast Opto-Isolated Serial interface modes on each channel.
DS2232L Version 1.4
© Future Technology Devices International Ltd. 2005 Page 20 of 51
FT2232L Dual USB UART / FIFO I.C.
8.3
USB Bus Powered and Self Powered Conﬁguration
Figure 8 - USB Bus Powered Conﬁguration
USB "B"
Connector
Ferrite Bead
470R
VCC
1
2
3
27R
3
V
C
C
27R
4
5
6
10nF
33nF
8
7
14 31
42
V
C
C
3v3OUT
43
A
V
C
C
V
C
C
I
O
A
USB DM
USB DP
1.5K
5
V
C
C
I
O
A
0.1uF
46
FT2232L
FT2232C
RSTOUT#
XTIN
6MHz
44 XTOUT
VCC
27pF
27pF
10K
VCC
+
0.1uF
0.1uF
10uF
Decoupling Capacitors
4
RESET#
48
EECS
1
EESK
2
EEDATA
47
TEST
A
G
N
D
45
G
N
D
G
N
D
9
G
N
D
18 25
G
N
D
34
Figure 8 illustrates the FT2232L in a typical USB bus powered conﬁguration. A USB Bus Powered device gets its
power from the USB bus. Basic rules for USB Bus power devices are as follows –
a) On plug-in, the device must draw no more than 100mA
b) On USB Suspend the device must draw no more than 500μA.
c) A High Power USB Bus Powered Device (one that draws more than 100mA) should use the PWREN# pin to keep
the current below 100mA on plug-in and 500μA on USB suspend.
d) A device that consumes more than 100mA can not be plugged into a USB Bus Powered Hub
e) No device can draw more that 500mA from the USB Bus.
The power descriptor in the EEPROM should be programmed to match the current draw required by the device.
A Ferrite Bead is connected in series with USB power to prevent noise from the device and associated circuitry (EMI)
being radiated down the USB cable to the Host. The value of the Ferrite Bead depends on the total current required
by the circuit – a suitable range of Ferrite Beads is available from Steward (www.steward.com) for example Steward
Part # MI0805K400R-00 also available from DigiKey, Part # 240-1035-1.
DS2232L Version 1.4
© Future Technology Devices International Ltd. 2005 Page 21 of 51
FT2232L Dual USB UART / FIFO I.C.
Figure 9 - USB Self Powered Conﬁguration
USB "B"
Connector
470R
VCC
1
2
3
4
27R
3
27R
6
33nF
V
C
C
3v3OUT
V
C
C
I
O
A
0.1uF
46
14 31
42
V
C
C
V
C
C
I
O
B
A
V
C
C
4.7K
8
7
10K
USB DP
FT2232L
FT2232C
1.5K
5
VCC
4
47
+
0.1uF
USB DM
0.1uF
10uF
RSTOUT#
RESET#
A
TEST G
N
D
45
G
N
D
G
N
D
G
N
D
G
N
D
9 18 25 34
Decoupling Capacitors
Figure 9 illustrates the FT2232L in a typical USB self powered conﬁguration. A USB Self Powered device gets its
power from its own POWER SUPPLY and does not draw current from the USB bus. The basic rules for USB Self
power devices are as follows –
a) A Self-Powered device should not force current down the USB bus when the USB Host or Hub Controller is
powered down.
b) A Self Powered Device can take as much current as it likes during normal operation and USB suspend as it has its
own POWER SUPPLY.
c) A Self Powered Device can be used with any USB Host and both Bus and Self Powered USB Hubs.
The USB power descriptor option in the EEPROM should be programmed to a value of zero (self powered).
To meet requirement a) the 1.5K pull-up resistor on USBDP is connected to RSTOUT# as per the bus-power circuit.
However, the USB Bus Power is used to control the RESET# Pin of the FT2232L device. When the USB Host or
Hub is powered up RSTOUT# will pull the 1.5K resistor on USBDP to 3.3V, thus identifying the device as a full speed
device to USB. When the USB Host or Hub power is off, RESET# will go low and the device will be held in reset. As
RESET# is low, RSTOUT# will also be low, so no current will be forced down USBDP via the 1.5K pull-up resistor
when the host or hub is powered down. Failure to do this may cause some USB host or hub controllers to power up
erratically.
Note : When the FT2232L is in reset, the I/O interface pins all go tri-state. These pins have internal 200K pull-up
resistors to VCCIO, so they will gently pull high unless driven by some external logic.
DS2232L Version 1.4
© Future Technology Devices International Ltd. 2005 Page 22 of 51
FT2232L Dual USB UART / FIFO I.C.
8.4 Interfacing to 3.3V Logic
Figure 10 - Bus Powered Circuit with 3.3V logic drive and IO supply voltage
3.3V LDO
Regulator
In
3.3V Power to
External Logic
VCC3V3
Out
Gnd
0.1uF
Ferrite Bead
1
2
USB "B"
Connector
470R
VCC
27R
3
4
V
C
C
27R
33nF
10nF
6
8
7
VCC
V
C
C
Decoupling
Capacitors
V
C
C
I
O
B
0.1uF
A
V
C
C
USB DM
SI/WUA
USB DP
VCC3V3
10
VCC3V3
5
10uF
46
FT2232L
FT2232C
+
0.1uF
V
C
C
I
O
A
3v3OUT
1.5K
0.1uF
14 31
42
3
VCC
RSTOUT#
4 RESET#
47
TEST
SI/WUB
A
G
N
D
45
G
N
D
G
N
D
9
G
N
D
G
N
D
18 25
34
26
Figure 10 shows how to conﬁgure the FT2232L to interface with a 3.3V logic devices. In this example, a discrete 3.3V
regulator is used to supply the 3.3V logic from the USB supply. VCCIOA and VCCIOB are connected to the output of
the 3.3V regulator, which in turn will cause the device interface IO pins on both channels to drive out at 3.3V level. It is
also possible to have one IO interface channel driving out at 5V level, and the other at 3.3V level. In this case one of
the VCCIO pins would be connected to 5V, and the other connected to 3.3V.
For USB bus powered circuits some considerations have to be taken into account when selecting the regulator –
a) The regulator must be capable of sustaining its output voltage with an input voltage of 4.35 volts. A Low Drop Out
(LDO) regulator must be selected.
b) The quiescent current of the regulator must be low in order to meet the USB suspend total current requirement of
<= 500μA during USB suspend.
An example of a regulator family that meets these requirements is the MicroChip (Telcom) TC55 Series. These
devices can supply up to 250mA current and have a quiescent current of under 1μA.
DS2232L Version 1.4
© Future Technology Devices International Ltd. 2005 Page 23 of 51
FT2232L Dual USB UART / FIFO I.C.
In some cases, where only a small amount of current is required (< 5mA) , it may be possible to use the in-built
regulator of the FT2232L to supply the 3.3V without any other components being required. In this case, connect
VCCIOA or VCCIOB to the 3V3OUT pin of the FT2232L.
Note : It should be emphasised that the 3.3V supply for VCCIO in a bus powered design with a 3.3V logic interface
should come from an LDO which is supplied by the USB bus, or from the 3V3OUT pin of the FT232BM, and not from
any other source. Please also note that if the SI/WU pins are not being used they should be pulled up to the same
supply as their respective VCCIO pin.
Figure 11 - Self Powered Circuit with 3.3V logic drive and IO supply voltage
VCC3V3
USB "B"
Connector
470R
1
27R
2
3
4
0.1uF
3
46
27R
6
33nF
VCC5V
V
C
C
A
V
C
C
3v3OUT
14 31
42
V V V
C C C
C C C
I I
O O
A B
VCC3V3
SI/WUA 10
4.7K
8
7
10K
USB DM
USB DP
FT2232L
FT2232C
1.5K
5
VCC5V
4
+
0.1uF
0.1uF
10uF
Decoupling Capacitors
VCC3V3
RSTOUT#
RESET#
TEST
SI/WUB 26
A
G
N
D
45
G
N
D
G
N
D
G
N
D
9 18 25
G
N
D
34
Figure 11 is an example of a FT2232L USB self powered design with 3.3V interface. In this case the VCCIOA and
VCCIOB pins are supplied by an external 3.3V supply in order to make both of the device’s IO channels drive out at
3.3V logic level, thus allowing them to be connected to a 3.3V MCU or other external logic. It is also possible to have
one IO interface channel driving out at 5V level, and the other at 3.3V level. In this case one of the VCCIO pins would
be connected to 5V, and the other connected to 3.3V.
DS2232L Version 1.4
© Future Technology Devices International Ltd. 2005 Page 24 of 51
FT2232L Dual USB UART / FIFO I.C.
A USB self powered design uses its own power supplies, and does not draw any of its power from the USB bus. In
such cases, no special care need be taken to meet the USB suspend current (0.5 mA) as the device does not get its
power from the USB port.
As with bus powered 3.3V interface designs, in some cases, where only a small amount of current is required (<5mA),
it may be possible to use the in-built regulator of the FT2232L to supply the 3.3V without any other components being
required. In this case, connect VCCIOA or VCCIOB to the 3V3OUT pin of the FT2232L.
Note that if the SI/WU pins are not being used they should be pulled up to the same supply as their respective VCCIO
pin.
DS2232L Version 1.4
© Future Technology Devices International Ltd. 2005 Page 25 of 51
FT2232L Dual USB UART / FIFO I.C.
8.5 Power Switching
Figure 12 - Bus Powered Circuit with Power Control
P-Channel Power
MOSFET
s
Switched 5V Power to
External Logic
d
0.1uF
0.1uF
Soft Start
1K Circuit
g
USB "B"
Connector
Ferrite Bead
1
2
27R
3
4
27R
470R
VCC
10nF
33nF
3 42 14 31
V
V
V V
C
C C C
C
C C C
I I
6 3V3OUT
O O
A B
0.1uF
46
A
V
C
C
FT2232C
FT2232L
8 USB DM
VCC
7
+
0.1uF
0.1uF
USB DP
PWREN#
41
1.5K
10uF
Decoupling Capacitors
5
RSTOUT#
VCC
4 RESET#
USB Bus powered circuits need to be able to power down in USB suspend mode in order to meet the <= 500μA total
suspend current requirement (including external logic). Some external logic can power itself down into a low current
state by monitoring the PWREN# pin. For external logic that cannot power itself down in that way, the FT2232L
provides a simple but effective way of turning off power to external circuitry during USB suspend.
Figure 12 shows how to use a discrete P-Channel Logic Level MOSFET to control the power to external logic circuits.
A suitable device would be an International Rectiﬁer (www.irf.com) IRLML6402, or equivalent. It is recommended that
a “soft start” circuit consisting of a 1K series resistor and a 0.1 μF capacitor are used to limit the current surge when
the MOSFET turns on. Without the soft start circuit there is a danger that the transient power surge of the MOSFET
turning on will reset the FT2232L, or the USB host / hub controller. The values used here allow attached circuitry to
power up with a slew rate of ~12.5 V per millisecond, in other words the output voltage will transition from GND to 5V
in approximately 400 microseconds.
DS2232L Version 1.4
© Future Technology Devices International Ltd. 2005 Page 26 of 51
FT2232L Dual USB UART / FIFO I.C.
Alternatively, a dedicated power switch I.C. with inbuilt “soft-start” can be used instead of a MOSFET. A suitable
power switch I.C. for such an application would be a Micrel (www.micrel.com) MIC2025-2BM or equivalent.
Please note the following points in connection with power controlled designs –
a) The logic to be controlled must have its own reset circuitry so that it will automatically reset itself when power is reapplied on coming out of suspend.
b) Set the Pull-down on Suspend option in the FT2232L’s EEPROM.
c) For USB high-power bus powered device (one that consumes greater than 100 mA, and up to 500 mA of current
from the USB bus), the power consumption of the device should be set in the max power ﬁeld in the EEPROM.
A high-power bus powered device must use this descriptor in the EEPROM to inform the system of its power
requirements.
d) For 3.3V power controlled circuits the VCCIO pins must not be powered down with the external circuitry. Either
connect the power switch between the output of the 3.3V regulator and the external 3.3V logic, or if appropriate
power the VCCIO pin from the 3V3OUT pin of the FT2232L.
Figure 13 - Bus Powered Circuit with Power Control and 3.3V Logic Drive / IO Supply
Voltage
3.3V LDO
Regulator
IN
OUT
GND
VCC3V3
s
d
0.1uF
0.1uF
0.1uF
Soft Start
1K Circuit
g
USB "B"
Connector
Ferrite
Bead
1
Switched 3.3V Power
to External Logic
P-Channel Power
MOSFET
470R
VCC5V
27R
2
3
27R
4
10nF
33nF
3 42 14 31
V
V
V V
C
C C C
C
C C C
I I
6 3V3OUT
O O
A B
FT2232L
FT2232
8 USB DM
VCC5V
0.1uF
46
A
V
C
C
SI/WUA
VCC3V3
10
VCC3V3
7 USB DP
+
0.1uF
0.1uF
SI/WUB
1.5K
10uF
5
Decoupling Capacitors
26
RSTOUT#
VCC5V
4 RESET#
PWREN#
41
Figure 13 is a FT2232L design example which effectively combines the circuits shown in Figures 13 and 14 to give a
USB bus powered design with power switching and 3.3V logic drive level on both channels. Once again a P-Channel
Power MOSFET and soft start circuit are used to control the power to external logic devices. A 3.3V LDO regulator
which is supplied by the USB bus is used to provide the 3.3V supply for the VCCIO pins, as well as the external logic.
If the SI/WU pins are not being used they should be pulled up to 3.3V.
DS2232L Version 1.4
© Future Technology Devices International Ltd. 2005 Page 27 of 51
FT2232L Dual USB UART / FIFO I.C.
9.0 Signal Descriptions By IO Mode and Interface Channel Conﬁgurations
9.1
232 UART Interface Mode Signal Descriptions and Interface Conﬁgurations
When either Channel A or Channel B are in 232 UART mode the IO signal lines are conﬁgured as follows:Pin#
Signal
Type
Description
Channel A
Channel B
24
40
TXD
OUTPUT Transmit Asynchronous Data Output
23
39
RXD
INPUT
22
38
RTS#
OUTPUT Request To Send Control Output / Handshake signal
21
37
CTS#
INPUT
20
36
DTR#
OUTPUT Data Terminal Ready Control Output / Handshake signal
19
35
DSR#
INPUT
Data Set Ready Control Input / Handshake signal **Note 16
17
33
DCD#
INPUT
Data Carrier Detect Control Input **Note 16
16
32
RI#
INPUT
Ring Indicator Control Input. When the Remote Wake up option
is enabled in the EEPROM, taking RI# low can be used to
resume the PC USB Host controller from suspend. **Note 16
15
30
TXDEN
OUTPUT Enable Transmit Data for RS485
13
29
SLEEP# OUTPUT Goes low during USB Suspend Mode. Typically used to powerdown an external TTL to RS232 level converter I.C. in USB to
RS232 converter designs.
12
28
RXLED# O.C.
LED Drive - Pulses Low when Transmitting Data via USB.
11
27
TXLED# O.C
LED Drive - Pulses Low when Receiving Data via USB.
10
26
SI/WU
The Send Immediate / WakeUp signal combines two functions
on a single pin. If USB is in suspend mode (PWREN# = 1) and
remote wakeup is enabled in the EEPROM , strobing this pin
low will cause the device to request a resume on the USB Bus.
Normally, this can be used to wake up the Host PC.
During normal operation (PWREN# = 0), if this pin is strobed low
any data in the device TX buffer will be sent out over USB on the
next Bulk-IN request from the drivers regardless of the pending
packet size. This can be used to optimise USB transfer speed for
some applications. Tie this pin to VCCIO if not used.
INPUT
Receive Asynchronous Data Input **Note 16
Clear To Send Control Input / Handshake signal **Note 16
**Note 16 : These pins are pulled to up VCCIO via internal 200K resistors during Reset and USB Suspend mode.
These can be programmed to gently pull low during USB suspend ( PWREN# = “1” ) by setting this option in the
EEPROM.
DS2232L Version 1.4
© Future Technology Devices International Ltd. 2005 Page 28 of 51
FT2232L Dual USB UART / FIFO I.C.
Figure 14 - USB <=> Dual Port RS232 Converter Conﬁguration
Figure 14 illustrates how to connect the
FT2232L, when both channels A and B are
conﬁgured as 232-style UART interfaces, to
two TTL – RS232 Level Converter I.C.’s to
make a USB <=> Dual Port RS232 converter
using the popular “213” series of TTL to
RS232 level converters. These devices
have 4 transmitters and 5 receivers in a 28LD SSOP package and feature an in-built
voltage converter to convert the 5V (nominal)
VCC to the +/- 9 volts required by RS232.
An important feature of these devices is
the SHDN# pin which can power down the
device to a low quiescent current during USB
suspend mode.
The device used in the example above
is a Sipex SP213EHCA which is capable
of RS232 communication at up to 500K
baud. If a lower baud rate is acceptable,
then several pin compatible alternatives
are available such as the Sipex SP213ECA
, the Maxim MAX213CAI and the Analog
Devices ADM213E, which are all good for
communication at up to 115,200 baud. If a
higher baud rate is desired, use a Maxim
MAX3245CAI part which is capable of RS232
communication at rates of up to 1M baud.
The MAX3245 is not pin compatible with
the 213 series devices, also its SHDN pin is
active high, so connect it to PWREN# instead
of SLEEP#. Dual RS232 level converters
such as the Maxim MAX3187 may also be a
suitable alternative.
DS2232L Version 1.4
© Future Technology Devices International Ltd. 2005 Page 29 of 51
FT2232L Dual USB UART / FIFO I.C.
Figure 15 - USB <=> RS422 Converter Conﬁguration
FT2232C
FT2232L
PWREN#
SLEEP# (ACBUS1)
TXD (ADBUS0)
RXD (ADBUS1)
RTS# (ADBUS2)
CTS# (ADBUS3)
DTR# (ADBUS4)
DSR# (ADBUS5)
DCD# (ADBUS6)
RI# (ADBUS7)
TXDEN (ACBUS0)
VCC
14 SP491
41
4
13
5
24
23
10
D
R
6
12
21
RXDM_A
VCC
14 SP491
20
4
19
5
RTS# (BDBUS2)
CTS# (BDBUS3)
DTR# (BDBUS4)
DSR# (BDBUS5)
DCD# (BDBUS6)
RI# (BDBUS7)
TXDEN (BCBUS0)
GND
10
D
RTSM_A
9
RTSP_A
CTSP_A
3
11
2
R
16
6
15
12
120R
CTSM_A
7
29
DB9-M
RS422 Channel B
10
5
RXD (BDBUS1)
120R
7
4
TXD (BDBUS0)
TXDP_A
RXDP_A
11
2
VCC
14 SP491
SLEEP# (BCBUS1)
TXDM_A
9
3
22
17
DB9-M
RS422 Channel A
D
40
TXDM_B
9
TXDP_B
RXDP_B
3
39
11
2
R
12
120R
38
6
RXDM_B
7
37
36
VCC
14 SP491
4
35
10
5
33
32
30
GND
D
RTSM_B
9
RTSP_B
CTSP_B
3
11
2
R
6
7
12
120R
CTSM_B
Figure 15 illustrates how to connect the UART interfaces of the FT2232L to two TTL – RS422 Level Converter I.C.’s
to make a USB to dual port RS422 converter. There are many such level converter devices available – this example
uses two Sipex SP491 devices which have enables on both their transmitters and receivers. Because the transmitter
enables are active high, they are connected to the SLEEP# pins. The receiver enables are active low and are both
connected to the PWREN# pin. This ensures that both the transmitters and receivers are enabled when the device
is active, and disabled when the device is in USB suspend mode. If the design is USB BUS powered, it may be
necessary to use a P-Channel logic level MOSFET (controlled by PWREN#) in the VCC line of the SP491 devices to
ensure that the USB standby current of 500μA is met.
The SP491 is good for sending and receiving data at a rate of up to 5M Baud – in this case the maximum rate is
limited to 3M Baud by the FT2232L.
DS2232L Version 1.4
© Future Technology Devices International Ltd. 2005 Page 30 of 51
FT2232L Dual USB UART / FIFO I.C.
Figure 16 - USB <=> RS485 Converter Conﬁguration
FT2232C
FT2232L
PWREN#
SLEEP# (ACBUS1)
41
13
3
24
4
23
2
8
VCC
SP481
7
TXD (ADBUS0)
RXD (ADBUS1)
RTS# (ADBUS2)
CTS# (ADBUS3)
DTR# (ADBUS4)
DSR# (ADBUS5)
DCD# (ADBUS6)
RI# (ADBUS7)
TXDEN (ACBUS0)
SLEEP# (BCBUS1)
22
D
6
1
R
21
RXD (BDBUS1)
RTS# (BDBUS2)
CTS# (BDBUS3)
DTR# (BDBUS4)
DSR# (BDBUS5)
DCD# (BDBUS6)
RI# (BDBUS7)
TXDEN (BCBUS0)
DM_A
DPA
GND
5
120R
20
LINK
19
17
16
15
29
3
40
4
39
2
8
VCC
SP481
7
TXD (BDBUS0)
DB9-M
RS485 Channel A
38
37
1
D
6
R
DB9-M
RS485 Channel B
DM_B
DP_B
GND
5
120R
36
35
LINK
33
32
30
Figure 16 illustrates how to connect the UART interfaces of the FT2232L to two TTL – RS485 Level Converter I.C.’s
to make a USB to dual port RS485 converter. This example uses two Sipex SP491 devices but there are similar parts
available from Maxim and Analog Devices amongst others. The SP491 is a RS485 device in a compact 8 pin SOP
package. It has separate enables on both the transmitter and receiver. With RS485, the transmitter is only enabled
when a character is being transmitted from the UART. The TXDEN pins on the FT2232L are provided for exactly that
purpose, and so the transmitter enables are wired to the TXDEN’s. The receiver enable is active low, so it is wired to
the PWREN# pin to disable the receiver when in USB suspend mode.
RS485 is a multi-drop network – i.e. many devices can communicate with each other over a single two wire cable
connection. The RS485 cable requires to be terminated at each end of the cable. Links are provided to allow the cable
to be terminated if the device is physically positioned at either end of the cable.
In this example the data transmitted by the FT2232L is also received by the device that is transmitting. This is a
common feature of RS485 and requires the application software to remove the transmitted data from the received
data stream. With the FT2232L it is possible to do this entirely in hardware – simply modify the schematic so that RXD
of the FT2232L is the logical OR of the SP481 receiver output with TXDEN using an HC32 or similar logic gate.
DS2232L Version 1.4
© Future Technology Devices International Ltd. 2005 Page 31 of 51
FT2232L Dual USB UART / FIFO I.C.
9.2 232 UART Mode LED Interface
VCCIO
VCCIO
FT2232C
TX
RX
LED
220R
220R
220R
FT2232L
FT2232C
FT2232L
TXLED#
TXLED#
RXLED#
RXLED#
Figure 17
Dual LED Conﬁguration
Figure 18
Single LED Conﬁguration
When conﬁgured in UART mode the FT2232L has two IO pins on each channel dedicated to controlling LED
status indicators, one for transmitted data the other for received data. When data is being transmitted / received
the respective pins drive from tri-state to low in order to provide indication on the LED’s of data transfer. A digital
one-shot timer is used so that even a small percentage of data transfer is visible to the end user. Figure 17 shows
a conﬁguration using two individual LED’s – one for transmitted data the other for received data. In Figure 18, the
transmit and receive LED indicators are wire-OR’ed together to give a single LED indicator which indicates any
transmit or receive data activity.
Another possibility (not shown here) is to use a 3 pin common anode tri-color LED based on the circuit in Figure 18 to
have a single LED that can display activity in a variety of colors depending on the ratio of transmit activity compared to
receive activity.
Note that the LED’s are connected to the same supply as VCCIO.
DS2232L Version 1.4
© Future Technology Devices International Ltd. 2005 Page 32 of 51
FT2232L Dual USB UART / FIFO I.C.
9.3
245 FIFO Interface Mode Signal Descriptions and Conﬁguration
When either Channel A or Channel B are in 245 FIFO mode the IO signal lines are conﬁgured as follows.
FIFO DATA BUS GROUP **Note 17
Pin#
Signal
Type
Description
Channel A
Channel B
24
40
D0
I/O
FIFO Data Bus Bit 0
23
39
D1
I/O
FIFO Data Bus Bit 1
22
38
D2
I/O
FIFO Data Bus Bit 2
21
37
D3
I/O
FIFO Data Bus Bit 3
20
36
D4
I/O
FIFO Data Bus Bit 4
19
35
D5
I/O
FIFO Data Bus Bit 5
17
33
D6
I/O
FIFO Data Bus Bit 6
16
32
D7
I/O
FIFO Data Bus Bit 7
Signal
Type
Description
FIFO CONTROL INTERFACE GROUP
Pin#
Channel A
Channel B
15
30
RXF#
OUTPUT When high, do not read data from the FIFO. When low, there is
data available in the FIFO which can be read by strobing RD#
low then high again ** Note 18
13
29
TXE#
OUTPUT When high, do not write data into the FIFO. When low, data can
be written into the FIFO by strobing WR high then low. ** Note 18
12
28
RD#
INPUT
Enables Current FIFO Data Byte on D0..D7 when low. Fetches
the next FIFO Data Byte (if available) from the Receive FIFO
Buffer when RD# goes from low to high. ** Note 17
11
27
WR
INPUT
Writes the Data Byte on the D0..D7 into the Transmit FIFO Buffer
when WR goes from high to low. ** Note 17
10
26
SI/WU
INPUT
The Send Immediate / WakeUp signal combines two functions
on a single pin. If USB is in suspend mode (PWREN# = 1) and
remote wakeup is enabled in the EEPROM , strobing this pin
low will cause the device to request a resume on the USB Bus.
Normally, this can be used to wake up the Host PC.
During normal operation (PWREN# = 0), if this pin is strobed low
any data in the device TX buffer will be sent out over USB on the
next Bulk-IN request from the drivers regardless of the pending
packet size. This can be used to optimise USB transfer speed for
some applications. Tie this pin to VCCIO if not used.
**Note 17 : In Input Mode, these pins are pulled to VCCIO via internal 200K resistors. These can be programmed to
gently pull low during USB suspend ( PWREN# = “1” ) by setting this option in the EEPROM.
**Note 18 : During device reset, these pins are tri-state but pulled up to VCCIO via internal 200K resistors.
DS2232L Version 1.4
© Future Technology Devices International Ltd. 2005 Page 33 of 51
245 FIFO Mode TIMING DIAGRAMS
Figure 19 - FIFO READ Cycle
FT2232L Dual USB UART / FIFO I.C.
T6
T5
RXF#
T2
T1
RD#
T4
T3
D[7...0]
Valid Data
Time
Description
Min
Max
T1
RD# Active Pulse Width
50
ns
T2
RD# to RD Pre-Charge Time
50 + T6
ns
T3
RD# Active to Valid Data **Note 19
20
T4
Valid Data Hold Time from RD# Inactive **Note 19
0
T5
RD# Inactive to RXF#
0
T6
RXF# inactive after RD# cycle
80
50
Unit
ns
ns
25
ns
ns
** Note 19 : Load 30 pF at standard drive level. These times will also vary if the high output drive level is enabled.
Figure 20 - FIFO Write Cycle
T12
T11
TXE#
T8
T7
WR
T9
D[7...0]
T10
Valid Data
Time
Description
Min
T7
WR Active Pulse Width
50
ns
T8
WR to WR Pre-Charge Time
50
ns
T9
Data Setup Time before WR inactive
20
ns
T10
Data Hold Time from WR inactive
0
ns
T11
WR Inactive to TXE#
5
T12
TXE inactive after WR cycle
80
DS2232L Version 1.4
Max
25
Unit
ns
ns
© Future Technology Devices International Ltd. 2005 Page 34 of 51
FT2232L Dual USB UART / FIFO I.C.
Figure 21 - Microprocessor Interface Example
FT2232C
FT2232L
IO10
D1
IO11
D2
IO12
D3
IO13
D4
IO14
D5
IO15
D6
IO16
D7
IO17
RD#
IO20
WR
IO21
TXE#
IO22
RXF#
IO23
SI / WU
PWREN#
( Optional )
41
( Optional )
IO Port 1
D0
IO Port 2
Channel A
or B
Microcontroller
IO24
IO25
Figure 21 illustrates a typical interface between one of the channels of the FT2232L, conﬁgured in 245-style FIFO
interface mode, and a MicroController (MCU). Either channel A or B, or both can be conﬁgured in this mode. This
examples uses two IO Ports of the MCU, one port (8 bits) to transfer data to one of the and the other port (4 / 5
bits) to monitor the TXE# and RXF# status bits and generate the RD# and WR strobes to the FT2232L as required.
Optionally, SI / WU can be connected to another IO pin if either of the functions of this pin are required. If the SI / WU
function is not required, tie this pin to VCCIO. If the MCU is handling power management functions, then PWREN#
should also be connected to an IO pin of the MCU.
The 8 data bits on IO Port 1 can be shared with other peripherals when the MCU is not accessing the FT2232L.
DS2232L Version 1.4
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FT2232L Dual USB UART / FIFO I.C.
9.5 Enhanced Asynchronous and Synchronous Bit-Bang Modes - Signal Description and
Interface Conﬁguration
Bit-bang mode is a special FT2232L device mode that changes the 8 IO lines on either (or both) channels into an 8
bit bi-directional data bus. The are two types of bit bang mode for the FT2232L - Enhanced Asynchronous Bit-Bang
Mode, which is virtually the same as FTDI BM chip-style Bit-Bang mode, with the addition of Read and Write strobes;
and Synchronous Bit-Bang mode, where data is only read from the device when the device is written to. Bit-Bang
mode is enabled by driver command. When either Channel A or Channel B (or both) have Enhanced Asynchronous
Bit-Bang mode, or Synchronous Bit-Bang mode enabled the IO signal lines are conﬁgured as follows :BIT-BANG DATA BUS GROUP **Note 24
Pin#
Signal
Type
Description
Channel A
Channel B
24
40
D0
I or O
Bit-Bang Data Bus Bit 0
23
39
D1
I or O
Bit-Bang Data Bus Bit 1
22
38
D2
I or O
Bit-Bang Data Bus Bit 2
21
37
D3
I or O
Bit-Bang Data Bus Bit 3
20
36
D4
I or O
Bit-Bang Data Bus Bit 4
19
35
D5
I or O
Bit-Bang Data Bus Bit 5
17
33
D6
I or O
Bit-Bang Data Bus Bit 6
16
32
D7
I or O
Bit-Bang Data Bus Bit 7
BIT-BANG CONTROL INTERFACE GROUP
Pin#
Signal
Type
Description
Channel A
Channel B
15
30
WR#
OUTPUT **Note 25
13
29
RD#
OUTPUT **Note 25
12
28
WR#
OUTPUT **Note 26
11
27
RD#
OUTPUT **Note 26
10
26
SI/WU
INPUT
The Send Immediate / WakeUp signal combines two functions
on a single pin. If USB is in suspend mode (PWREN# = 1) and
remote wakeup is enabled in the EEPROM , strobing this pin
low will cause the device to request a resume on the USB Bus.
Normally, this can be used to wake up the Host PC.
During normal operation (PWREN# = 0), if this pin is strobed low
any data in the device TX buffer will be sent out over USB on the
next Bulk-IN request from the drivers regardless of the pending
packet size. This can be used to optimise USB transfer speed for
some applications. Tie this pin to VCCIO if not used.
**Note 24 : In Input Mode, these pins are pulled to VCCIO via internal 200K resistors. These can be programmed to
gently pull low during USB suspend ( PWREN# = “1” ) by setting this option in the EEPROM.
DS2232L Version 1.4
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FT2232L Dual USB UART / FIFO I.C.
**Note 25 : The Bit-Bang Mode (synchronous and asynchronous) WR# and RD# strobes are on these pins when the
main Channel mode is 245 FIFO, or Fast Opto-Isolated Serial Mode. Bit-Bang mode is not available on Channel B
when Fast Opto-Isolated Serial Mode is enabled.
**Note 26 : The Bit-Bang Mode (synchronous and asynchronous) WR# and RD# strobes are on these pins when the
main Channel mode is set to 232 UART Mode.
Enhanced Asynchronous Bit-Bang Mode
Enhanced Asynchronous Bit-Bang mode is the same as BM-style Bit-Bang mode, except that the internal RD# and
WR# strobes are now brought out of the device to allow external logic to be clocked by accesses to the bit-bang IO
bus.
On either or both channels any data written to the device in the normal manner will be self clocked onto the data pins
(those which have been conﬁgured as outputs). Each pin can be independently set as an input or an output. The rate
that the data is clocked out at is controlled by the baud rate generator.
For the data to change there has to be new data written, and the baud rate clock has to tick. If no new data is written
to the channel, the pins will hold the last value written.
To allow time for the data to be setup and held around the WR# strobe, the baud rate should be less than 1
MegaBaud.
See the application note AN232B-01, “FT232BM/FT245BM Bit Bang Mode” for more details and a sample
application.
Enabling
Asynchronous Bit-Bang mode is enabled using Set Bit Bang Mode driver command. A hex value of 1 will enable it,
and a hex value of 0 will reset the device. See application note AN2232L-02, “Bit Mode Functions for the FT2232L”
for more details and examples of this.
DS2232L Version 1.4
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FT2232L Dual USB UART / FIFO I.C.
Synchronous Bit-Bang Mode
With Synchronous Bit-Bang mode data will only be sent out by the FT2232L if there is space in the device for data to
be read from the pins. This Synchronous Bit-Bang mode will read the data bus pins ﬁrst, before it sends out the byte
that has just been transmitted. It is therefore 1 byte behind the output, and so to read the inputs for the byte that you
have just sent, another byte must be sent.
For example :(1) Pins start at 0xFF
Send 0x55,0xAA
Pins go to 0x55 and then to 0xAA
Data read = 0xFF,0x55
(2) Pins start at 0xFF
Send 0x55,0xAA,0xAA
(repeat the last byte sent)
Pins go to 0x55 and then to 0xAA
Data read = 0xFF,0x55,0xAA
DS2232L Version 1.4
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FT2232L Dual USB UART / FIFO I.C.
Enabling
Synchronous Bit-Bang mode is enabled using Set Bit Bang Mode driver command. A hex value of 4 will enable it, and
a hex value of 0 will reset the device. See application note AN2232L-02, “Bit Mode Functions for the FT2232L” for
more details and examples.
Figure 25 - Synchronous Bit Bang Mode Signal Timing
t1
t2
t3
t4
t5
t6
Clk Time
D7..0
Current Data
New Data
WR#
RD#
Time
Description
t1
Current pin state is read
t2
RD# is set inactive
t3
RD# is set active again, and any pins that are output will change to the new data.
t4
Clock state for data setup
t5
WR# goes active
t6
WR# goes inactive
The internal RD# and WR# strobes are brought out of the device to allow external logic to be clocked by accesses to
the bit-bang IO bus.
DS2232L Version 1.4
© Future Technology Devices International Ltd. 2005 Page 39 of 51
FT2232L Dual USB UART / FIFO I.C.
9.6 Multi-Protocol Synchronous Serial Engine (MPSSE) Mode Signal Descriptions and
Interface Conﬁgurations
MPSSE Mode is designed to allow the FT2232L to interface efﬁciently with synchronous serial protocols such as JTAG
and SPI Bus. It can also be used to program SRAM based FPGA’s over USB. The MPSSE interface is designed to
be ﬂexible so that it can be conﬁgured to allow any synchronous serial protocol (industry standard or proprietary) to be
interfaced to the FT2232L. MPSSE is available on channel A only.
MPSSE is fully conﬁgurable, and is programmed by sending commands down the data pipe. These can be sent
individually, or more efﬁciently in packets. MPSSE is capable of a maximum sustained data rate of 5.6 Mega bits / s.
When Channel A is conﬁgured in MPSSE mode the IO signal lines are conﬁgured as follows :Pin#
Signal
(Channel A Only)
Type
Description
24
TCK/SK
OUTPUT
Clock signal Output
23
TDI/D0
OUTPUT
Serial Data Out
22
TDO/DI
INPUT
Serial Data In **Note 27
21
TMS/CS OUTPUT
Select Signal Out
20
GPIOL0
I/O
General Pupose input / Output **Note 27
19
GPIOL1
I/O
General Pupose input / Output **Note 27
17
GPIOL2
I/O
General Pupose input / Output **Note 27
16
GPIOL3
I/O
General Pupose input / Output **Note 27
15
GPIOH0 I/O
General Pupose input / Output **Note 27
13
GPIOH1 I/O
General Pupose input / Output **Note 27
12
GPIOH2 I/O
General Pupose input / Output **Note 27
11
GPIOH3 I/O
General Pupose input / Output **Note 27
**Note 27 : In Input Mode, these pins are pulled to VCCIO via internal 200K resistors. These can be programmed to
gently pull low during USB suspend ( PWREN# = “1” ) by setting this option in the EEPROM.
Enabling
MPSSE mode is enabled using Set Bit Bang Mode driver command. A hex value of 2 will enable it, and a hex value of
0 will reset the device. See application note AN2232L-02, “Bit Mode Functions for the FT2232L” for more details
and examples.
The MPSSE command set is fully described in application note AN2232L-01 - “Command Processor For MPSSE
and MCU Host Bus Emulation Modes”.
DS2232L Version 1.4
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FT2232L Dual USB UART / FIFO I.C.
9.7
MCU Host Bus Emulation Mode Signal Descriptions and Interface Conﬁguration
MCU host bus emulation mode uses both of the FT2232L’s A and B channel interfaces to make the chip emulate a
standard 8048 / 8051 MCU host bus. This allows peripheral devices for these MCU families to be directly connected to
USB via the FT2232L.
The lower 8 bits (AD7 to AD0) is a multiplexed Address / Data bus. A8 to A15 provide upper (extended) addresses.
There are 4 basic operations :1) Read (does not change A15 to A8)
2) Read Extended (changes A15 to A8)
3) Write (does not change A15 to A8)
4) Write Extended (changes A15 to A8)
Enabling
MCU Host Bus Emulation mode is enabled using Set Bit Bang Mode driver command. A hex value of 8 will enable it,
and a hex value of 0 will reset the device. See application note AN2232L-02, “Bit Mode Functions for the FT2232L”
for more details and examples.
The MCU Host Bus Emulation Mode command set is fully described in application note AN2232L-01 - “Command
Processor For MPSSE and MCU Host Bus Emulation Modes”.
DS2232L Version 1.4
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FT2232L Dual USB UART / FIFO I.C.
When MCU Host Bus Emulation mode is enabled the IO signal lines on both channels work together and the pins are
conﬁgured as follows :Pin#
Signal
Type
Description
24
AD0
I/O
Address / Data Bus Bit 0 **Note 28
23
AD1
I/O
Address / Data Bus Bit 1 **Note 28
22
AD2
I/O
Address / Data Bus Bit 2 **Note 28
21
AD3
I/O
Address / Data Bus Bit 3 **Note 28
20
AD4
I/O
Address / Data Bus Bit 4 **Note 28
19
AD5
I/O
Address / Data Bus Bit 5 **Note 28
17
AD6
I/O
Address / Data Bus Bit 6 **Note 28
16
AD7
I/O
Address / Data Bus Bit 7 **Note 28
15
I/O0
I/O
MPSSE mode instructions to set / clear or read the high byte of
data can be used with this pin. **Note 28, **Note 29
13
I/O1
I/O
MPSSE mode instructions to set / clear or read the high byte of
data can be used with this pin. In addition this pin has instructions
which will make the controller wait until it is high, or wait until it is
low. This can be used to connect to an IRQ pin of a peripheral chip.
The FT2232L will wait for the interrupt, and then read the device,
and pass the answer back to the host PC. I/O1 must be held in
input mode if this option is used. **Note 28, **Note 29
12
IORDY
INPUT
Extends the time taken to perform a Read or Write operation if
pulled low. Pull up to Vcc if not being used.
11
OSC
OUTPUT
Shows the clock signal that the circuit is using.
40
A8
OUTPUT
Extended Address Bus Bit 8
39
A9
OUTPUT
Extended Address Bus Bit 9
38
A10
OUTPUT
Extended Address Bus Bit 10
37
A11
OUTPUT
Extended Address Bus Bit 12
36
A12
OUTPUT
Extended Address Bus Bit 13
35
A13
OUTPUT
Extended Address Bus Bit 14
33
A14
OUTPUT
Extended Address Bus Bit 15
32
A15
OUTPUT
Extended Address Bus Bit 16
30
CS#
OUTPUT
Negative pulse to select device during Read or Write.
29
ALE
OUTPUT
Positive pulse to latch the address.
28
RD#
OUTPUT
Negative Read Output.
27
WR#
OUTPUT
Negative Write Output. (Data is setup before WR# goes low, and is
held after WR# goes high)
**Note 28 : In Input Mode, these pins are pulled to VCCIO via internal 200K resistors. These can be programmed to
gently pull low during USB suspend ( PWREN# = “1” ) by setting this option in the EEPROM.
**Note 29 : These instrucions are fully described in the application note AN2232L-01 - “Command Processor For
MPSSE and MCU Host Bus Emulation Modes”.
DS2232L Version 1.4
© Future Technology Devices International Ltd. 2005 Page 42 of 51
FT2232L Dual USB UART / FIFO I.C.
Figure 29 - MCU Host Bus Emulation Mode Signal Timing - Write Cycle
t1
t2
t3
t4
t5
t6
t8
t7
t9 t10
t11
OSC
A15..A8
High Address
AD7..0
Low Address
Data
ALE
CS#
WR#
IORDY
Time
Description
t1
High address byte is placed on the bus if the extended write is used.
t2
Low address byte is put out.
t3
1 clock period for address is set up.
t4
ALE goes high to enable latch. This will extend to 2 clocks wide if IORDY is low.
t5
ALE goes low to latch address and CS# is set active low.
t6
Data driven onto the bus.
t7
1 clock period for data setup.
t8
WR# is driven active low. This will extend to 6 clocks wide if IORDY is low.
t9
WR# is driven inactive high.
t10
CS# is driven inactive, 1/2 a clock period after WR# goes inactive
t11
Data is held until this point, and may now change
DS2232L Version 1.4
© Future Technology Devices International Ltd. 2005 Page 43 of 51
FT2232L Dual USB UART / FIFO I.C.
Figure 30 - MCU Host Bus Emulation Mode Signal Timing - Read Cycle
t1
t3
t2
t4
t5
t6
t7
t8 t9
OSC
A15..A8
High Address
AD7..0
Low Address
Hi-Z
ALE
CS#
RD#
IORDY
Time
Description
t1
High address byte is placed on the bus if the extended read is used - otherwise t1 will not occur.
t2
Low address byte is put out.
t3
1 clock period for address set up.
t4
ALE goes high to enable address latch. This will extend to 2 clocks wide if IORDY is low.
t5
ALE goes low to latch address, and CS# is set active low. This will extend to 3 clocks if IORDY is sampled
low. CS# will always drop 1 clock after ALE has gone high no matter the state of IORDY.
t6
Data is set as input (Hi-Z), and RD# is driven active low.
t7
1 clock period for data setup. This will extend to 5 clocks wide if IORDY# is sampled low.
t8
RD# is driven inactive high.
t9
CS# is driven inactive 1/2 a clock period after RD# goes inactive, and the data bus is set back to output.
Figure 31 - MCU Host Bus Emulation Mode Signal Timing - Clock (OSC) Signal
thigh
OSC
tlow
tperiod
Time
Description
Minimum
Typical Value
Maximum
Unit
tperiod
thigh
tlow
Clock Period
41.6
83.3
125.0
ns
Clock signal high time
20.8
41.6
62.5
ns
Clock signal low time
20.8
41.6
62.5
ns
DS2232L Version 1.4
© Future Technology Devices International Ltd. 2005 Page 44 of 51
FT2232L Dual USB UART / FIFO I.C.
Figure 32 - MCU Host Bus Emulation Example - USB <=> CAN Bus Interface
FT2232C
FT2232L
CS# (BCBUS0)
ALE (BCBUS1)
RD# (BCBUS2)
WR# (BCBUS3)
30
CS#
29
28
RD#
27
Vcc
I/O0 (ACBUS0)
I/O1 (ACBUS1)
CANBus
Transeiver
Rx
WR#
AD[0...7]
ADDRESS / DATA BUS
12
Tx
ALE/AS
AD[0...7]
(ADBUS[0...7])
IORDY# (ACBUS2)
SJA1000
CANBus
Controller
CAN
Bus
Vcc
MODE
15
13
INT#
Figure 32 shows an example where the FT2232L is used to interface a Philips SJA1000 CAN Bus Controller to a PC
over USB. In this example IORDY is not used and so is pulled up to Vcc. I/O1 is used to monitor the Interrupt output
(INT) of the SJA1000. The MODE pin on the SJA1000 is pulled high to select Intel mode. See the semiconductors
section of the Philips website (www.philips.com) for more details on the SJA1000, and suitable CAN Bus transceiver
devices.
DS2232L Version 1.4
© Future Technology Devices International Ltd. 2005 Page 45 of 51
FT2232L Dual USB UART / FIFO I.C.
9.8
Fast Opto-Isolated Serial Interface Mode Signal Description and Conﬁguration
Fast Opto-Isolated Serial Interface Mode provides a method of communicating with an external device over USB using
4 wires that can have opto-isolators in their path, thus providing galvanic isolation between systems. If either channel
A or channel B are enabled in fast opto-isolated serial mode then the pins on channel B are switched to the fast serial
interface conﬁguration. The I/O interface for fast serial mode is always on channel B, even if both channels are being
used in this mode. An address bit is used to determine the source or destination channel of the data. It therefore
makes sense to always use at least channel B or both for fast serial mode, but not A own its own.
When either Channel B or Both Channel A and B are conﬁgured in Fast Opto-Isolated Serial Interface mode following
IO signal lines are conﬁgured as follows :Pin#
Signal
Type
Description
40
FSDI
INPUT
Fast serial data input **Note 30
39
FSCLK
INPUT
Clock input to FT2232L chip to clock data in or out. The external
device has to provide a clock signal or nothing will change on
the interface pins. This gives the external device full control over
the interface. It is designed to be half duplex so that data is only
transferred in one direction at a time. **Note 30
38
FSDO
OUTPUT
Fast serial data output. Driven low to indicate that the chip is ready
to send data.
37
FSCTS
OUTPUT
Clear To Send control signal output
26
SI/WU
INPUT
The Send Immediate / WakeUp signal combines two functions on
a single pin. If USB is in suspend mode (PWREN# = 1) and remote
wakeup is enabled in the EEPROM , strobing this pin low will cause
the device to request a resume on the USB Bus. Normally, this can
be used to wake up the Host PC.
During normal operation (PWREN# = 0), if this pin is strobed low
any data in the device TX buffer will be sent out over USB on the
next Bulk-IN request from the drivers regardless of the pending
packet size. This can be used to optimise USB transfer speed for
some applications. Tie this pin to VCCIO if not used.
**Note 30 : Pulled up to VCCIO via internal 200K resistors. These pins can be programmed to gently pull low during
USB suspend ( PWREN# = “1” ) by setting this option in the EEPROM.
Fast Opto-Isolated serial interface mode is enabled in the external EEPROM.
DS2232L Version 1.4
© Future Technology Devices International Ltd. 2005 Page 46 of 51
FT2232L Dual USB UART / FIFO I.C.
Figure 33 - Fast Opto-Isolated Serial Signal Timing Diagram
FSCLK
t1
t6
t5
t2
FSDO / FSCTS
t7
FSDI
t3
t4
Time
Description
Min
Max
Unit
t1
FSDO / FSCTS hold time
5
-
ns
t2
FSDO / FSCTS setup time
5
-
ns
t3
FSDI hold time
5
-
ns
t4
FSDI setup time
10
-
ns
t5
FSCLK low
10
-
ns
t6
FSCLK high
10
ns
t7
FSCLK Period
20
-
ns
Outgoing Fast Serial Data
To send fast serial data out of the chip, the external device must clock. If the chip has data ready to send, it will drive
FSDO low to indicate the start bit. It will not do this if it is currently receiving data from the external device.
Figure 34 - Fast Opto-Isolated Serial Data Format - Data output from the FT2232L
FSCLK
FSDO
0
Start
Bit
D0
D1
D2
D3
D4
D5
Data Bits - LSB first
D6
D7
SRCE
Source
Bit
Notes :(i) Start Bit is always 0.
(ii) Data is sent LSB ﬁrst.
(iii) The source bit (SRCE) indicates which channel the data has come from. A ‘0’ means that it has come from Channel A, a ‘1’ means that it has come from Channel B.
(iv) If the target device is unable to accept the data when it detects the start bit, it should stop the FSCLK until it can
accept the data.
DS2232L Version 1.4
© Future Technology Devices International Ltd. 2005 Page 47 of 51
FT2232L Dual USB UART / FIFO I.C.
Incoming Fast Serial Data
The external device is allowed to send data into the chip if FSCTS is high. On receipt of a Zero start bit on FSDI, the
chip will drop FSCTS on the next positive clock edge. The data from bits 0 to 7 is then clocked in (LSB ﬁrst). The
next bit determines where the data will be written to. It can go to either channel A or to channel B. A ‘0’ will send it to
channel A, providing channel A is enabled for fast serial mode, otherwise it will go to channel B. A ‘1’ will send it to
channel B, providing channel B is enabled for fast serial mode, otherwise it will go to channel A. ( Either channel A, or
channel B, or both must be enabled as fast serial mode or the circuit is disabled).
Figure 35 - Fast Opto-Isolated Serial Data Format - Data input to the FT2232L
FSCTS
FSCLK
FSDI
0
Start
Bit
D0
D1
D2
D3
D4
D5
Data Bits - LSB first
D6
D7
DEST
Destination
Bit
Notes :(i) Start Bit is always 0.
(ii) Data is sent LSB ﬁrst.
(iii) The destination bit (DEST) indicates which channel the data should go to. A ‘0’ means that it should go to channel
A, a ‘1’ means that it should go to channel B.
(iv) The target device should check CTS is high before it sends data. CTS goes low after data bit 0 (D0) and stays low
until the chip can accept more data.
Contention
There is a possibility that contention may occur, where the interface goes from being completely idle to both sending
and receiving at the same clock instance. In this case the chip backs off, and allows the data from the external device
to be received.
Data Format
The data format for either direction is :1) Zero Start Bit
2) Data bit 0
3) Data bit 1
4) Data bit 2
5) Data bit 3
6) Data bit 4
7) Data bit 5
8) Data bit 6
9) Data bit 7
10) Source/Destination (‘0’ indicates channel A; ‘1’ indicates channel B)
DS2232L Version 1.4
© Future Technology Devices International Ltd. 2005 Page 48 of 51
FT2232L Dual USB UART / FIFO I.C.
Reset / Enable
Fast serial mode is enabled by setting the appropriate bits in the external EEPROM. The fast serial mode can be held
in reset by setting a bit value of 10 using the Set Bit Bang Mode command. While this bit is set the device is held reset
- data can be sent to the device, but it will not be sent out by the device until the device is enabled again. This is done
by sending a bit value of 0 using the set bit mode command. See application note AN2232L-02, “Bit Mode Functions
for the FT2232L” for more details and examples.
Figure 36 - Fast Opto-Isolated Serial Interface Example
VCC5V
FT2232L
FT2232C
FSDI (BDBUS0)
FSCLK (BDBUS1)
Cable
8
40
1K
VCCE
1
1K
7
6
39
HCPL-2430
470R
2
3
470R
5
VCCE
1
FSDO (BDBUS2)
FSCTS (BDBUS0)
470R
37
CLK
4
VCC5V
38
DI
2
3
470R
4
HCPL-2430
8
1K
7
1K
6
DO
CTS
5
In the example shown in ﬁgure 12 two Agilent HCPL-2430 (see the semiconductor section at www.agilent.com) high
speed opto-couplers are used to optically isolate an external device which interfaced to USB using the FT2232L. In
this example VCC5V is the supply for the FT2232L (bus or self powered), and VCCE is the supply to the external
device.
Care must be taken with the voltage used to power the photoLED’s. It should be the same supply that the I/Os are
driving to, or the LED’s may be permanently on. Limiting resistors should be ﬁtted in the lines that drive the diodes.
The outputs of the opto-couplers are open-collector and so need a pullup resistor.
Testing
Fast serial mode has been tested using an Scenix (Ubicom), SX28 microcontroller (see www.ubicom.com) which
was conﬁgured in loopback mode. This was done both with, and without HP HCPL-2430 opto-isolators in place. The
isolators add a considerable delay to the turnaround time seen by the micro. This was close to 100 nS with the high
speed HCPL-2430 device. This is the combined delay of the clock signal from the microcontroller going through
an opto-coupler to the chip, and the data from the FT2232L chip going through the other opto-coupler back to the
microcontroller.
DS2232L Version 1.4
© Future Technology Devices International Ltd. 2005 Page 49 of 51
FT2232L Dual USB UART / FIFO I.C.
10.0 Document Revision History
DS2232L Version 1.0 – Initial document created January 2004.
DS2232L Version 1.1 – Updated February 2004.
•
•
•
•
•
•
Grammar Corrections
Section 4.0 Device Pin Out Figure 2 corrected.
Section 5.1 TEST pin number corrected.
Section 5.1 VCCIOA and VCCIOB pin descriptions updated.
Section 9.1 Figure 14 SP214EHCA pin numbers corrected.
Section 12.0 Company contact information updated.
DS2232L Version 1.2 – Updated April 2004.
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Section 1.1 Linux now supported.
Section 2.0 Extended EEPROM Support corrected.
Section 2.0 Synchronous Bit-Bang Mode description clariﬁed.
Section 4.0 Figure 3 Pin 46 AVCC name corrected.
Section 5.2 Note 2 modiﬁed.
Section 5.3 IO Mode Command Hex Values added.
Section 8.1 Additional Murata part number added.
Section 8.3 TEST pin number added to ﬁgure 8.
Section 8.3 TEST pin number and missing GND added to ﬁgure 9.
Section 8.4 SI/WU pin numbers added to ﬁgure 10.
Section 8.4 TEST pin number added to ﬁgure 11.
Section 9.3 FIFO Write Cycle timings ameded. Figure 19 amended.
Section 9.5 Synchronous Bit-Bang Mode description ameded.
Sections 9.5, 9.6, 9.7, and 9.8 Enabling IO Bit Mode clariﬁed.
Section 12.0 Email Addresses Updated.
DS2232L Version 1.3 – Updated July 2004.
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Section 1.1 Windows CE now supported.
Section 5.2 IO Pin Deﬁnition Table. Pins 32, 33, 35 - 40. MCU Host Bus Emulation Signal Names corrected.
DS2232L Version 1.4 – Updated July 2004.
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Section 1.1 D2XX for Windows CE and Linux now supported.
Section 5.2 CPU FIFO Interface Mode Removed.
Section 6.0 Date code format corrected.
Section 6.0 Lead free version (FT2232L) now available.
Section 9.4 CPU FIFO Interface mode removed - no longer supported.
DS2232L Version 1.5 – Updated May 2005.
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Figure 14 corrected.
DS2232L Version 1.4
© Future Technology Devices International Ltd. 2005 Page 50 of 51
FT2232L Dual USB UART / FIFO I.C.
11.0 Disclaimer
© Future Technology Devices International Limited , 2002 - 2004
Neither the whole nor any part of the information contained in, or the product described in this manual, may be
adapted or reproduced in any material or electronic form without the prior written consent of the copyright holder.
This product and its documentation are supplied on an as-is basis and no warranty as to their suitability for any
particular purpose is either made or implied.
Future Technology Devices International Ltd. will not accept any claim for damages howsoever arising as a result of
use or failure of this product. Your statutory rights are not affected.
This product or any variant of it is not intended for use in any medical appliance, device or system in which the failure
of the product might reasonably be expected to result in personal injury.
This document provides preliminary information that may be subject to change without notice.
12.0 Contact Information
Future Technology Devices International. Limited
373 Scotland Street,
Glasgow G5 8QB,
United Kingdom.
Tel : +44 ( 0 )141 429 2777
Fax : +44 ( 0 )141 429 2758
E-Mail ( Sales ) : [email protected]
E-Mail ( Support ) : [email protected]
E-Mail ( General Enquiries ) : [email protected]
Web Site URL : http://www.ftdichip.com
Agents and Sales Representatives
At the time of writing our Sales Network covers over 40 different countries world-wide. Please visit the Sales Network
page of our Web site for the contact details our distributor(s) in your country.
DS2232L Version 1.4
© Future Technology Devices International Ltd. 2005 Page 51 of 51

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