LINER LTC3717 Ultrathin, triple output, step-down î¼module regulator for ddr-qdr4 memory Datasheet

LTM4632
Ultrathin, Triple Output,
Step-Down µModule Regulator
for DDR-QDR4 Memory
DESCRIPTION
FEATURES
Complete DDR-QDR4 SRAM Power Solution
Including VDDQ, VTT, VTTR (or VREF)
nn Solution in 0.5cm2 (Dual-Sided PCB)
nn Wide Input Voltage Range: 3.6V to 15V
nn 3.3V Input Compatible with V Tied to INTV
IN
CC
nn 0.6V to 2.5V Output Voltage Range
nn Dual ±3A DC Output Current with Sink and Source
Capability
nn ±1.5%, ±10mA Buffered VTTR = VDDQ/2 Output
nn 3A VDDQ + 3A VTT or Dual Phase Single 6A VTT
nn ±1.5% Maximum Total Output Voltage Regulation
Error Over Load, Line and Temperature
nn Current Mode Control, Fast Transient Response
nn External Frequency Synchronization
nn Multiphase Parallelable with Current Sharing
nn Selectable Burst Mode® Operation
nn Overvoltage Input and Overtemperature Protection
nn Power Good Indicator
nn Ultrathin 6.25mm × 6.25mm × 1.82mm LGA and
6.25mm × 6.25mm × 2.42mm BGA Packages
The LTM®4632 is an ultrathin triple output step-down
µModule® (power module) regulator to provide complete
power solution for DDR-QDR4 SRAM. Operating from a
3.6V to 15V input voltage, the LTM4632 supports two ±3A
output rails, both sink and source capable, for VDDQ and
VTT, plus a 10mA low noise reference VTTR output. Both
VTT and VTTR track and are equal to VDDQ/2. Housed
in a 6.25mm × 6.25mm × 1.82mm LGA and 6.25mm ×
6.25mm × 2.42mm BGA packages, the LTM4632 includes
the switching controller, power FETs, inductors and support components. Alternatively, the power module can
also be configured as a two phase single ±6A output
VTT. Only a few ceramic input and output capacitors are
needed to complete the design.
nn
The LTM4632 supports selectable Burst Mode operation
(CH1 only) and output voltage tracking for supply rail
sequencing. Its high switching frequency and current
mode control enable a very fast transient response to
line and load changes without sacrificing stability.
Fault protection features include overvoltage input, overcurrent and overtemperature protection.
APPLICATIONS
The LTM4632 is available with SnPb (BGA) or RoHS compliant terminal finish
DDR Memory Power Supply
nn General Purpose Point-of-Load Conversion
nn Telecom, Networking and Industrial Equipment
nn
L, LT, LTC, LTM, µModule, Burst Mode, Linear Technology and the Linear logo are registered
trademarks of Analog Devices, Inc. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
Output Efficiency vs Load Current
QDR4 Memory Power µModule Regulator
10µF
25V
VDDQ
VIN
RUN1
RUN2 LTM4632
INTVCC
SYNC/MODE
VOUT1
VOUT2
22µF
4V
VTTR
FB1
TRACK/SS1
COMP1
VDDQIN
COMP2
VTT
0.65V, ±3A
VTTR
0.65V, 10mA
GND
90
VDDQ
1.3V, 3A
52.3k
4632 TA01a
EFFICIENCY (%)
22µF
4V
PGOOD1 PGOOD2
VIN
3.6V TO 15V
95
85
80
75
70
65
5V INPUT
12V INPUT
0
1
2
LOAD CURRENT (A)
3
4632 TA01b
4632fc
For more information www.linear.com/LTM4632
1
LTM4632
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(See Pin Functions, Pin Configuration Table)
(Note 1)
VIN.............................................................. –0.3V to 16V
VOUT.............................................................. –0.3V to 6V
PGOOD1, PGOOD2...................................... –0.3V to 16V
RUN1, RUN2....................................... –0.3V to VIN+0.3V
INTVCC, TRACK/SS1, VDDQIN, VTTR.......... –0.3V to 3.6V
MODE/SYNC, COMP1, COMP2,
FB1, FB2................................................. –0.3V to INTVCC
Operating Internal Temperature Range
(Notes 2, 3, 5)......................................... –40°C to 125°C
Storage Temperature Range................... –55°C to 125°C
Peak Solder Reflow Body Temperature.................. 260°C
ORDER INFORMATION
TOP VIEW
SYNC/
COMP2 GND MODE GND COMP1
5
PGOOD2
VDDQIN
INTVCC 4
VTTR
VIN 3
RUN2
2
VIN
VOUT2 1
GND
PGOOD1
FB1
VIN
TRACK/SS1
RUN1
VIN
GND
VOUT1
A
B
C
D
E
LGA PACKAGE 25-LEAD (6.25mm × 6.25mm × 1.82mm)
BGA PACKAGE 25-LEAD (6.25mm × 6.25mm × 2.42mm)
TJMAX = 125°C, θJCtop = 17°C/W, θJCbottom = 11°C/W,
θJB +θBA = 22°C/W, θJA = 20°C/W
WEIGHT = 0.21g
http://www.linear.com/product/LTM4632#orderinfo
PART MARKING*
PAD OR BALL FINISH
DEVICE
FINISH CODE
PACKAGE
TYPE
MSL
RATING
LTM4632EV#PBF
Au (RoHS)
LTM4632V
e4
LGA
3
–40°C to 125°C
LTM4632IV#PBF
Au (RoHS)
LTM4632V
e4
LGA
3
–40°C to 125°C
PART NUMBER
TEMPERATURE RANGE
(SEE NOTE 2)
LTM4632EY#PBF
SAC305 (RoHS)
LTM4632Y
e1
BGA
3
–40°C to 125°C
LTM4632IY#PBF
SAC305 (RoHS)
LTM4632Y
e1
BGA
3
–40°C to 125°C
SnPb (63/37)
LTM4632Y
e0
BGA
3
–40°C to 125°C
LTM4632IY
• Consult Marketing for parts specified with wider operating temperature
ranges. *Device temperature grade is indicated by a label on the shipping
container. Pad or ball finish code is per IPC/JEDEC J-STD-609.
• Terminal Finish Part Marking: www.linear.com/leadfree
2
• Recommended LGA and BGA PCB Assembly and Manufacturing
Procedures: www.linear.com/umodule/pcbassembly
• LGA and BGA Package and Tray Drawings: www.linear.com/packaging
4632fc
For more information www.linear.com/LTM4632
LTM4632
ELECTRICAL CHARACTERISTICS
The l denotes the specifications that apply over the specified internal
operating temperature range (Note 2). Specified as each individual output channel at TA = 25°C (Note 2), VIN = 12V, unless otherwise
noted, per the typical application in Figure 19
SYMBOL
PARAMETER
CONDITIONS
MIN
VIN
Input DC Voltage
l
3.6
VIN_3.3
3.3V Input DC Voltage
VIN = INTVCC
l
3.1
VOUT1(RANGE)
VOUT2(RANGE)
Output Voltage Range
VIN = 3.6V to 15V
l
l
0.6
l
1.28
TYP
MAX
UNITS
15
V
3.3
3.5
V
2.5
1.8
V
V
1.32
V
3
A
Output Specification (Channel 1)
VOUT1(DC)
IOUT1(DC)
IQ1(VIN)
CH1 Output Voltage, Total Variation CIN = 22µF, COUT = 100µF Ceramic
with Line and Load
RFB1 = 51.7k, MODE = GND, IOUT = –3A to 3A
CH1 Output Continuous Current
VIN = 12V, VOUT1 = 1.3V (Note 3)
Range
CH1 Input Supply Bias Current
1.30
–3
VIN = 12V, VOUT1 = 1.3V, MODE = GND
VIN = 12V, VOUT1 = 1.3V, MODE = INTVCC
Shutdown, RUN1 = GND
13
400
40
mA
µA
µA
IS1(VIN)
CH1 Input Supply Current
VIN = 12V, VOUT1 = 1.3V, IOUT = 3A
ΔVOUT1(Line)/VOUT1
CH1 Line Regulation Accuracy
VOUT1 = 1.3V, VIN = 3.6V to 15V, IOUT1 = 0A
l
0.01
0.4
0.05
A
ΔVOUT1(Load)/VOUT1 CH1 Load Regulation Accuracy
VOUT1 = 1.3V, IOUT = –3A to 3A
l
0.2
1.0
VOUT1(AC)
CH1 Output Ripple Voltage
IOUT = 0A, COUT = 47µF Ceramic
VIN = 12V, VOUT1 = 1.3V
30
mV
ΔVOUT1(START)
CH1 Turn-On Overshoot
IOUT = 0A, COUT = 47µF Ceramic,
TRACK/SS1 = –0.1µF, VIN = 12V, VOUT1 = 1.3V
30
mV
tSTART
Turn-On Time
COUT = 100µF Ceramic, TRACK/SS1 = 0.01µF
No Load, VIN = 12V, VOUT1 = 1.3V
1.2
ms
ΔVOUTLS1
CH1 Peak Deviation for Dynamic
Load
Load: 0% to 25% to 0% of Full Load
COUT = 47µF Ceramic, VIN = 12V, VOUT1 = 1.3V
85
mV
tSETTLE1
CH1 Settling Time for Dynamic
Load Step
Load: 0% to 25% to 0% of Full Load
COUT = 47µF Ceramic, VIN = 12V, VOUT1 = 1.3V
20
µs
IOUTPK1
CH1 Output Current Limit
VIN = 12V, VOUT1 = 1.3V
4.5
A
%/V
%
Output Specification (Channel 2)
VOUT2(DC)
CH2 Output Voltage, Total Variation CIN = 22µF, COUT = 100µF Ceramic
with Line and Load
VDDQIN= 1.3V, MODE = GND, IOUT = –3A to 3A
IOUT2(DC)
CH2 Output Continuous Current
Range
VIN = 12V, VDDQIN = 1.3V (Note 3)
IQ2(VIN)
CH2 Input Supply Bias Current
VIN = 12V, VDDQIN = 1.3V, MODE = GND
Shutdown, RUN2 = 0
l
637
650
–3
663
3
7
40
mV
A
mA
µA
IS2(VIN)
CH2 Input Supply Current
VIN = 12V, VDDQIN = 1.3V, IOUT = 3A
ΔVOUT2(Line)/VOUT2
CH2 Line Regulation Accuracy
VDDQIN = 1.3V, VIN = 3.6V to 15V, IOUT2 = 0A
l
0.01
0.25
0.05
A
ΔVOUT2(Load)/VOUT2 CH2 Load Regulation Accuracy
VDDQIN = 1.3V, IOUT = –3A to 3A
l
0.2
1.0
VOUT2(AC)
CH2 Output Ripple Voltage
IOUT = 0A, COUT = 100µF Ceramic
VIN = 12V, VDDQIN = 1.3V
30
mV
ΔVOUTLS2
CH2 Peak Deviation for Dynamic
Load
Load: 0% to 25% to 0% of Full Load
COUT = 47µF Ceramic, VIN = 12V, VOUT1 = 1.3V
85
mV
tSETTLE2
CH2 Settling Time for Dynamic
Load Step
Load: 0% to 25% to 0% of Full Load
COUT = 47µF Ceramic, VIN = 12V, VOUT1 = 1.3V
20
µs
IOUTPK2
CH2 Output Current Limit
4.5
A
%/V
%
4632fc
For more information www.linear.com/LTM4632
3
LTM4632
ELECTRICAL CHARACTERISTICS
The l denotes the specifications that apply over the specified internal
operating temperature range (Note 2). Specified as each individual output channel at TA = 25°C (Note 2), VIN = 12V, unless otherwise
noted, per the typical application in Figure 19
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
0.593
0.600
0.607
V
±30
nA
Control Section
VFB1
Voltage at VFB1 Pin
IOUT = 0A, VOUT1 = 1.3V
IFB1
Current at VFB1 Pin
(Note 4)
RFBHI1
Resistor Between VOUT1 and
VFB1 Pins
VTTR
VTTR Voltage Reference
VDDQIN = 1.3V,
IVTTR = ±10mA, CVTTR < 10nF
VRUN1, VRUN2
RUN Pin On Threshold
RUN Threshold Rising
RUN Threshold Falling
IRUN1, IRUN2
RUN Pin Leakage Current
ITRACK/SS1
TRACK/SS1 Pin Soft-Start Pull-Up
Current
TRACK/SS1 = 0V
1.2
µA
tON(MIN)
Minimum On-Time
(Note 4)
20
ns
ns
l
l
60.00
60.40
60.80
kΩ
0.492x
VDDQIN
0.50x
VDDQIN
0.508x
VDDQIN
V
1.18
0.95
1.28
1.01
1.39
1.05
V
V
0
±1
µA
tOFF(MIN)
Minimum Off-Time
(Note 4)
45
VPGOOD
PGOOD Trip Level
VFB With Respect to 0.6V
VOUT2 With Respect to VDDQIN/2 (Note 4)
Ramping Negative
Ramping Positive
–8
8
15
RPGOOD
PGOOD Pull-Down Resistance
1mA Load
VINTVCC
Internal VCC Voltage
VIN = 3.6V to 15V
ICC = 0 to 50mA
VINTVCC Load Reg
INTVCC Load Regulation
fOSC
Oscillator Frequency
SYNC
SYNC Threshold Voltage
ISYNC/MODE
MODE Input Current
3.3
1.3
1
SYNC/MODE = INTVCC
Note 1. Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2. The LTM4632 is tested under pulsed load conditions such that
TJ ≈ TA. The LTM4632E is guaranteed to meet performance specifications
over the 0°C to 125°C internal operating temperature range. Specifications
over the –40°C to 125°C internal operating temperature range are assured
by design, characterization and correlation with statistical process
controls. The LTM4632I is guaranteed to meet specifications over the
full –40°C to 125°C internal operating temperature range. Note that the
maximum ambient temperature consistent with these specifications is
determined by specific operating conditions in conjunction with board
layout, the rated package thermal resistance and other environmental
factors.
4
3.1
–14
14
%
%
Ω
3.5
V
%
MHz
0.95
V
–1.5
µA
Note 3. See output current derating curves for different VIN, VOUT and TA.
Note 4. 100% tested at wafer level.
Note 5. This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
4632fc
For more information www.linear.com/LTM4632
LTM4632
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency vs Load Current at
12VIN
Efficiency vs Load Current at 5VIN
100
100
95
95
95
90
90
90
85
80
75
1VOUT
1.2VOUT
1.5VOUT
1.8VOUT
2.5VOUT
70
65
60
0
0.5
1.0
2.0
1.5
LOAD CURRENT (A)
85
80
75
1VOUT
1.2VOUT
1.5VOUT
1.8VOUT
2.5VOUT
70
65
2.5
3.0
EFFICIENCY (%)
100
EFFICIENCY (%)
EFFICIENCY (%)
Efficiency vs Load Current at
3.6VIN
60
0
4632 G01
0.5
1.0
2.0
1.5
LOAD CURRENT (A)
85
80
75
1VOUT
1.2VOUT
1.5VOUT
1.8VOUT
2.5VOUT
70
65
2.5
3.0
60
0
4632 G02
1V Output Transient Response
1.0
2.0
1.5
LOAD CURRENT (A)
2.5
3.0
4632 G03
1.2V Output Transient Response
1.5V Output Transient Response
VOUT
AC-COUPLED
50mV/DIV
VOUT
AC-COUPLED
50mV/DIV
VOUT
AC-COUPLED
50mV/DIV
LOAD STEP
1A/DIV
LOAD STEP
1A/DIV
LOAD STEP
1A/DIV
4632 G04
0.5
4632 G05
4632 G06
20µs/DIV
VIN = 12V
VOUT = 1V
fS = 1MHz
OUTPUT CAPACITOR = 1 × 47µF CERAMIC
LOAD STEP = 2.25A TO 3A
20µs/DIV
VIN = 12V
VOUT = 1.2V
fS = 1MHz
OUTPUT CAPACITOR = 1 × 47µF CERAMIC
LOAD STEP = 2.25A TO 3A
20µs/DIV
VIN = 12V
VOUT = 1.5V
fS = 1MHz
OUTPUT CAPACITOR = 1 × 47µF CERAMIC
LOAD STEP = 2.25A TO 3A
1.8V Output Transient Response
2.5V Output Transient Response
Start-Up with No Load Current
Applied
VOUT
AC-COUPLED
50mV/DIV
VOUT
AC-COUPLED
50mV/DIV
LOAD STEP
1A/DIV
LOAD STEP
1A/DIV
4632 G07
20µs/DIV
VIN = 12V
VOUT = 1.8V
fS = 1MHz
OUTPUT CAPACITOR = 1 × 47µF CERAMIC
LOAD STEP = 2.25A TO 3A
SW
10V/DIV
VOUT
1A/DIV
IIN
0.5A/DIV
4632 G08
20µs/DIV
VIN = 12V
VOUT = 2.5V
fS = 1MHz
OUTPUT CAPACITOR = 1 × 47µF CERAMIC
LOAD STEP = 2.25A TO 3A
4632 G09
20µs/DIV
VIN = 12V
VOUT = 1.8V
fS = 1MHz
IOUT = 0A
INPUT CAPACITOR = 1 × 22µF CERAMIC
OUTPUT CAPACITOR = 1 × 47µF CERAMIC
SOFT-START CAPACITOR = 0.1µF
4632fc
For more information www.linear.com/LTM4632
5
LTM4632
TYPICAL PERFORMANCE CHARACTERISTICS
Start-Up with 3A Load Current
Applied
Short-Circuit with No Load
Current Applied
Short-Circuit with 3A Load
Current Applied
SW
10V/DIV
SW
10V/DIV
SW
10V/DIV
VOUT
1V/DIV
VOUT
1V/DIV
VOUT
1V/DIV
IIN
2A/DIV
IIN
2A/DIV
IIN
0.5A/DIV
4632 G10
4632 G11
20µs/DIV
VIN = 12V
VOUT = 1.8V
fS = 1MHz
IOUT = 0A
INPUT CAPACITOR = 1 × 22µF CERAMIC
OUTPUT CAPACITOR = 1 × 47µF CERAMIC
20µs/DIV
VIN = 12V
VOUT = 1.8V
fS = 1MHz
IOUT = 3A
INPUT CAPACITOR = 1 × 22µF CERAMIC
OUTPUT CAPACITOR = 1 × 47µF CERAMIC
Recover from Short-Circuit with
No Load Current Applied
Steady-State Output Voltage
Ripple
Start-Up Into Pre-Biased Output
SW
10V/DIV
VOUT
AC-COUPLED
50mV/DIV
SW
5V/DIV
SW
5V/DIV
RUN
10V/DIV
VOUT
1V/DIV
VOUT
1V/DIV
IIN
2A/DIV
20µs/DIV
4632 G13
VIN = 12V
VOUT = 1.8V
fS = 1MHz
IOUT = 0A
INPUT CAPACITOR = 1 × 22µF CERAMIC
OUTPUT CAPACITOR = 1 × 47µF CERAMIC
6
4632 G12
20ms/DIV
VIN = 12V
VOUT = 1.8V
fS = 1MHz
IOUT = 3A
INPUT CAPACITOR = 1 × 22µF CERAMIC
OUTPUT CAPACITOR = 1 × 47µF CERAMIC
SOFT-START CAPACITOR = 0.1µF
1µs/DIV
4632 G14
VIN = 12V
VOUT = 1.8V
fS = 1MHz
IOUT = 0A
INPUT CAPACITOR = 1 × 22µF CERAMIC
OUTPUT CAPACITOR = 1 × 47µF CERAMIC
50ms/DIV
4632 G15
VIN = 12V
VOUT = 1.8V
fS = 1MHz
IOUT = 0A
INPUT CAPACITOR = 1 × 22µF CERAMIC
OUTPUT CAPACITOR = 1 × 47µF CERAMIC
4632fc
For more information www.linear.com/LTM4632
LTM4632
PIN FUNCTIONS
VIN (A2, B3, D3, E2): Power Input Pins. Apply input
voltage between these pins and GND pins. Recommend
placing input decoupling capacitance directly between VIN
pins and GND pins.
VOUT1 (D1, E1), VOUT2 (A1, B1): Power Output Pins of
each Switching Mode Regulator. Apply output load between these pins and GND pins. Recommend placing output decoupling capacitance directly between these pins
and GND pins.
GND (C1-C2, C4, B5, D5): Power Ground Pins for Both
Input and Output Returns.
PGOOD1 (D4): Output Power Good with Open-Drain Logic
of the Channel 1 Switching Mode Regulator. PGOOD1 is
pulled to ground when the voltage on the FB1 pin is not
within ±8% (typical) of the internal 0.6V reference. This
threshold has 15mV of hysteresis.
PGOOD2 (B4): Output Power Good with Open-Drain Logic
of the Channel 2 Switching Mode Regulator. PGOOD2 is
pulled to ground when the voltage on the VOUT2 pin is
not within ±8% (typical) of the VDDQIN/2 voltage. This
threshold has 15mV of hysteresis.
SYNC/MODE (C5): Mode Select and External
Synchronization Input. Tie this pin to ground to force
continuous synchronous operation at all output loads.
Floating this pin or tying it to INTVCC enables high efficiency Burst Mode operation at light loads. Drive this
pin with a clock to synchronize the LTM4632 switching
frequency. An internal phase-locked loop will force the
bottom power NMOS’s turn on signal to be synchronized
with the rising edge of the clock signal. When this pin is
driven with a clock, forced continuous mode is automatically selected.
INTVCC (C3): Internal 3.3V Regulator Output of the
Switching Mode Regulator Channel. The internal power
drivers and control circuits are powered from this voltage. This pin is internally decoupled to GND with a 2.2µF
low ESR ceramic capacitor. No more external decoupling
capacitor needed.
RUN1 (D2), RUN2 (B2): Run Control Input of Each
Switching Mode Regulator Channel. Enables chip operation by tying RUN above 1.28V. Tying this pin below 1V
shuts down the specific regulator channel. Do not float
this pin.
COMP1 (E5), COMP2 (A5): Current Control Threshold and
Error Amplifier Compensation Point of Each Switching
Mode Regulator Channel. The current comparator’s trip
threshold is linearly proportional to this voltage, whose
normal range is from 0.3V to 1.8V. The device is internal compensated. Tie COMP pins together in Dual Phase
Single Output VTT Configuration. See the Applications
Information section for details.
FB1 (E4): The Negative Input of the Error Amplifier for
the Channel 1 Switching Mode Regulator. Internally,
this pin is connected to VOUT1 with a 60.4k precision
resistor. Different output voltages can be programmed
with an additional resistor between FB1 and GND pins.
Connect this pin to INTVCC in Dual Phase Single Output
VTT Configuration. See the Applications Information section for details.
TRACK/SS1 (E3): Output Tracking and Soft-Start Pin of
the Channel 1 Switching Mode Regulator. It allows the
user to control the rise time of the output voltage. Putting
a voltage below 0.6V on this pin bypasses the internal
reference input to the error amplifier, instead it servos the
FB pin to the TRACK/SS voltage. Above 0.6V, the tracking
function stops and the internal reference resumes control
of the error amplifier. There’s an internal 1.2µA pull-up
current from INTVCC on this pin, so putting a capacitor
here provides a soft-start function.
VTTR (A3): Reference Output. This output is used to supply the VREF voltage for DDR memory. An on-chip buffer
amplifier outputs a low noise reference voltage equal to
VDDQIN/2. This output is capable of supplying 10mA. VTTR
has internal 0.01µF capacitor. Additional R-C filter can
be used to further reduce the ripple on VTTR. The error
amplifier for channel 2 uses this voltage as its reference
voltage.
VDDQIN (A4): External Reference Input for Channel 2. An
internal resistor divider sets the VTTR pin voltage to be
equal to half the voltage applied to this input. Channel 2
uses the VTTR pin voltage as its error amplifier reference.
4632fc
For more information www.linear.com/LTM4632
7
LTM4632
BLOCK DIAGRAM
VDDQ
VOUT1
60.4k
FB1
51.7k
VDDQIN
VOUT2
VTTR
BUFFER
PGOOD1
10k
PGOOD2
10k
INTVCC
INTVCC
0.01µF
INTVCC
VIN
2.2µF
0.22µF
10µF
SYNC/MODE
TRACK/SS1
0.82µH
VDDQ
1.3V
3A
VOUT1
0.1µF
VIN
3.6V TO 15V
1µF
22µF
GND
RUN1
RUN2
COMP1
0.22µF
POWER CONTROL
INTERNAL
COMP
0.82µH
VTT
0.65V
±3A
VOUT2
1µF
COMP2
22µF
GND
INTERNAL
COMP
FREQ
312k
SGND
4632 BD
DECOUPLING REQUIREMENTS
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
CIN
External Input Capacitor Requirement
(VIN = 3.6V to 15V, VOUT = 1.5V)
IOUT = 3A
4.7
10
µF
COUT
External Output Capacitor Requirement
(VIN = 3.6V to 15V, VOUT = 1.5V)
IOUT = 3A
10
22
µF
8
MAX
UNITS
4632fc
For more information www.linear.com/LTM4632
LTM4632
OPERATION
The LTM4632 is a dual output standalone non-isolated
switch mode DC/DC power supply for DDR-QDR4 SRAM
memory supplies and bus termination. It can deliver two
output rails which could both sink and source 3A DC current with few external input and output ceramic capacitors, plus a 10mA buffered VTTR (VREF) reference voltage
which equal to one half of VDDQIN voltage.
Two or more module outputs can be easily paralleled to
achieve a single VTT output with a higher sink and source
current capability. Up to 8 phases can be paralleled to run
simultaneously with a good current sharing guaranteed
by current mode control loop.
This module provides precisely regulated output voltage
(VOUT1) programmable via one external resistor from 0.6V
to 2.5V over 3.6V to 15V input voltage range. With INTVCC
tied to VIN, this module is able to operate from 3.3V input.
The LTM4632 has an integrated a dual constant on-time
valley current mode regulator, power MOSFETs, inductor, and other supporting discrete components. The typical switching frequency is internally set to 1MHz. For
switching noise-sensitive applications, the µModule can
be externally synchronized to a clock within ±30% of the
set frequency. See the Applications Information section.
With current mode control and internal feedback loop
compensation, the LTM4632 module has sufficient stability margins and good transient performance with a wide
range of output capacitors, even with all ceramic output
capacitors.
Current mode control provides cycle-by-cycle fast current limiting. An internal overvoltage and undervoltage
comparators pull the open-drain PGOOD output low if
the output feedback voltage exits a ±8% window around
the regulation point. Furthermore, an input overvoltage
protection been utilized by shutting down both power
MOSFETs when VIN rises above 17.5V to protect internal
devices.
Pulling the RUN pin below 1V forces the controller into
its shutdown state, turning off both power MOSFETs and
most of the internal control circuitry. At light load currents, burst mode operation can be enabled to achieve
higher efficiency compared to continuous mode (CCM) by
setting MODE pin to INTVCC. The TRACK/SS pin is used
for power supply tracking and soft-start programming.
See the Applications Information section.
APPLICATIONS INFORMATION
The typical LTM4632 application circuit is shown in
Figure 19. External component selection is primarily determined by the input voltage, the output voltage and the
maximum load current. Refer to Table 5 for specific external capacitor requirements for a particular application.
where tOFF(MIN) is the minimum off-time, 45ns typical for
LTM4632, and fSW is the switching frequency. Conversely
the minimum on-time limit imposes a minimum duty
cycle of the converter which can be calculated as
VIN to VOUT Step-Down Ratios
where tON(MIN) is the minimum on-time, 20ns typical for
LTM4632. In the rare cases where the minimum duty
cycle is surpassed, the output voltage will still remain
in regulation, but the switching frequency will decrease
from its programmed value. Note that additional thermal
derating may be applied. See the Thermal Considerations
and Output Current Derating section in this data sheet.
There are restrictions in the maximum VIN and VOUT step
down ratio that can be achieved for a given input voltage
due to the minimum off-time and minimum on-time limits
of the regulator. The minimum off-time limit imposes a
maximum duty cycle which can be calculated as:
DMAX = 1 – tOFF(MIN) • fSW
DMIN = tON(MIN) • fSW
4632fc
For more information www.linear.com/LTM4632
9
LTM4632
APPLICATIONS INFORMATION
Channel 1 Output Voltage Programming (Configured
as VDDQ)
The PWM controller for the VOUT1 has an internal 0.6V
reference voltage. As shown in the Block Diagram, a 60.4k
internal feedback resistor connects VOUT1 and FB1 pins
together. Adding a resistor RFB from FB1 pin to GND programs the output voltage:
RFB =
0.6V
• 60.4k
VOUT – 0.6V
RFB(k)
0.6
1.0
1.2
1.3
1.5
1.8
2.5
OPEN
90.9
60.4
52.3
40.2
30.1
19.1
Channel 2 Output Voltage Programming (Configured
as VTT)
The PWM controller for the VOUT2 uses VTTR voltage as
a reference voltage. VOUT2 is directly connected to the
negative side of the error compiler to internally program
VOUT2 to equal to VTTR voltage, which equals to one half
of VDDQIN voltage.
VOUT2 = VTTR = VDDQIN/2
In a complete DDR memory power application which
require both VDDQ supply and VTT terminal outputs,
configure LTM4632 Channel 1 as VDDQ output by adding a feed-back resistor from FB1 pin to GND. Feed VOUT1
(VDDQ output) voltage to VDDQIN pin to program Channel
2 as VTT output which equals half of the Channel 1 (VDDQ
output) voltage.
Input Decoupling Capacitors
The LTM4632 module should be connected to a low
AC-impedance DC source. For each regulator channel,
one piece 4.7µF input ceramic capacitor is required for
RMS ripple current decoupling. Bulk input capacitor is
only needed when the input source impedance is compromised by long inductive leads, traces or not enough
source capacitance. The bulk capacitor can be an electrolytic aluminum capacitor and polymer capacitor.
10
ICIN(RMS) =
IOUT(MAX )
η%
• D • (1– D)
where η% is the estimated efficiency of the power module.
Output Decoupling Capacitors
Table 1. VFB Resistor Table (1%) vs Various Output Voltages
VOUT(V)
Without considering the inductor current ripple, for each
output, the RMS current of the input capacitor can be
estimated as:
With an optimized high frequency, high bandwidth design,
only single piece of 22µF low ESR output ceramic capacitor is required for each LTM4632 output to achieve low
output voltage ripple and very good transient response.
Additional output filtering may be required by the system designer, if further reduction of output ripples or
dynamic transient spikes is required. Table 5 shows a
matrix of different output voltages and output capacitors
to minimize the voltage droop and overshoot during a
0.75A (25%) load step transient. Multiphase operation
will reduce effective output ripple as a function of the
number of phases. Application Note 77 discusses this
noise reduction versus output ripple current cancellation, but the output capacitance will be more a function
of stability and transient response. The Linear Technology
LTpowerCAD Design Tool is available to download online
for output ripple, stability and transient response analysis
and calculating the output ripple reduction as the number
of phases implemented increases by N times.
Burst Mode Operation
In applications where high efficiency at intermediate
current are more important than output voltage ripple,
burst mode operation could be used on Channel 1 by
connecting SYNC/MODE pin to INTVCC to improve light
load efficiency. In Burst Mode operation, a current reversal comparator (IREV) detects the negative inductor current and shuts off the bottom power MOSFET, resulting
in discontinuous operation and increased efficiency. Both
power MOSFETs will remain off and the output capacitor
will supply the load current until the COMP voltage rises
above the zero current level to initiate another cycle.
4632fc
For more information www.linear.com/LTM4632
LTM4632
APPLICATIONS INFORMATION
Force Continuous Current Mode (CCM) Operation
In applications where fixed frequency operation is more
critical than low current efficiency, and where the lowest output ripple is desired, forced continuous operation should be used. Forced continuous operation can
be enabled by tying the SYNC/MODE pin to GND. In this
mode, inductor current is allowed to reverse during low
output loads, the COMP voltage is in control of the current
comparator threshold throughout, and the top MOSFET
always turns on with each oscillator pulse. During startup, forced continuous mode is disabled and inductor
current is prevented from reversing until the LTM4632’s
output voltage is in regulation.
Operating Frequency
The two switching mode regulator channels inside the
LTM4632 are internally set to operate 180° out of phase.
Multiple LTM4632s could easily operate 90 degrees,
60 degrees or 45 degrees shift which corresponds to
4-phase, 6-phase or 8-phase operation by letting SYNC/
MODE of the LTM4632 synchronize to an external multiphase oscillator like LTC6902. Figure 2 shows a 4-phase
single output VTT termination supply design example for
clock phasing.
33.2k
3.3
INTVCC
V+
SET
PH
MOD
LTC6902
The operating frequency of the LTM4632 is optimized to
achieve the compact package size and the minimum output
ripple voltage while still keeping high efficiency. The default
operating frequency is internally set to 1MHz. In most applications, no additional frequency adjusting is required.
Frequency Synchronization
The power module has a phase-locked loop comprised
of an internal voltage controlled oscillator and a phase
detector. This allows the internal top MOSFET turn-on to
be locked to the rising edge of the external clock. The
external clock frequency range must be within ±30%
around the set operating frequency. A pulse detection
circuit is used to detect a clock on the SYNC/MODE pin
to turn on the phase locked loop. The pulse width of the
clock has to be at least 100ns. The clock high level must
be above 2V and clock low level below 0.3V. The presence
of an external clock will place both regulator channels into
forced continuous mode operation. During the start-up of
the regulator, the phase-locked loop function is disabled.
Multiphase Operation (Configured as Multiphase
Single Output VTT)
For VTT termination output loads that demand more than
3A of current, two outputs in the LTM4632 or even multiple LTM4632s can be paralleled to run out of phase to
provide a multiphase single output VTT termination supply
capable of souring and sinking higher current.
DIV
OUT1
GND
OUT2
LTM4632
0°
VOUT1
SYNC/
MODE
0°
90°
VOUT2
180°
VTT
12A
LTM4632
90°
VOUT1
SYNC/
MODE
VOUT2
270°
4632 F02
Figure 2. Example of Clock Phasing for 4-Phase
Single Output VTT Operation with LTC6902
Tie FB1 pin of the LTM4632 to its INTVCC pin to put the
module into two phase single VTT output operation mode.
This will internally switch the Channel 1 error amplifier
reference voltage from 0.6V to VTTR voltage, which is the
same as Channel 2. Repeat this for each LTM4632 module
in multiple LTM4632s paralleling application.
Also tie RUN, TRACK/SS and COMP pin of each paralleling channel together. Figure 20 shows an example of
paralleled multiphase single output VTT termination supply operation and pin connection.
The LTM4632 device is an inherently current mode controlled device, so parallel modules will have very good current sharing. This will balance the thermals on the design.
Multiphase Operation (Configured as VDDQ+VTT)
For application which both VDDQ and VTT termination
output loads demand more than 3A of current, two or
multiple Channel 1 outputs from different LTM4632 modules can be easily paralleled to provide a multiphase single VDDQ output while Channel 2 outputs from different
LTM4632 modules can paralleled to provide a multiphase
single VTT output.
4632fc
For more information www.linear.com/LTM4632
11
LTM4632
APPLICATIONS INFORMATION
In this case, multiple LTM4632s should be setup to operate 180 degrees, 120 degrees or 90 degrees shift which
corresponds to 2-phase, 3-phase or 4-phase operation
by letting SYNC/MODE of the LTM4632 synchronize to
an external multiphase oscillator like LTC6902.
33.2k
3.3
INTVCC
V+
SET
PH
MOD
DIV
OUT1
GND
OUT2
SYNC/
MODE
VOUT1
SYNC/
MODE
VOUT1
VOUT2
0°
180°
VOUT2
0°
VDDQ
6A
180°
VTT
6A
180°
360°
4632 F03
Figure 3. Example of Clock Phasing for 2-Phase
VDDQ Plus 2-Phase VTT Operation with LTC6902
Tie RUN1, TRACK/SS1 FB1 and COMP1 pin of each paralleling module together for VDDQ output. Tie RUN2,
VDDQIN, FB2 and COMP2 pin of each paralleling module
together for VTT output. Figure 22 shows an example of
two LTM4632 get paralleled to provide 6A VDDQ and 6A
VTT termination supply.
Input and Output RMS Ripple Current Cancellation
A multiphase power supply significantly reduces the
amount of ripple current in both the input and output
capacitors. The RMS input ripple current is reduced by,
and the effective ripple frequency is multiplied by, the
number of phases used (assuming that the input voltage is greater than the number of phases used times
the output voltage). The output ripple amplitude is also
reduced by the number of phases used when all of the
outputs are tied together to achieve a single high output
current design.
0.60
1-PHASE
2-PHASE
3-PHASE
4-PHASE
6-PHASE
0.55
0.50
RMS INPUT RIPPLE CURRENT
DC LOAD CURRENT
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
0.1 0.15
0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9
DUTY CYCLE (VOUT/VIN)
4632 F04
Figure 4. Input RMS Current Ratios to DC Load Current as a Function of Duty Cycle
12
4632fc
For more information www.linear.com/LTM4632
LTM4632
APPLICATIONS INFORMATION
Channel 1 Output Voltage Tracking and Soft-Start
The TRACK/SS pin provides a means to either soft-start
the Channel 1 regulator or track it to a different power
supply. A capacitor on the TRACK/SS pin will program
the ramp rate of the channel 1 output voltage. An internal
1.2µA current source will charge up the external soft-start
capacitor towards INTVCC voltage. When the TRACK/SS
voltage is below 0.6V, it will take over the internal 0.6V
reference voltage to control the output voltage. The total
soft-start time can be calculated as:
C
t SS = 0.6 • SS
1.2µA
where CSS is the capacitance on the TRACK/SS pin.
Forced continuous mode are disabled during the softstart process.
Channel 1 output voltage tracking can also be programmed
externally using the TRACK/SS pin. The output can be
tracked up and down with another regulator. Figure 5 and
Figure 6 show an example waveform and schematic of a
Ratiometric tracking where the slave regulator’s output
slew rate is proportional to the master’s.
Since the slave regulator’s TRACK/SS is connected to
the master’s output through a RTR(TOP)/RTR(BOT) resistor
divider and its voltage used to regulate the slave output
voltage when TRACK/SS voltage is below 0.6V, the slave
output voltage and the master output voltage should satisfy the following equation during the start-up.
VOUT(SL) •
RFB(SL)
RFB(SL) + 60.4k
VOUT(MA) •
=
R TR(BOT)
R TR(TOP) +R TR(BOT)
The RFB(SL) is the feedback resistor and the RTR(TOP)/
RTR(BOT) is the resistor divider on the TRACK/SS pin of
the slave regulator, as shown in Figure 6.
Following the upper equation, the master’s output slew
rate (MR) and the slave’s output slew rate (SR) in Volts/
Time is determined by:
RFB(SL)
RFB(SL) + 60.4k
MR
=
R TR(BOT)
SR
R TR(TOP) +R TR(BOT)
For example, VOUT(MA) = 1.5V, MR = 1.5V/1ms and
VOUT(SL) = 1.2V, SR = 1.2V/1ms. From the equation, we
could solve out that RTR(TOP) = 60.4k and RTR(BOT) = 40.2k
is a good combination for the Ratiometric tracking.
MASTER OUTPUT
OUTPUT VOLTAGE
Application Note 77 provides a detailed explanation of
multiphase operation. The input RMS ripple current cancellation mathematical derivations are presented, and
a graph is displayed representing the RMS ripple current reduction as a function of the number of interleaved
phases. Figure 4 shows this graph.
SLAVE OUTPUT
TIME
4632 F05
Figure 5. Output Ratiometric Tracking Waveform
The TRACK pins will have the 1.2µA current source on
when a resistive divider is used to implement tracking on
that specific channel. This will impose an offset on the
TRACK pin input. Smaller values resistors with the same
ratios as the resistor values calculated from the above
equation can be used. For example, where the 60.4k is
used then a 6.04k can be used to reduce the TRACK pin
offset to a negligible value.
The Coincident output tracking can be recognized as a
special Ratiometric output tracking which the master’s
output slew rate (MR) is the same as the slave’s output
slew rate (SR), as waveform shown in Figure 7.
4632fc
For more information www.linear.com/LTM4632
13
LTM4632
APPLICATIONS INFORMATION
PGOOD1
VIN
3.6V TO 15V RAIL
10µF
16V
PGOOD2
VIN
VOUT1
RUN1
VOUT2
RUN2
COMP1
TRACK/SS1
COMP2
40.2k
VDDQIN
GND
PGOOD2
VIN
VOUT1
RUN1
VOUT2
RUN2
INTVCC
60.4k
40.2k
FB1
SYNC/MODE
PGOOD1
VOUT1
VOUT2
1.2V, 3A
22µF
4V
VTTR
LTM4632
FB1
SYNC/MODE
COMP1
TRACK/SS1
COMP2
VDDQIN
22µF
4V
VTTR
LTM4632
INTVCC
0.1µF
VOUT1
1.5V, 3A
60.4k
GND
4632 F06
Figure 6. Example Schematic of Ratiometric Output Voltage Tracking
From the equation, we could easily find out that, in the
Coincident tracking, the slave regulator’s TRACK/SS pin
resistor divider is always the same as its feedback divider.
RFB(SL) + 60.4k
=
R TR(BOT)
R TR(TOP) +R TR(BOT)
For example, RTR(TOP) = 60.4k and RTR(BOT) = 60.4k is a
good combination for Coincident tracking for VOUT(MA) =
1.5V and VOUT(SL) = 1.2V application.
OUTPUT VOLTAGE
RFB(SL)
MASTER OUTPUT
SLAVE OUTPUT
TIME
4632 F07
Figure 7. Output Coincident Tracking Waveform
14
4632fc
For more information www.linear.com/LTM4632
LTM4632
APPLICATIONS INFORMATION
Power Good
Overtemperature Protection
The PGOOD pins are open drain pins that can be used to
monitor valid output voltage regulation. This pin monitors
a ±8% window around the regulation point. A resistor can
be pulled up to a particular supply voltage for monitoring.
To prevent unwanted PGOOD glitches during transients
or dynamic VOUT changes, the LTM4632’s PGOOD falling
edge includes a blanking delay of approximately 40μs.
The internal overtemperature protection monitors the
junction temperature of the module. If the junction
temperature reaches approximately 170°C, both power
switches will be turned off until the temperature drops
about 10°C cooler.
Stability Compensation
The LTM4632 module internal compensation loop is
de-signed and optimized for low ESR ceramic output
capacitors only application. Table 5 is provided for most
application requirements. The LTpowerCAD Design Tool is
available to download for control loop analysis for further
optimization.
RUN Enable
Pulling the RUN pin to ground forces the LTM4632 into
its shutdown state, turning off both power MOSFETs and
most of its internal control circuitry. Tying the RUN pin
voltage above 1.28V will turn on the entire chip.
Low Input Application
The LTM4632 is capable to run from 3.3V input when
the VIN pin is tied to INTVCC pin. See Figure 21 for the
application circuit. Please note the INTVCC pin has 3.6V
ABS max voltage rating.
Pre-Biased Output Start-Up (Channel 1)
There may be situations that require the power supply to
start up with a pre-bias on the output capacitors. In this
case, it is desirable to start up without discharging that
output pre-bias. The LTM4632 channel 1 can safely power
up into a pre-biased output without discharging it.
The LTM4632 accomplishes this by forcing discontinuous
mode (DCM) operation until the TRACK/SS1 pin voltage
reaches 80% of the 0.6V reference voltage for channel 1.
This will prevent the BG from turning on during the prebiased output start-up which would discharge the output. Do not pre-bias LTM4632 with a voltage higher than
INTVCC (3.3V) voltage.
Input Overvoltage Protection
In order to protect the internal power MOSFET devices
against transient voltage spikes, the LTM4632 constantly
monitors each VIN pin for an overvoltage condition. When
VIN rises above 17.5V, the regulator suspends operation
by shutting off both power MOSFETs on the corresponding channel. Once VIN drops below 16.5V, the regulator
immediately resumes normal operation. The regulator
executes its soft-start function when exiting an overvoltage condition.
Thermal Considerations and Output Current Derating
The thermal resistances reported in the Pin Configuration
section of the data sheet are consistent with those parameters defined by JESD51-9 and are intended for use with
finite element analysis (FEA) software modeling tools that
leverage the outcome of thermal modeling, simulation,
and correlation to hardware evaluation per-formed on a
µModule package mounted to a hardware test board—
also defined by JESD51-9 (“Test Boards for Area Array
Surface Mount Package Thermal Measurements”). The
motivation for providing these thermal coefficients in
found in JESD51-12 (“Guidelines for Reporting and Using
Electronic Package Thermal Information”).
Many designers may opt to use laboratory equipment and
a test vehicle such as the demo board to anticipate the
µModule regulator’s thermal performance in their application at various electrical and environmental operating
conditions to compliment any FEA activities. Without
FEA software, the thermal resistances reported in the
Pin Configuration section are in-and-of themselves not
relevant to providing guidance of thermal performance;
instead, the derating curves provided in the data sheet can
be used in a manner that yields insight and guidance pertaining to one’s application-usage, and can be adapted to
correlate thermal performance to one’s own application.
4632fc
For more information www.linear.com/LTM4632
15
LTM4632
APPLICATIONS INFORMATION
The Pin Configuration section typically gives four thermal
coefficients explicitly defined in JESD 51-12; these coefficients are quoted or paraphrased below:
1. θJA, the thermal resistance from junction to ambient,
is the natural convection junction-to-ambient air thermal resistance measured in a one cubic foot sealed
enclosure. This environment is sometimes referred to
as “still air” although natural convection causes the
air to move. This value is determined with the part
mounted to a JESD 51-9 defined test board, which
does not reflect an actual application or viable operating condition.
2. θJCbottom, the thermal resistance from junction to
ambient, is the natural convection junction-to-ambient air thermal resistance measured in a one cubic
foot sealed enclosure. This environment is sometimes
referred to as “still air” although natural convection
causes the air to move. This value is determined with
the part mounted to a JESD 51-9 defined test board,
which does not reflect an actual application or viable
operating condition.
3. θJCtop, the thermal resistance from junction to top of
the product case, is determined with nearly all of the
component power dissipation flowing through the top
of the package. As the electrical connections of the
typical µModule are on the bottom of the package, it
is rare for an application to operate such that most of
the heat flows from the junction to the top of the part.
As in the case of θJCbottom, this value may be useful
for comparing packages but the test conditions don’t
generally match the user’s application.
4. θJB, the thermal resistance from junction to the
printed circuit board, is the junction-to-board thermal
resistance where almost all of the heat flows through
the bottom of the µModule and into the board, and
is really the sum of the θJCbottom and the thermal
resistance of the bottom of the part through the solder
joints and through a portion of the board. The board
temperature is measured a specified distance from
the package, using a two sided, two layer board. This
board is described in JESD 51-9.
16
A graphical representation of the aforementioned thermal resistances is given in Figure 8; blue resistances are
contained within the μModule regulator, whereas green
resistances are external to the µModule package.
As a practical matter, it should be clear to the reader that
no individual or sub-group of the four thermal resistance
parameters defined by JESD51-12 or provided in the
Pin Configuration section replicates or conveys normal
operating conditions of a μModule. For example, in normal board-mounted applications, never does 100% of
the device’s total power loss (heat) thermally conduct
exclusively through the top or exclusively through bottom of the µModule package as the standard defines for
θJCtop and θJCbottom, respectively. In practice, power loss
is thermally dissipated in both directions away from the
package–granted, in the absence of a heat sink and airflow, a majority of the heat flow is into the board.
Within a SIP (system-in-package) module, be aware there
are multiple power devices and components dissipating
power, with a consequence that the thermal resistances
relative to different junctions of components or die are
not exactly linear with respect to total package power loss.
To reconcile this complication without sacrificing modeling simplicity–but also, not ignoring practical realities–an
approach has been taken using FEA software modeling
along with laboratory testing in a controlled-environment
chamber to reasonably define and correlate the thermal
resistance values supplied in this data sheet: (1) Initially,
FEA software is used to accurately build the mechanical
geometry of the µModule and the specified PCB with all
of the correct material coefficients along with accurate
power loss source definitions; (2) this model simulates
a software-defined JEDEC environment consistent with
JESD51-12 to predict power loss heat flow and temperature readings at different interfaces that enable the calculation of the JEDEC-defined thermal resistance values;
(3) the model and FEA software is used to evaluate the
µModule with heat sink and airflow; (4) having solved for
and analyzed these thermal resistance values and simulated various operating conditions in the software model,
a thorough laboratory evaluation replicates the simulated
conditions with thermocouples within a controlled-environment chamber while operating the device at the same
4632fc
For more information www.linear.com/LTM4632
LTM4632
APPLICATIONS INFORMATION
power loss as that which was simulated. The outcome of
this process and due diligence yields the set of derating
curves provided in other sections of this data sheet. After
these laboratory test have been performed and correlated
to the µModule model, then the θJB and θBA are summed
together to correlate quite well with the µModule model
with no airflow or heat sinking in a properly define chamber. This θJB + θBA value is shown in the Pin Configuration
section and should accurately equal the θJA value because
approximately 100% of power loss flows from the junction through the board into ambient with no airflow or top
mounted heat sink.
The 1.0V, 1.5V, and 2.5V power loss curves in Figures 9 to
11 can be used in coordination with the load current derating curves in Figures 12 to 17 for calculating an approximate θJA thermal resistance for the LTM4632 with no heat
sinking and various airflow conditions. The power loss
curves are taken at room temperature, and are increased
with multiplicative factors of 1.35 assuming junction
temperature at 120°C. The derating curves are plotted
with the output current starting at 6A by putting LTM4632
into two phase single output setup (Figure 20) and the
ambient temperature at 40°C. These output voltages are
chosen to include the lower and higher output voltage
ranges for correlating the thermal resistance. Thermal
models are derived from several temperature measurements in a controlled temperature chamber along with
thermal modeling analysis. The junction temperatures
are monitored while ambient temperature is increased
with and without airflow. The power loss increase with
ambient temperature change is factored into the derating
curves. The junctions are maintained at 120°C maximum
while lowering output current or power with increasing
ambient temperature. The decreased output current will
decrease the internal module loss as ambient temperature is increased. The monitored junction temperature of
120°C minus the ambient operating temperature specifies how much module temperature rise can be allowed.
As an example in Figure 12 the load current is derated
to ~3A at ~100°C with no air or heat sink and the power
loss for the 5V to 1V at 3A output is about 0.95W. The
0.95W loss is calculated with the ~0.7W room temperature loss from the 5V to 1V power loss curve at 3A, and
the 1.35 multiplying factor at 120°C measured junction
temperature. If the 100°C ambient temperature is subtracted from the 120°C junction temperature, then the
difference of 20°C divided by 0.95W equals a 20°C/W
θJA thermal resistance. Table 2 specifies a 19°C~20°C/W
value which is very close. Table 2 to 4 provide equivalent
thermal resistances for 1.0V, 1.5V, and 2.5V outputs with
and without airflow. The derived thermal resistances in
Table 2 to 4 for the various conditions can be multiplied
by the calculated power loss as a function of ambient
temperature to derive temperature rise above ambient,
thus maximum junction temperature. Room temperature
power loss can be derived from the efficiency curves
in the Typical Performance Characteristics section and
adjusted with the above ambient temperature multiplicative factors. The printed circuit board is a 1.6mm thick
four layer board with two ounce copper for the two outer
layers and one ounce copper for the two inner layers. The
PCB dimensions are 95mm × 76mm.
JUNCTION-TO-AMBIENT RESISTANCE (JESD 51-9 DEFINED BOARD)
JUNCTION-TO-CASE (TOP)
RESISTANCE
CASE (TOP)-TO-AMBIENT
RESISTANCE
JUNCTION-TO-BOARD RESISTANCE
JUNCTION
JUNCTION-TO-CASE
CASE (BOTTOM)-TO-BOARD
(BOTTOM) RESISTANCE
RESISTANCE
AMBIENT
BOARD-TO-AMBIENT
RESISTANCE
4638 F08
µMODULE DEVICE
Figure 8. Graphical Representation of JESD51-12 Thermal Coefficients
4632fc
For more information www.linear.com/LTM4632
17
LTM4632
APPLICATIONS INFORMATION
Figure 10. 1.5V Output Power Loss
3.6
3.6
3.6
3.2
3.2
3.2
2.8
2.8
2.8
2.4
2.0
1.6
1.2
12VIN
2.4
2.0
1.6
12VIN
1.2
0.8
0.4
0
POWER LOSS (W)
4.0
0.8
0.4
5VIN
0
1
3
2
4
LOAD CURRENT (A)
5
0
6
2.0
1.6
0.4
5VIN
0
1
3
2
4
LOAD CURRENT (A)
5
0
6
Figure 13. 12V to 1.0V Derating
Curve, No Heat Sink
6
6
5
5
5
0LFM
200LFM
400LFM
1
0
30
40
LOAD CURRENT (A)
6
LOAD CURRENT (A)
7
2
4
3
2
0LFM
200LFM
400LFM
1
0
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
30
40
2
0
6
5
5
5
0
30
40
2
0LFM
200LFM
400LFM
1
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
4632 F15
18
LOAD CURRENT (A)
6
LOAD CURRENT (A)
6
0LFM
200LFM
400LFM
30
40
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
Figure 17. 12V to 2.5V Derating
Curve, No Heat Sink
7
1
0LFM
200LFM
400LFM
4632 F14
7
3
0
30
40
4
3
2
0LFM
200LFM
400LFM
1
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
4632 F16
6
3
Figure 16. 5V to 2.5V Derating
Curve, No Heat Sink
4
5
4
7
2
3
2
4
LOAD CURRENT (A)
4632 F13
Figure 15. 12V to 1.5V Derating
Curve, No Heat Sink
3
1
1
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
4632 F12
4
0
Figure 14. 5V to 1.5V Derating
Curve, No Heat Sink
7
3
5VIN
4632 F11
7
4
12VIN
1.2
4632 F10
Figure 12. 5V to 1.0V Derating
Curve, No Heat Sink
LOAD CURRENT (A)
2.4
0.8
4632 F09
LOAD CURRENT (A)
Figure 11. 2.5V Output Power Loss
4.0
POWER LOSS (W)
POWER LOSS (W)
Figure 9. 1.0V Output Power Loss
4.0
0
30
40
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
4632 F17
4632fc
For more information www.linear.com/LTM4632
LTM4632
APPLICATIONS INFORMATION
Table 2. 1.0V Output
DERATING CURVE
Figures 12, 13
VIN (V)
POWER LOSS CURVE
AIRFLOW (LFM)
HEAT SINK
θJA (°C/W)
5, 12
Figure 9
0
None
19 to 20
Figures 12, 13
5, 12
Figure 9
200
None
18 to 19
Figures 12, 13
5, 12
Figure 9
400
None
17 to 18
Table 3. 1.5V Output
VIN (V)
POWER LOSS CURVE
AIRFLOW (LFM)
HEAT SINK
θJA (°C/W)
Figures 14, 15
5, 12
Figure 10
0
None
19 to 20
Figures 14, 15
5, 12
Figure 10
200
None
18 to 19
Figures 14, 15
5, 12
Figure 10
400
None
17 to 18
VIN (V)
POWER LOSS CURVE
AIRFLOW (LFM)
HEAT SINK
θJA (°C/W)
DERATING CURVE
Table 4. 2.5V Output
DERATING CURVE
Figures 16, 17
5, 12
Figure 11
0
None
19 to 20
Figures 16, 17
5, 12
Figure 11
200
None
18 to 19
Figures 16, 17
5, 12
Figure 11
400
None
17 to 18
4632fc
For more information www.linear.com/LTM4632
19
LTM4632
APPLICATIONS INFORMATION
Table 5. Output Voltage Response for Each Regulator Channel vs Component Matrix (Refer to Figure 19)
25% Load Step Typical Measured Values
CIN
(CERAMIC) PART NUMBER
COUT1
(CERAMIC) PART NUMBER
VALUE
COUT2
(BULK)
VALUE
Murata
GRM188R61E475KE11# 4.7µF, 25V, Murata
0603, X5R
GRM21R60J476ME15#
Murata
GRM188R61E106MA73# 10µF, 25V, Murata
0603, X5R
GRM188R60J226MEA0# 22µF, 6.3V,
0603, X5R
Taiyo Yuden TMK212BJ475KG-T
VOUT
(V)
4.7µF, 25V, Taiyo
0805, X5R Yuden
COUT1
CIN
(CERAMIC)
(CERAMIC)
CIN
(µF)
(µF)
(BULK)
47µF, 6.3V,
0805, X5R
JMK212BJ476MG-T
PART NUMBER VALUE
Panasonic 6TPC150M
150µF, 6.3V 3.5
× 2.8 × 1.4mm
47µF, 6.3V,
0805, X5R
COUT2
(BULK)
(µF)
CFF
(pF)
VIN
(V)
DROOP
(mV)
P-P
DERIVATION
(mV)
RECOVERY
TIME
(µS)
LOAD
STEP
(A)
LOAD STEP
SLEW RATE
(A/µS)
RFB
(kΩ)
1
2 × 10
0
1 × 47µF
0
0
5, 12
0
77
15
0.75
10
90.9
1.2
2 × 10
0
1 × 47µF
0
0
5, 12
0
83
15
0.75
10
60.4
1.5
2 × 10
0
1 × 47µF
0
0
5, 12
0
94
18
0.75
10
40.2
1.8
2 × 10
0
1 × 47µF
0
0
5, 12
0
105
20
0.75
10
30.1
2.5
2 × 10
0
1 × 47µF
0
0
5, 12
0
138
20
0.75
10
19.1
20
4632fc
For more information www.linear.com/LTM4632
LTM4632
APPLICATIONS INFORMATION
SAFETY CONSIDERATIONS
•
Place a dedicated power ground layer underneath the
unit.
•
To minimize the via conduction loss and reduce module thermal stress, use multiple vias for interconnection between top layer and other power layers.
•
Do not put via directly on the pad, unless they are
capped or plated over.
LAYOUT CHECKLIST/EXAMPLE
•
The high integration of LTM4632 makes the PCB board
layout very simple and easy. However, to optimize its
electrical and thermal performance, some layout considerations are still necessary.
Use a separated SGND ground copper area for components connected to signal pins. Connect the SGND
to GND underneath the unit.
•
For parallel modules, tie the VOUT, VFB, and COMP
pins together. Use an internal layer to closely connect these pins together. The TRACK pin can be tied
a common capacitor for regulator soft-start.
The LTM4632 modules do not provide galvanic isolation
from VIN to VOUT. There is no internal fuse. If required,
a slow blow fuse with a rating twice the maximum input
current needs to be provided to protect each unit from
catastrophic failure. The device does support thermal
shutdown and over current protection.
•
•
Use large PCB copper areas for high current paths,
including VIN, GND, VOUT1 and VOUT2. It helps to minimize the PCB conduction loss and thermal stress.
Place high frequency ceramic input and output capacitors next to the VIN, PGND and VOUT pins to minimize
high frequency noise.
• Bring out test points on the signal pins for monitoring.
Figure 18 gives a good example of the recommended
layout.
GND
COUT
COUT
VIN
VIN
CIN
CIN
GND
Figure 18. Recommend PCB Layout
4632fc
For more information www.linear.com/LTM4632
21
LTM4632
APPLICATIONS INFORMATION
VIN
3.6V TO 15V RAIL
22µF
25V
VDDQ
22µF
4V
PGOOD1 PGOOD2
VOUT1
VIN
RUN1
RUN2 LTM4632 VOUT2
INTVCC
VTTR
SYNC/MODE
FB1
COMP1
TRACK/SS1
VDDQIN
22µF
4V
VDDQ
1.3V, 3A
VTT
0.65V, ±3A
VTTR
0.65V, 10mA
COMP2
GND
52.3k
4632 F19
Figure 19. 3.6V to 15V Input, 1.3V/3A VDDQ, 0.65V/±3A VTT and 10mA VTTR Design
VIN
4V TO 15V RAIL
VIN
LTM4630
22µF
25V
×4
22µF
25V
VDDQ
VOUT1
VOUT2
100µF
4V
×6
GND
PGOOD1 PGOOD2
VOUT1
VIN
RUN1
VOUT2
RUN2 LTM4632
VTTR
INTVCC
FB1
SYNC/MODE
COMP1
TRACK/SS1
VDDQIN
VDDQ
1.8V, 36A
47µF
4V
VTT
0.9V, ±6A
INTVCC
COMP2
VTTR
0.9V, 10mA
GND
4632 F20
Figure 20. 4V to 15V Input, Two Phase Single Output ±6A VTT Termination Design with LTM4630 36A VDDQ Supply
22
4632fc
For more information www.linear.com/LTM4632
LTM4632
APPLICATIONS INFORMATION
VIN
3.1V TO 3.5V RAIL
22µF
6.3V
VDDQ
22µF
4V
PGOOD1 PGOOD2
VOUT1
VIN
RUN1
RUN2 LTM4632 VOUT2
INTVCC
VTTR
SYNC/MODE
FB1
COMP1
TRACK/SS1
VDDQIN
22µF
4V
VDDQ
1.5V, 3A
VTT
0.75V, ±3A
VTTR
0.75V, 10mA
COMP2
GND
40.2k
4632 F21
Figure 21. 3.3V Input, 1.5V/3A VDDQ, 0.75V/±3A VTT and 10mA VTTR Design
VIN
3.6V TO 15V RAIL
22µF
25V
33.2k
1
INTVCC
1µF
2
3
4
5
V+
LTC6902
SET
DIV
MOD
PH
GND
OUT1
OUT4
OUT2
OUT3
INTVCC
22µF
4V
PGOOD1 PGOOD2
VIN
VOUT1
RUN1
VOUT2
RUN2 LTM4632
VTTR
INTVCC
FB1
SYNC/MODE
COMP1
TRACK/SS1
COMP2
VDDQIN
VDDQ
1.2V, 6A
VTT
22µF 0.6V, ±6A
4V
VTTR
0.6V, 10mA
GND
10
9
8
7
6
PGOOD1 PGOOD2
VIN
VOUT1
RUN1
VOUT2
RUN2 LTM4632
VTTR
INTVCC
FB1
SYNC/MODE
VDDQ
TRACK/SS1
VDDQIN
COMP1
COMP2
GND
30.2k
4632 F22
Figure 22. Two Module in Parallel, 3.6V to 15V Input, 1.2V/6A VDDQ, 0.6V/±6A VTT and 10mA VTTR Design
4632fc
For more information www.linear.com/LTM4632
23
LTM4632
PACKAGE DESCRIPTION
PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY.
LTM4632 Component LGA and BGA Pinout
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
A1
VOUT2
A2
VIN
A3
VTTR
A4
VDDQIN
A5
COMP2
B1
VOUT2
B2
RUN2
B3
VIN
B4
PGOOD2
B5
GND
C1
GND
C2
GND
C3
INTVCC
C4
SGND
C5
SYNC/MODE
D1
VOUT1
D2
RUN1
D3
VIN
D4
PGOOD1
D5
GND
E1
VOUT1
E2
VIN
E3
TRACK/SS1
E4
FB1
E5
COMP1
24
4632fc
For more information www.linear.com/LTM4632
0.000
For more information www.linear.com/LTM4632
2.540
1.270
0.3175
0.3175
1.270
2.540
SUGGESTED PCB LAYOUT
TOP VIEW
2.540
PACKAGE TOP VIEW
1.270
4
0.3175
0.000
0.3175
PIN “A1”
CORNER
E
1.270
aaa Z
2.540
Y
D
X
aaa Z
// bbb Z
SYMBOL
A
b
D
E
e
F
G
H1
H2
aaa
bbb
eee
H1
SUBSTRATE
0.27
1.45
MIN
1.72
0.60
NOM
1.82
0.63
6.25
6.25
1.27
5.08
5.08
0.32
1.50
DIMENSIONS
Ø eee S Z X Y
Z
0.37
1.55
0.15
0.10
0.15
MAX
1.92
0.66
TOTAL NUMBER OF LGA PADS: 25
DETAIL A
Øb (25 PLACES)
DETAIL B
H2
MOLD
CAP
NOTES
DETAIL B
A
b
F
3
e
SEE NOTES
4
3
2
1
PACKAGE BOTTOM VIEW
5
G
DETAIL A
E
D
C
B
A
PIN 1
7
SEE NOTES
DETAILS OF PAD #1 IDENTIFIER ARE OPTIONAL,
BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.
THE PAD #1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE
4
7
TRAY PIN 1
BEVEL
!
PACKAGE IN TRAY LOADING ORIENTATION
LTMXXXXXX
µModule
LGA 25 0613 REV Ø
PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY
6. THE TOTAL NUMBER OF PADS: 25
5. PRIMARY DATUM -Z- IS SEATING PLANE
LAND DESIGNATION PER JESD MO-222, SPP-010
3
2. ALL DIMENSIONS ARE IN MILLIMETERS
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
COMPONENT
PIN “A1”
(Reference LTC DWG # 05-08-1949 Rev Ø)
LGA Package
25-Lead (6.25mm × 6.25mm × 1.82mm)
LTM4632
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LTM4632#packaging for the most recent package drawings.
4632fc
25
0.000
2.540
1.270
0.3175
0.3175
1.270
2.540
PACKAGE TOP VIEW
SUGGESTED PCB LAYOUT
TOP VIEW
2.540
4
1.270
PIN “A1”
CORNER
E
1.270
aaa Z
0.3175
0.000
0.3175
D
X
0.630 ±0.025
Y
aaa Z
// bbb Z
SYMBOL
A
A1
A2
b
b1
D
E
e
F
G
H1
H2
aaa
bbb
ccc
ddd
eee
For more information www.linear.com/LTM4632
0.27
1.45
MIN
2.22
0.50
1.72
0.60
0.60
NOM
2.42
0.60
1.82
0.75
0.63
6.25
6.25
1.27
5.08
5.08
0.32
1.50
DIMENSIONS
ddd M Z X Y
eee M Z
H1
SUBSTRATE
b1
A2
MAX
2.62
0.70
1.92
0.90
0.66
NOTES
DETAIL B
PACKAGE SIDE VIEW
0.37
1.55
0.15
0.10
0.20
0.30
0.15
TOTAL NUMBER OF BALLS: 25
DETAIL A
Øb (25 PLACES)
DETAIL B
H2
MOLD
CAP
ccc Z
A1
A
Z
(Reference LTC DWG # 05-08-1502 Rev Ø)
Z
26
2.540
b
F
3
e
SEE NOTES
4
3
2
1
PACKAGE BOTTOM VIEW
5
G
DETAIL A
E
D
C
B
A
PIN 1
7
SEE NOTES
DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL,
BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.
THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE
BALL DESIGNATION PER JESD MS-028 AND JEP95
7
TRAY PIN 1
BEVEL
!
PACKAGE IN TRAY LOADING ORIENTATION
LTMXXXXXX
µModule
BGA 25 0515 REV Ø
PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY
6. SOLDER BALL COMPOSITION IS 96.5% Sn/3.0% Ag/0.5% Cu
5. PRIMARY DATUM -Z- IS SEATING PLANE
4
3
2. ALL DIMENSIONS ARE IN MILLIMETERS
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
COMPONENT
PIN “A1”
BGA Package
25-Lead (6.25mm × 6.25mm × 2.42mm)
LTM4632
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LTM4632#packaging for the most recent package drawings.
4632fc
LTM4632
REVISION HISTORY
REV
DATE
DESCRIPTION
A
05/16
Added BGA package
PAGE NUMBER
1, 2, 26
B
09/16
Corrected equations of tracking start-up time from RTR(TOP)/[RTR(TOP) + RTR(BOT)] to RTR(BOT)/[RTR(TOP) + RTR(BOT)]
13, 14
C
05/17
Changed VDDQ to 1.3V/3A and VTT to 0.65V
22
4632fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representaFor more
information
www.linear.com/LTM4632
tion that the interconnection
of its circuits
as described
herein will not infringe on existing patent rights.
27
LTM4632
PACKAGE PHOTO
DESIGN RESOURCES
SUBJECT
DESCRIPTION
µModule Design and Manufacturing Resources
Design:
• Selector Guides
• Demo Boards and Gerber Files
• Free Simulation Tools
µModule Regulator Products Search
1. Sort table of products by parameters and download the result as a spread sheet.
Manufacturing:
• Quick Start Guide
• PCB Design, Assembly and Manufacturing Guidelines
• Package and Board Level Reliability
2. Search using the Quick Power Search parametric table.
TechClip Videos
Quick videos detailing how to bench test electrical and thermal performance of µModule products.
Digital Power System Management
Linear Technology’s family of digital power supply management ICs are highly integrated solutions that
offer essential functions, including power supply monitoring, supervision, margining and sequencing,
and feature EEPROM for storing user configurations and fault logging.
RELATED PARTS
PART NUMBER DESCRIPTION
COMMENTS
LTM4622
Ultrathin, Dual 2.5A or Single 5A Step-Down µModule 3.6V < VIN < 20V, 0.6V < VOUT < 5.5V, 6.25mm × 6.25mm × 1.82mm LGA
Regulator
Package, 6.25mm × 6.25mm × 2.42 BGA Package
LTM4623
Ultrathin, Single 3A Step-Down µModule Regulator
4V ≤ VIN ≤ 20V, 0.6V ≤ VOUT ≤ 5.5V, 6.25mm × 6.25mm × 1.82mm LGA Package,
6.25mm × 6.25mm × 2.42 BGA Package
LTM4644
Quad 4A Step-Down µModule Regulator
4V < VIN < 14V, 0.6V < VOUT < 5.5V, 9mm × 15mm × 5.01mm BGA Package
LTM4630
µModule Regulator for Higher Power VDDQ Supply
4.5V < VIN < 15V, 0.6V <VOUT <1.8V, Single 36A or Dual 18A, 16mm × 16mm ×
5.01mm BGA Package, 16mm × 16mm × 4.41mm LGA Package
LTM4650
µModule Regulator for High Power FPGA/ASIC
Core Supply
4.5V < VIN < 15V, 0.6V <VOUT <1.8V, Single 50A or Dual 25A, 16mm × 16mm ×
5.01mm BGA Package
LTM4639
Low Input Voltage, Single 20A Step-Down µModule
Regulator
2.375V < VIN < 7V, 0.6V < VOUT < 5.5V, 15mm × 15mm × 4.92mm BGA Package
LTM4675
µModule Regulator with PSM for High Power, High
Accuracy FPGA/ASIC Core Supply
DC/DC µModule with Digital Power System Management, 4.5V < VIN < 17V,
0.5V < VOUT < 5.5V with ±0.5% Accuracy, Single 18A or Dual 9A
LTM4677
µModule Regulator with PSM for High Power, High
Accuracy FPGA/ASIC Core Supply
DC/DC µModule with Digital Power System Management, 4.5V < VIN < 16V,
0.5V < VOUT < 1.8V with ±0.5% Accuracy, Single 36A or Dual 18A
LTC3717
Step-Down Controller for VTT for DDR Memory
Termination
4V < VIN < 36V, IOUT = ±20A, Requires External Inductor and MOSFET
LTC6902
Multiphase Oscillator for Multiphase Operation
2-, 3- or 4-Phase, 5kHz to 20MHz Frequency Range
28
4632fc
LT 0517 REV C • PRINTED IN USA
For more information www.linear.com/LTM4632
www.linear.com/LTM4632
 LINEAR TECHNOLOGY CORPORATION 2016
Similar pages