IPD50N03S4L-06 OptiMOS®-T2 Power-Transistor Product Summary V DS 30 V R DS(on),max 5.5 mW ID 50 A PG-TO252-3-11 • N-channel - Enhancement mode • Automotive AEC Q101 qualified • MSL1 up to 260°C peak reflow • 175°C operating temperature • Green product (RoHS compliant) • 100% Avalanche tested Type Package Marking IPD50N03S4L-06 PG-TO252-3-11 4N03L06 Maximum ratings, at T j=25 °C, unless otherwise specified Parameter Symbol Continuous drain current1) ID Conditions Value T C=25°C, V GS=10V 50 T C=100°C, V GS=10V2) 50 Unit A Pulsed drain current2) I D,pulse T C=25°C 200 Avalanche energy, single pulse2) E AS I D=50A 36 mJ Avalanche current, single pulse I AS - 50 A Gate source voltage V GS - ±16 V Power dissipation P tot T C=25°C 56 W Operating and storage temperature T j, T stg - -55 ... +175 °C IEC climatic category; DIN IEC 68-1 - - 55/175/56 - Rev. 1.1 page 1 2010-10-05 IPD50N03S4L-06 Parameter Symbol Values Conditions Unit min. typ. max. Thermal resistance, junction - case R thJC - - - 2.7 SMD version, device on PCB R thJA minimal footprint - - 62 6 cm2 cooling area3) - - 40 K/W Electrical characteristics, at T j=25 °C, unless otherwise specified Static characteristics Drain-source breakdown voltage V (BR)DSS V GS=0V, I D= 1mA 30 - - Gate threshold voltage V GS(th) V DS=V GS, I D=20µA 1.0 1.5 2.2 Zero gate voltage drain current I DSS V DS=30V, V GS=0V, T j=25°C - 0.1 1 T j=125°C2) - 10 100 V DS=30V, V GS=0V, V µA Gate-source leakage current I GSS V GS=16V, V DS=0V - - 100 nA Drain-source on-state resistance R DS(on) V GS=4.5V, I D=25A - 6.9 9.0 mW V GS= 10V, I D=50 A - 4.9 5.5 Rev. 1.1 page 2 2010-10-05 IPD50N03S4L-06 Parameter Symbol Values Conditions Unit min. typ. max. - 1790 2330 - 460 600 Input capacitance C iss Output capacitance C oss Reverse transfer capacitance Crss - 17 34 Turn-on delay time t d(on) - 3 - Rise time tr - 1 - Turn-off delay time t d(off) - 19 - Fall time tf - 7 - Gate to source charge Q gs - 6 8 Gate to drain charge Q gd - 3 6 Gate charge total Qg - 24 31 Gate plateau voltage V plateau - 3.2 - V - - 50 A - - 200 0.6 0.95 1.3 V - 17 - ns - 14 - nC V GS=0V, V DS=25V, f =1MHz V DD=15V, V GS=10V, I D=30A, R G=1.6W pF ns Gate Charge Characteristics2) V DD=24V, I D=50A, V GS=0 to 10V nC Reverse Diode Diode continous forward current2) IS Diode pulse current2) I S,pulse Diode forward voltage V SD V GS=0V, I F=50A, T j=25°C Reverse recovery time2) t rr V R=30V, I F=I S, di F/dt =100A/µs Reverse recovery charge2) Q rr T C=25°C 1) Current is limited by bondwire; with an R thJC = 2.7K/W the chip is able to carry 77A at 25°C. 2) Defined by design. Not subject to production test. 3) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 µm thick) copper area for drain connection. PCB is vertical in still air. Rev. 1.1 page 3 2010-10-05 IPD50N03S4L-06 2 Drain current P tot = f(T C); V GS ≥ 6 V I D = f(T C); V GS ≥ 6 V 60 60 50 50 40 40 I D [A] P tot [W] 1 Power dissipation 30 30 20 20 10 10 0 0 0 50 100 150 200 0 50 100 T C [°C] 150 200 T C [°C] I D = f(V DS); T C = 25 °C; D = 0 Z thJC = f(t p) parameter: t p parameter: D =t p/T 101 1000 0.5 1 µs 0.1 100 0.05 Z thJC [K/W] 10 µs 100 I D [A] 100 µs 0.01 10-1 single pulse 1 ms 10 10-2 10-3 1 0.1 1 10 100 10-5 10-4 10-3 10-2 10-1 100 t p [s] V DS [V] Rev. 1.1 10-6 page 4 2010-10-05 IPD50N03S4L-06 5 Typ. output characteristics 6 Typ. drain-source on-state resistance I D = f(V DS); T j = 25 °C R DS(on) = f(I D); T j = 25 °C parameter: V GS parameter: V GS 200 40 10 V 3V 3.5 V 4V 5V 4.5 V 160 30 4:5 V R DS(on) [mW] I D [A] 120 4V 80 20 3:5 V 10 5V 40 3V 10 V 0 0 0 1 2 3 4 0 40 80 V DS [V] 120 160 200 I D [A] I D = f(V GS); V DS = 6V R DS(on) = f(T j); I D = 50 A; V GS = 10 V parameter: T j 200 9 -55 °C 25 °C 175 °C 8 160 7 I D [A] R DS(on) [mW] 120 80 6 5 40 4 0 0 1 2 3 4 5 6 V GS [V] Rev. 1.1 3 -60 -20 20 60 100 140 180 T j [°C] page 5 2010-10-05 IPD50N03S4L-06 9 Typ. gate threshold voltage 10 Typ. capacitances V GS(th) = f(T j); V GS = V DS C = f(V DS); V GS = 0 V; f = 1 MHz parameter: I D 104 2 1.75 200 µA Ciss C [pF] 1.5 20 µA V GS(th) [V] 1.25 103 Coss 1 0.75 102 0.5 0.25 Crss 101 0 -60 -20 20 60 100 140 0 180 5 10 15 20 25 30 V DS [V] T j [°C] IF = f(VSD) I A S= f(t AV) parameter: T j parameter: Tj(start) 103 1000 100 102 I F [A] I AV [A] 25 °C 101 175 °C 100 °C 10 150 °C 25 °C 1 100 0.1 0 0.2 0.4 0.6 0.8 1 1.2 1.4 V SD [V] Rev. 1.1 0.1 1 10 100 1000 t AV [µs] page 6 2010-10-05 IPD50N03S4L-06 13 Avalanche energy 14 Drain-source breakdown voltage E AS = f(T j) V BR(DSS) = f(T j); I D = 1 mA parameter: I D 175 34 150 33 125 32 V BR(DSS) [V] E AS [mJ] 12.5 A 100 75 31 30 25 A 50 29 25 50 A 28 0 25 75 125 175 -55 -15 T j [°C] 25 65 105 145 T j [°C] V GS = f(Q gate); I D = 50 A pulsed parameter: V DD 10 V GS 9 Qg 8 7 6V 24 V V GS [V] 6 5 V g s(th) 4 3 2 Q g (th) Q sw 1 Q gs 0 0 5 10 15 20 Q gate Q gd 25 Q gate [nC] Rev. 1.1 page 7 2010-10-05 IPD50N03S4L-06 Published by Infineon Technologies AG 81726 Munich, Germany © Infineon Technologies AG 2008 All Rights Reserved. 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Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Rev. 1.1 page 8 2010-10-05 IPD50N03S4L-06 Revision History Version Date Changes Revision 1.1 05.10.2010 Correction of pinout diagram Rev. 1.1 page 9 2010-10-05