Dual Fractional-N/Integer-N Frequency Synthesizer ADF4251 FEATURES 3.0 GHz Fractional-N/1.2 GHz Integer-N 2.7 V to 3.3 V Power Supply Separate V P Allows Extended Tuning Voltage to 5 V Programmable Dual Modulus Prescaler RF: 4/5, 8/9 IF: 8/9, 16/17, 32/33, 64/65 Programmable Charge Pump Currents 3-Wire Serial Interface Digital Lock Detect Power-Down Mode Programmable Modulus on Fractional-N Synthesizer Trade-Off Noise versus Spurious Performance Software and Hardware Power-Down GENERAL DESCRIPTION The ADF4251 is a dual fractional-N/integer-N frequency synthesizer that can be used to implement local oscillators (LO) in the upconversion and downconversion sections of wireless receivers and transmitters. Both the RF and IF synthesizers consist of a low noise digital PFD (phase frequency detector), a precision charge pump, and a programmable reference divider. The RF synthesizer has a ⌺-⌬ based fractional interpolator that allows programmable fractional-N division. The IF synthesizer has programmable integer-N counters. A complete PLL (phase-locked loop) can be implemented if the synthesizer is used with an external loop filter and VCO (voltage controlled oscillator). Control of all the on-chip registers is via a simple 3-wire interface. The devices operate with a power supply ranging from 2.7 V to 3.3 V and can be powered down when not in use. APPLICATIONS Base Stations for Mobile Radio (GSM, PCS, DCS, CDMA, WCDMA) Wireless Handsets (GSM, PCS, DCS, CDMA, WCDMA, PHS) Wireless LANs Communications Test Equipment CATV Equipment FUNCTIONAL BLOCK DIAGRAM VDD1 VDD2 VDD3 DVDD VP1 VP2 ADF4251 CE REFERENCE 4-BIT R COUNTER 2 DOUBLER REFIN OUTPUT MUX MUXOUT RSET PHASE FREQUENCY DETECTOR CHARGE PUMP LOCK DETECT RFINA FRACTIONAL N RF DIVIDER CLK CPRF RFINB 24-BIT DATA REGISTER DATA LE INTEGER N IF DIVIDER IFINB FROM REFIN IFINA 2 DOUBLER PHASE FREQUENCY DETECTOR 15-BIT R COUNTER AGND1 AGND2 DGND CHARGE PUMP CPIF CPGND1 CPGND2 REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved. 2 = V 3 = DV = 3 V 10%, V 1 = V 2 = 5 V 10%, GND = 0 V, dBm referred to 50 , T = T to T , unless otherwise noted.) ADF4251–SPECIFICATIONS1 (VR 1==2.7V k, DD DD DD DD SET Parameter B Version Unit RF CHARACTERISTICS RF Input Frequency (RFINA, RFINB)2 RF Input Sensitivity RF Input Frequency (RFINA, RFINB)2 RF Phase Detector Frequency Allowable Prescaler Output Frequency 0.25/3.0 –10/0 0.1/3.0 30 375 GHz min/max dBm min/max GHz min/max MHz max MHz max IF CHARACTERISTICS IF Input Frequency (IFINA, IFINB)2 IF Input Sensitivity IF Phase Detector Frequency Allowable Prescaler Output Frequency 50/1200 –10/0 55 150 MHz min/max dBm min/max MHz max MHz max REFERENCE CHARACTERISTICS REFIN Input Frequency 250 MHz max REFIN Input Sensitivity 0.5/VDD1 V p-p min/max REFIN Input Current REFIN Input Capacitance ±100 10 µA max pF max 4.375 625 5 625 1 2 2 2 2 mA typ µA typ mA typ µA typ nA typ % typ % typ % typ % typ LOGIC INPUTS VINH, Input High Voltage VINL, Input Low Voltage IINH/IINL, Input Current CIN Input Capacitance 1.35 0.6 ±1 10 V min V max µA max pF max LOGIC OUTPUTS VOH, Output High Voltage VOL, Output Low Voltage VDD – 0.4 0.4 V min V max 2.7/3.3 VDD1 VDD1/5.5 13 10 4 10 V min/V max –141 dBc/Hz typ –90 –95 –103 dBc/Hz typ dBc/Hz typ dBc/Hz typ CHARGE PUMP RF ICP Sink/Source IF ICP Sink/Source High Value Low Value High Value Low Value ICP Three-State Leakage Current RF Sink and Source Current Matching IF Sink and Source Current Matching ICP vs. VCP ICP vs. Temperature POWER SUPPLIES VDD1, VDD2, VDD3 DVDD VP1, VP2 IDD3 RF + IF RF Only IF Only Low Power Sleep Mode/Power-Down RF NOISE AND SPURIOUS CHARACTERISTICS Noise Floor In-Band Phase Noise Performance4 Lowest Spur Mode Low Noise and Spur Mode Lowest Noise Mode Spurious Signals P A V min/V max mA typ mA typ mA typ pA typ P MIN MAX Test Conditions/Comments Input Level = –8/0 dBm min/max Guaranteed by Design Guaranteed by Design For f < 10 MHz, use dc-coupled square wave (0 to VDD). AC-coupled. When dc-coupled, use 0 to VDD max (CMOS compatible). See Table V See Table IX 0.5 V < VCP < VP – 0.5 0.5 V < VCP < VP – 0.5 VCP = VP /2 IOH = 0.2 mA IOL = 0.2 mA 16 mA max 13 mA max 5.5 mA max @ 20 MHz PFD Frequency @ VCO Output RFOUT = 1.8 GHz, PFD = 20 MHz RFOUT = 1.8 GHz, PFD = 20 MHz RFOUT = 1.8 GHz, PFD = 20 MHz See Typical Performance Characteristics NOTES 1 Operating Temperature Range (B Version): –40°C to +85°C. 2 Use a square wave for frequencies less than F MIN. 3 RF = 1 GHz, RF PFD = 10 MHz, MOD = 4095, IF = 500 MHz, IF PFD = 200 kHz, REF = 10 MHz, V DD = 3 V, VP1 = 5 V, and VP2 = 3 V. 4 The in-band phase noise is measured with the EVAL-ADF4251EB2 Evaluation Board and the HP5500E Phase Noise Test System. The spectrum analyzer provides the REFIN for the synthesizer (fREFOUT = 10 MHz @ 0 dBm). FOUT = 1.74 GHz, FREF = 20 MHz, N = 87, MOD = 100, Channel Spacing = 200 kHz, V DD = 3.3 V, and VP = 5 V. Specifications subject to change without notice. –2– REV. 0 ADF4251 TIMING CHARACTERISTICS*(V DD1 = VDD2 = VDD3 = DVDD = 3 V 10%, VP1 = VP2 = 5 V 10%, GND = 0 V, unless otherwise noted.) Parameter Limit at TMIN to TMAX (B Version) Unit Test Conditions/Comments t1 t2 t3 t4 t5 t6 t7 10 10 10 25 25 10 20 ns min ns min ns min ns min ns min ns min ns min LE Setup Time DATA to CLOCK Setup Time DATA to CLOCK Hold Time CLOCK High Duration CLOCK Low Duration CLOCK to LE Setup Time LE Pulsewidth *Guaranteed by design but not production tested. t4 t5 CLOCK t2 DATA DB23 (MSB) t3 DB22 DB2 DB1 (CONTROL BIT C2) DB0 (LSB) (CONTROL BIT C1) t7 LE t1 t6 LE Figure 1. Timing Diagram REV. 0 –3– ADF4251 ABSOLUTE MAXIMUM RATINGS 1, 2 NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 This device is a high performance RF integrated circuit with an ESD rating of <2 kW, and it is ESD sensitive. Proper precautions should be taken for handling and assembly. 3 GND = CPGND1, AGND1, DGND, AGND2, and CPGND2. (TA = 25°C, unless otherwise noted.) VDD1, VDD2, VDD3, DVDD to GND3 . . . . . . . . –0.3 V to +4 V REFIN, RFINA, RFINB to GND . . . . . . –0.3 V to VDD + 0.3 V VP1, VP2 to GND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +5.8 V VP1, VP2 to VDD1 . . . . . . . . . . . . . . . . . . . . . –3.3 V to +3.5 V Digital I/O Voltage to GND . . . . . . . . –0.3 V to VDD + 0.3 V Analog I/O Voltage to GND . . . . . . . . –0.3 V to VDD + 0.3 V Operating Temperature Range Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150°C LFCSP JA Thermal Impedance . . . . . . . . . . . . . . . . 122°C/W Soldering Reflow Temperature Vapor Phase (60 sec max) . . . . . . . . . . . . . . . . . . . . . 240°C IR Reflow (20 sec max) . . . . . . . . . . . . . . . . . . . . . . . 240°C 24 23 22 21 20 19 VP1 VDD1 VDD3 VDD2 VP2 CPIF PIN CONFIGURATION PIN 1 INDICATOR ADF4251 TOP VIEW (Not to Scale) 18 17 16 15 14 13 CPGND2 DVDD IFINA IFINB AGND2 RSET REFIN 7 CE 8 DGND 9 CLK 10 DATA 11 LE 12 CPRF 1 CPGND1 2 RFINA 3 RFINB 4 AGND1 5 MUXOUT 6 ORDERING GUIDE Model Temperature Range Package Option* ADF4251BCP ADF4251BCP-REEL ADF4251BCP-REEL7 –40ºC to +85ºC –40ºC to +85ºC –40ºC to +85ºC CP-24 CP-24 CP-24 *CP = Lead Frame Chip Scale Package CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADF4251 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –4– REV. 0 ADF4251 PIN FUNCTION DESCRIPTIONS Mnemonic Function CPRF RF Charge Pump Output. This is normally connected to a loop filter that drives the input to an external VCO. CPGND1 RF Charge Pump Ground RFINA Input to the RF Prescaler. This small signal input is normally taken from the VCO. RFINB Complementary Input to the RF Prescaler AGND1 Analog Ground for the RF Synthesizer MUXOUT This multiplexer output allows either the RF or IF lock detect, the scaled RF or IF, or the scaled reference frequency to be accessed externally. REFIN Reference Input. This is a CMOS input with a nominal threshold of VDD /2 and an equivalent input resistance of 100 kW. This input can be driven from a TTL or CMOS crystal oscillator. CE Chip Enable. A Logic Low on this bit powers down the device and puts the charge pump outputs into three-state. A Logic High on this pin powers up the device, depending on the status of the software power-down bits. DGND Digital Ground for the Fractional Interpolator CLK Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the shift register on the CLK rising edge. This input is a high impedance CMOS input. DATA Serial Data Input. The serial data is loaded MSB first with the three LSBs being the control bits. This input is a high impedance CMOS input. LE Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the seven latches, the latch being selected using the control bits. RSET Connecting a resistor between this pin and ground sets the minimum charge pump output current. The relationship between ICP and RSET is: 1.6875 RSET Therefore, with RSET = 2.7 kW, ICP MIN = 0.625 mA. I CP MIN = AGND2 Ground for the IF Synthesizer IFINB Complementary Input to the IF Prescaler IFINA Input to the IF Prescaler. This small signal input is normally taken from the IF VCO. DVDD Positive Power Supply for the Fractional Interpolator Section. Decoupling capacitors to the ground plane should be placed as close as possible to this pin. DVDD must have the same voltage as VDD1, VDD2, and VDD3. CPGND2 IF Charge Pump Ground CPIF IF Charge Pump Output. This is normally connected to a loop filter that drives the input to an external VCO. V P2 IF Charge Pump Power Supply. Decoupling capacitors to the ground plane should be placed as close as possible to this pin. This voltage should be greater than or equal to VDD2. VDD2 Positive Power Supply for the IF Section. Decoupling capacitors to the ground plane should be placed as close as possible to this pin. VDD2 has a value 3 V ± 10%. VDD2 must have the same voltage as VDD1, VDD3, and DVDD. VDD3 Positive Power Supply for the RF Digital Section. Decoupling capacitors to the ground plane should be placed as close as possible to this pin. VDD3 has a value 3 V ± 10%. VDD3 must have the same voltage as VDD1, VDD2, and DVDD. VDD1 Positive Power Supply for the RF Analog Section. Decoupling capacitors to the ground plane should be placed as close as possible to this pin. VDD1 has a value 3 V ± 10%. VDD1 must have the same voltage as VDD2, VDD3, and DVDD. V P1 RF Charge Pump Power Supply. Decoupling capacitors to the ground plane should be placed as close as possible to this pin. This voltage should be greater than or equal to VDD1. REV. 0 –5– ADF4251 VDD1 VDD2 VDD3 DVDD VP1 VP2 ADF4251 CE REFERENCE 4-BIT R COUNTER 2 DOUBLER REFIN OUTPUT MUX MUXOUT RSET PHASE FREQUENCY DETECTOR CHARGE PUMP LOCK DETECT RFINA FRACTIONAL N RF DIVIDER CLK CPRF RFINB 24-BIT DATA REGISTER DATA LE INTEGER N IF DIVIDER IFINB FROM REFIN IFINA 2 DOUBLER PHASE FREQUENCY DETECTOR 15-BIT R COUNTER AGND1 AGND2 DGND CHARGE PUMP CPIF CPGND1 CPGND2 Figure 2. Detailed Functional Block Diagram –6– REV. 0 Typical Performance Characteristics–ADF4251 OUTPUT POWER – dB –20 –30 VDD = 3V, VP = 5V ICP = 1.875mA PFD FREQUENCY = 10MHz CHANNEL STEP = 200kHz LOOP BANDWIDTH = 20kHz FRACTION = 59/100 RBW = 10Hz 0 –10 REFERENCE LEVEL = – 4.2dBm –20 OUTPUT POWER – dB 0 –10 –30 –50 –50 –70 –70 – 99.19dBc/Hz –80 –80 –90 –90 –100 –100 –2kHz –1kHz 1.7518GHz FREQUENCY 1kHz 2kHz TPC 1. Phase Noise Plot, Lowest Noise Mode, 1.7518 GHz RFOUT, 10 MHz PFD Frequency, 200 kHz Channel Step Resolution –30 VDD = 3V, VP = 5V ICP = 1.875mA PFD FREQUENCY = 10MHz CHANNEL STEP = 200kHz LOOP BANDWIDTH = 20kHz FRACTION = 59/100 RBW = 10Hz 0 –10 REFERENCE LEVEL = – 4.2dBm –20 –30 –40 –90 –100 –100 –2kHz –1kHz 1.7518GHz FREQUENCY 1kHz 2kHz –51dBc@ 100kHz –400kHz TPC 2. Phase Noise Plot, Low Noise and Spur Mode, 1.7518 GHz RFOUT, 10 MHz PFD Frequency, 200 kHz Channel Step Resolution VDD = 3V, VP = 5V ICP = 1.875mA PFD FREQUENCY = 10MHz CHANNEL STEP = 200kHz LOOP BANDWIDTH = 20kHz FRACTION = 59/100 RBW = 10Hz –200kHz 1.7518GHz FREQUENCY 200kHz 400kHz TPC 5. Spurious Plot, Low Noise and Spur Mode, 1.7518 GHz RFOUT, 10 MHz PFD Frequency, 200 kHz Channel Step Resolution 0 –10 REFERENCE LEVEL = – 4.2dBm –20 OUTPUT POWER – dB OUTPUT POWER – dB REFERENCE LEVEL = – 4.2dBm –80 –90 –30 –40 VDD = 3V, VP = 5V ICP = 1.875mA PFD FREQUENCY = 10MHz CHANNEL STEP = 200kHz LOOP BANDWIDTH = 20kHz FRACTION = 59/100 RBW = 1kHz REFERENCE LEVEL = – 4.2dBm –40 –50 –50 –60 –72dBc@ 100kHz –60 –85.86dBc/Hz –70 –70 –80 –80 –90 –90 –100 –100 –2kHz –1kHz 1.7518GHz FREQUENCY 1kHz 2kHz –400kHz TPC 3. Phase Noise Plot, Lowest Spur Mode, 1.7518 GHz RFOUT, 10 MHz PFD Frequency, 200 kHz Channel Step Resolution –200kHz 1.7518GHz FREQUENCY 200kHz 400kHz TPC 6. Spurious Plot, Lowest Spur Mode, 1.7518 GHz RFOUT, 10 MHz PFD Frequency, 200 kHz Channel Step Resolution TPCs 1–12 attained using EVAL-ADF4252EB1 Evaluation Board; measurements from HP8562E spectrum analyzer. REV. 0 400kHz –70 –80 –30 200kHz –60 –90.36dBc/Hz –70 –20 1.7518GHz FREQUENCY VDD = 3V, VP = 5V ICP = 1.875mA PFD FREQUENCY = 10MHz CHANNEL STEP = 200kHz LOOP BANDWIDTH = 20kHz FRACTION = 59/100 RBW = 1kHz –50 –60 –10 –200kHz –40 –50 0 –400kHz TPC 4. Spurious Plot, Lowest Noise Mode, 1.7518 GHz RFOUT, 10 MHz PFD Frequency, 200 kHz Channel Step Resolution OUTPUT POWER – dB OUTPUT POWER – dB –20 –50dBc@ 100kHz –60 –60 –10 REFERENCE LEVEL = – 4.2dBm –40 –40 0 VDD = 3V, VP = 5V ICP = 1.875mA PFD FREQUENCY = 10MHz CHANNEL STEP = 200kHz LOOP BANDWIDTH = 20kHz FRACTION = 59/100 RBW = 1kHz –7– ADF4251 OUTPUT POWER – dB –20 –30 VDD = 3V, VP = 5V ICP = 1.875mA PFD FREQUENCY = 20MHz CHANNEL STEP = 200kHz LOOP BANDWIDTH = 20kHz FRACTION = 59/100 RBW = 10Hz 0 –10 REFERENCE LEVEL = – 4.2dBm –20 OUTPUT POWER – dB 0 –10 –30 –50 –50 –70 –70 –102dBc/Hz –80 –80 –90 –90 –100 –100 –2kHz –1kHz 1.7518GHz FREQUENCY 1kHz 2kHz TPC 7. Phase Noise Plot, Lowest Noise Mode, 1.7518 GHz RFOUT, 20 MHz PFD Frequency, 200 kHz Channel Step Resolution –30 VDD = 3V, VP = 5V ICP = 1.875mA PFD FREQUENCY = 20MHz CHANNEL STEP = 200kHz LOOP BANDWIDTH = 20kHz FRACTION = 59/100 RBW = 10Hz 0 –10 REFERENCE LEVEL = – 4.2dBm –20 –30 –40 –50 –60 –93.86dBc/Hz –90 –100 –100 –2kHz –1kHz 1.7518GHz FREQUENCY 1kHz 2kHz VDD = 3V, VP = 5V ICP = 1.875mA PFD FREQUENCY = 20MHz CHANNEL STEP = 200kHz LOOP BANDWIDTH = 20kHz FRACTION = 59/100 RBW = 1kHz REFERENCE LEVEL = – 4.2dBm –63.2dBc@ 100kHz –400kHz TPC 8. Phase Noise Plot, Low Noise and Spur Mode, 1.7518 GHz RFOUT, 20 MHz PFD Frequency, 200 kHz Channel Step Resolution VDD = 3V, VP = 5V ICP = 1.875mA PFD FREQUENCY = 20MHz CHANNEL STEP = 200kHz LOOP BANDWIDTH = 20kHz FRACTION = 59/100 RBW = 10Hz –200kHz 1.7518GHz FREQUENCY 200kHz 400kHz TPC 11. Spurious Plot, Low Noise and Spur Mode, 1.7518 GHz RFOUT, 20 MHz PFD Frequency, 200 kHz Channel Step Resolution 0 –10 REFERENCE LEVEL = – 4.2dBm –20 OUTPUT POWER – dB OUTPUT POWER – dB 400kHz –80 –90 –30 200kHz –70 –80 –20 1.7518GHz FREQUENCY –60 –70 –10 –200kHz –40 –50 0 –400kHz TPC 10. Spurious Plot, Lowest Noise Mode, 1.7518 GHz RFOUT, 20 MHz PFD Frequency, 200 kHz Channel Step Resolution OUTPUT POWER – dB OUTPUT POWER – dB –20 –53dBc@ 100kHz –60 –60 –10 REFERENCE LEVEL = – 4.2dBm –40 –40 0 VDD = 3V, VP = 5V ICP = 1.875mA PFD FREQUENCY = 20MHz CHANNEL STEP = 200kHz LOOP BANDWIDTH = 20kHz FRACTION = 59/100 RBW = 1kHz –30 VDD = 3V, VP = 5V ICP = 1.875mA PFD FREQUENCY = 20MHz CHANNEL STEP = 200kHz LOOP BANDWIDTH = 20kHz FRACTION = 59/100 RBW = 1kHz REFERENCE LEVEL = – 4.2dBm –40 –40 –50 –50 –60 –60 –89.52dBc/Hz –70 –72.33dBc@ 100kHz –70 –80 –80 –90 –90 –100 –100 –2kHz –1kHz 1.7518GHz FREQUENCY 1kHz –400kHz 2kHz TPC 9. Phase Noise Plot, Lowest Spur Mode, 1.7518 GHz RFOUT, 20 MHz PFD Frequency, 200 kHz Channel Step Resolution –200kHz 1.7518GHz FREQUENCY 200kHz 400kHz TPC 12. Spurious Plot, Lowest Spur Mode, 1.7518 GHz RFOUT, 20 MHz PFD Frequency, 200 kHz Channel Step Resolution –8– REV. 0 –70 –20 –75 –30 –80 –40 SPURIOUS LEVEL – dBc PHASE NOISE – dBc/Hz ADF4251 –85 LOWEST SPUR MODE –90 –95 –100 LOW NOISE AND SPUR MODE –105 –60 –70 –80 –90 –110 –115 –120 1.430 1.435 1.440 1.445 1.450 1.455 LOWEST SPUR MODE –120 1.430 1.435 1.440 1.445 1.450 FREQUENCY – GHz 1.460 FREQUENCY – GHz –20 –30 –30 –40 SPURIOUS LEVEL – dBc SPURIOUS LEVEL – dBc –10 –20 –40 LOWEST NOISE MODE –50 –60 –70 –80 –50 –60 –70 –110 1.430 –80 –90 1.435 1.440 1.445 1.450 FREQUENCY – GHz 1.455 LOWEST SPUR MODE –120 1.430 1.435 1.440 1.445 1.450 FREQUENCY – GHz 1.460 –20 –30 –40 –40 SPURIOUS LEVEL – dBc –20 –30 –50 LOWEST NOISE MODE –70 –80 –90 –100 1.435 1.440 1.445 1.450 FREQUENCY – GHz 1.460 –50 –60 –70 –80 –90 –100 LOWEST NOISE MODE –110 LOWEST SPUR MODE –120 1.430 1.455 TPC 17. 600 kHz Spur vs. Frequency* TPC 14. 100 kHz Spur vs. Frequency* SPURIOUS LEVEL – dBc LOWEST NOISE MODE –110 LOWEST SPUR MODE 1.455 LOWEST SPUR MODE –120 1.430 1.435 1.440 1.445 1.450 FREQUENCY – GHz 1.460 1.455 TPC 18. 3 MHz Spur vs. Frequency* TPC 15. 200 kHz Spur vs. Frequency* *TPCs 13–18: Across all fractional channel steps from f = 0/130 to f = 129/130. RFOUT = 1.45 GHz, Int Reg = 55, Ref = 26 MHz, and LBW = 40 kHz. TPCs 13–24 attained using EVAL-ADF4252EB2 Evaluation Board. REV. 0 1.460 –100 –90 –100 –110 1.455 TPC 16. 400 kHz Spur vs. Frequency* TPC 13. In-Band Phase Noise vs. Frequency* –60 LOWEST NOISE MODE –100 LOWEST NOISE MODE –110 –50 –9– 1.460 ADF4251 0 –120 –5 –130 PHASE NOISE – dB/Hz VDD = 3V VP = 3V AMPLITUDE – dBm –10 PRESCALER = 4/5 –15 –20 PRESCALER = 8/9 –25 0 1 2 3 4 FREQUENCY – GHz 5 100k 1M PHASE DETECTOR FREQUENCY – Hz 10M TPC 22. Phase Noise (Referred to CP Output) vs. PFD Frequency, IF Side 6 VDD = 3V VP2 = 3V 4 10 2 15 ICP – mA IF INPUT POWER – dBm 5 –160 –180 10k 6 TPC 19. RF Input Sensitivity 0 –150 –170 –30 –35 –140 20 25 VDD = 3V VP1 = 5.5V 0 –2 30 –4 35 –6 40 –0.4 0.1 0.6 1.1 IF INPUT FREQUENCY – GHz 1.6 0.5 1.0 1.5 2.0 2.5 3.0 VCP – V 3.5 4.0 4.5 5.0 5.5 TPC 23. RF Charge Pump Output Characteristics TPC 20. IF Input Sensitivity 6 –120 VDD = 3V VP = 5V –130 4 –140 2 ICP – mA PHASE NOISE – dB/Hz 0 –150 0 –160 –2 –170 –4 –180 10k –6 100k 1M PHASE DETECTOR FREQUENCY – Hz 10M VDD = 3V VP2 = 3V 0 0.5 1.0 1.5 VCP – V 2.0 2.5 3.0 TPC 24. IF Charge Pump Output Characteristics TPC 21. Phase Noise (Referred to CP Output) vs. PFD Frequency, RF Side –10– REV. 0 ADF4251 REFIN = the reference input frequency, D = RF REFIN Doubler Bit, R = the preset divide ratio of the binary 4-bit programmable reference counter (1 to 15), INT = the preset divide ratio of the binary 8-bit counter (31 to 255), MOD = the preset modulus ratio of binary 12-bit programmable FRAC counter (2 to 4095), and FRAC = the preset fractional ratio of the binary 12-bit programmable FRAC counter (0 to MOD). CIRCUIT DESCRIPTION Reference Input Section The reference input stage is shown in Figure 3. SW1 and SW2 are normally closed switches. SW3 is normally open. When power-down is initiated, SW3 is closed and SW1 and SW2 are opened. This ensures that there is no loading of the REFIN pin on power-down. POWER-DOWN CONTROL RF N DIVIDER 100k NC FROM RF INPUT STAGE SW2 REFIN NC BUFFER SW1 SW3 N = INT + FRAC/MOD TO PFD N-COUNTER TO R COUNTER THIRD-ORDER FRACTIONAL INTERPOLATOR REFOUT NO XOEB INT REG NC = NORMALLY CLOSED NO = NORMALLY OPEN MOD REG FRAC VALUE Figure 3. Reference Input Stage RF and IF Input Stage The RF input stage is shown in Figure 4. The IF input stage is the same. It is followed by a two-stage limiting amplifier to generate the CML clock levels needed for the N counter. Figure 5. N Counter RF R Counter The 4-bit RF R counter allows the input reference frequency (REFIN) to be divided down to produce the reference clock to the RF PFD. Division ratios from 1 to 15 are allowed. 1.6V BIAS GENERATOR VDD1 2k 2k IF R Counter RFINA The 15-bit IF R counter allows the input reference frequency (REFIN) to be divided down to produce the reference clock to the IF PFD. Division ratios from 1 to 32767 are allowed. RFINB IF Prescaler (P/P + 1) The dual modulus IF prescaler (P/P + 1), along with the IF A and B counters, enables the large division ratio, N, to be realized (N = PB + A). Operating at CML levels, it takes the clock from the IF input stage and divides it down to a manageable frequency for the CMOS IF A and CMOS IF B counters. AGND Figure 4. RF Input Stage IF A and B Counters RF INT Divider The IF A CMOS and IF B CMOS counters combine with the dual modulus IF prescaler to allow a wide ranging division ratio in the PLL feedback counter. The counters are guaranteed to work when the prescaler output is 150 MHz or less. The RF INT CMOS counter allows a division ratio in the PLL feedback counter. Division ratios from 31 to 255 are allowed. INT, FRAC, MOD, and R Relationship The INT, FRAC, and MOD values, in conjunction with the RF R counter, make it possible to generate output frequencies that are spaced by fractions of the RF phase frequency detector (PFD). The equation for the RF VCO frequency (RFOUT) is Ê FRAC ˆ RFOUT = FPFD ¥ Á INT + MOD ˜¯ Ë Pulse Swallow Function (1) [ FPFD = REFIN REV. 0 R ] IFOUT = (P ¥ B ) + A ¥ FPFD where RFOUT is the output frequency of external voltage controlled oscillator (VCO). (1 + D) ¥ The IF A and IF B counters, in conjunction with the dual modulus IF prescaler, make it possible to generate output frequencies that are spaced only by the reference frequency divided by R. See the Device Programming after Initial Power-Up section for examples. The equation for the IF VCO (IFOUT) frequency is (2) (3) where IFOUT = the output frequency of the external voltage controlled oscillator (VCO), P = the preset modulus of the IF dual modulus prescaler, B = the preset divide ratio of the binary 12-bit counter (3 to 4095), and A = the preset divide ratio of the binary 6-bit swallow counter (0 to 63). FPFD is obtained using Equation 2. –11– ADF4251 Phase Frequency Detector (PFD) and Charge Pump Lock Detect The PFD takes inputs from the R counter and N counter and produces an output proportional to the phase and frequency difference between them. Figure 6 is a simplified schematic. The PFD includes a delay element that controls the width of the antibacklash pulse. This pulse ensures that there is no dead zone in the PFD transfer function and minimizes phase noise and reference spurs. MUXOUT can be programmed for two types of lock detect: digital and analog. Digital is active high. The N-channel open-drain analog lock detect should be operated with an external pull-up resistor of 10 kW nominal. When lock has been detected, this output will be high with narrow low going pulses. Hardware Power-Down/Chip Enable In addition to the software power-down methods described on pages 21 and 22, the ADF4251 also has a hardware powerdown feature. This is accessed via the Chip Enable (CE) pin. When this pin is Logic High, the device is in normal operation. Bringing the CE pin Logic Low will power down the device. When this happens, the following events occur: 1. All active dc current paths are removed. 2. The RF and IF counters are forced to their load state conditions. 3. The RF and IF charge pumps are forced into three-state mode. 4. The digital lock detect circuitry is reset. 5. The RFIN and IFIN inputs are debiased. 6. The REFIN input buffer circuitry is disabled. 7. The serial interface input register remains active and capable of loading and latching data. U1 HI D1 Q1 +IN UP CLR1 CHARGE PUMP DELAY ELEMENT HI CP U3 CLR2 D2 DOWN Q2 Bringing the CE pin back up again to Logic High will reinstate normal operation, depending on the software power-down settings. –IN U2 Input Shift Register Figure 6. PFD Simplified Schematic MUXOUT and Lock Detect The output multiplexer on the ADF4251 allows the user to access various internal points on the chip. The state of MUXOUT is controlled by M4, M3, M2, and M1 in the Master Register. Table VI shows the full truth table. Figure 7 shows the MUXOUT section in block diagram format. DVDD LOGIC LOW Data is clocked in on each rising edge of CLK. The data is clocked in MSB first. Data is transferred from the input register to one of seven latches on the rising edge of LE. The destination latch is determined by the state of the three control bits (C2, C1, and C0) in the shift register. These are the three LSBs: DB2, DB1, and DB0, as shown in Figure 1. The truth table for these bits is shown in Table I. Table II shows a summary of how the registers are programmed. IF ANALOG LOCK DETECT Table I. Control Bit Truth Table IF R DIVIDER OUTPUT IF N DIVIDER OUTPUT RF ANALOG LOCK DETECT IF/RF ANALOG LOCK DETECT IF DIGITAL LOCK DETECT LOGIC HIGH MUX MUXOUT CONTROL RF R DIVIDER OUTPUT RF N DIVIDER OUTPUT THREE STATE OUTPUT RF DIGITAL LOCK DETECT RF/IF DIGITAL LOCK DETECT C2 C1 C0 Data Latch 0 0 0 0 1 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 RF N Divider Reg RF R Divider Reg RF Control Reg Master Reg IF N Divider Reg IF R Divider Reg IF Control Reg LOGIC HIGH LOGIC LOW DGND Figure 7. MUXOUT Circuit –12– REV. 0 ADF4251 Table II. Register Summary RESERVED RF N DIVIDER REG 8-BIT RF INTEGER VALUE (INT) CONTROL BITS 12-BIT RF FRACTIONAL VALUE (FRAC) DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 P1 N8 N7 N6 N5 N4 N3 N2 N1 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 C3 (0) C2 (0) C1 (0) PRESCALER RF REFIN DOUBLER DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 P3 P2 R4 R3 R2 R1 M12 M11 M10 M9 M8 M7 M6 M5 M4 M3 M2 M1 C3 (0) C2 (0) C1 (1) RF COUNTER RESET RF R DIVIDER REG 4-BIT RF R COUNTER CONTROL BITS 12-BIT INTERPOLATOR MODULUS VALUE (MOD) RESERVED RF PD POLARITY NOISE AND SPUR SETTING 1 RF POWERDOWN RF CP THREESTATE DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 N3 T3 T2 T1 N2 CP2 CP1 0 P8 N1 P6 P5 P4 RESERVED NOISE AND SPUR SETTING 2 NOISE AND SPUR SETTING 3 RF CONTROL REG RESERVED RF CP CURRENT SETTING CONTROL BITS DB2 DB1 DB0 C3 (0) C2 (1) C1 (0) DB9 DB8 DB7 M4 M3 M2 M1 DB6 COUNTER RESET DB10 CP THREESTATE MUXOUT POWERDOWN MASTER REG DB5 DB4 DB3 DB2 DB1 DB0 P11 P10 P9 C3 (0) C2 (1) C1 (1) CONTROL BITS IF CP GAIN IF N DIVIDER REG 12-BIT IF B COUNTER IF PRESCALER CONTROL BITS 6-BIT IF A COUNTER DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 P15 P14 P13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 A6 A5 A4 A3 A2 A1 C3 (1) C2 (0) C1 (0) IF REFIN DOUBLER IF R DIVIDER REG CONTROL BITS 15-BIT IF R COUNTER DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 P16 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 C3 (1) C2 (0) C1 (1) IF LDP IF POWERDOWN IF CP THREESTATE IF COUNTER RESET DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 PR3 PR2 T8 T7 PR1 CP3 CP2 CP1 P21 P20 P19 P18 P17 RF PHASE RESYNC REV. 0 RESERVED RF PHASE RESYNC IF PD POLARITY IF CONTROL REG –13– IF CP CURRENT SETTING CONTROL BITS DB2 DB1 DB0 C3 (1) C2 (1) C1 (0) ADF4251 RESERVED Table III. RF N Divider Register Map 8-BIT RF INTEGER VALUE (INT) DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 P1 N8 N7 N6 P1 RESERVED 0 RESERVED N5 N4 N2 N3 CONTROL BITS 12-BIT RF FRACTIONAL VALUE (FRAC) N1 F12 F11 F10 F9 F8 F7 DB8 DB7 DB6 DB5 DB4 DB3 F6 F5 F4 F3 F2 F1 DB2 DB1 DB0 C3 (0) C2 (0) C1 (0) F12 0 0 0 0 . . . 1 F11 0 0 0 0 . . . 1 F10 0 0 0 0 . . . 1 .......... .......... .......... .......... .......... .......... .......... .......... F3 0 0 0 0 . . . 1 F2 0 0 1 1 . . . 0 F1 0 1 0 1 . . . 0 FRACTIONAL VALUE (FRAC) 0 1 2 3 . . . 4092 1 1 1 .......... 1 0 1 4093 1 1 1 .......... 1 1 0 4094 1 1 1 .......... 1 1 1 4095 RF INTEGER VALUE (INT)* N8 0 0 0 0 . . . 1 N7 0 0 0 0 . . . 1 N6 0 1 1 1 . . . 1 N5 1 0 0 0 . . . 1 N4 1 0 0 0 . . . 1 N3 1 0 0 0 . . . 1 N2 1 0 0 1 . . . 0 N1 1 0 1 0 . . . 1 31 32 33 34 . . . 253 1 1 1 1 1 1 1 0 254 1 1 1 1 1 1 1 1 255 *WHEN P = 8/9, NMIN = 91 –14– REV. 0 ADF4251 PRESCALER RF REFIN DOUBLER Table IV. RF R Divider Register Map DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 P3 P2 R4 R3 R2 R1 M12 M11 M10 M9 M8 M7 M6 M5 M4 M3 M2 M1 C3 (0) C2 (0) C1 (1) P2 RF REFIN DOUBLER 0 1 DISABLED ENABLED CONTROL BITS 12-BIT INTERPOLATOR MODULUS VALUE (MOD) 4-BIT RF R COUNTER M12 0 0 0 . . . 1 M11 0 0 0 . . . 1 M10 0 0 0 . . . 1 .......... .......... .......... .......... .......... .......... .......... M3 0 0 1 . . . 1 M2 1 1 0 . . . 0 M1 0 1 0 . . . 0 INTERPOLATOR MODULUS VALUE (MOD) DIVIDE RATIO 2 3 4 . . . 4092 P3 RF PRESCALER 1 1 1 .......... 1 0 1 4093 0 1 4/5 8/9 1 1 1 .......... 1 1 0 4094 1 1 1 .......... 1 1 1 4095 REV. 0 R4 0 0 0 . . . 1 R3 0 0 0 . . . 1 R2 0 1 1 . . . 0 R1 1 0 1 . . . 1 RF R COUNTER DIVIDE RATIO 1 2 3 . . . 13 1 1 1 0 14 1 1 1 1 15 –15– ADF4251 DB14 DB13 N3 T3 T2 DB12 T1 DB11 DB10 N2 CP2 DB9 DB8 CP1 0 RF POWERDOWN DB6 DB5 DB4 DB3 DB2 DB1 DB0 P8 N1 P6 P5 P4 C3 (0) C2 (1) C1 (0) RF COUNTER RESET DB7 RF CP THREESTATE NOISE AND SPUR SETTING 1 DB15 RF CP CURRENT SETTING RF PD POLARITY RESERVED RESERVED NOISE AND SPUR SETTING 2 NOISE AND SPUR SETTING 3 Table V. RF Control Register Map CONTROL BITS THESE BITS SHOULD EACH BE SET TO 0 FOR NORMAL OPERATION P4 0 1 N3 SETTING 0 0 1 N2 N1 NOISE AND SPUR 0 0 1 0 1 1 LOWEST SPUR LOW NOISE AND SPUR LOWEST NOISE P5 0 1 ICP (mA) CP2 0 0 1 1 CP1 0 1 0 1 1.5k 1.125 3.375 5.625 7.7875 2.7k 0.625 1.875 3.125 4.375 5.6k 0.301 0.904 1.506 2.109 P8 0 1 –16– P6 0 1 RF COUNTER RESET DISABLED ENABLED RF CP THREE-STATE DISABLED THREE-STATE RF POWER-DOWN DISABLED ENABLED RF PD POLARITY NEGATIVE POSITIVE REV. 0 ADF4251 DB10 M4 REV. 0 M4 M3 M2 M1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 DB9 DB8 DB7 M3 M2 M1 DB6 COUNTER RESET CP THREESTATE MUXOUT POWERDOWN RESERVED Table VI. Master Register Map DB5 DB4 DB3 P11 P10 P9 CONTROL BITS DB2 DB1 DB0 C3 (0) C2 (1) C1 (1) MUXOUT P9 COUNTER RESET LOGIC LOW IF ANALOG LOCK DETECT IF R DIVIDER OUTPUT IF N DIVIDER OUTPUT RF ANALOG LOCK DETECT RF/IF ANALOG LOCK DETECT IF DIGITAL LOCK DETECT LOGIC HIGH RF R DIVIDER OUTPUT RF N DIVIDER OUTPUT THREE-STATE OUTPUT LOGIC LOW RF DIGITAL LOCK DETECT RF/IF DIGITAL LOCK DETECT LOGIC HIGH LOGIC LOW 0 1 DISABLED ENABLED –17– P10 CP THREE-STATE 0 1 DISABLED THREE-STATE P11 POWER-DOWN 0 1 DISABLED ENABLED P12 RESERVED 0 THIS BIT SHOULD BE SET TO “0” FOR NORMAL OPERATION. ADF4251 IF CP GAIN Table VII. IF N Divider Register Map IF PRESCALER* 12-BIT IF B COUNTER* 6-BIT IF A COUNTER* CONTROL BITS DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 P15 P14 P13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 A6 A5 A4 A3 A2 A1 P14 0 0 1 1 P15 IF CP GAIN 0 1 DISABLED ENABLED P13 0 1 0 1 PRESCALER VALUE 8/9 16/17 32/33 64/65 B12 B11 B10 0 0 . . . 1 0 0 . . . 1 0 0 . . . 1 1 1 1 1 DB2 C3 (1) DB1 DB0 C2 (0) C1 (0) A6 0 0 0 0 . . . 1 A5 0 0 0 0 . . . 1 .......... .......... .......... .......... .......... .......... .......... .......... .......... A2 0 0 1 1 . . . 0 A1 0 1 0 1 . . . 0 A COUNTER DIVIDE RATIO 0 1 2 3 . . . 60 1 1 .......... 0 1 61 1 1 .......... 1 0 62 1 1 .......... 1 1 63 B3 B2 B1 B COUNTER DIVIDE RATIO .......... .......... .......... .......... .......... .......... 0 1 . . . 1 1 0 . . . 0 1 0 . . . 0 3 4 . . . 4092 1 .......... 1 0 1 4093 1 1 .......... 1 1 0 4094 1 1 .......... 1 1 1 4095 *N = BP + A, P IS PRESCALER VALUE. B MUST BE GREATER THAN OR EQUAL TO A FOR CONTIGUOUS VALUES OF N, NMIN IS (P2 – P) . –18– REV. 0 ADF4251 IF REFIN DOUBLER Table VIII. IF R Divider Register Map DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 P16 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 C3 (1) C2 (0) C1 (1) P16 0 1 REV. 0 CONTROL BITS 15-BIT IF R COUNTER R15 0 0 0 0 . . . 32764 R14 0 0 0 0 . . . 1 R13 0 0 0 0 . . . 1 R12 0 0 0 0 . . . 1 .......... .......... .......... .......... .......... .......... .......... .......... .......... R3 0 0 0 1 . . . 1 R2 0 1 1 0 . . . 0 R1 1 0 1 0 . . . 0 DIVIDE RATIO 1 2 3 4 . . . 16380 32765 1 1 1 .......... 1 0 1 16381 32766 1 1 1 .......... 1 1 0 16382 32767 1 1 1 .......... 1 1 1 16383 IF REFIN DOUBLER DISABLED ENABLED –19– ADF4251 IF LDP IF POWERDOWN IF CP THREESTATE IF COUNTER RESET RESERVED DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 CP1 P21 P20 P19 P18 P17 C3 (1) C2 (1) C1 (0) IF CP CURRENT SETTING DB15 DB14 DB13 DB12 DB11 DB10 PR3 PR2 T8 T7 PR1 CP3 DB9 CP2 IF PD POLARITY RF PHASE RESYNC RF PHASE RESYNC Table IX. IF Control Register Map THESE BITS SHOULD BE SET TO 0 FOR NORMAL OPERATION PR3 0 1 PR2 0 1 PR1 0 1 P17 0 1 RF PHASE RESYNC DISABLED ENABLED P18 0 1 P19 0 1 ICP (mA) IF CP3 0 0 0 0 1 1 1 1 IF CP2 0 0 1 1 0 0 1 1 IF CP1 0 1 0 1 0 1 0 1 1.5k 1.125 2.25 3.375 4.5 5.625 6.75 7.7875 9 2.7k 0.625 1.25 1.875 2.5 3.125 3.75 4.375 5.0 5.6k 0.301 0.602 0.904 1.205 1.506 1.808 2.109 2.411 P20 0 1 P21 0 1 –20– CONTROL BITS IF COUNTER RESET DISABLED ENABLED IF CP THREE-STATE DISABLED THREE-STATE IF POWER-DOWN DISABLED ENABLED IF LDP 3 5 IF PD POLARITY NEGATIVE POSITIVE REV. 0 ADF4251 RF N DIVIDER REGISTER (Address R0) RF CONTROL REGISTER (Address R2) With R0[2, 1, 0] set to [0, 0, 0], the on-chip RF N Divider register will be programmed. Table III shows the input data format for programming this register. With R2[2, 1, 0] set to [0, 1, 0], the on-chip RF control register will be programmed. Table V shows the input data format for programming this register. Upon initialization, DB15–DB11 should all be set to 0. 8-Bit RF INT Value These eight bits control what is loaded as the INT value. This is used to determine the overall feedback division factor. It is used in Equation 1. 12-Bit RF FRAC Value These 12 bits control what is loaded as the FRAC value into the fractional interpolator. This is part of what determines the overall feedback division factor. It is used in Equation 1. The FRAC value must be less than or equal to the value loaded into the MOD register. RF R DIVIDER REGISTER (Address R1) With R1[2, 1, 0] set to [0, 0, 1], the on-chip RF R Divider register will be programmed. Table IV shows the input data format for programming this register. RF Prescaler (P/P + 1) The RF dual-modulus prescaler (P/P +1), along with the INT, FRAC, and MOD counters, determine the overall division ratio from the RFIN to the PFD input. Operating at CML levels, it takes the clock from the RF input stage and divides it down to a manageable frequency for the CMOS counters. It is based on a synchronous 4/5 core (see Table IV). RF REFIN Doubler Setting this bit to 0 feeds the REFIN signal directly to the 4-bit RF R counter, disabling the doubler. Setting this bit to 1 multiplies the REFIN frequency by a factor of 2 before feeding into the 4bit RF R counter. When the doubler is disabled, the REFIN falling edge is the active edge at the PFD input to the fractional-N synthesizer. When the doubler is enabled, both the rising and falling edges of REFIN become active edges at the PFD input. When the doubler is enabled and lowest spur mode is chosen, the in-band phase noise performance is sensitive to the REFIN duty cycle. The phase noise degradation can be as much as 5 dB for REFIN duty cycles outside a 45% to 55% range. The phase noise is insensitive to REFIN duty cycle in the lowest noise mode and in low noise and spur mode. The phase noise is insensitive to REFIN duty cycle when the doubler is disabled. 4-Bit RF R Counter The 4-bit RF R counter allows the input reference frequency (REFIN) to be divided down to produce the reference clock to the phase frequency detector (PFD). Division ratios from 1 to 15 are allowed. Noise and Spur Setting The noise and spur setting (R2[15, 11, 06]) is a feature that allows the user to optimize his or her design either for improved spurious performance or for improved phase noise performance. When set to [0, 0, 0], the lowest spurs setting is chosen. Here, dither is enabled. This randomizes the fractional quantization noise so that it looks more like white noise than spurious noise. This means that the part is optimized for improved spurious performance. This operation would normally be used when the PLL closed-loop bandwidth is wide1 for fast-locking applications. A wide loop filter does not attenuate the spurs to a level that a narrow2 loop bandwidth would. When this bit is set to [0, 0, 1], the low noise and spur setting is enabled. Here, dither is disabled. This optimizes the synthesizer to operate with improved noise performance. However, the spurious performance is degraded in this mode compared to lowest spurs setting. To improve noise performance even further, another option is available that reduces the phase noise. This is the lowest noise setting [1, 1, 1]. As well as disabling the dither, it also ensures the charge pump is operating in an optimum region for noise performance. This setting is extremely useful where a narrow loop filter bandwidth is available. The synthesizer ensures extremely low noise and the filter attenuates the spurs. The Typical Performance Characteristics (TPCs) give the user an idea of the trade-off in a typical WCDMA setup for the different noise and spur settings. RF Counter Reset DB3 is the RF counter reset bit for the ADF4251. When this is 1, the RF synthesizer counters are held in reset. For normal operation, this bit should be 0. RF Charge Pump Three-State This bit puts the charge pump into three-state mode when programmed to a 1. It should be set to 0 for normal operation. RF Power-Down DB5 on the ADF4251 provides the programmable power-down mode. Setting this bit to a 1 will perform a power-down on both the RF and IF sections. Setting this bit to 0 will return the RF and IF sections to normal operation. While in software powerdown, the part will retain all information in its registers. Only when supplies are removed will the register contents be lost. When a power-down is activated, the following events occur: 12-Bit Interpolator Modulus This programmable register sets the fractional modulus. This is the ratio of the PFD frequency to the channel step resolution on the RF output. 1. All active RF dc current paths are removed. 2. The RF synthesizer counters are forced to their load state conditions. 3. The RF charge pump is forced into three-state mode. 4. The RF digital lock detect circuitry is reset. 5. The RFIN input is debiased. 6. The input register remains active and capable of loading and latching data. NOTES 1 Wide loop bandwidth is seen as a loop bandwidth greater than 1/10th of the RFOUT channel step resolution (F RES). 2 Narrow loop bandwidth is seen as a loop bandwidth less than 1/10th of the RFOUT channel step resolution (F RES). REV. 0 –21– ADF4251 RF Phase Detector Polarity IF CP Gain DB7 in the ADF4251 sets the RF phase detector polarity. When the VCO characteristics are positive, this should be set to 1. When they are negative, it should be set to 0. When set to 1, this bit changes the IF charge pump current setting to its maximum value. When the bit is set to 0, the charge pump current reverts back to its previous state. RF Charge Pump Current Setting IF Prescaler DB9 and DB10 set the RF charge pump current setting. This should be set to whatever charge pump current the loop filter has been designed with (see Table V). The dual-modulus prescaler (P/P + 1), along with the IF A and IF B counters, determine the overall division ratio, N, to be realized (N = PB + A) from the IFIN to the IF PFD input. Operating at CML levels, it takes the clock from the IF input stage and divides it down to a manageable frequency for the CMOS counters. It is based on a synchronous 4/5 core. See Equation 2 and Table VII. RF Test Modes These bits should be set to 0, 0, 0 for normal operation. MASTER REGISTER (Address R3) IF B and A Counter The IF A and IF B counters, in conjunction with the dual modulus prescaler, make it possible to generate output frequencies that are spaced only by the reference frequency (REFIN), divided by R. The equation for the IFOUT VCO frequency is given in Equation 2. With R3[2, 1, 0] set to 0, 1, 1, the on-chip master register will be programmed. Table VI shows the input data format for programming the Master Register. RF and IF Counter Reset DB3 is the counter reset bit for the ADF4251. When this is 1, both the RF and IF R, INT, and MOD counters are held in reset. For normal operation, this bit should be 0. Upon powering up, the DB3 bit needs to be disabled, the INT counter resumes counting in “close” alignment with the R counter. (The maximum error is one prescaler cycle). IF R DIVIDER REGISTER (Address R5) With R5[2, 1, 0] set to 1, 0, 1, the on-chip IF R divider register will be programmed. Table VIII shows the input data format for programming this register. IF REFIN Doubler Charge Pump Three-State This bit puts both the RF and IF charge pump into three-state mode when programmed to a 1. It should be set to 0 for normal operation. Power-Down R3[3] on the ADF4251 provides the programmable power-down mode. Setting this bit to a 1 will perform a power-down on both the RF and IF sections. Setting this bit to 0 will return the RF and IF sections to normal operation. While in software powerdown, the part will retain all information in its registers. Only when supplies are removed will the register contents be lost. When a power-down is activated, the following events occur: 1. 2. 3. 4. 5. 6. 7. Setting this bit to 0 feeds the REFIN signal directly to the 15-bit IF R counter. Setting this bit to 1 multiplies the REFIN frequency by a factor of 2 before feeding into the 15-bit IF R counter. 15-Bit IF R Counter The 15-bit IF R counter allows the input reference frequency (REFIN) to be divided down to produce the reference clock to the IF phase frequency detector (PFD). Division ratios from 1 to 32767 are allowed. IF CONTROL REGISTER (Address R6) With R6[2, 1, 0] set to 1, 1, 0, the on-chip IF control register will be programmed. Table IX shows the input data format for programming this register. Upon initialization, DB15–DB11 should all be set to 0. All active dc current paths are removed. The RF and IF counters are forced to their load state conditions. The RF and IF charge pumps are forced into three-state mode. The digital lock detect circuitry is reset. The RFIN input and IFIN input are debiased. The oscillator input buffer circuitry is disabled. The input register remains active and capable of loading and latching data. IF Counter Reset DB3 is the IF counter reset bit for the ADF4251. When this is 1, the IF synthesizer counters are held in reset. For normal operation, this bit should be 0. MUXOUT Control IF Charge Pump Three-State The on-chip multiplexer is controlled by R3[10–7] on the ADF4251. Table VI shows the truth table. This bit puts the IF charge pump into three-state mode when programmed to a 1. It should be set to 0 for normal operation. If the user updates the RF control register or the IF control register, the MUXOUT contents will be lost. To retrieve the MUXOUT signal, the user must write to the Master Register. IF Power-Down IF N DIVIDER REGISTER (Address R4) With R4[2, 1, 0] set to [1, 0, 0], the on-chip IF N divider register will be programmed. Table VII shows the input data format for programming this register. DB5 on the ADF4251 provides the programmable power-down mode. Setting this bit to a 1 will perform a power-down on the IF section. Setting this bit to 0 will return the section to normal operation. While in software power-down, the part will retain all information in its registers. Only when supplies are removed will the register contents be lost. –22– REV. 0 ADF4251 and R6 are not programmed so that the rest of the IF circuitry remains in power-down. When a power-down is activated, the following events occur: 1. All active IF dc current paths are removed. 2. The IF synthesizer counters are forced to their load state conditions. 3. The IF charge pump is forced into three-state mode. 4. The IF digital lock detect circuitry is reset. 5. The IFIN input is debiased. 6. The input register remains active and capable of loading and latching data. DEVICE PROGRAMMING AFTER INITIAL POWER-UP After initially applying power to the supply pins, there are three ways to operate the device. RF and IF Synthesizers Operational All registers must be written to when powering up both the RF and IF synthesizer. IF Phase Detector Polarity RF Synthesizer Operational, IF Power-Down DB7 in the ADF4251 sets the IF phase detector polarity. When the VCO characteristics are positive, this should be set to 1. When they are negative, it should be set to 0. It is necessary to write to registers R3, R2, R1, and R0 only when powering up the RF synthesizer only. The IF side will remain in power-down until registers R6, R5, R4, and R3 are written to. IF Charge Pump Current Setting DB8, DB9, and DB10 set the IF charge pump current setting. This should be set to whatever charge pump current the loop filter has been designed with (see Table VII). IF Synthesizer Operational, RF Power-Down IF Test Modes It is necessary to write only to registers R6, R5, R4, and R3 when powering up the IF synthesizer only. The RF side will remain in power-down until registers R3, R2, R1, and R0 are written to. These bits should be set to 0, 0 for normal operation. RF Synthesizer: An Example RF Phase Resync The RF synthesizer should be programmed as follows: Setting the Phase Resync Bits [15, 14, 11] to 1, 1, 1 enables the phase resync feature. With a fractional modulus of M, a fractional-N PLL can settle with any one of (2 ⫻ )/M valid phase offsets with respect to the reference input. This is different to integer-N (where the RF output always settles to the same static phase offset with respect to the input reference, which is zero ideally), but does not matter in most applications where all that is required is consistent frequency lock. Ê FRAC ˆ RFOUT = Á INT + ¥ FPFD MOD ˜¯ Ë (4) where RFOUT = the RF frequency output, INT = the integer division factor, FRAC = the fractionality, and MOD = the modulus. Ê 1 + Dˆ FPFD = Á REFIN ¥ R ˜¯ Ë For applications where a consistent phase relationship between the output and reference is required (i.e., digital beamforming), the ADF4251 fractional-N synthesizer can be used with the phase resync feature enabled. This ensures that if the user programs the PLL to jump from frequency (and Phase) A to frequency (and Phase) B and back again to frequency A, the PLL will return to the original phase (Phase A). When enabled, it will activate every time the user programs register R0 or R1 to set a new output frequency. However, if a cycle slip occurs in the settling transient after the phase re-resync operation, the phase resync will be lost. This can be avoided by delaying the resync activation until the locking transient is close to its final frequency. In the IF R Divider register, Bits R5[17–3] are used to set a time interval from when the new channel is programmed to the time the resync is activated. Although the time interval resolution available from the 15-bit IF R register is one REFIN clock cycle, IF R should be programmed to be a value that is an integer multiple of the programmed MOD value to set a time interval that is at least as long as the RF PLL loop’s lock time. For example, if REFIN = 26 MHz, MOD = 130 to give 200 kHz output steps (FRES), and the RF loop has a settling time of 150 µs, then IF R should be programmed to 3900, as: where REF IN = the reference frequency input, D = the RF REFIN Doubler Bit, and R = the RF reference division factor. For example, in a GSM 1800 system where 1.8 GHz RF frequency output (RFOUT) is required, a 13 MHz reference frequency input (REF IN) is available and a 200 kHz channel resolution (FRES) is required on the RF output. MOD = MOD = REFIN FRES 13 MHz 200 kHz = 65 So, from Equation 5: 1+ 0 = 13 MHz 1 Ê FRAC ˆ 1.8 GHz = 13 MHz ¥ Á INT + 65 ˜¯ Ë FPFD = 13 MHz ¥ where INT = 138 and FRAC = 30. IF Synthesizer: An Example The IF synthesizer should be programmed as follows: [ 26 MHz ¥ 150 ms = 3900 Note that if it is required to use the IF synthesizer with phase resync enabled on the RF synth, the IF synth must operate with a PFD frequency of 26 MHz/3900. In an application where the IF synth is not required, the user should ensure that registers R4 (5) ] IFOUT = (P ¥ B ) + A ¥ FPFD where IFOUT = the output frequency of external voltage controlled oscillator (VCO), P = the IF prescaler, B = the B counter value, and A = the A counter value. Equation 5 applies in this example as well. REV. 0 (6) –23– ADF4251 The modulus would be reprogrammed to 65 for GSM1800 operation (13 MHz/65 = 200 kHz). It is important that the PFD frequency remains constant (13 MHz). This allows the user to design one loop filter that can be used in both setups without running into stability issues. It is the ratio of the RF frequency to the PFD frequency that affects the loop design. Keeping this relationship constant and instead changing the modulus factor, results in a stable filter. For example, in a GSM1800 system, where 540 MHz IF frequency output (IFOUT) is required, a 13 MHz reference frequency input (REFIN) is available and a 200 kHz channel resolution (FRES) is required on the IF output. The prescaler is set to 16/17. IF REFIN doubler is disabled. By Equation 5: 200 kHz = 13 MHz ¥ 1+ 0 R Spurious Optimization and Fastlock As mentioned in the Noise and Spur Setting section, the part can be optimized for spurious performance. However, in fast-locking applications, the loop bandwidth needs to be wide. Therefore, the filter does not provide much attenuation of the spurious. The programmable charge pump can be used to get around this issue. The filter is designed for a narrow loop bandwidth so that steady-state spurious specifications are met. This is designed using the lowest charge pump current setting. To implement fastlock during a frequency jump, the charge pump current is set to the maximum setting for the duration of the jump. This has the effect of widening the loop bandwidth, which improves lock time. When the PLL has locked to the new frequency, the charge pump is again programmed to the lowest charge pump current setting. This will narrow the loop bandwidth to its original cutoff frequency to allow for better attenuation of the spurious than the wide loop bandwidth. if R = 65. By Equation 6: [ 540 MHz = 200 kHz ¥ (16 ¥ B ) + A ] if B = 168 and A = 12. Modulus The choice of modulus (MOD) depends on the reference signal (REFIN) available and the channel resolution (FRES) required at the RF output. For example, a GSM system with 13 MHz REFIN would set the modulus to 65. This means that the RF output resolution (FRES) is the 200 kHz (13 MHz/65) necessary for GSM. Reference Doubler and Reference Divider There is a reference doubler on-chip. This allows the input reference signal to be doubled. This is useful for increasing the PFD comparison frequency. Making the PFD frequency higher improves the noise performance of the system. Doubling the PFD frequency will usually result in an improvement in noise performance of 3 dB. It is important to note that the PFD cannot be operated above 30 MHz. This is due to a limitation in the speed of the ⌺-⌬ circuit of the N divider. Spurious Signals—Predicting Where They Will Appear 12-Bit Programmable Modulus Unlike most other fractional-N PLLs, the ADF4251 allows the user to program the modulus over a 12-bit range. This means that the user can set up the part in many different configurations for his or her application, when combined with the reference doubler and the 4-bit R counter. Take for example an application that requires 1.75 GHz RF and 200 kHz channel step resolution. The system has a 13 MHz reference signal. One possible setup is feeding the 13 MHz directly to the PFD and programming the modulus to divide by 65. This would result in the required 200 kHz resolution. Another possible setup is using the reference doubler to create 26 MHz from the 13 MHz input signal. This 26 MHz is then fed into the PFD. The modulus is now programmed to divide by 130. This also results in 200 kHz resolution. This would offer superior phase noise performance over the previous setup. The programmable modulus is also very useful for multistandard applications. If a dual-mode phone requires PDC and GSM1800 standards, the programmable modulus is of huge benefit. PDC requires 25 kHz channel step resolution, whereas GSM1800 requires 200 kHz channel step resolution. A 13 MHz reference signal could be fed directly to the PFD. The modulus would be programmed to 520 when in PDC mode (13 MHz /520 = 25 kHz). Just as in integer-N PLLs, spurs will appear at PFD frequency offsets on either side of the carrier (and multiples of the PFD frequency). In a fractional-N PLL, spurs will also appear at frequencies equal to the RFOUT channel step resolution (FRES). The ADF4251 uses a high order fractional interpolator engine. This results in spurious signals also appearing at frequencies equal to 1/2 of the channel step resolution. For example, examine the GSM-1800 setup with a 26 MHz PFD and 200 kHz resolution. Spurs will appear at ±26 MHz from the RF carrier (at an extremely low level due to filtering). Also, there will be spurs at ±200 kHz from the RF carrier. Due to the fractional interpolator architecture used in the ADF4251, spurs will also appear at ±100 kHz from the RF carrier. Harmonics of all spurs mentioned will also appear. With lowest spur setting enabled, the spurs will be attenuated into the noise floor. Prescaler The prescaler limits the INT value. With P = 4/5, NMIN = 31. With P = 8/9, NMIN = 91. The prescaler can also influence the phase noise performance. If INT < 91, a prescaler of 4/5 should be used. For applications where INT > 91, P = 8/9 should be used for optimum noise performance. Filter Design: ADIsimPLL A filter design and analysis program is available to help users implement their PLL design. Visit www.analog.com/pll for a free download of the ADIsimPLL software. The software designs, simulates, and analyzes the entire PLL frequency domain and time domain response. Various passive and active filter architectures are allowed. –24– REV. 0 ADF4251 IF Side Not In Use If the IF side is not being used, the following pinout is recommended for the IF side: SCLOCK SCLK MOSI Pin No. Mnemonic Description 14 AGND2 Short to all other ground pins. 15 IFINB Leave open circuit. (This is biased up to VDD/2 internally.) 16 IFINA Leave open circuit. (This is biased up to VDD/2 internally.) SDATA LE CE I/O PORTS 19 CP_IF Leave open circuit. (This is internally three-stated until power-up.) 20 V P2 Short to VP1. (VP1 is the RF CP supply.) 21 VDD2 Short to VDD1 (VDD1 is the RF VDD supply.) MUXOUT (LOCK DETECT) ADuC812 ADF4251 Figure 8. ADuC812 to ADF4251 Interface ADuC812 Interface Figure 8 shows the interface between the ADF4251 and the ADuC812 microconverter. Since the ADuC812 is based on an 8051 core, this interface can be used with any 8051-based microcontroller. The microconverter is set up for SPI Master mode with CPHA = 0. To initiate the operation, the I/O port driving LE is brought low. Each latch of the ADF4251 needs (at most) a 24-bit word. This is accomplished by writing three 8-bit bytes from the microconverter to the device. When the third byte has been written, the LE input should be brought high to complete the transfer. INTERFACING The ADF4251 has a simple SPI compatible serial interface for writing to the device. SCLK, SDATA, and LE control the data transfer. When LE (Latch Enable) goes high, the 24 bits that have been clocked into the input register on each rising edge of SCLK will be transferred to the appropriate latch. See Figure 1 for the Timing Diagram and Table I for the Control Bit Truth Table. I/O port lines on the ADuC812 are also used to control powerdown (CE input) and to detect lock (MUXOUT configured as lock detect and polled by the port input). The maximum allowable serial clock rate is 20 MHz. This means that the maximum update rate possible for the device is 833 kHz or one update every 1.2 µs. This is certainly more than adequate for systems that will have typical lock times in hundreds of microseconds. When operating in the mode described, the maximum SCLOCK rate of the ADuC812 is 4 MHz. This means that the maximum rate at which the output frequency can be changed will be 166 kHz. VP POWER-DOWN CONTROL S VDD IFOUT D 18 VCC 18 100pF IF VCO VDD DVDD VP IF LOOP FILTER RFOUT IN 100pF 18 VDD ADG702 IF CP GND 100pF CE RF LOOP FILTER RF CP VCC 100pF 18 RF VCO GND RSET ADF4251 REFIN GND 2.7k REFIN 100pF RFINB DGND IFINB AGND 100pF RFINA CPGND 51 100pF IFINA 51 100pF DECOUPLING CAPACITORS AND INTERFACE SIGNALS HAVE BEEN OMITTED FROM THE DIAGRAM IN THE INTERESTS OF GREATER CLARITY. Figure 9. Power-Down Circuit REV. 0 –25– 18 18 ADF4251 Powerdown Circuit SCLK The attached circuit in Figure 10 shows how to shut down the ADF4251 and the accompanying RF and IF VCO. The ADG701 switch goes closed circuit when a Logic High is applied to the IN input. The low cost switch is available in SOT-23 and SOIC packages. SCLK DT SDATA TFS LE CE I/O FLAGS PCB DESIGN GUIDELINES FOR CHIP-SCALE PACKAGE MUXOUT (LOCK DETECT) The leads on the chip-scale package (CP-24) are rectangular. The printed circuit board pad for these should be 0.1 mm longer than the package land length and 0.05 mm wider than the package land width. The land should be centered on the pad. This will ensure that the solder joint size is maximized. ADF4251 ADSP-21xx Figure 10. ADSP-21xx to ADF4251 Interface ADSP-2181 Interface The bottom of the chip-scale package has a central thermal pad. The thermal pad on the printed circuit board should be at least as large as this exposed pad. On the printed circuit board, there should be a clearance of at least 0.25 mm between the thermal pad and the inner edges of the pad pattern. This will ensure that shorting is avoided. Figure 10 shows the interface between the ADF4251 and the ADSP-21xx digital signal processor. Each latch of the ADF4251 needs (at most) a 24-bit word. The easiest way to accomplish this using the ADSP-21xx family is to use the autobuffered transmit mode of operation with alternate framing. This provides a means for transmitting an entire block of serial data before an interrupt is generated. Set up the word length for eight bits and use three memory locations for each 24-bit word. To program each 24-bit latch, store the three 8-bit bytes, enable the autobuffered mode, and then write to the transmit register of the DSP. This last operation initiates the autobuffer transfer. R48 0 6.3V VDD VP VVCO 6.3V Thermal vias may be used on the printed circuit board thermal pad to improve thermal performance of the package. If vias are used, they should be incorporated in the thermal pad at 1.2 mm pitch grid. The via diameter should be between 0.3 mm and 0.33 mm, and the via barrel should be plated with 1 oz copper to plug the via. R44 0 VP R1 20 6.3V VVCO R49 0 6.3V 6.3V C7 22F C11 22F C29 22F C8 10pF C12 10pF C30 10pF 6.3V VDD’ C10 10pF C6 10pF C15 100pF 14 VCC R12 18 R13 C16 18 100pF R14 18 10 RF OUT VIN 2 C19 2.2nF C18 270pF R16 7.5k C23 10nF U1 C24 100nF ADF4251BCP VCC 2 V IN C25 3.3nF R19 270 REFIN T13 J5 C14 1nF C43 100pF R47 0 3V 3 R46 0 O/P 4 B+ C45 10pF GND Y3 2 R27 10k T16 R28 10k MUXOUT R27 2.7k R11 51 C26 R21 100pF 18 R23 18 C28 100pF C44 100pF 5V R45 0 R22 18 R24 51 RFINB C13 1nF 10 RFINA IFINA C17 100pF RFOUT VCO1 VCO190–1730T CPGND1 R15 51 C46 22F R20 470 CPRF CPIF C20 82pF VCO2 VCO190–540T C27 100pF 14 VP1 VP2 R17 13k RFOUT J7 DVDD C4 10pF R43 0 VDD3 C5 22F VDD2 C9 22F VDD1 IFOUT J6 C3 22F AGND1 LE DGND DATA AGND2 CLK CPGND2 VDD R29 10k D4 T14 Figure 11. Typical PLL Circuit Schematic –26– REV. 0 ADF4251 OUTLINE DIMENSIONS 24-Lead Frame Chip Scale Package [LFCSP] 4 mm 4 mm Body (CP-24) Dimensions shown in millimeters 0.60 MAX 4.0 BSC SQ PIN 1 INDICATOR 0.50 BSC 3.75 BSC SQ TOP VIEW 0.50 0.40 0.30 1.00 0.90 0.85 12 MAX 0.25 REF SEATING PLANE 0.25 MIN 0.60 MAX 1.00 MAX 0.65 NOM 0.30 0.23 0.18 24 19 18 BOTTOM VIEW 13 12 7 2.50 REF 0.05 MAX 0.02 NOM 0.20 REF COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-2 REV. 0 –27– PIN 1 INDICATOR 1 6 2.25 1.70 SQ 0.75 –28– C03269–0–10/03(0)