Data sheet acquired from Cypress Semiconductor Corporation. Data sheet modified to remove devices not offered. CY54/74FCT841T 10-Bit Latch SCCS035 - September 1994 - Revised March 2000 Features • High-speed parallel latches • Buffered common latch enable input • Function, pinout, and drive compatible with FCT, F, and AM29841 logic • FCT-C speed at 5.5 ns max. (Com’l) FCT-B speed at 6.5 ns max. (Com’l) • Reduced VOH (typically = 3.3V) versions of equivalent FCT functions • Edge-rate control circuitry for significantly improved noise characteristics • Power-off disable feature • Matched rise and fall times • ESD > 2000V • Fully compatible with TTL input and output logic levels • Sink current 64 mA (Com’l), 32 mA (Mil) Source current 32 mA (Com’l), 12 mA (Mil) Functional Description The FCT841T bus interface latch is designed to eliminate the extra packages required to buffer existing latches and provide extra data width for wider address/data paths or buses carrying parity. The FCT841T is a buffered 10-bit wide version of the FCT373 function. The FCT841T high-performance interface is designed for high-capacitance load drive capability while providing low-capacitance bus loading at both inputs and outputs. Outputs are designed for low-capacitance bus loading in the high impedance state and are designed with a power-off disable feature to allow for live insertion of boards. Functional Block Diagram D1 D0 D LE Q D2 D3 D4 D5 DN- 1 DN D Q D Q D Q D Q D Q D Q D Q LE Q LE Q LE Q LE Q LE Q LE Q LE Q LE OE Y0 Y2 Y1 Logic Block Diagram D 10 D Q LE LE OE Y3 Y4 Y5 YN- 1 YN Pin Configurations 10 DIP/QSOP/SOIC Top View Y OE 1 24 VCC D0 2 23 Y0 D1 3 22 Y1 D2 4 21 Y2 D3 5 20 Y3 D4 6 19 Y4 D5 7 18 Y5 D6 8 17 Y6 D7 9 16 D8 10 15 Y7 Y8 D9 11 14 Y9 GND 12 13 LE Copyright © 2000, Texas Instruments Incorporated CY54/74FCT841T Pin Description Name I/O Description D I The latch data inputs. LE I The latch enable input. The latches are transparent when LE is HIGH. Input data is latched on the HIGH-to-LOW transition. Y O The three-state latch outputs. OE I The output enable control. When the OE is LOW, the outputs are enabled. When OE is HIGH, the outputs Y1 are in the high impedance (off) state. Function Table[1] Inputs Internal Outputs OE LE D O Y Function H H H X H H X L H X L H Z Z Z High Z H L X NC Z Latched (High Z) L L H H L H L H L H Transparent L L X NC NC Latched Maximum Ratings[2, 3] DC Output Current (Maximum Sink Current/Pin) ...... 120 mA Power Dissipation .......................................................... 0.5W (Above which the useful life may be impaired. For user guidelines, not tested.) Static Discharge Voltage............................................>2001V (per MIL-STD-883, Method 3015) Storage Temperature .................................–65°C to +150°C Ambient Temperature with Power Applied .............................................–65°C to +135°C Operating Range Supply Voltage to Ground Potential ............... –0.5V to +7.0V Range DC Input Voltage............................................ –0.5V to +7.0V DC Output Voltage ......................................... –0.5V to +7.0V Range VCC Commercial All –40°C to +85°C 5V ± 5% Military[4] All –55°C to +125°C 5V ± 10% Notes: 1. H = HIGH Voltage Level, L = LOW Voltage Level, X = Don’t Care, NC = No Change, Z = High Impedance. 2. Unless otherwise noted, these limits are over the operating free-air temperature range. 3. Unused inputs must always be connected to an appropriate logic voltage level, preferably either VCC or ground. 4. TA is the “instant on” case temperature. 2 Ambient Temperature CY54/74FCT841T Electrical Characteristics Over the Operating Range Parameter VOH Description Output HIGH Voltage VOL Output LOW Voltage VIH Input HIGH Voltage VIL Input LOW Voltage [6] Test Conditions Min. Typ.[5] Max. Unit VCC= Min., IOH = −32 mA Com’l 2.0 VCC= Min., IOH = −15 mA Com’l 2.4 3.3 V VCC= Min., IOH = −12 mA Mil 2.4 3.3 V VCC= Min., IOL = 64 mA Com’l VCC= Min., IOL = 32 mA Mil V 0.3 0.55 V 0.3 0.55 V 2.0 V 0.8 V VH Hysteresis All inputs 0.2 VIK Input Clamp Diode Voltage VCC= Min., IIN= −18 mA −0.7 −1.2 V II Input HIGH Current VCC= Max., VIN= VCC 5 µA IIH Input HIGH Current VCC= Max., VIN= 2.7V ±1 µA IIL Input LOW Current VCC= Max., VIN= 0.5V ±1 µA IOZH Off State HIGH-Level Output Current VCC = Max., VOUT = 2.7V 10 µA IOZL Off State LOW-Level Output Current VCC = Max., VOUT = 0.5V −10 µA IOS Output Short Circuit Current[7] VCC = Max., VOUT = 0.0V −225 mA IOFF Power-Off Disable VCC = 0V, VOUT = 4.5V ±1 µA −60 −120 V Capacitance[6] Parameter Description Typ.[5] Max. Unit CIN Input Capacitance 5 10 pF COUT Output Capacitance 9 12 pF Notes: 5. Typical values are at VCC=5.0V, TA=+25˚C ambient. 6. This parameter is specified but not tested. 7. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter tests, IOS tests should be performed last. 3 CY54/74FCT841T Power Supply Characteristics Parameter Description Test Conditions Typ.[5] Max. Unit ICC Quiescent Power Supply Current VCC = Max., VIN ≤ 0.2V, VIN ≥ VCC-0.2V 0.1 0.2 mA ∆ICC Quiescent Power Supply Current (TTL inputs HIGH) VCC = Max., VIN = 3.4V, f1 = 0, Outputs Open[8] 0.5 2.0 mA ICCD Dynamic Power Supply Current[9] VCC = Max., 50% Duty Cycle, Outputs Open, One Input Toggling, OE =GND, LE = VCC, VIN ≤ 0.2V or VIN ≥ VCC−0.2V 0.06 0.12 mA/MHz IC Total Power Supply Current[10] VCC=Max., 50% Duty Cycle, Outputs Open, One Bit Toggling at f1=10 MHz, OE = GND, LE = VCC, VIN ≤ 0.2V or VIN ≥ VCC−0.2V 0.7 1.4 mA VCC = Max., 50% Duty Cycle, Outputs Open, One Bit Toggling at f1 =10 MHz, OE = GND, LE = VCC, VIN = 3.4V or VIN = GND 1.0 2.4 mA VCC = Max., 50% Duty Cycle, Outputs Open, Ten Bits Toggling at f1 = 2.5 MHz, OE =GND, LE = VCC, VIN ≤ 0.2V or VIN ≥ VCC−0.2V 1.0 3.2[11] mA VCC=Max., 50% Duty Cycle, Outputs Open, Ten Bits Toggling at f1 = 2.5 MHz, OE = GND, LE = VCC, VIN = 3.4V or VIN = GND 4.1 13.2[11] mA Notes: 8. Per TTL driven input (VIN=3.4V); all other inputs at VCC or GND. 9. This parameter is not directly testable, but is derived for use in Total Power Supply calculations. = IQUIESCENT + IINPUTS + IDYNAMIC 10. IC IC = ICC+∆ICCDHNT+ICCD(f0/2 + f1N1) ICC = Quiescent Current with CMOS input levels ∆ICC = Power Supply Current for a TTL HIGH input (VIN=3.4V) DH = Duty Cycle for TTL inputs HIGH NT = Number of TTL inputs at DH ICCD = Dynamic Current caused by an input transition pair HLH or LHL) = Clock frequency for registered devices, otherwise zero f0 = Input signal frequency f1 N1 = Number of inputs changing at f1 All currents are in milliamps and all frequencies are in megahertz. 11. Values for these conditions are examples of the ICC formula. These limits are specified but not tested. 4 CY54/74FCT841T Switching Characteristics Over the Operating Range[12] FCT841AT Military FCT841BT FCT841CT Commercial Commercial Commercial Test Load Min. Max. Min. Max. Min. Max. Min. Propagation Delay D1 to Y1 (L =HIGH) CL = 50 pF RL = 500Ω 1.5 10.0 1.5 9.0 1.5 6.5 1.5 5.5 ns 1, 3 Propagation Delay D1 to Y1 (LE=HIGH) CL = 300 pF RL = 500Ω 1.5 15.0 1.5 13.0 1.5 13.0 1.5 13.0 ns 1, 3 tSU Data to LE Set-Up Time CL = 50 pF RL = 500Ω 2.5 2.5 2.5 2.5 ns 9 tH Data to LE Hold Time CL = 50 pF RL = 500Ω 3.0 2.5 2.5 2.5 ns 9 tPLH tPHL Propagation Delay LE to Y1 CL = 50 pF RL = 500Ω 1.5 13.0 1.5 12.0 1.5 8.0 1.5 6.4 ns 1, 3 Propagation Delay LE to Y1 [12] CL = 300 pF RL = 500Ω 1.5 20.0 1.5 16.0 1.5 15.5 1.5 15.0 ns 1, 3 tW LE Pulse Width (HIGH) CL = 50 pF RL = 500Ω 5.0 ns 5 tPZH tPZL Output Enable Time OE to Y1 CL = 50 pF RL = 500Ω 1.5 13.0 1.5 11.5 1.5 8.0 1.5 6.5 ns 1, 7, 8 Output Enable Time OE to Y1[12] CL = 300 pF RL = 500Ω 1.5 25.0 1.5 23.0 1.5 14.0 1.5 12.0 ns 1, 7, 8 Output Disable Time OE to Y1[12] CL = 5 pF RL = 500Ω 1.5 9.0 1.5 7.0 1.5 6.0 1.5 5.7 ns 1, 7, 8 Output Disable Time OE to Y1 CL = 50 pF RL = 500Ω 1.5 10.0 1.5 8.0 1.5 7.0 1.5 6.0 ns 1, 7, 8 Parameter tPLH tPHL tPHZ tPLZ Description 4.0 4.0 Fig. Max. Unit No.[13] 4.0 Ordering Information Speed (ns) 5.5 Ordering Code Package Name Package Type CY74FCT841CTQCT Q13 24-Lead (150-Mil) QSOP CY74FCT841CTSOC/SOCT S13 24-Lead (300-Mil) Molded SOIC P13/P13A Operating Range Commercial 6.5 CY74FCT841BTPC 24-Lead (300-Mil) Molded DIP Commercial 9.0 CY74FCT841ATSOC/SOCT S13 24-Lead (300-Mil) Molded SOIC Commercial 10.0 CY54FCT841ATDMB D14 24-Lead (300-Mil) CerDIP Military Notes: 12. Minimum limits are specified but not tested on Propagation Delays. 13. See “Parameter Measurement Information” in the General Information section. Document #: 38-00273-B 5 CY54/74FCT841T Package Diagrams 24-Lead (300-Mil) CerDIP D14 MIL-STD-1835 D- 9Config.A 24-Lead (300-Mil) Molded DIP P13/P13A 6 CY54/74FCT841T Package Diagrams (continued) 24-Lead Quarter Size Outline Q13 24-Lead (300-Mil) Molded SOIC S13 7 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. 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