ICST ICS843101AG-312LF Femtoclocksâ ¢ crystal-to-lvpecl 312.5mhz frequency margining synthesizer Datasheet

ADVANCE INFORMATION
ICS843101-312
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-LVPECL
312.5MHZ FREQUENCY MARGINING SYNTHESIZER
GENERAL DESCRIPTION
FEATURES
The ICS843101-312 is a low phase-noise
frequency margining synthesizer with freHiPerClockS™ quency margining capability and is a member of
the HiPerClockS™ family of high performance
clock solutions from ICS. In the default mode,
the device nominally generates a 312.5MHz LVPECL output
clock signal from a 25MHz crystal input. There is also a
frequency margining mode available where the device can
be programmed, using the serial interface, to vary the
output frequency up or down from nominal in 2% steps.
The ICS843101-312 is provided in a 16-pin TSSOP.
• One 312.5MHz nominal LVPECL output
ICS
• Selectable crystal oscillator interface designed for 25MHz,
18pF parallel resonant crystal or LVCMOS single-ended
input
• Output frequency can be varied in 2% steps ± from nominal
• VCO range: 560MHz - 690MHz
• RMS phase jitter @ 312.5MHz, using a 25MHz crystal
(1.875MHz-20MHz): <1ps (typical) design target
• Output supply modes
Core/Output
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
• 0°C to 70°C ambient operating temperature
• Available in both standard and lead-free RoHS-complaint
packages
BLOCK DIAGRAM
OE
CLK
Pullup
Pulldown
1
÷P
25MHz
XTAL_IN
PIN ASSIGNMENT
OSC
Phase
Detector
VCO
÷N
560 - 690MHz
0
XTAL_OUT
SEL
Pulldown
S_CLOCK
Pulldown
S_DATA
Pulldown
S_LOAD
Pulldown
MODE
Pulldown
VEE
S_LOAD
S_DATA
Q S_CLOCK
SEL
nQ
OE
VCCA
V CC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
MODE
VCCO
Q
nQ
VEE
CLK
XTAL_OUT
XTAL_IN
ICS843101-312
÷M
16-Lead TSSOP
4.4mm x 5.0mm x 0.92mm
package body
G Package
Top View
Serial Control
The Advance Information presented herein represents a product currently in design or being considered for design. The noted characteristics are
design targets. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
843101AG-312
www.icst.com/products/hiperclocks.html
1
OCTOBER 18, 2005
ADVANCE INFORMATION
ICS843101-312
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-LVPECL
312.5MHZ FREQUENCY MARGINING SYNTHESIZER
FUNCTIONAL DESCRIPTION
The ICS843101-312 features a fully integrated PLL and
therefore requires no external components for setting the
loop bandwidth. A 25MHz fundamental crystal is used as
the input to the on chip oscillator. The output of the oscillator is fed into the pre-divider. In frequency margining
mode, the 25MHz crystal frequency is divided by 2 and
a 12.5MHz reference frequency is applied to the phase
detector. The VCO of the PLL operates over a range of
560MHz to 690MHz. The output of the M divider is also
applied to the phase detector.
quency by adjusting the VCO control voltage. Note that for
some values of M (either too high or too low), the PLL will
not achieve lock. The output of the VCO is scaled by an
output divider prior to being sent to the LVPECL output
buffer. The divider provides a 50% output duty cycle. The
relationship between the crystal input frequency, the M
divider, the VCO frequency and the output frequency
is provided in Table 1. When changing back from frequency margining mode to nominal mode, the device will
return to the default nominal configuration that will provide
312.5 MHz output frequency.
The default mode for the ICS843101-312 is 312.5MHz
output frequency using a 25MHz crystal. The output frequency can be changed by placing the device into the
margining mode using the mode pin and using the serial
interface to program the M feedback divider. Frequency
margining mode operation occurs when the MODE input
is HIGH. The phase detector and the M divider force the
VCO output frequency to be M times the reference fre-
Serial operation occurs when S_LOAD is HIGH. Serial
data can be loaded in either the default mode or the frequency margining mode. The 6-bit shift register is loaded
by sampling the S_DATA bits with the rising edge of
S_CLOCK. After shifting in the 6-bit M divider value,
S_LOAD is transitioned from HIGH to LOW which latches
the contents of the shift-register into the M divider control
register. When S_LOAD is LOW, any transitions of
S_CLOCK or S_DATA are ignored.
TABLE 1. FREQUENCY MARGIN FUNCTION TABLE
XTAL
(MHz)
25
Pre-Divider
(P)
2
Reference
Frequency (MHz)
12.5
Feedback
Divider (M)
45
M-Data
(Binary)
101101
VCO
(MHz)
562.5
Output
Divider (N)
2
Output
Frequency (MHz)
281.25
%
Change
-10.0
25
2
12.5
46
101110
575
2
287.5
-8.0
25
2
12.5
47
101111
587.5
2
293.75
-6.0
25
2
12.5
48
110000
600
2
300
-4.0
25
2
12.5
49
110001
612.5
2
306.25
-2.0
25
2
12.5
50
110010
625
2
312.5
0
25
2
12.5
51
110011
637.5
2
318.75
2.0
25
2
12.5
52
110100
650
2
325
4.0
25
2
12.5
53
110101
662.5
2
331.25
6.0
25
2
12.5
54
110110
675
2
337.5
8.0
25
2
12.5
55
110111
687.5
2
343.75
10.0
SERIAL LOADING
S_CLOCK
M5 M4
S_DATA
t
S
M3
M2
M1
M0
t
t
H
S
S_LOAD
Time
FIGURE 1. SERIAL LOAD OPERATIONS
843101AG-312
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OCTOBER 18, 2005
ADVANCE INFORMATION
ICS843101-312
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-LVPECL
312.5MHZ FREQUENCY MARGINING SYNTHESIZER
TABLE 2. PIN DESCRIPTIONS
Number
Name
1, 12
VEE
Power
2
S_LOAD
Input
3
S_DATA
Input
4
S_CLOCK
Input
5
SEL
Input
6
OE
Input
7
VCCA
Power
8
Power
11
VCC
XTAL_IN,
XTAL_OUT
CL K
13, 14
nQ, Q
Ouput
15
VCCO
Power
9, 10
Type
Input
Input
Description
Negative supply pins.
Pulldown Controls the operation of the Serial input. LVCMOS/LVTTL interface levels.
Shift register serial input. Data sampled on the rising edge of S_CLOCK.
Pulldown
LVCMOS/LVTTL interface levels.
Clock in serial data present at S_DATA input into the shift register on the
Pulldown
rising edge of S_CLOCK. LVCMOS/LVTTL interface levels.
Select pin. When HIGH, selects CLK input.
Pulldown
When LOW, selects XTAL inputs. LVCMOS/LVTTL interface levels.
Output enable pin. Controls enabling and disabling of Q/nQ outputs.
Pullup
LVCMOS/LVTTL interface levels
Analog supply pin.
Core supply pin.
Parallel resonant cr ystal interface. XTAL_OUT is the output, XTAL_IN is the
input.
Pulldown LVCMOS/LVTTL clock input.
Differential output pair. LVPECL interface levels.
Output supply pin.
MODE pin. LOW = default mode. HIGH = frequency margining mode.
16
MODE
Input
Pulldown
LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 3. PIN CHARACTERISTICS
Symbol
Parameter
CIN
Input Capacitance
4
pF
RPULLDOWN
Input Pulldown Resistor
51
kΩ
RPULLUP
Input Pulldown Resistor
51
kΩ
843101AG-312
Test Conditions
Minimum
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3
Typical
Maximum
Units
OCTOBER 18, 2005
ADVANCE INFORMATION
ICS843101-312
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-LVPECL
312.5MHZ FREQUENCY MARGINING SYNTHESIZER
TABLE 4A. OE CONTROL INPUT FUNCTION TABLE
Input
Outputs
OE
0
Q , nQ
HiZ
1
Enabled
TABLE 4B. SEL CONTROL INPUT FUNCTION TABLE
Input
SEL
0
Selected Source
XTAL_IN, XTAL_OUT
1
CLK
TABLE 4C. MODE CONTROL INPUT FUNCTION TABLE
Input
Condition
Mode
0
Q, nQ
Default Mode
1
Frequency Margining Mode
TABLE 4D. SERIAL MODE FUNCTION TABLE
Inputs
Conditions
S_LOAD
S_CLOCK
S_DATA
L
X
X
H
↑
Data
L
X
↓
NOTE: L = LOW
H = HIGH
X = Don't care
↑ = Rising edge transition
↓ = Falling edge transition
843101AG-312
Serial inputs are ignored.
Serial input mode.
Shift register is loaded with data on S_DATA on each rising edge of S_CLOCK.
Contents of the shift register are latched.
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OCTOBER 18, 2005
ADVANCE INFORMATION
ICS843101-312
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-LVPECL
312.5MHZ FREQUENCY MARGINING SYNTHESIZER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC
4.6V
Inputs, VI
-0.5V to VCC + 0.5V
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
Package Thermal Impedance, θJA
89°C/W (0 lfpm)
Storage Temperature, TSTG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 5A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
VCC
Core Supply Voltage
Test Conditions
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
VCCA
Analog Supply Voltage
3.135
3.3
3.465
V
VCCO
Output Supply Voltage
3.135
3.3
3.465
V
IEE
Power Supply Current
TBD
mA
ICC
Core Supply Current
TBD
mA
ICCA
Analog Supply Current
TBD
mA
ICCO
Output Supply Current
TBD
mA
TABLE 5B. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = 3.3V±5%,VCCO = 2.5V±5%, TA = 0°C TO 70°C
Symbol
Parameter
VCC
Core Supply Voltage
Test Conditions
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
VCCA
Analog Supply Voltage
3.135
3.3
3.465
V
VCCO
Output Supply Voltage
2.375
2.5
2.625
V
IEE
Power Supply Current
TBD
mA
ICC
Core Supply Current
TBD
mA
ICCA
Analog Supply Current
TBD
mA
ICCO
Output Supply Current
TBD
mA
TABLE 5C. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 2.5V±5%, TA = 0°C TO 70°C
Symbol
Parameter
VCC
VCCA
Minimum
Typical
Maximum
Units
Core Supply Voltage
2.375
2.5
2.625
V
Analog Supply Voltage
2.375
2.5
2.625
V
VCCO
Output Supply Voltage
2.375
2.5
2.625
V
IEE
Power Supply Current
TBD
mA
ICC
Core Supply Current
TBD
mA
ICCA
Analog Supply Current
TBD
mA
ICCO
Output Supply Current
TBD
mA
843101AG-312
Test Conditions
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OCTOBER 18, 2005
ADVANCE INFORMATION
ICS843101-312
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-LVPECL
312.5MHZ FREQUENCY MARGINING SYNTHESIZER
TABLE 5D. LVCMOS / LVTTL DC CHARACTERISTICS, TA = 0°C TO 70°C
Symbol
VIH
VIL
IIH
IIL
Δt/Δv
Parameter
Test Conditions
Input High Voltage
Input Low Voltage
Input
High Current
Input
Low Current
Input Transistion
Rise/Fall Rate
Minimum Typical
VCC = 3.3V
Maximum
Units
2
VCC + 0.3
V
VCC = 2.5V
1. 7
VCC + 0.3
V
VCC = 3.3V
-0.3
0.8
V
VCC = 2.5V
-0.3
1.7
V
CLK, SEL,
S_DATA, S_LOAD,
S_CLOCK, MODE
VCC = VIN = 3.465
or 2.625V
150
µA
OE
VCC = VIN = 3.465
or 2.625V
5
µA
CLK, SEL,
S_DATA, S_LOAD,
S_CLOCK, MODE
VCC = 3.465V or 2.625V,
VIN = 0V
-5
µA
OE
VCC = 3.465V or 2.625V,
VIN = 0V
-150
µA
OE, SEL,
S_CLOCK, S_DATA,
S_LOAD, MODE
20
ns/v
Maximum
Units
TABLE 5E. LVPECL DC CHARACTERISTICS, TA = 0°C TO 70°C
Symbol
Parameter
Test Conditions
Minimum
Typical
VOH
Output High Voltage; NOTE 1
VCCO - 1.4
VCCO - 0.9
V
VOL
Output Low Voltage; NOTE 1
VCCO - 2.0
VCCO - 1.7
V
VSWING
Peak-to-Peak Output Voltage Swing
0.6
1. 0
V
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.
TABLE 6. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Mode of Oscillation
Typical Maximum
Units
Fundamental
Frequency
25
MHz
Equivalent Series Resistance (ESR)
50
Ω
Shunt Capacitance
7
pF
100
µW
Maximum
Units
Drive Level
NOTE: Characterized using an 18pF parallel resonant cr ystal.
TABLE 7. INPUT FREQUENCY CHARACTERISTICS, TA = 0°C TO 70°C
Symbol Parameter
fIN
Input
Frequency
Test Conditions
Typical
25
XTAL_IN/XTAL_OUT
25
S_CLOCK
843101AG-312
Minimum
CLK
MHz
MHz
50
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6
MHz
OCTOBER 18, 2005
ADVANCE INFORMATION
ICS843101-312
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-LVPECL
312.5MHZ FREQUENCY MARGINING SYNTHESIZER
TABLE 8A. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
fOUT
Output Frequency
t jit(Ø)
RMS Phase Jitter ; NOTE 1
tR / t F
Output Rise/Fall Time
Test Conditions
Minimum
Mode = LOW
312.5MHz, (1.875MHz - 20MHz)
20% to 80%
odc
Output Duty Cycle
S_DATA to
S_CLOCK
tS
Setup Time
S_CLOCK
to S_LOAD
S_DATA to
Hold Time
tH
S_CLOCK
NOTE 1: Characterized using a 25MHz cr ystal.
Typical
Maximum
Units
312.5
MHz
TBD
ps
TBD
ps
50
%
10
ns
10
ns
10
ns
TABLE 8B. AC CHARACTERISTICS, VCC = VCCA = 3.3V±5%,VCCO = 2.5V±5%, TA = 0°C TO 70°C
Symbol
Parameter
fOUT
Output Frequency
t jit(Ø)
RMS Phase Jitter ; NOTE 1
tR / t F
Output Rise/Fall Time
Test Conditions
Minimum
Mode = LOW
312.5MHz, (1.875MHz - 20MHz)
20% to 80%
odc
Output Duty Cycle
S_DATA to
S_CLOCK
tS
Setup Time
S_CLOCK
to S_LOAD
S_DATA to
Hold Time
tH
S_CLOCK
NOTE 1: Characterized using a 25MHz cr ystal.
Typical
Maximum
Units
312.5
MHz
TBD
ps
TBD
ps
50
%
10
ns
10
ns
10
ns
TABLE 8C. AC CHARACTERISTICS, VCC = VCCA = 3.3V±5%,VCCO = 2.5V±5%, TA = 0°C TO 70°C
Symbol
Parameter
fOUT
Output Frequency
t jit(Ø)
RMS Phase Jitter ; NOTE 1
tR / t F
Output Rise/Fall Time
Test Conditions
Minimum
Mode = LOW
312.5MHz, (1.875MHz - 20MHz)
20% to 80%
odc
Output Duty Cycle
S_DATA to
S_CLOCK
tS
Setup Time
S_CLOCK
to S_LOAD
S_DATA to
Hold Time
tH
S_CLOCK
NOTE 1: Characterized using a 25MHz cr ystal.
843101AG-312
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7
Typical
Maximum
Units
312.5
MHz
TBD
ps
TBD
ps
50
%
10
ns
10
ns
10
ns
OCTOBER 18, 2005
ADVANCE INFORMATION
ICS843101-312
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-LVPECL
312.5MHZ FREQUENCY MARGINING SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
2.8V±0.04V
2V
2V
Qx
VCC,
VCCA, VCCO
SCOPE
SCOPE
Qx
VCC,
VCCA VCCO
LVPECL
LVPECL
VEE
nQx
nQx
VEE
-0.5V ± 0.125V
-1.3V ± 0.165V
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
2V
Phase Noise Plot
SCOPE
Noise Power
Qx
VCC,
VCCA, VCCO
LVPECL
Phase Noise Mask
nQx
VEE
f1
Offset Frequency
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
-0.5V ± 0.125V
2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
RMS PHASE JITTER
nQ
80%
80%
Q
VSW I N G
Clock
Outputs
t PW
20%
20%
tR
t
PERIOD
tF
odc =
t PW
x 100%
t PERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
OUTPUT RISE/FALL TIME
843101AG-312
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OCTOBER 18, 2005
ADVANCE INFORMATION
ICS843101-312
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-LVPECL
312.5MHZ FREQUENCY MARGINING SYNTHESIZER
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS843101-312 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. V CC, VCCA, and
VCCO should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 2 illustrates how
a 10Ω resistor along with a 10µF and a .01μF bypass
capacitor should be connected to each VCCA. The 10Ω resistor can also be replaced by a ferrite bead.
3.3V or 2.5V
VCC
.01μF
10Ω
VCCA
.01μF
10μF
FIGURE 2. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
allel resonant crystal and were chosen to minimize the
ppm error.
The ICS843101-312 has been characterized with 18pF
parallel resonant crystals. The capacitor values shown in
Figure 3 below were determined using a 25MHz, 18pF par-
XTAL_OUT
C1
27p
X1
18pF Parallel Crystal
XTAL_IN
C2
27p
Figure 3. CRYSTAL INPUt INTERFACE
843101AG-312
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OCTOBER 18, 2005
ADVANCE INFORMATION
ICS843101-312
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-LVPECL
312.5MHZ FREQUENCY MARGINING SYNTHESIZER
RECOMMENDATIONS FOR UNUSED INPUT PINS
INPUTS:
CRYSTAL INPUT:
For applications not requiring the use of the crystal oscillator
input, both XTAL_IN and XTAL_OUT can be left floating.
Though not required, but for additional protection, a 1kΩ
resistor can be tied from XTAL_IN to ground.
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
CLK INPUT:
For applications not requiring the use of the test clock, it can
be left floating. Though not required, but for additional
protection, a 1kΩ resistor can be tied from the CLK input to
ground.
TERMINATION FOR 3.3V LVPECL OUTPUT
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts
mentioned are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs
that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground)
or current sources must be used for functionality. These
outputs are designed to drive 50Ω transmission lines.
Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which
are recommended only as guidelines. Other suitable
clock layouts may exist and it would be recommended
that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
3.3V
Zo = 50Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
FOUT
50Ω
1
RTT =
Z
((VOH + VOL) / (VCC – 2)) – 2 o
FIN
50Ω
Zo = 50Ω
VCC - 2V
RTT
84Ω
FIGURE 4A. LVPECL OUTPUT TERMINATION
843101AG-312
125Ω
84Ω
FIGURE 4B. LVPECL OUTPUT TERMINATION
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OCTOBER 18, 2005
ADVANCE INFORMATION
ICS843101-312
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-LVPECL
312.5MHZ FREQUENCY MARGINING SYNTHESIZER
TERMINATION FOR 2.5V LVPECL OUTPUT
Figure 5A and Figure 5B show examples of termination for
2.5V LVPECL driver. These terminations are equivalent to
terminating 50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is
very close to ground level. The R3 in Figure 4B can be
eliminated and the termination is shown in Figure 4C.
2.5V
VCC=2.5V
2.5V
2.5V
VCC=2.5V
R1
250
Zo = 50 Ohm
R3
250
+
Zo = 50 Ohm
+
Zo = 50 Ohm
-
Zo = 50 Ohm
2,5V LVPECL
Driv er
-
R1
50
2,5V LVPECL
Driv er
R2
62.5
R2
50
R4
62.5
R3
18
FIGURE 5B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 5A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V
VCC=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
2,5V LVPECL
Driv er
R1
50
R2
50
FIGURE 5C. 2.5V LVPECL TERMINATION EXAMPLE
843101AG-312
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OCTOBER 18, 2005
ADVANCE INFORMATION
ICS843101-312
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-LVPECL
312.5MHZ FREQUENCY MARGINING SYNTHESIZER
RELIABILITY INFORMATION
TABLE 9.
θJAVS. AIR FLOW TABLE FOR 16 LEAD TSSOP
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
137.1°C/W
89.0°C/W
118.2°C/W
81.8°C/W
106.8°C/W
78.1°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS843101-312 is: TBD
843101AG-312
www.icst.com/products/hiperclocks.html
12
OCTOBER 18, 2005
ADVANCE INFORMATION
ICS843101-312
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-LVPECL
312.5MHZ FREQUENCY MARGINING SYNTHESIZER
PACKAGE OUTLINE - G SUFFIX FOR 16 LEAD TSSOP
TABLE 10. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Minimum
N
Maximum
16
A
--
1.20
A1
0.05
0.15
A2
0.80
1.05
b
0.19
0.30
c
0.09
0.20
D
4.90
5.10
E
6.40 BASIC
E1
4.30
e
4.50
0.65 BASIC
L
0.45
0.75
α
0°
8°
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
843101AG-312
www.icst.com/products/hiperclocks.html
13
OCTOBER 18, 2005
ADVANCE INFORMATION
Integrated
Circuit
Systems, Inc.
ICS843101-312
FEMTOCLOCKS™ CRYSTAL-TO-LVPECL
312.5MHZ FREQUENCY MARGINING SYNTHESIZER
TABLE 11. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging Temperature
ICS843101AG-312
3101A100
16 Lead TSSOP
tube
-40°C to 85°C
ICS843101AG-312T
3101A100
16 Lead TSSOP
2500 tape & reel
-40°C to 85°C
ICS843101AG-312LF
TBD
16 Lead "Lead-Free" TSSOP
tube
-40°C to 85°C
ICS843101AG-312LFT
TBD
16 Lead "Lead-Free" TSSOP
2500 tape & reel
-40°C to 85°C
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS complaint.
The aforementioned trademarks, HiPerClockS and FemtoClocks are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
843101AG-312
www.icst.com/products/hiperclocks.html
14
OCTOBER 18, 2005
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