MC10ELT25, MC100ELT25 -5 V Differential ECL to TTL Translator Description Features • • • MARKING DIAGRAMS* 8 8 1 SOIC−8 D SUFFIX CASE 751 1 1 TSSOP−8 DT SUFFIX CASE 948R 1 KLT25 ALYW G 1 8 8 2.6 ns Typical Propagation Delay 100 MHz FMAX CLK 24 mA TTL Outputs Flow Through Pinouts Operating Range: VCC = 4.5 V to 5.5 V with GND = 0 V; VEE = −4.2 V to −5.7 V with GND = 0 V Internal Input 50 KW Pulldown Resistors Q Output will default HIGH with inputs open or < 1.3 V These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant 8 HLT25 ALYW G 8 HT25 ALYWG G 1 KT25 ALYWG G 5F MG G • • • • • www.onsemi.com 2U MG G The MC10ELT/100ELT25 is a differential ECL to TTL translator. Because ECL levels are used, a +5 V, −5.2 V (or −4.5 V) and ground are required. The small outline 8-lead package and the single gate of the ELT25 makes it ideal for those applications where space, performance and low power are at a premium. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. The 100 Series contains temperature compensation. 1 4 1 4 DFN8 MN SUFFIX CASE 506AA H K 5F 2U M = MC10 = MC100 = MC10 = MC100 = Date Code A L Y W G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. © Semiconductor Components Industries, LLC, 2015 August, 2015 − Rev. 14 1 Publication Order Number: MC10ELT25/D MC10ELT25, MC100ELT25 VEE D 1 8 TTL 2 7 Table 1. PIN DESCRIPTION VCC Pin Q ECL D VBB 3 6 4 5 NC GND Figure 1. 8−Lead Pinout (Top View) and Logic Diagram Function D, D ECL Differential Inputs Q TTL Output VBB Reference Voltage Output VCC Positive Supply VEE Negative Supply GND Ground NC No Connect EP (DFN8 only) Thermal exposed pad must be connected to a sufficient thermal conduit. Electrically connect to the most negative supply (GND) or leave unconnected, floating open. Table 2. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 kW Internal Input Pullup Resistor ESD Protection N/A Human Body Model Machine Model > 1 kV > 400 V Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb−Free Pkg SOIC−8 TSSOP−8 DFN8 Flammability Rating Level 1 Level 3 Level 1 Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in Transistor Count 38 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Table 3. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 VCC Positive Power Supply GND = 0 V VEE = −5.0 V VEE Negative Power Supply GND = 0 V VCC = +5.0 V VIN Input Voltage GND = 0 V IBB VBB Sink/Source TA Tstg qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm qJC Thermal Resistance (Junction−to−Case) qJA Rating Unit 7 V −8 V 0 to VEE V ± 0.5 mA Operating Temperature Range −40 to +85 °C Storage Temperature Range −65 to +150 °C SOIC−8 SOIC−8 190 130 °C/W °C/W Standard Board SOIC−8 41 to 44 °C/W Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm TSSOP−8 TSSOP−8 185 140 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) Standard Board TSSOP−8 41 to 44 ± 5% °C/W qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm DFN8 DFN8 129 84 °C/W °C/W Tsol Wave Solder <2 to 3 sec @ 260°C 265 °C qJC Thermal Resistance (Junction−to−Case) DFN8 35 to 40 °C/W Pb−Free (Note 2) Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 2. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) www.onsemi.com 2 MC10ELT25, MC100ELT25 Table 4. 10ELT SERIES NECL INPUT DC CHARACTERISTICS VCC = 5.0 V; VEE = −5.0 V; GND = 0 V (Note 3) −40°C Typ 85°C Characteristic Min Max Min Max Min Max Unit VIH Input HIGH Voltage (Single−Ended) (Note 4) −1230 −890 −1130 −810 −1060 −720 mV VIL Input LOW Voltage (Single−Ended) (Note 4) −1950 −1500 −1950 −1480 −1950 −1445 mV VBB Output Voltage Reference −1.43 −1.30 −1.35 −1.25 −1.31 −1.19 V VIHCMR Input HIGH Voltage Common Mode Range (Differential) (Notes 4 and 5) −2.8 0.0 −2.8 0.0 −2.8 0.0 V IIH Input HIGH Current 175 mA IIL Input LOW Current Symbol Typ 25°C 255 0.5 Typ 175 0.5 mA 0.3 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. 3. Input parameters vary 1:1 with GND. VEE can vary +0.06 V to −0.5 V. 4. TTL output RL = 500 W to GND 5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with GND. Table 5. 100ELT SERIES NECL INPUT DC CHARACTERISTICS VCC = 5.0 V; VEE = −5.0 V; GND = 0 V (Note 6) −40°C Characteristic Min Max Min VIH Input HIGH Voltage (Single−Ended) (Note 7) −1165 −880 VIL Input LOW Voltage (Single−Ended) (Note 7) −1810 VBB Output Voltage Reference VIHCMR Input HIGH Voltage Common Mode Range (Differential) (Notes 7 and 8) IIH Input HIGH Current IIL Input LOW Current Symbol Typ 25°C Typ 85°C Max Min −1165 −880 −1475 −1810 −1.38 −1.26 −2.8 0.0 Max Unit −1165 −880 mV −1475 −1810 −1475 mV −1.38 −1.26 −1.38 −1.26 V −2.8 0.0 −2.8 0.0 V 175 mA 255 0.5 Typ 175 0.5 mA 0.5 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. 6. Input parameters vary 1:1 with GND. VEE can vary +0.8 V to −0.5 V. 7. TTL output RL = 500 W to GND 8. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with GND. Table 6. TTL OUTPUT DC CHARACTERISTICS VCC = 4.5 V to 5.5 V; TA = −40°C to +85°C Symbol Characteristic Condition VOH Output HIGH Voltage IOH = −3.0 mA VOL Output LOW Voltage IOL = 24 mA ICCH Power Supply Current ICCL Min Typ Max 2.4 Unit V 0.5 V 11 16 mA Power Supply Current 13 18 mA IEE Negative Power Supply Current 15 21 mA IOS Output Short Circuit Current −60 mA −150 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. www.onsemi.com 3 MC10ELT25, MC100ELT25 Table 7. AC CHARACTERISTICS VCC= 5.0 V; VEE= −5.0 V; GND= 0 V (Note 9 and Note 10) −40°C Symbol Characteristic Min Typ 25°C Max Min Typ 85°C Max Min Typ Max 100 Unit fmax Maximum Toggle Frequency tPLH Propagation Delay @ 1.5 V 1.7 3.6 1.7 3.6 1.7 3.6 ns tPHL Propagation Delay @ 1.5 V 2.6 4.1 2.6 4.1 2.6 4.1 ns tJITTER Random Clock Jitter (RMS) 35 ps tr tf Output Rise/Fall Times QTTL 10% − 90% 1.9 2.3 ns VPP Input Swing (Note 11) 200 1000 200 MHz 1000 200 1000 mV NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. 9. VCC can vary ± 0.25 V. VEE can vary +0.06 V to −0.5 V for 10ELT; VEE can vary +0.8 V to −0.5 V for 100ELT. 10. RL = 500 W to GND and CL = 20 pF to GND. Refer to Figure 2. 11. VPP(min) is the minimum input swing for which AC parameters are guaranteed. The device has a DC gain of ≈ 40. APPLICATION TTL RECEIVER CHARACTERISTIC TEST *CL includes fixture capacitance CL * RL AC TEST LOAD GND Figure 2. TTL Output Loading Used for Device Evaluation www.onsemi.com 4 MC10ELT25, MC100ELT25 ORDERING INFORMATION Package Shipping† MC10ELT25DG SOIC−8 (Pb−Free) 98 Units / Rail MC10ELT25DR2G SOIC−8 (Pb−Free) 2500 / Tape & Reel MC10ELT25DTG TSSOP−8 (Pb−Free) 100 Units / Rail MC10ELT25DTR2G TSSOP−8 (Pb−Free) 2500 / Tape & Reel MC10ELT25MNR4G DFN8 (Pb−Free) 1000 / Tape & Reel MC100ELT25DG SOIC−8 (Pb−Free) 98 Units / Rail MC100ELT25DR2G SOIC−8 (Pb−Free) 2500 / Tape & Reel MC100ELT25DTG TSSOP−8 (Pb−Free) 100 Units / Rail MC100ELT25DTR2G TSSOP−8 (Pb−Free) 2500 / Tape & Reel MC100ELT25MNR4G DFN8 (Pb−Free) 1000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPSt I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ECL AN1672/D − The ECL Translator Guide AND8001/D − Odd Number Counters Design AND8002/D − Marking and Date Codes AND8020/D − Termination of ECL Logic Devices AND8066/D − Interfacing with ECLinPS AND8090/D − AC Characteristics of ECL Devices www.onsemi.com 5 MC10ELT25, MC100ELT25 PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AK NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. −X− A 8 5 S B 0.25 (0.010) M Y M 1 4 K −Y− G C N DIM A B C D G H J K M N S X 45 _ SEATING PLANE −Z− 0.10 (0.004) H M D 0.25 (0.010) M Z Y S X J S SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. www.onsemi.com 6 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 MC10ELT25, MC100ELT25 PACKAGE DIMENSIONS TSSOP−8 DT SUFFIX CASE 948R−02 ISSUE A 8x 0.15 (0.006) T U K REF 0.10 (0.004) S 2X L/2 8 1 PIN 1 IDENT S T U V S NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 6. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. S 5 0.25 (0.010) B −U− L 0.15 (0.006) T U M M 4 A −V− F DETAIL E C 0.10 (0.004) −T− SEATING PLANE D −W− G DETAIL E www.onsemi.com 7 DIM A B C D F G K L M MILLIMETERS MIN MAX 2.90 3.10 2.90 3.10 0.80 1.10 0.05 0.15 0.40 0.70 0.65 BSC 0.25 0.40 4.90 BSC 0_ 6_ INCHES MIN MAX 0.114 0.122 0.114 0.122 0.031 0.043 0.002 0.006 0.016 0.028 0.026 BSC 0.010 0.016 0.193 BSC 0_ 6_ MC10ELT25, MC100ELT25 PACKAGE DIMENSIONS DFN8 2x2, 0.5P CASE 506AA ISSUE E D PIN ONE REFERENCE 0.10 C 2X 0.10 C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994 . 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.20 MM FROM TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. L L L1 ÇÇÇ ÇÇÇ ÇÇÇ 0.10 C 2X A B DETAIL A E OPTIONAL CONSTRUCTIONS ÉÉÉ ÉÉÉ EXPOSED Cu TOP VIEW A DETAIL B DIM A A1 A3 b D D2 E E2 e K L L1 MOLD CMPD DETAIL B OPTIONAL CONSTRUCTION 0.08 C (A3) NOTE 4 A1 C SIDE VIEW SEATING PLANE RECOMMENDED SOLDERING FOOTPRINT* 8X DETAIL A 1.30 D2 1 8X L 8 5 8X e/2 e 0.50 PACKAGE OUTLINE 4 E2 K MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.20 0.30 2.00 BSC 1.10 1.30 2.00 BSC 0.70 0.90 0.50 BSC 0.30 REF 0.25 0.35 −−− 0.10 0.90 2.30 1 b 0.10 C A B 0.05 C 8X 0.30 NOTE 3 0.50 PITCH DIMENSIONS: MILLIMETERS BOTTOM VIEW *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC). 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