Vicor NBM6123T46C15A6T01 Non-isolated, fixed ratio dc-dc converter Datasheet

NBM™ Bus Converter
NBM6123x46C15A6yzz
®
C
S
US
C
NRTL
US
Non-Isolated, Fixed Ratio DC-DC Converter
Features
Product Ratings
• Up to 160A continuous secondary current
• Up to 3600W/in3 power density
• Parallel operation for multi-kW arrays
• OV, OC, UV, short circuit and thermal protection
• 6123​through-hole ChiP package
n 2.402” x 0.990” x 0.286”
(61.00mm x 25.14mm x 7.26mm)
VPRI = 42V (36 – 46V)
ISEC= up to 160A
VSEC = 14V (12.0 – 15.3V)
(no load)
K = 1/3
Product Description
The VI Chip® Non-Isolated Bus Converter (NBM™) is a high
efficiency Sine Amplitude Converter™ (SAC™), operating from
a 36 to 46VDC primary bus to deliver a non-isolated, ratiometric
secondary voltage from 12.0 to 15.3VDC.
Typical Applications
The NBM6123x46C15A6yzz offers low noise, fast transient
response, and industry leading efficiency and power density. In
addition, it provides an AC impedance beyond the bandwidth of
most downstream regulators, allowing input capacitance normally
located at the input of a POL regulator to be located at the primary
side of the NBM module. With a primary to secondary K factor
of 1/3, that capacitance value can be reduced by a factor of 9x,
resulting in savings of board area, material and total system cost.
• DC Power Distribution
• High End Computing Systems
• Automated Test Equipment
• Industrial Systems
• High Density Power Supplies
• Communications Systems
Leveraging the thermal and density benefits of Vicor’s ChiP
packaging technology, the NBM module offers flexible thermal
management options with very low top and bottom side thermal
impedances. Thermally-adept ChiP-based power components,
enable customers to achieve low cost power system solutions
with previously unattainable system size, weight and efficiency
attributes, quickly and predictably.
• Transportation
The NBM non-isolated topology allows operation in forward and
reverse directions and provides bidirectional protections. However
if power train is disabled by any protection, and VSEC is present,
then voltage equal to VSEC minus two diode drops will appear on
primary side.
NBM™ Bus Converter
Page 1 of 26
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Typical Application
NBM
TM
EN
enable/disable
switch
VAUX
FUSE
+VSEC
+VPRI
SGND
VPRI
PGND
PRIMARY
SECONDARY
CI_NBM_ELEC
POL
SOURCE_RTN
NBM6123x46C15A6yzz+ Point of Load
NBM™ Bus Converter
Page 2 of 26
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Pin Configuration
1
TOP VIEW
2
+VSEC
A
A’ +VSEC
PGND1
B
B’ PGND2
PGND1
C
C’ PGND2
+VSEC
D
D’ +VSEC
+VSEC
E
E’
+VSEC
PGND1
F
F’
PGND2
PGND1
G
G’ PGND2
+VSEC
H
H’ +VSEC
+VPRI
I
I’
TM
+VPRI
J
J’
EN
+VPRI
K
K’ VAUX
+VPRI
L
L’
SGND
6123 ChiP Package
Pin Descriptions
Pin Number
Signal Name
Type
Function
I1, J1, K1, L1
+VPRI
PRIMARY POWER
I’2
TM
OUTPUT
J’2
EN
INPUT
K’2
VAUX
OUTPUT
L’2
SGND
SIGNAL RETURN
Signal return terminal only. Do not connect to PGND
A1, D1, E1, H1, A’2,
D’2, E’2, H’2
+VSEC
SECONDARY
POWER
Positive secondary auto-transformer power terminal
B1, C1, F1, G1
B’2, C’2, F’2, G’2
PGND*
POWER RETURN
Positive primary auto-transformer power terminal
Temperature Monitor; Primary side referenced signals
Enables and disables power supply; Primary side referenced signals
Auxilary Voltage Source; Primary side referenced signals
Common negative primary and secondary auto-transformer power return terminal
*For proper operation an external low impedance connection must be made between listed -PGND1 and PGND2 terminals.
NBM™ Bus Converter
Page 3 of 26
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Part Ordering Information
Product
Function
Package
Size
Package
Mounting
Max Primary
Input Voltage
Range
Identifier
Max
Secondary
Voltage
Secondary
Output
Current
Temperature
Grade
Option
NBM
6123
x
46
C
15
A6
y
zz
61 = L
23 = W
T = TH
00 = Analog Ctrl
Non-isolated
Bus Converter
Module
S = SMT
46V
36 – 46V
15V
No Load
160A
T = -40°C – 125°C
01 = PMBus Ctrl
M = -55°C – ­125°C
0R = Reversible Analog Ctrl
0P = Reversible PMBus Ctrl
All products shipped in JEDEC standard high profile (0.400” thick) trays (JEDEC Publication 95, Design Guide 4.10).
Standard Models
Product
Function
Package
Size
Package
Mounting
Max Primary
Input Voltage
Range
Identifier
Max
Secondary
Voltage
Secondary
Output
Current
Temperature
Grade
Option
NBM
6123
T
46
C
15
A6
T
0R
Absolute Maximum Ratings
The absolute maximum ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause permanent damage to the device.
Parameter
Comments
+VPRI_DC to –VPRI_DC
Min
Max
Unit
-1
60
V
1
V/µs
20
V
4.6
V
5.5
V
4.6
V
VPRI_DC or VSEC_DC slew rate (operational)
+VSEC_DC to –VSEC_DC
-1
TM to –VPRI_DC
EN to –VPRI_DC
-0.3
VAUX to –VPRI_DC
NBM™ Bus Converter
Page 4 of 26
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Electrical Specifications
Specifications apply over all line and load conditions, unless otherwise noted; Boldface specifications apply over the temperature range of -40°C ≤ TINTERNAL
≤ 125°C (T-Grade); All other specifications are at TINTERNAL = 25ºC unless otherwise noted.
­Attribute
Symbol
Conditions / Notes
Min
Typ
Max
Unit
46
V
15
V
General Powetrain PRIMARY to SECONDARY Specification (Forward Direction)
Primary Input Voltage range,
continuous
VPRI µController
PRI to SEC Input Quiescent Current
36
VPRI_DC
VPRI_DC voltage where µC is initialized,
(ie VAUX = Low, powertrain inactive)
VµC_ACTIVE
Disabled, EN Low, VPRI_DC = 42V
IPRI_Q
8
TINTERNAL ≤ 100ºC
12
VPRI_DC = 42V, TINTERNAL = 25ºC
PRI to SEC No Load Power
Dissipation
PRI to SEC Inrush Current Peak
5
VPRI_DC = 42V
PPRI_NL
12.5
IPRI_INR_PK
28
22
VPRI_DC = 36V to 46V
31
30
TINTERNAL ≤ 100ºC
DC Primary Input Current
Transformation Ratio
Secondary Output Current
(continuous)
Secondary Output Current (pulsed)
IPRI_IN_DC
1/3
ISEC_OUT_DC
10ms pulse, 25% Duty cycle, ISEC_OUT_AVG ≤ 50% rated
ISEC_OUT_DC
VPRI_DC = 42V, ISEC_OUT_DC = 160A
97.4
VPRI_DC = 36V to 46V, ISEC_OUT_DC = 160A
97.1
hAMB
VPRI_DC = 42V, ISEC_OUT_DC = 80A
97.5
98.2
PRI to SEC Efficiency (hot)
hHOT
VPRI_DC = 42V, ISEC_OUT_DC = 160A
96.9
97.4
PRI to SEC Efficiency
(over load range)
ηh20%
32A < ISEC_OUT_DC < 160A
90
RSEC_COLD
VPRI_DC = 42V, ISEC_OUT_DC = 160A, TINTERNAL = -40°C
0.8
RSEC_AMB
VPRI_DC = 42V, ISEC_OUT_DC = 160A
RSEC_HOT
VPRI_DC = 42V, ISEC_OUT_DC = 160A, TINTERNAL = 100°C
FSW
Frequency of the Output Voltage Ripple = 2x FSW
VSEC_OUT_PP
CSEC_EXT = 0μF, ISEC_OUT_DC = 160A, VPRI_DC = 42V,
20MHz BW
Switching Frequency
Secondary Output Voltage Ripple
Secondary Output Leads Inductance
(Parasitic)
NBM™ Bus Converter
Page 5 of 26
V/V
160
A
176
A
%
%
%
0.95
1.1
0.9
1.3
1.7
1.5
1.75
2.0
1.14
1.20
1.26
110
TINTERNAL ≤ 100ºC
Primary Input Leads Inductance
(Parasitic)
A
98
PRI to SEC Efficiency (ambient)
PRI to SEC Output Resistance
A
53.9
Primary to secondary, K = VSEC_DC / VPRI_DC, at no load
ISEC_OUT_PULSE
W
75
At ISEC_OUT_DC = 160A, TINTERNAL ≤ 100ºC
K
19.5
VPRI_DC = 36V to 46V, TINTERNAL = 25 ºC
VPRI_DC = 46V, CSEC_EXT = 3000μF, RLOAD_SEC = 20% of
full load current
mA
mΩ
MHz
mV
205
LPRI_IN_LEADS
Frequency 2.5MHz (double switching frequency),
Simulated lead model
3
nH
LSEC_OUT_LEADS
Frequency 2.5MHz (double switching frequency),
Simulated lead model
0.64
nH
Rev 1.3
09/2016
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NBM6123x46C15A6yzz
Electrical Specifications (Cont.)
Specifications apply over all line and load conditions, unless otherwise noted; Boldface specifications apply over the temperature range of -40°C ≤ TINTERNAL
≤ 125°C (T-Grade); All other specifications are at TINTERNAL = 25ºC unless otherwise noted.
­Attribute
Symbol
Conditions / Notes
Min
Typ
Max
Unit
General Powetrain PRIMARY to SECONDARY Specification (Forward Direction) Cont.
Effective Primary Capacitance
(Internal)
CPRI_INT
Effective Value at 42VPRI_DC
16.8
µF
Effective Secondary Capacitance
(Internal)
CSEC_INT
Effective Value at 14VSEC_DC
140
µF
Effective Secondary Output
Capacitance (External)
CSEC_OUT_EXT
Excessive capacitance may drive module into SC
protection
Effective Secondary Output
Capacitance (External)
CSEC_OUT_AEXT
CSEC_OUT_AEXT Max = N * 0.5 * CSEC_OUT_EXT MAX, where
N = the number of units in parallel
3000
µF
1010
ms
Protection PRIMARY to SECONDARY (Forward Direction)
Auto Restart Time
tAUTO_RESTART
Startup into a persistent fault condition. Non-Latching
fault detection given VPRI_DC > VPRI_UVLO+
940
Primary Overvoltage Lockout
Threshold
VPRI_OVLO+
48
50
52
V
Primary Overvoltage Recovery
Threshold
VPRI_OVLO-
46
48
50
V
Primary Overvoltage Lockout
Hysteresis
VPRI_OVLO_HYST
2
V
Primary Overvoltage Lockout
Response Time
tPRI_OVLO
30
µs
Primary Undervoltage Lockout
Threshold
VPRI_UVLO-
28
30
32
V
Primary Undervoltage Recovery
Threshold
VPRI_UVLO+
30
32
34
V
Primary Undervoltage Lockout
Hysteresis
VPRI_UVLO_HYST
2
V
Primary Undervoltage Lockout
Response Time
tPRI_UVLO
100
µs
From VPRI_DC = VPRI_UVLO+ to powertrain active, EN
tPRI_UVLO+_DELAY floating, (i.e One time Startup delay from application
of VPRI_DC to VSEC_DC)
30
ms
From powertrain active. Fast Current limit protection
disabled during Soft-Start
1
ms
Primary Undervoltage Startup Delay
Primary Soft-Start Time
tPRI_SOFT-START
Secondary Output Overcurrent Trip
Threshold
ISEC_OUT_OCP
Secondary Output Overcurrent
Response Time Constant
tSEC_OUT_OCP
Secondary Output Short Circuit
Protection Trip Threshold
ISEC_OUT_SCP
Secondary Output Short Circuit
Protection Response Time
tSEC_OUT_SCP
Overtemperature Shutdown
Threshold
tOTP+
Overtemperature Recovery
Threshold
tOTP–
Undertemperature Shutdown
Threshold
tUTP
Undertemperature Restart Time
NBM™ Bus Converter
Page 6 of 26
177
Effective internal RC filter
200
4
A
1
°C
110
Temperature sensor located inside controller IC;
Protection not available for M-Grade units.
Startup into a persistent fault condition. Non-Latching
fault detection given VPRI_DC > VPRI_UVLO+
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µs
125
105
A
ms
240
Temperature sensor located inside controller IC
tUTP_RESTART
240
3
115
°C
-45
°C
s
NBM6123x46C15A6yzz
Electrical Specifications (Cont.)
Specifications apply over all line and load conditions, unless otherwise noted; Boldface specifications apply over the temperature range of -40°C ≤ TINTERNAL
≤ 125°C (T-Grade); All other specifications are at TINTERNAL = 25ºC unless otherwise noted.
­Attribute
Symbol
Conditions / Notes
Min
Typ
Max
Unit
15.3
V
General Powetrain SECONDARY to PRIMARY Specification (Reverse Direction)
Secondary Input Voltage range,
continuous
12
VSEC_DC
VSEC_DC = 14V, TINTERNAL = 25ºC
SEC to PRI No Load Power
Dissipation
DC Secondary Input Current
ISEC_IN_DC
Primary Output Current (continuous)
IPRI_OUT_DC
Primary Output Current (pulsed)
5
VSEC_DC = 14V
PSEC_NL
IPRI_OUT_PULSE
hAMB
20
29
22
VSEC_DC = 12V to 15.3V
31
At IPRI_DC = 53.3A, TINTERNAL ≤ 100ºC
162
A
53.3
A
58.7
A
10ms pulse, 25% Duty cycle,
IPRI_OUT_AVG ≤ 50% rated IPRI_OUT_DC
97
98
VSEC_DC = 12V to 15.3V, IPRI_OUT_DC= 53.3A
96.7
%
VSEC_DC = 14V, IPRI_OUT_DC = 26.7A
97.6
98.3
96.6
97
SEC to PRI Efficiency (hot)
hHOT
VSEC_DC = 14V, IPRI_OUT_DC = 53.3A
SEC to PRI Efficiency
(over load range)
ηh20%
10.66A < IPRI_OUT_DC < 53.3A
90
RPRI_COLD
VSEC_DC = 14V, IPRI_OUT_DC = 53.3A, TINTERNAL = -40°C
10
12
14
RPRI_AMB
VSEC_DC = 14V, IPRI_OUT_DC = 53.3A
12
16
20
RPRI_HOT
VSEC_DC = 14V, IPRI_OUT_DC = 53.3A, TINTERNAL = 100°C
16
19
22
SEC to PRI Output Resistance
Primary Output Voltage Ripple
VPRI_OUT_PP
CPRI_OUT_EXT = 0μF, IPRI_OUT_DC = 53.3A,
VSEC_DC = 14V, 20MHz BW
Rev 1.3
09/2016
%
%
330
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mΩ
mV
615
TINTERNAL ≤ 100ºC
NBM™ Bus Converter
Page 7 of 26
W
VSEC_DC = 12V to 15.3V, TINTERNAL = 25ºC
VSEC_DC = 14V, IPRI_OUT_DC = 53.3A
SEC to PRI Efficiency (ambient)
12.5
NBM6123x46C15A6yzz
Electrical Specifications (Cont.)
Specifications apply over all line and load conditions, unless otherwise noted; Boldface specifications apply over the temperature range of -40°C ≤ TINTERNAL
≤ 125°C (T-Grade); All other specifications are at TINTERNAL = 25ºC unless otherwise noted.
­Attribute
Symbol
Conditions / Notes
Min
Typ
Max
Unit
300
µF
Protection SECONDARY to PRIMARY (Reverse Direction)
Effective Primary Output
Capacitance (External)
CPRI_OUT_EXT
Secondary Overvoltage Lockout
Threshold
VSEC_OVLO+
16
16.7
17.4
V
Secondary Overvoltage Recovery
Threshold
VPRI_OVLO-
15.3
16
16.7
V
Secondary Overvoltage Lockout
Response Time
tPRI_OVLO
Excessive capacitance may drive module into SC
protection when starting from Secondary to Primary
30
µs
Secondary Undervoltage Lockout
Threshold
VSEC_UVLO-
9.3
10
10.7
V
Secondary Undervoltage Recovery
Threshold
VPRI_UVLO+
10
10.7
11.4
V
Secondary Undervoltage Lockout
Response Time
tSEC_UVLO
Primary Output Overcurrent Trip
Threshold
IPRI_OUT_OCP
Powertrain is stopped but current can flow from
Secondary to Primary through MOSFET body Diodes
Primary Output Overcurrent
Response Time Constant
tPRI_OUT_OCP
Effective internal RC filter
Primary Short Circuit Protection Trip
Threshold
IPRI_SCP
Primary Short Circuit Protection
Response Time
tPRI_SCP
NBM™ Bus Converter
Page 8 of 26
100
59
66.7
4
Powertrain is stopped but current can flow from
Secondary to Primary through MOSFET body Diodes
80
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80
A
ms
A
1
Rev 1.3
09/2016
µs
µs
NBM6123x46C15A6yzz
200
180
Secondary
Output Current (A)
160
140
120
100
80
60
40
20
0
25
50
75
100
125
Case Temperature (°C)
Top only at temperature
Top and leads at
temperature
Leads at temperature
Top, leads, & belly at
temperature
3000
Secondary Output Current (A)
Secondary Output Power (W)
Figure 1 — Specified thermal operating area
2700
2400
2100
1800
1500
1200
900
600
300
0
36
37
38
39
40
41
42
43
44
45
200
180
160
140
120
100
80
60
40
20
0
46
36
37
38
Primary Input Voltage (V)
PSEC_OUT_DC
39
ISEC_OUT_DC
Secondary Output Capacitance
(% Rated CSEC_EXT_MAX)
Figure 2 — Specified electrical operating area using rated RSEC_HOT
0
20
40
60
80
Secondary Output Current (% ISEC_OUT_DC)
Figure 3 — Specified Primary start-up into load current and external capacitance
NBM™ Bus Converter
Page 9 of 26
Rev 1.3
09/2016
41
42
43
44
Primary Input Voltage (V)
PSEC_OUT_PULSE
110
100
90
80
70
60
50
40
30
20
10
0
40
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100
ISEC_OUT_PULSE
45
46
NBM6123x46C15A6yzz
Signal Characteristics
Specifications apply over all line and load conditions, unless otherwise noted; Boldface specifications apply over the temperature range of -40°C ≤ TINTERNAL
≤ 125°C (T-Grade); All other specifications are at TINTERNAL = 25ºC unless otherwise noted.
Temperature Monitor
• The TM pin is a standard analog I/O configured as an output from an internal µC.
• The TM pin monitors the internal temperature of the controller IC within an accuracy of ±5°C.
• µC 250kHz PWM output internally pulled high to 3.3V.
SIGNAL TYPE
STATE
Startup
ATTRIBUTE
Powertrain active to TM
time
TM Duty Cycle
SYMBOL
CONDITIONS / NOTES
TYP
MAX
100
tTM
18.18
TMPWM
TM Current
MIN
ITM
UNIT
µs
68.18
%
4
mA
Recommended External filtering
DIGITAL
OUTPUT
Regular
Operation
TM Capacitance (External)
CTM_EXT
Recommended External filtering
0.01
µF
TM Resistance (External)
RTM_EXT
Recommended External filtering
1
kΩ
10
mV / °C
1.27
V
Specifications using recommended filter
TM Gain
ATM
TM Voltage Reference
TM Voltage Ripple
VTM_AMB
VTM_PP
RTM_EXT = 1K Ohm, CTM_EXT = 0.01µF,
VPRI_DC = 42V, ISEC_DC = 160A
28
TINTERNAL ≤ 100ºC
mV
40
Enable / Disable Control
• The EN pin is a standard analog I/O configured as an input to an internal µC.
• It is internally pulled high to 3.3V.
• When held low the NBM™ internal bias will be disabled and the powertrain will be inactive.
• In an array of NBMs, EN pins should be interconnected to synchronize startup.
• Unit must not be disabled if a load is present on +VPRI while in reverse operation.
SIGNAL TYPE
STATE
Startup
ANALOG
INPUT
Regular
Operation
ATTRIBUTE
EN to Powertrain active
time
tEN_START
EN Voltage Threshold
VEN_TH
EN Resistance (Internal)
REN_INT
EN Disable Threshold
NBM™ Bus Converter
Page 10 of 26
SYMBOL
Rev 1.3
09/2016
CONDITIONS / NOTES
MIN
VPRI_DC > VPRI_UVLO+, EN held low both
conditions satisfied for T > tPRI_UVLO+_DELAY
TYP
MAX
10
ms
2.3
Internal pull up resistor
V
1.5
kΩ
1
VEN_DISABLE_TH
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UNIT
V
NBM6123x46C15A6yzz
Signal Characteristics (Cont.)
Specifications apply over all line and load conditions, unless otherwise noted; Boldface specifications apply over the temperature range of -40°C ≤ TINTERNAL
≤ 125°C (T-Grade); All other specifications are at TINTERNAL = 25ºC unless otherwise noted.
Auxiliary Voltage Source
• The VAUX pin is a standard analog I/O configured as an output from an internal µC.
• VAUX is internally connected to µC output as internally pulled high to a 3.3V regulator with 2% tolerance, a 1% resistor of 1.5kΩ.
• VAUX can be used as a “Ready to process full power” flag. This pin transitions VAUX voltage after a 2ms delay from the start of powertrain activating,
signaling the end of softstart.
• VAUX can be used as “Fault flag”. This pin is pulled low internally when a fault protection is detected.
SIGNAL TYPE
ANALOG
OUTPUT
STATE
ATTRIBUTE
SYMBOL
Startup
Powertrain ­active to VAUX
time
tVAUX
VAUX Voltage
VVAUX
VAUX Available Current
IVAUX
Regular
Operation
Fault
VAUX Voltage Ripple
VVAUX_PP
VAUX Capacitance
(External)
CVAUX_EXT
VAUX Resistance (External)
RVAUX_EXT
VAUX Fault Response Time
tVAUX_FR
CONDITIONS / NOTES
2.8
MAX
3.3
V
4
mA
100
TINTERNAL ≤ 100ºC
0.01
VPRI_DC < VµC_ACTIVE
From fault to VVAUX = 2.8V, CVAUX = 0pF
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800 927.9474
1.5
UNIT
ms
50
• Signal ground is internally connect to PGND through a zero ohm resistor.
• Internal SGND traces are not designed to support high current.
Rev 1.3
09/2016
TYP
2
Powertrain active to VAUX High
Signal Ground
NBM™ Bus Converter
Page 11 of 26
MIN
mV
µF
kΩ
10
µs
NBM™ Bus Converter
Page 12 of 26
Rev 1.3
09/2016
VAUX
TM
OUTPUT
OUTPUT
OUTPUT
EN
+VPRI
+VSEC
BIDIR
INPUT
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STARTUP
tVAUX
tPRI_UVLO+_DELAY
VPRI_UVLO+
VµC_ACTIVE
VPRI_OVLO+
VNOM
OVER VOLTAGE
VPRI_UVLO-
VPRI_OVLO-
up
ll u
N
O P
ER
T
N- AL
PU
OV
R
N
T
T
U
TU TER
U
E YO N
NP G E
U T IN
Z
I
I
R
P
O
L
Y TA
IN U X
IA NDA RN
A R OL
T
C
A
I
D
V
_
IN CO TU RIM V
RI
P
VP N &
µc SE
E
tAUTO-RESTART
ENABLE CONTROL
OVER CURRENT
>
tPRI_UVLO+_DELAY
tSEC_OUT_SCP
SHUTDOWN
GE
NT
TA
H
L
E
W G
EV
VO
LO HI
S
T F
IT
D
D
RE
U
U
F
E
E
P
C
LL ULL
UT
IN N-O
IR
U
P
C
Y R
P
P
T
IN
E
E
A R TU
C
BL ABL
OR
M
_D
I
I
A
H
R
S
PR
VP
EN EN
RT
TA
NBM6123x46C15A6yzz
NBM™ Forward Direction Timing Diagram
NBM™ Bus Converter
Page 13 of 26
Rev 1.3
09/2016
+VPRI
VAUX
TM
OUTPUT
OUTPUT
EN
+VSEC
OUTPUT
BIDIR
INPUT
VSEC_OVLO+
VNOM
STARTUP
tVAUX
tPRI_UVLO+_DELAY
VPRI = +VSEC – (~1.4V)
VµC_ACTIVE
VSEC_UVLO+
OVER VOLTAGE
VSEC_UVLO-
VSEC_OVLO-
up
llN
u
-O L P
R
UT
VE
RN NA
P
U
O
R
T
T E
U
RY E
E
UT INT
IZ RY O -ON DA AG
P
L
X
N LT
IN U
IA A N
IT IM UR ECO VO
DC VA
_
N
I PR T
S
EC
VS N &
µc
E
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OVER CURRENT
tAUTO-RESTART
SHUTDOWN
RED LINE: LOAD MUST NOT BE PRESENT
TO PRENEVENT DAMAGE TO UNIT
/
T
T NT
PU F
EN EVE
IN -OF
R
R IT
RY RN
CU C U
DA TU
R
R
N
E CI
E
CO G
O V RT
SE L T A
O
VO
SH
NOT SUPPORTED CONDITION,
PERMANENT DAMAGE MAY OCCUR
ENABLE CONTROL
>
tPRI_UVLO+_DELAY
tPRI_OUT_OCP
W GH
LO H I
D
R
E
ED
LL LL
UT
U
U
P
P
P
IN
E
E
C
BL ABL
_D
A
C
E
EN EN
VS
RT
TA
ES
NBM6123x46C15A6yzz
NBM™ Reverse Direction Timing Diagram
NBM6123x46C15A6yzz
High Level Functional State Diagram
Conditions that cause state transitions are shown along arrows. Sub-sequence activities listed inside the state bubbles.
Application
of input voltage to VPRI_DC
VµC_ACTIVE < VPRI_DC < VPRI_UVLO+
STANDBY SEQUENCE
Application
of input voltage to VSEC_DC
VµC_ACTIVE <
VSEC_DC
K
< VPRI_UVLO+
VPRI_DC > VPRI_UVLO+
or VSEC_DC > VSEC_UVLO+
STARTUP SEQUENCE
TM Low
TM Low
EN High
EN High
VAUX Low
VAUX Low
Powertrain Stopped
Powertrain Stopped
ENABLE falling edge,
or OTP detected
tPRI_UVLO+_DELAY
expired
ONE TIME DELAY
INITIAL STARTUP
Input OVLO or UVLO,
Output OCP,
UTP, OVLO or UVLO, or
Input OCP detected
Fault
Autorecovery
ENABLE falling edge,
or OTP detected
FAULT
SEQUENCE
Input OVLO or UVLO,
Output OCP,
UTP, OVLO or UVLO, or
Input OCP detected
TM Low
EN High
VAUX Low
Powertrain Stopped
Short Circuit detected
SUSTAINED
OPERATION
TM PWM
EN High
VAUX High
Powertrain Active
Note: During reverse direction operation a load must not be present if the powertrain is in any stopped state while the supply voltage is present on +VSEC.
NBM™ Bus Converter
Page 14 of 26
Rev 1.3
09/2016
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Application Characteristics
20
18
16
14
12
10
8
6
36
37
38
39
40
41
42
43
44
45
46
PRI to SEC, Full Load Efficiency (%)
PRI to SEC, Power Dissipation (W)
Product is mounted and temperature controlled via top side cold plate, unless otherwise noted. All data presented in this section are collected data from
primary sourced units processing power in forward direction.See associated figures for general trend data.
98.5
98.0
97.5
97.0
-40
-20
0
Primary Input Voltage (V)
-40°C
25°C
80°C
VPRI:
PRI to SEC, Efficiency (%)
99
98
97
96
95
94
93
92
91
90
89
88
0
16
32
48
64
80
96
112
128
144
160
0
42V
46V
32
48
64
80
PRI to SEC, Efficiency (%)
16
32
36V
96
112
128
42V
46V
Figure 8 — Efficiency at TCASE = 25°C
NBM™ Bus Converter
Page 15 of 26
42V
46V
48
64
80
96
112
128
144
160
36V
42V
144
160
46V
144
160
88
80
72
64
56
48
40
32
24
16
8
0
0
16
32
Secondary Output Current (A)
VPRI :
100
Figure 7 — Power dissipation at TCASE = -40°C
99
98
97
96
95
94
93
92
91
90
89
88
16
36V
VPRI :
Figure 6 — Efficiency at TCASE = -40°C
0
80
Secondary Output Current (A)
PRI to SEC, Power Dissipation
36V
60
88
80
72
64
56
48
40
32
24
16
8
0
Secondary Output Current (A)
VPRI :
40
Figure 5 — Full load efficiency vs. temperature; VPRI_DC
Figure 4 — No load power dissipation vs. VPRI_DC
PRI to SEC, Power Dissipation
TTOP SURFACE CASE:
20
Case Temperature (ºC)
48
64
80
96
112
VPRI :
36V
42V
Figure 9 — Power dissipation at TCASE = 25°C
Rev 1.3
09/2016
128
Secondary Output Current (A)
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46V
99
98
97
96
95
94
93
92
91
90
89
88
0
16
32
48
64
80
96
112
128
144
160
PRI to SEC, Power Dissipation
PRI to SEC, Efficiency (%)
NBM6123x46C15A6yzz
88
80
72
64
56
48
40
32
24
16
8
0
0
16
Secondary Output Current (A)
36V
42V
VPRI:
PRI to SEC, Output Resistance (mΩ)
Figure 10 — Efficiency at TCASE = 80°C
1.5
1.0
0.5
-20
0
20
40
60
80
Case Temperature (°C)
ISEC_OUT:
80
96
112
128
144
160
36V
42V
144
160
46V
100
140
120
100
80
60
40
20
0
0
16
32
48
64
Rev 1.3
09/2016
80
96
112
128
Secondary Output Current (A)
VPRI:
160A
Figure 12 — RSEC vs. temperature; Nominal VPRI_DC
ISEC_DC = 160A at TCASE = 80°C
NBM™ Bus Converter
Page 16 of 26
64
Figure 11 — Power dissipation at TCASE = 80°C
2.0
-40
48
Secondary Output Current (A)
46V
Secondary Output Voltage Ripple (mV)
VPRI:
32
42V
Figure 13 — VSEC_OUT_PP vs. ISEC_DC ; No external CSEC_OUT_EXT. Board
mounted module, scope setting: 20MHz analog BW
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Figure 14 — Full load ripple, 270µF CPRI_IN_EXT; No external
CSEC_OUT_EXT. Board mounted module, scope setting:
20MHz analog BW
Figure 15 — 0A – 160A transient response:
CPRI_IN_EXT = 270µF, no external CSEC_OUT_EXT
Figure 16 — 160A – 0A transient response:
CPRI_IN_EXT = 270µF, no external CSEC_OUT_EXT
Figure 17 — Start up from application of VPRI_DC= 42V, 20% ISEC_DC,
100% CSEC_OUT_EXT
Figure 18 — Start up from application of EN with pre-applied VPRI_DC = 42V, 20% ISEC_DC, 100% CSEC_OUT_EXT
NBM™ Bus Converter
Page 17 of 26
Rev 1.3
09/2016
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General Characteristics
Specifications apply over all line and load conditions, unless otherwise noted; Boldface specifications apply over the temperature range of -40°C ≤ TINTERNAL
≤ 125°C (T-Grade); All other specifications are at TINTERNAL = 25ºC unless otherwise noted.
­Attribute
Symbol
Conditions / Notes
Min
Typ
Max
Unit
Mechanical
Length
L
60.87 / [2.396] 61.00 / [2.402] 61.13 / [2.407]
mm/[in]
Width
W
24.76 / [0.975] 25.14 / [0.990] 25.52 / [1.005]
mm/[in]
Height
H
7.21 / [0.284]
mm/[in]
Volume
Vol
Weight
W
Lead finish
Without Heatsink
7.26 / [0.286]
7.31 / [0.288]
cm3/[in3]
11.13 / [0.679]
41 / [1.45]
g/[oz]
Nickel
0.51
2.03
Palladium
0.02
0.15
Gold
0.003
0.051
-40
125
µm
Thermal
Operating Temperature
TINTERNAL
NBM6123T46C15A6T0R (T-Grade)
Thermal Resistance Top Side
ΦφINT-TOP
Estimated thermal resistance to maximum
temperature internal component from
isothermal top
1.36
°C/W
Thermal Resistance Leads
φINT-LEADS
Estimated thermal resistance to
maximum temperature internal
component from isothermal leads
1.36
°C/W
1.24
°C/W
34
Ws/°C
Thermal Resistance Bottom Side
Estimated thermal resistance to
ΦφINT-BOTTOM maximum temperature internal
component from isothermal bottom
Thermal Capacity
°C
Assembly
Storage temperature
ESD Withstand
NBM™ Bus Converter
Page 18 of 26
NBM6123T46C15A6T0R (T-Grade)
-40
ESDHBM
Human Body Model, “ESDA / JEDEC JDS-001-2012” Class I-C (1kV to < 2kV)
ESDCDM
Charge Device Model, “JESD 22-C101-E” Class II (200V to < 500V)
Rev 1.3
09/2016
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125
°C
NBM6123x46C15A6yzz
General Characteristics
Specifications apply over all line and load conditions, unless otherwise noted; Boldface specifications apply over the temperature range of -40°C ≤ TINTERNAL
≤ 125°C (T-Grade); All other specifications are at TINTERNAL = 25ºC unless otherwise noted.
Soldering[1]
Peak Temperature Top Case
135
°C
Safety
Isolation voltage / Dielectric test
VHIPOT
PRIMARY to SECONDARY
N/A
PRIMARY to CASE
2250
SECONDARY to CASE
2250
N/A
Isolation Capacitance
CPRI_SEC
Unpowered Unit
Insulation Resistance
RPRI_SEC
At 500VDC
MTBF
V
N/A
0
MIL-HDBK-217Plus Parts Count - 25°C
Ground Benign, Stationary, Indoors /
Computer
3.34
MHrs
Telcordia Issue 2 - Method I Case III; 25°C
Ground Benign, Controlled
5.26
MHrs
cURus; UL 60950-1
CE Marked for Low Voltage Directive and RoHS Recast Directive, as applicable
[1]
Product is not intended for reflow solder attach.
NBM™ Bus Converter
Page 19 of 26
pF
MΩ
cTUVus; EN 60950-1
Agency Approvals / Standards
N/A
Rev 1.3
09/2016
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Sine Amplitude Converter™ Point of Load Conversion
CPRI_INT
CPRI_INT_ESR
0.5mΩ
16.8µF
1.8nH
LPRI_IN_LEADS = 3nH
ISEC
RSEC
1.3mΩ
LSEC_OUT_LEADS = 0.64nH
+VSEC
+VPRI
1.3mΩ
V•I
1/3 • ISEC
IPRI_Q
220mA
+
+
–
K
1/3 • VPRI
CSEC_INT_ESR
60.4µΩ
–
CSEC_INT
140µF
–PGND
Figure 19 — NBM module AC model
The Sine Amplitude Converter (SAC™) uses a high frequency
resonant tank to move energy from Primary to secondary and
vice versa. The resonant LC tank, operated at high frequency,
is amplitude modulated as a function of primary voltage and
seconday current. A small amount of capacitance embedded in the
primary and secondary stages of the module is sufficient for full
functionality and is key to achieving high power density.
The use of DC voltage transformation provides additional
interesting attributes. Assuming that RSEC = 0Ω and IPRI_Q = 0A,
Eq. (3) now becomes Eq. (1) and is essentially load independent,
resistor R is now placed in series with VPRI.
The NBM6123x46C15A6yzz SAC can be simplified into the
preceeding model.
R
R
At no load:
Vin
V
PRI
VSEC = VPRI • K
Vout
V
SEC
Figure 20 — K = 1/3 Sine Amplitude Converter
with series primary resistor
VSEC
(2)
VPRI
VSEC = VPRI • K – ISEC • RSEC
The relationship between VPRI and VSEC becomes:
VSEC = (VPRI – IPRI • R) • K
In the presence of load, VSEC is represented by:
(3)
and ISEC is represented by:
IPRI – IPRI_Q
K
(4)
RSEC represents the impedance of the SAC, and is a function of
the RDSON of the primary and secondary MOSFETs and the winding
resistance of the power transformer. IPRI_Q represents the quiescent
current of the SAC control, gate drive circuitry, and core losses.
Rev 1.3
09/2016
(5)
Substituting the simplified version of Eq. (4)
(IPRI_Q is assumed = 0A) into Eq. (5) yields:
VSEC = VPRI • K – ISEC • R • K2
ISEC =
NBM™ Bus Converter
Page 20 of 26
SAC™
SAC
1/3
KK==1/32
(1)
K represents the “turns ratio” of the SAC.
Rearranging Eq (1):
K=
+
–
(6)
This is similar in form to Eq. (3), where RSEC is used to represent the
characteristic impedance of the SAC™. However, in this case a real
R on the primary side of the SAC is effectively scaled by K 2 with
respect to the secondary.
Assuming that R = 1Ω, the effective R as seen from the secondary
side is 111mΩ, with K = 1/3.
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A similar exercise should be performed with the additon of a
capacitor or shunt impedance at the primary of the SAC. A switch
in series with VPRI is added to the circuit. This is depicted
in Figure 21.
S
VVin
PRI
+
–
C
SAC™
SAC
K = 1/3
K = 1/32
Vout
V
SEC
not useful if the series impedance of the SAC is too high. The
impedance of the SAC must be low, i.e. well beyond the crossover
frequency of the system.
A solution for keeping the impedance of the SAC low involves
switching at a high frequency. This enables small magnetic
components because magnetizing currents remain low. Small
magnetics mean small path lengths for turns. Use of low loss core
material at high frequencies also reduces core losses.
The two main terms of power loss in the NBM™ module are:
n No load power dissipation (PPRI_NL): defined as the power
used to power up the module with an enabled powertrain
at no load.
n Resistive loss (PRSEC): refers to the power loss across Figure 21 — Sine Amplitude Converter with primary capacitor
A change in VPRI with the switch closed would result in a change in
capacitor current according to the following equation:
dV
(7)
Ic(t) = C PRI
dt
Assume that with the capacitor charged to VPRI, the switch is
opened and the capacitor is discharged through the idealized SAC.
In this case,
Ic= ISEC • K
(8)
the NBM module modeled as pure resistive impedance.
Pdissipated= PPRI_NL + PRSEC
(10)
Therefore,
PSEC_OUT = PPRI_IN – Pdissipated = PPRI_IN – PPRI_NL – PRSEC (11)
The above relations can be combined to calculate the overall
module efficiency:
h =
PSEC_OUT
=PPRI_IN – PPRI_NL – PRSEC
PPRI_in
PPRI_in
substituting Eq. (1) and (8) into Eq. (7) reveals:
C
dVSEC
ISEC =
•
2
K
dt
(9)
The equation in terms of the secondary has yielded a K 2 scaling
factor for C, specified in the denominator of the equation.
A K factor less than unity results in an effectively larger capacitance
on the secondary when expressed in terms of the primary. With a
K = 1/3 as shown in Figure 21, C = 1µF would appear as
C = 9µF when viewed from the secondary.
=
VPRI • IPRI – PPRI_NL – (ISEC)2 • RSEC
VPRI • IPRI
= 1–
(
Low impedance is a key requirement for powering a highcurrent, low-voltage load efficiently. A switching regulation stage
should have minimal impedance while simultaneously providing
appropriate filtering for any switched current. The use of a SAC
between the regulation stage and the point of load provides a
dual benefit of scaling down series impedance leading back to
the source and scaling up shunt capacitance or energy storage
as a function of its K factor squared. However, the benefits are
NBM™ Bus Converter
Page 21 of 26
Rev 1.3
09/2016
)
PPRI_NL + (ISEC)2 • RSEC
VPRI • IPRI
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Input and Output Filter Design
Thermal Considerations
A major advantage of SAC™ systems versus conventional PWM
converters is that the auto-transformer based SAC does not require
external filtering to function properly. The resonant LC tank,
operated at extreme high frequency, is amplitude modulated as a
function of primary voltage and secondary current and efficiently
transfers charge through the auto-transformer. A small amount
of capacitance embedded in the primary and secondary stages of
the module is sufficient for full functionality and is key to achieving
power density.
The ChiP package provides a high degree of flexibility in that it
presents three pathways to remove heat from internal power
dissipating components. Heat may be removed from the top
surface, the bottom surface and the leads. The extent to which
these three surfaces are cooled is a key component for determining
the maximum current that is available from a ChiP, as can be seen
from Figure 1.
This paradigm shift requires system design to carefully evaluate
external filters in order to:
n Guarantee low source impedance:
To take full advantage of the NBM™ module’s dynamic
response, the impedance presented to its primary terminals
must be low from DC to approximately 5MHz. The
connection of the bus converter module to its power
source should be implemented with minimal distribution
inductance. If the interconnect inductance exceeds
100nH, the primary should be bypassed with a RC damper
to retain low source impedance and stable operation. With
an interconnect inductance of 200nH, the RC damper
may be as high as 1µF in series with 0.3Ω. A single
electrolytic or equivalent low-Q capacitor may be used in
place of the series RC bypass.
Since the ChiP has a maximum internal temperature rating, it is
necessary to estimate this internal temperature based on a real
thermal solution. Given that there are three pathways to remove
heat from the ChiP, it is helpful to simplify the thermal solution into
a roughly equivalent circuit where power dissipation is modeled as
a current source, isothermal surface temperatures are represented
as voltage sources and the thermal resistances are represented as
resistors. Figure 22 shows the “thermal circuit” for a NBM module
6123 in an application where the top, bottom, and leads are
cooled. In this case, the NBM power dissipation is PDTOTAL and the
three surface temperatures are represented as TCASE_TOP,
TCASE_BOTTOM, and TLEADS. This thermal system can now be very
easily analyzed using a SPICE simulator with simple resistors,
voltage sources, and a current source. The results of the simulation
would provide an estimate of heat flow through the various
pathways as well as internal temperature.
Thermal Resistance Top
n Further reduce primary and/or secondary voltage ripple without
sacrificing dynamic response:
Given the wide bandwidth of the module, the source
response is generally the limiting factor in the overall
system response. Anomalies in the response of the primary
source will appear at the secondary of the module multiplied
by its K factor.
n Protect the module from overvoltage transients imposed
by the system that would exceed maximum ratings and
induce stresses:
The module primary/secondary voltage ranges shall not be
exceeded. An internal overvoltage lockout function
prevents operation outside of the normal operating primary
range. Even when disabled, the powertrain is exposed to the applied voltage and power MOSFETs must withstand it.
Total load capacitance of the NBM module shall not exceed the
specified maximum. Owing to the wide bandwidth and low
secondary impedance of the module, low-frequency bypass
capacitance and significant energy storage may be more densely
and efficiently provided by adding capacitance at the primary of
the module. At frequencies <500kHz the module appears as an
impedance of RSEC between the source and load.
Within this frequency range, capacitance at the primary appears as
effective capacitance on the secondary per the relationship
defined in Eq. (13).
CPRI_EXT
(13)
CSEC_EXT =
K2
This enables a reduction in the size and number of capacitors used
in a typical system.
NBM™ Bus Converter
Page 22 of 26
Rev 1.3
09/2016
MAX INTERNAL TEMP
ΦINT-TOP
Thermal Resistance Bottom
Thermal Resistance Leads
ΦINT-BOTTOM
TCASE_BOTTOM(°C)
Power Dissipation (W)
ΦINT-LEADS
+
–
TLEADS(°C)
+
–
TCASE_TOP(°C)
+
–
Figure 22 — Top case, Bottom case and leads thermal model
Alternatively, equations can be written around this circuit and
analyzed algebraically:
TINT – PD1 • ΦINT-TOP = TCASE_TOP
TINT – PD2 • ΦINT-BOTTOM = TCASE_BOTTOM
TINT – PD3 • ΦINT-LEADS = TLEADS
PDTOTAL = PD1+ PD2+ PD3
Where TINT represents the internal temperature and PD1, PD2, and
PD3 represent the heat flow through the top side, bottom side, and
leads respectively.
Thermal Resistance Top
MAX INTERNAL TEMP
ΦINT-TOP
Thermal Resistance Bottom
ΦINT-BOTTOM
Power Dissipation (W)
TCASE_BOTTOM(°C)
Thermal Resistance Leads
ΦINT-LEADS
TLEADS(°C)
+
–
Figure 23 — Top case and leads thermal model
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TCASE_TOP(°C)
+
–
NBM6123x46C15A6yzz
Figure 23 shows a scenario where there is no bottom side cooling.
In this case, the heat flow path to the bottom is left open and the
equations now simplify to:
VPRI
ZPRI_EQ1
NBM1
ZSEC_EQ1
R0_1
TINT – PD1 • ΦINT-TOP = TCASE_TOP
VSEC
TINT – PD3 • ΦINT-LEADS = TLEADS
PDTOTAL = PD1 + PD3
ZPRI_EQ2
NBM2
ZSEC_EQ2
R0_2
+ DC
Thermal Resistance Top
Load
MAX INTERNAL TEMP
ΦINT-TOP
Thermal Resistance Bottom
Thermal Resistance Leads
ΦINT-BOTTOM
Power Dissipation (W)
TCASE_BOTTOM(°C)
ΦINT-LEADS
TLEADS(°C)
TCASE_TOP(°C)
+
–
ZPRI_EQn
NBMn
ZSEC_EQn
R0_n
Figure 24 — Top case thermal model
Figure 25 — NBM module array
Figure 24 shows a scenario where there is no bottom side and
leads cooling. In this case, the heat flow paths to the bottom and
leads are left open and the equations now simplify to:
TINT – PD1 • ΦINT-TOP = TCASE_TOP
PDTOTAL = PD1
Please note that Vicor has a suite of online tools, including a
simulator and thermal estimator which greatly simplify the task of
determining whether or not a NBM™ thermal configuration is valid
for a given condition. These tools can be found at:
http://www.vicorpower.com/powerbench.
Fuse Selection
In order to provide flexibility in configuring power systems
VI Chip® modules are not internally fused. Input line fusing
of VI Chip products is recommended at system level to provide
thermal protection in case of catastrophic failure.
The fuse shall be selected by closely matching system
requirements with the following characteristics:
n Current rating
(usually greater than maximum current of NBM module)
Current Sharing
n Maximum voltage rating
The performance of the SAC™ topology is based on efficient
transfer of energy through an auto-transformer without the need
of closed loop control. For this reason, the transfer characteristic
can be approximated by an ideal auto-transformer with a positive
temperature coefficient series resistance.
This type of characteristic is close to the impedance characteristic
of a DC power distribution system both in dynamic (AC) behavior
and for steady state (DC) operation.
When multiple NBM modules of a given part number are
connected in an array they will inherently share the load current
according to the equivalent impedance divider that the system
implements from the power source to the point of load.
Some general recommendations to achieve matched array
impedances include:
n Dedicate common copper planes within the PCB
to deliver and return the current to the modules.
n Provide as symmetric a PCB layout as possible among modules
n An input filter is required for an array of NBMs in order to prevent circulating currents.
For further details see AN:016 Using BCM Bus Converters
in High Power Arrays.
NBM™ Bus Converter
Page 23 of 26
Rev 1.3
09/2016
(usually greater than the maximum possible input voltage)
n Ambient temperature
n Nominal melting I2t
n Recommend fuse: ≤ 60A Littelfuse TLS Series (primary side)
Startup and Reverse Operation
The NBM6123T46C15A6T0R is capable of startup in forward
and reverse direction once the applied voltage is greater than the
undervoltage lockout threshold.
The non-isolated bus converter modules are capable of reverse
power operation. Once the unit is enabled, energy can be
transferred from secondary back to the primary whenever the
secondary voltage exceeds VPRI • K. The module will continue
operation in this fashion for as long as no faults occur.
Startup loading could be set to no greater than 20% of rated max
current respectively in forward or reverse direction. A load must
not be present on the +VPRI pin if the powertrain is not actively
switching. Remove +VPRI load prior to disabling the module using
EN pin. Primary MOSEFT body diode conduction will occur if unit
stops switching while a load is present on the +VPRI and +VSEC
voltage is two diodes drop higher than +VPRI.
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NBM™ Module Through Hole Package Mechanical Drawing and Recommended Land Pattern
+VSEC
PGND1
PGND2
PGND1
PGND2
+VSEC
+VSEC
NBM™ Bus Converter
Page 24 of 26
Rev 1.3
09/2016
+VSEC
+VSEC
+VSEC
PGND1
PGND2
PGND1
PGND2
+VSEC
+VSEC
+VPRI
TM
+VPRI
EN
+VPRI
VAUX
+VPRI
SGND
vicorpower.com
800 927.9474
NBM6123x46C15A6yzz
Revision History
Revision
Date
1.0
09/08/15
1.1
09/28/15
Changed PRI to SEC Input Quiescent Current
1.2
07/26/16
Removed redundant information
Updated information
1.3
09/12/2016
NBM™ Bus Converter
Page 25 of 26
Description
Initial Release
n/a
5
new 19
All
Corrected the enable to powertrain active time
Rev 1.3
09/2016
Page Number(s)
vicorpower.com
800 927.9474
10
NBM6123x46C15A6yzz
Vicor’s comprehensive line of power solutions includes high density AC-DC and DC-DC modules and accessory components, fully configurable AC-DC and DC-DC power supplies, and complete custom power
systems.
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NBM™ Bus Converter
Page 26 of 26
Rev 1.3
09/2016
vicorpower.com
800 927.9474