TI1 LMC6001AIN Ultra, ultra-low input current amplifier Datasheet

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LMC6001
SNOS694I – MARCH 1995 – REVISED SEPTEMBER 2015
LMC6001 Ultra, Ultra-Low Input Current Amplifier
1 Features
•
•
•
•
•
•
1
(Maximum Limit, 25°C Unless Otherwise Noted)
Input Current (100% Tested): 25 fA
Input Current Over Temperature: 2 pA
Low Power: 750 μA
Low VOS: 350 μV
Low Noise: 22 nV/√Hz at 1 kHz Typical
2 Applications
•
•
•
•
Electrometer Amplifiers
Photodiode Preamplifiers
Ion Detectors
A.T.E. Leakage Testing
3 Description
Featuring 100% tested input currents of 25 fA
maximum, low operating power, and ESD protection
of 2000 V, the LMC6001 device achieves a new
industry benchmark for low input current operational
amplifiers. By tightly controlling the molding
compound, Texas Instruments is able to offer this
ultra-low input current in a lower cost molded
package.
To avoid long turnon settling times common in other
low input current op amps, the LMC6001A is tested
three times in the first minute of operation. Even units
that meet the 25-fA limit are rejected if they drift.
Because of the ultra-low input current noise of 0.13
fA/√Hz, the LMC6001 can provide almost noiseless
amplification of high resistance signal sources.
Adding only 1 dB at 100 kΩ, 0.1 dB at 1 MΩ and 0.01
dB or less from 10 MΩ to 2,000 MΩ, the LMC6001 is
an almost noiseless amplifier.
The LMC6001 is ideally suited for electrometer
applications requiring ultra-low input leakage such as
sensitive photodetection transimpedance amplifiers
and sensor amplifiers. Because input referred noise is
only 22 nV/√Hz, the LMC6001 can achieve higher
signal to noise ratio than JFET input type
electrometer amplifiers. Other applications of the
LMC6001 include long interval integrators, ultra-high
input impedance instrumentation amplifiers, and
sensitive electrical-field measurement circuits.
Device Information(1)
PART NUMBER
LMC6001
PACKAGE
BODY SIZE (NOM)
PDIP (8)
9.81 mm × 6.35 mm
TO-99 (8)
9.08 mm × 9.08 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
R2
R1
VIN
±
LMC6001
VOUT
+
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMC6001
SNOS694I – MARCH 1995 – REVISED SEPTEMBER 2015
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Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
7
1
1
1
2
3
3
Absolute Maximum Ratings ...................................... 3
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 4
DC Electrical Characteristics for LMC6001AI ........... 4
DC Electrical Characteristics for LMC6001BI ........... 6
DC Electrical Characteristics for LMC6001CI ........... 7
AC Electrical Characteristics for LMC6001AIC......... 9
AC Electrical Characteristics for LM6001BI .............. 9
AC Electrical Characteristics for LMC6001CI ....... 10
Dissipation Ratings ............................................... 10
Typical Characteristics .......................................... 11
Detailed Description ............................................ 14
7.1 Overview ................................................................. 14
7.2 Functional Block Diagram ....................................... 14
7.3 Feature Description................................................. 14
7.4 Device Functional Modes........................................ 14
8
Applications and Implementation ...................... 15
8.1 Application Information............................................ 15
8.2 Typical Application .................................................. 16
8.3 System Example ..................................................... 18
9 Power Supply Recommendations...................... 19
10 Layout................................................................... 19
10.1 Layout Guidelines ................................................. 19
10.2 Layout Example .................................................... 20
11 Device and Documentation Support ................. 21
11.1
11.2
11.3
11.4
11.5
11.6
Documentation Support ........................................
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
21
21
21
21
21
21
12 Mechanical, Packaging, and Orderable
Information ........................................................... 21
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision H (March 2013) to Revision I
•
Added Pin Functions table ESD Ratings table, Recommended Operating Conditions table, Thermal Information
table, Timing Requirements table, Switching Characteristics table, Feature Description section, Device Functional
Modes, Parameter Measurement Information section, Detailed Description section, Register Maps section,
Application and Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section. .................................... 1
Changes from Revision F (March 2013) to Revision H
•
2
Page
Page
Changed layout of National Data Sheet to TI format ........................................................................................................... 18
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5 Pin Configuration and Functions
P Package
8-Pin PDIP
Top View
LMC Package
8-Pin TO-99
Top View
Pin Functions
PIN
NAME
I/O
DESCRIPTION
PDIP NO.
TO-99 NO.
CAN
—
8
—
+IN
3
3
I
Noninverting Input
No internal connection; connected to the external casing.
–IN
2
2
I
Inverting Input
NC
1, 5, 8
1, 5
—
No connection
OUTPUT
6
6
O
Output
V+
7
7
—
Positive (higher) power supply
V–
4
4
—
Negative (lower) power supply
6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted) (1) (2)
MIN
Differential Input Voltage
Unit
±Supply Voltage
Voltage at Input/Output Pin
+
MAX
−
Supply Voltage (V − V )
(V+) + 0.3
(V−) − 0.3
V
−0.3
+16
V
Output Short Circuit to V+
See
Output Short Circuit to V−
(3) (4)
See
(3)
Lead Temperature (Soldering, 10 Sec.)
260
°C
Junction Temperature
150
°C
Current at Input Pin
±10
mA
Current at Output Pin
±30
mA
Current at Power Supply Pin
40
mA
Storage Temperature, Tstg
−65
(1)
(2)
(3)
(4)
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
Applies to both single supply and split supply operation. Continuous short circuit operation at elevated ambient temperature can result in
exceeding the maximum allowed junction temperature of 150°C. Output currents in excess of ±30 mA over long term may adversely
affect reliability.
Do not connect the output to V+, when V+ is greater than 13 V or reliability will be adversely affected.
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6.2 ESD Ratings
V(ESD)
(1)
(2)
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) (2)
Electrostatic discharge
VALUE
UNIT
±2000
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
Human body model, 1.5 kΩ in series with 100 pF.
6.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted).
MIN
MAX
UNIT
VSS
Supply input voltage
4.5
15.5
V
TJ
Operating junction temperature
–40
85
°C
6.4 Thermal Information
LMC6001
THERMAL METRIC
(1)
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
(1)
P (PDIP)
LMC (TO-99)
8 PINS
8 PINS
UNIT
100
145
°C/W
—
45
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 DC Electrical Characteristics for LMC6001AI
Limits are ensured for TJ = 25°C unless otherwise specified. Unless otherwise specified, V+ = 5 V, V− = 0 V, VCM = 1.5 V, and
RL > 1 M.
PARAMETER
IB
Input Current
IOS
Input Offset
Current
TEST CONDITIONS
Either Input, VCM = 0 V,
VS = ±5 V
LMC6001AI
MIN
(1)
TYP (2)
10
At the temperature extremes
MAX (1)
UNIT
25
2000
fA
5
At the temperature extremes
1000
0.7
Input Offset
Voltage
VOS
At the temperature extremes
VS = ±5 V, VCM = 0 V
1
At the temperature extremes
1.35
TCVOS
Input Offset
Voltage Drift
2.5
RIN
Input
Resistance
>1
CMRR
Common Mode 0 V ≤ VCM ≤ 7.5 V
Rejection Ratio V+ = 10 V
+PSRR
Positive Power
Supply
5 V ≤ V+ ≤ 15 V
Rejection Ratio
−PSRR
Negative
Power Supply
0 V ≥ V− ≥ −10 V
Rejection Ratio
75
At the temperature extremes
At the temperature extremes
(1)
(2)
(3)
4
Large Signal
Voltage Gain
Sinking, RL = 2 kΩ (3)
83
83
dB
94
77
400
1400
300
180
At the temperature extremes
TΩ
70
80
At the temperature extremes
μV/°C
72
73
Sourcing, RL = 2 kΩ (3)
AV
mV
10
350
V/mV
100
All limits are specified by testing or statistical analysis.
Typical values represent the most likely parametric norm.
V+ = 15 V, VCM = 7.5 V and RL connected to 7.5 V. For Sourcing tests, 7.5 V ≤ VO ≤ 11.5 V. For Sinking tests, 2.5 V ≤ VO ≤ 7.5 V.
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DC Electrical Characteristics for LMC6001AI (continued)
Limits are ensured for TJ = 25°C unless otherwise specified. Unless otherwise specified, V+ = 5 V, V− = 0 V, VCM = 1.5 V, and
RL > 1 M.
PARAMETER
VCM Low
VCM
LMC6001AI
TEST CONDITIONS
Input Common- V+ = 5 V and 15 V For
Mode Voltage
CMRR ≥ 60 dB
MIN (1)
MAX (1)
–0.4
–0.1
At the temperature
extremes
At the temperature
extremes
V+ = 15 V, RL = 2 kΩ to
2.5 V
V+ − 2.5
VO
Output Swing
Sourcing, V+ = 5 V,
VO = 0 V
Sinking, V+ = 5 V,
VO = 5 V
Output Current
Sourcing, V+ = 15 V,
VO = 0 V
V+ =
(4)
Sinking,
VO = 13 V
VO Low
At the temperature
extremes
VO High
At the temperature
extremes
Supply Current
V+ = 15 V, VO = 7.5 V
(4)
4.87
4.73
21
mA
30
22
28
At the temperature extremes
22
13
28
At the temperature extremes
14.63
10
16
At the temperature extremes
V
14.34
16
At the temperature extremes
0.35
0.45
14.5
15 V,
V+ = 5 V, VO = 1.5 V
IS
At the temperature
extremes
0.14
0.17
0.26
V+ = 15 V, RL = 2 kΩ to
7.5 V
IO
At the temperature
extremes
4.8
VO High
V
V+ − 1.9
0.1
VO Low
UNIT
0
V+ − 2.3
VCM High
TYP (2)
34
22
450
At the temperature extremes
750
900
550
At the temperature extremes
850
μA
950
Do not connect the output to V + , when V + is greater than 13 V or reliability will be adversely affected.
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6.6 DC Electrical Characteristics for LMC6001BI
Limits are ensured for TJ = 25°C unless otherwise specified. Unless otherwise specified, V+ = 5 V, V− = 0 V, VCM = 1.5 V, and
RL > 1 M.
PARAMETER
TEST CONDITIONS
LMC6001BI
MIN (1)
TYP (2)
MAX (1)
UNIT
100
IB
Input Current
IOS
Input Offset
Current
Either Input, VCM = 0 V, VS = ±5 V
At the temperature
extremes
4000
At the temperature extremes
fA
2000
1.35
Input Offset
Voltage
VOS
At the temperature extremes
10
VS = ±5 V, VCM = 0 V
TCVOS
Input Offset
Voltage Drift
RIN
Input
Resistance
Common Mode
CMRR
1.7
At the temperature
extremes
2
μV/°C
TΩ
0 V ≤ VCM ≤ 7.5 V
72
At the temperature
extremes
+
Rejection Ratio
V = 10 V
+PSRR
Positive Power
Supply
Rejection Ratio
5 V ≤ V+ ≤ 15 V
−PSRR
Negative Power
Supply
Rejection Ratio
0 V ≥ V− ≥ −10 V
68
66
At the temperature
extremes
Large Signal
Voltage Gain
83
dB
63
74
At the temperature
extremes
94
71
300
Sourcing, RL = 2 kΩ (3)
AV
1400
200
90
At the temperature
extremes
Sinking, RL = 2 kΩ (3)
Input CommonMode Voltage
V+ = 5 V and 15 V For
CMRR ≥ 60 dB
60
At the temperature
extremes
V − 2.3
At the temperature
extremes
VO Low
At the temperature
extremes
VO High
At the temperature
extremes
VO
V − 1.9
V+ − 2.5
VO Low
At the temperature
extremes
VO High
At the temperature
extremes
V = 15 V, RL = 2 kΩ to
7.5 V
(1)
(2)
(3)
6
4.87
4.67
0.26
+
0.2
0.24
4.75
Output Swing
V
+
0.1
V+ = 15 V, RL = 2 kΩ to
2.5 V
–0.1
0
+
VCM High
V/mV
350
–0.4
VCM Low
VCM
mV
0.44
V
0.56
14.37
14.63
14.25
All limits are specified by testing or statistical analysis.
Typical values represent the most likely parametric norm.
V+ = 15 V, VCM = 7.5 V and RL connected to 7.5V. For Sourcing tests, 7.5 V ≤ VO ≤ 11.5 V. For Sinking tests, 2.5 V ≤ VO ≤ 7.5 V.
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DC Electrical Characteristics for LMC6001BI (continued)
Limits are ensured for TJ = 25°C unless otherwise specified. Unless otherwise specified, V+ = 5 V, V− = 0 V, VCM = 1.5 V, and
RL > 1 M.
PARAMETER
TEST CONDITIONS
Sourcing, V+ = 5 V,
VO = 0 V
At the temperature
extremes
TYP (2)
13
22
At the temperature
extremes
Output Current
At the temperature
extremes
10
At the temperature
extremes
18
34
18
450
V+ = 5 V, VO = 1.5 V
IS
At the temperature
extremes
Supply Current
(4)
750
900
550
V+ = 15 V, VO = 7.5 V
mA
30
23
Sinking, V+ = 15 V,
VO = 13 V (4)
UNIT
21
23
Sourcing, V+ = 15 V,
VO = 0 V
MAX (1)
8
13
Sinking, V+ = 5 V,
VO = 5 V
IO
LMC6001BI
MIN (1)
At the temperature
extremes
850
μA
950
Do not connect the output to V + , when V + is greater than 13 V or reliability will be adversely affected.
6.7 DC Electrical Characteristics for LMC6001CI
Limits are ensured for TJ = 25°C unless otherwise specified. Unless otherwise specified, V+ = 5 V, V− = 0 V, VCM = 1.5 V, and
RL > 1 M.
PARAMETER
TEST CONDITIONS
LMC6001CI
MIN (1)
TYP (2)
MAX (1)
UNIT
1000
IB
Input Current
IOS
Input Offset
Current
VOS
Input Offset
Voltage
TCVOS
Input Offset
Voltage Drift
RIN
Input
Resistance
Either Input, VCM = 0 V, VS = ±5 V
At the temperature
extremes
At the temperature extremes
2000
VS = ±5 V, VCM = 0 V
1.35
1
mV
TΩ
66
At the temperature
extremes
+
Rejection Ratio V = 10 V
+PSRR
Positive Power
Supply
5 V ≤ V+ ≤ 15 V
Rejection Ratio
−PSRR
Negative
Power Supply 0 V ≥ V− ≥ −10 V
Rejection Ratio
(1)
(2)
fA
μV/°C
Common Mode 0 V ≤ VCM ≤ 7.5 V
CMRR
4000
63
66
At the temperature
extremes
dB
63
74
At the temperature
extremes
83
94
71
All limits are specified by testing or statistical analysis.
Typical values represent the most likely parametric norm.
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DC Electrical Characteristics for LMC6001CI (continued)
Limits are ensured for TJ = 25°C unless otherwise specified. Unless otherwise specified, V+ = 5 V, V− = 0 V, VCM = 1.5 V, and
RL > 1 M.
PARAMETER
TEST CONDITIONS
Sourcing, RL = 2 kΩ (3)
AV
Large Signal
Voltage Gain
LMC6001CI
MIN (1)
TYP (2)
300
1400
200
At the temperature
extremes
Sinking, RL = 2 kΩ (3)
90
Input
CommonMode Voltage
V+ = 5 V and 15 V For
CMRR ≥ 60 dB
60
At the temperature
extremes
At the temperature
extremes
VO Low
At the temperature
extremes
V+ − 2.5
VO
Output Swing
4.87
4.67
0.26
VO Low
At the temperature
extremes
VO High
At the temperature
extremes
V+ = 15 V, RL = 2 kΩ to
7.5 V
Sourcing, V+ = 5 V,
VO = 0 V
Sinking, V+ = 5 V,
VO = 5 V
IO
At the temperature
extremes
Output Current
Sourcing, V+ = 15 V,
VO = 0 V
Sinking, V+ = 15 V,
VO = 13 V (4)
22
21
10
23
34
18
450
V+ = 5 V, VO = 1.5 V
IS
Supply Current
V = 15 V, VO = 7.5 V
(3)
(4)
8
At the temperature
extremes
At the temperature
extremes
750
900
550
+
mA
30
18
23
At the temperature
extremes
14.63
8
13
At the temperature
extremes
V
14.25
13
At the temperature
extremes
0.44
0.56
14.37
At the temperature
extremes
0.2
0.24
4.75
VO High
V
V+ − 1.9
0.1
V+ = 15 V, RL = 2 kΩ to
2.5 V
–0.1
0
V+ − 2.3
VCM High
UNIT
V/mV
350
–0.4
VCM Low
VCM
MAX (1)
850
μA
950
V+ = 15 V, VCM = 7.5 V and RL connected to 7.5 V. For Sourcing tests, 7.5 V ≤ VO ≤ 11.5 V. For Sinking tests, 2.5 V ≤ VO ≤ 7.5 V.
Do not connect the output to V + , when V + is greater than 13 V or reliability will be adversely affected.
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6.8 AC Electrical Characteristics for LMC6001AIC
Limits in standard typeface ensured for TJ = 25°C unless otherwise specified. Unless otherwise specified, V+ = 5 V, V− = 0 V,
VCM = 1.5 V and RL > 1 M.
PARAMETER
TEST CONDITIONS
(3)
TYP (2)
0.8
1.5
MAX (1)
UNIT
SR
Slew Rate
GBW
Gain-Bandwidth Product
1.3
MHz
φfm
Phase Margin
50
Deg
GM
Gain Margin
17
dB
en
Input-Referred Voltage
Noise
F = 1 kHz
22
nV/√Hz
in
Input-Referred Current
Noise
F = 1 kHz
0.13
fA/√Hz
THD
Total Harmonic Distortion
F = 10 kHz, AV = −10,
RL = 100 kΩ,
VO = 8 VPP
(1)
(2)
(3)
See
LMC6001AIC
MIN (1)
At the temperature
extremes
V/μs
0.6
0.01%
All limits are specified by testing or statistical analysis.
Typical values represent the most likely parametric norm.
V+ = 15 V. Connected as Voltage Follower with 10-V step input. Limit specified is the lower of the positive and negative slew rates.
6.9 AC Electrical Characteristics for LM6001BI
Limits in standard typeface ensured for TJ = 25°C unless otherwise specified. Unless otherwise specified, V+ = 5 V, V− = 0 V,
VCM = 1.5 V and RL > 1 M.
PARAMETER
TEST CONDITIONS
(3)
TYP (2)
0.8
1.5
MAX (1)
UNIT
SR
Slew Rate
GBW
Gain-Bandwidth Product
1.3
MHz
φfm
Phase Margin
50
Deg
GM
Gain Margin
17
dB
en
Input-Referred Voltage Noise F = 1 kHz
22
nV/√Hz
in
Input-Referred Current Noise F = 1 kHz
0.13
fA/√Hz
THD
(1)
(2)
(3)
Total Harmonic Distortion
See
LM6001BI
MIN (1)
At the temperature
extremes
F = 10 kHz, AV = −10,
RL = 100 kΩ,
VO = 8 VPP
V/μs
0.6
0.01%
All limits are specified by testing or statistical analysis.
Typical values represent the most likely parametric norm.
V+ = 15 V. Connected as Voltage Follower with 10-V step input. Limit specified is the lower of the positive and negative slew rates.
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6.10 AC Electrical Characteristics for LMC6001CI
Limits in standard typeface ensured for TJ = 25°C unless otherwise specified. Unless otherwise specified, V+ = 5 V, V− = 0 V,
VCM = 1.5 V and RL > 1 M.
PARAMETER
TEST CONDITIONS
(4)
TYP (2)
0.8
1.5
MAX (3)
UNIT
SR
Slew Rate
GBW
Gain-Bandwidth Product
1.3
MHz
φfm
Phase Margin
50
Deg
GM
Gain Margin
17
dB
en
Input-Referred Voltage
Noise
F = 1 kHz
22
nV/√Hz
in
Input-Referred Current
Noise
F = 1 kHz
0.13
fA/√Hz
THD
Total Harmonic Distortion
F = 10 kHz, AV = −10,
RL = 100 kΩ,
VO = 8 VPP
(1)
(2)
(3)
(4)
See
LMC6001CI
MIN (1)
At the temperature
extremes
V/μs
0.6
0.01%
All limits are specified by testing or statistical analysis.
Typical values represent the most likely parametric norm.
All limits are specified by testing or statistical analysis.
V+ = 15 V. Connected as Voltage Follower with 10-V step input. Limit specified is the lower of the positive and negative slew rates.
6.11 Dissipation Ratings
MIN
Power Dissipation
(1)
10
See
MAX
UNIT
(1)
For operating at elevated temperatures the device must be derated based on the thermal resistance θJA with PD = (TJ − TA)/θJA.
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6.12 Typical Characteristics
VS = ±7.5 V, TA = 25°C, unless otherwise specified
INPUT BIAS CURRENT
100 pA
10 pA
1 pA
100 fA
10 fA
1 fA
0
25
50
75
100
TEMPERATURE (°C)
125
VS = ±5 V
Figure 1. Input Current vs. Temperature
Figure 2. Input Current vs. VCM
Figure 3. Supply Current vs. Supply Voltage
Figure 4. Input Voltage vs. Output Voltage
Figure 5. Common-Mode Rejection Ratio vs. Frequency
Figure 6. Power Supply Rejection Ratio vs. Frequency
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Typical Characteristics (continued)
VS = ±7.5 V, TA = 25°C, unless otherwise specified
Figure 7. Input Voltage Noise vs. Frequency
Figure 8. Noise Figure vs. Source Resistance
Figure 9. Output Characteristics Sourcing Current
Figure 10. Output Characteristics Sinking Current
RL = 500 kω
Figure 11. Gain and Phase Response vs. Temperature
(−55°C to +125°C)
12
Figure 12. Gain and Phase Response vs. Capacitive Load
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Typical Characteristics (continued)
VS = ±7.5 V, TA = 25°C, unless otherwise specified
Figure 13. Open-Loop Frequency Response
Figure 14. Inverting Small Signal Pulse Response
Figure 15. Inverting Large Signal Pulse Response
Figure 16. Noninverting Small Signal Pulse Response
Figure 17. Noninverting Large Signal Pulse Response
Figure 18. Stability vs. Capacitive Load
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7 Detailed Description
7.1 Overview
LMC6001 has an extremely low input current of 25 fA. In addition, its ultra-low input current noise of 0.13 fA/√Hz
allows almost noiseless amplification of high-resistance signal sources. LMC6001 is ideally suited for
electrometer applications requiring ultra-low input leakage current such as sensitive photodetection
transimpedance amplifiers and sensor amplifiers.
7.2 Functional Block Diagram
7.3 Feature Description
7.3.1 Amplifier Topology
The LMC6001 incorporates a novel op amp design topology that enables it to maintain rail-to-rail output swing
even when driving a large load. Instead of relying on a push-pull unity gain output buffer stage, the output stage
is taken directly from the internal integrator, which provides both low output impedance and large gain. Special
feed-forward compensation design techniques are incorporated to maintain stability over a wider range of
operating conditions than traditional op amps. These features make the LMC6001 both easier to design with, and
provide higher speed than products typically found in this low-power class.
7.3.2 Latch-Up Prevention
CMOS devices tend to be susceptible to latch-up due to their internal parasitic SCR effects. The (I/O) input and
output pins look similar to the gate of the SCR. There is a minimum current required to trigger the SCR gate
lead. The LMC6001 is designed to withstand 100-mA surge current on the I/O pins. Some resistive method
should be used to isolate any capacitance from supplying excess current to the I/O pins. In addition, like an SCR,
there is a minimum holding current for any latch-up mode. Limiting current to the supply pins will also inhibit
latch-up susceptibility.
7.4 Device Functional Modes
The LMC6001 has a single functional mode and operates according to the conditions listed in Recommended
Operating Conditions.
14
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8 Applications and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Compensating For Input Capacitance
It is quite common to use large values of feedback resistance for amplifiers with ultra-low input current, like the
LMC6001.
Although the LMC6001 is highly stable over a wide range of operating conditions, certain precautions must be
met to achieve the desired pulse response when a large feedback resistor is used. Large feedback resistors with
even small values of input capacitance, due to transducers, photodiodes, and printed-circuit-board parasitics,
reduce phase margins.
When high input impedances are demanded, TI suggests guarding the LMC6001. Guarding input lines will not
only reduce leakage, but lowers stray input capacitance as well. See Printed-Circuit-Board Layout For HighImpedance Work.
The effect of input capacitance can be compensated for by adding a capacitor, Cf, around the feedback resistors
(as in Figure 19) such that:
(1)
or
R1 CIN ≤ R2 Cf
(2)
Because it is often difficult to know the exact value of CIN, Cf can be experimentally adjusted so that the desired
pulse response is achieved. Refer to the LMC660 (SNOSBZ3) and LMC662 (SNOSC51) for a more detailed
discussion on compensating for input capacitance.
Figure 19. Cancelling the Effect of Input Capacitance
8.1.2 Capacitive Load Tolerance
All rail-to-rail output swing operational amplifiers have voltage gain in the output stage. A compensation capacitor
is normally included in this integrator stage. The frequency location of the dominant pole is affected by the
resistive load on the amplifier. Capacitive load driving capability can be optimized by using an appropriate
resistive load in parallel with the capacitive load. See Typical Characteristics.
Direct capacitive loading will reduce the phase margin of many op amps. A pole in the feedback loop is created
by the combination of the output impedance of the op amp and the capacitive load. This pole induces phase lag
at the unity-gain crossover frequency of the amplifier resulting in either an oscillatory or underdamped pulse
response. With a few external components, op amps can easily indirectly drive capacitive loads, as shown in
Figure 20.
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Application Information (continued)
Figure 20. LMC6001 Noninverting Gain of 10 Amplifier, Compensated to Handle Capacitive Loads
In the circuit of Figure 20, R1 and C1 serve to counteract the loss of phase margin by feeding the high frequency
component of the output signal back to the inverting input of the amplifier, thereby preserving phase margin in
the overall feedback loop.
Capacitive load driving capability is enhanced by using a pullup resistor to V+ (Figure 21). Typically a pullup
resistor conducting 500 μA or more will significantly improve capacitive load responses. The value of the pullup
resistor must be determined based on the current sinking capability of the amplifier with respect to the desired
output swing. Open-loop gain of the amplifier can also be affected by the pullup resistor. See DC Electrical
Characteristics for LMC6001AI.
Figure 21. Compensating for Large Capacitive Loads With a Pullup Resistor
8.2 Typical Application
The extremely high input resistance, and low power consumption, of the LMC6001 make it ideal for applications
that require battery-powered instrumentation amplifiers. Examples of these types of applications are hand-held
pH probes, analytic medical instruments, electrostatic field detectors and gas chromotographs.
R2
R1
VIN
±
LMC6001
VOUT
+
Figure 22. Typical Application Schematic, LMC6001
16
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Typical Application (continued)
8.2.1 Two Op Amp, Temperature Compensated Ph Probe Amplifier
The signal from a pH probe has a typical resistance between 10 MΩ and 1000 MΩ. Because of this high value, it
is very important that the amplifier input currents be as small as possible. The LMC6001 with less than 25-fA
input current is an ideal choice for this application.
The LMC6001 amplifies the probe output providing a scaled voltage of ±100 mV/pH from a pH of 7. The second
op amp, a micropower LMC6041 provides phase inversion and offset so that the output is directly proportional to
pH, over the full range of the probe. The pH reading can now be directly displayed on a low-cost, low-power
digital panel meter. Total current consumption will be about 1 mA for the whole system.
The micropower dual-operational amplifier, LMC6042, would optimize power consumption but not offer these
advantages:
1. The LMC6001A ensures a 25-fA limit on input current at 25°C.
2. The input ESD protection diodes in the LMC6042 are only rated at 500 V while the LMC6001 has much more
robust protection that is rated at 2000 V.
(1)
R1 100 k + 3500 ppm/°C
R2 68.1 k
R3, 8 5 k
R4, 9 100 k
R5 36.5 k
R6 619 k
R7 97.6 k
D1 LM4040D1Z-2.5
C1 2.2 μF
(2)
µΩ style 137 or similar
Figure 23. Ph Probe Amplifier
8.2.1.1 Design Requirements
The theoretical output of the standard Ag/AgCl pH probe is 59.16 mV/pH at 25°C with 0 V out at a pH of 7.00.
This output is proportional to absolute temperature. To compensate for this, a temperature-compensating
resistor, R1, is placed in the feedback loop. This cancels the temperature dependence of the probe. This resistor
must be mounted where it will be at the same temperature as the liquid being measured.
8.2.1.2 Detailed Design Procedure
The set-up and calibration is simple with no interactions to cause problems.
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Typical Application (continued)
1. Disconnect the pH probe and with R3 set to about mid-range and the noninverting input of the LMC6001
grounded, adjust R8 until the output is 700 mV.
2. Apply −414.1 mV to the noninverting input of the LMC6001. Adjust R3 for and output of 1400 mV. This
completes the calibration. As real pH probes may not perform exactly to theory, minor gain and offset
adjustments should be made by trimming while measuring a precision buffer solution.
8.2.1.3 Application Curve
VS = ±5 V
Figure 24. Input Current vs. VCM
8.3 System Example
8.3.1 Ultra-Low Input Current Instrumentation Amplifier
Figure 25 shows an instrumentation amplifier that features high-differential and common-mode input resistance
(>1014Ω), 0.01% gain accuracy at AV = 1000, excellent CMRR with 1-MΩ imbalance in source resistance. Input
current is less than 20 fA and offset drift is less than 2.5 μV/°C. R2 provides a simple means of adjusting gain
over a wide range without degrading CMRR. R7 is an initial trim used to maximize CMRR without using super
precision matched resistors. For good CMRR over temperature, low-drift resistors should be used.
If R1 = R5, R3 = R6, and R4 = R7; then
∴AV ≈ 100 for circuit shown (R2 = 9.85k).
Figure 25. Instrumentation Amplifier
18
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9 Power Supply Recommendations
See the Recommended Operating Conditions for the minimum and maximum values for the supply input voltage
and operating junction temperature.
10 Layout
10.1 Layout Guidelines
10.1.1 Printed-Circuit-Board Layout For High-Impedance Work
It is generally recognized that any circuit which must operate with less than 1000 pA of leakage current requires
special layout of the PCB. When one wishes to take advantage of the ultra-low bias current of the LMC6001,
typically less than 10 fA, it is essential to have an excellent layout. Fortunately, the techniques of obtaining low
leakages are quite simple. First, the user must not ignore the surface leakage of the PCB, even though it may
sometimes appear acceptably low, because under conditions of high humidity or dust or contamination, the
surface leakage will be appreciable.
To minimize the effect of any surface leakage, lay out a ring of foil completely surrounding the inputs of the
LMC6001 and the terminals of capacitors, diodes, conductors, resistors, relay terminals, and so forth, connected
to the inputs of the op amp, as in Figure 30. To have a significant effect, guard rings must be placed on both the
top and bottom of the PCB. This PC foil must then be connected to a voltage which is at the same voltage as the
amplifier inputs, because no leakage current can flow between two points at the same potential. For example, a
PCB trace-to-pad resistance of 10 TΩ, which is normally considered a very large resistance, could leak 5 pA if
the trace were a 5-V bus adjacent to the pad of the input.
This would cause a 500 times degradation from the LMC6001's actual performance. If a guard ring is used and
held within 1 mV of the inputs, then the same resistance of 10 TΩ will only cause 10 fA of leakage current. Even
this small amount of leakage will degrade the extremely low input current performance of the LMC6001. See
Figure 28 for typical connections of guard rings for standard op amp configurations.
Figure 26. Inverting Amplifier
Figure 27. Noninverting Amplifier
Figure 28. Typical Connections Of Guard Rings
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Layout Guidelines (continued)
The designer should be aware that when it is inappropriate to lay out a PCB for the sake of just a few circuits,
there is another technique which is even better than a guard ring on a PCB: Do not insert the input pin of the
amplifier into the board at all, but bend it up in the air and use only air as an insulator. Air is an excellent
insulator. In this case you may have to forego some of the advantages of PCB construction, but the advantages
are sometimes well worth the effort of using point-to-point up-in-the-air wiring. See Figure 29.
(Input pins are lifted out of PCB and soldered directly to components. All other pins connected to PCB).
Figure 29. Air Wiring
Another potential source of leakage that might be overlooked is the device package. When the LMC6001 is
manufactured, the device is always handled with conductive finger cots. This is to assure that salts and skin oils
do not cause leakage paths on the surface of the package. We recommend that these same precautions be
adhered to, during all phases of inspection, test and assembly.
10.2 Layout Example
Figure 30. Examples Of Guard
Ring In PCB Layout
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation, see the following:
• LMC660 CMOS Quad Operational Amplifier, SNOSBZ3
• LMC662 CMOS Dual Operational Amplifier, SNOSC51
11.2 Related Links
Table 1 lists quick access links. Categories include technical documents, support and community resources,
tools and software, and quick access to sample or buy.
Table 1. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
LMC6001
Click here
Click here
Click here
Click here
Click here
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LMC6001AIN/NOPB
ACTIVE
PDIP
P
8
40
Green (RoHS
& no Sb/Br)
CU SN
Level-1-NA-UNLIM
-40 to 85
LMC6001
AIN
LMC6001BIN/NOPB
ACTIVE
PDIP
P
8
40
Green (RoHS
& no Sb/Br)
CU SN
Level-1-NA-UNLIM
-40 to 85
LMC6001
BIN
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
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