T NT DUC PRO LACEME r at E T E P t L E n O e e R OBS ENDED ort C om/tsc p p u M . il c lS M ECO echnica w.inters R O T w N DataouSheet r w December 1995, Rev. G IL or act cont -INTERS 8 1-88 ® Low Power, 70MHz Buffer Amplifier Features The EL2001 is a low cost monolithic, high slew rate, buffer amplifier. Built using the Elantec monolithic Complementary Bipolar process, this patented buffer has a -3dB bandwidth of 70MHz, and delivers 100mA, yet draws only 1.3mA of supply current. It typically operates from ±15V power supplies but will work with as little as ±5V. • 1.3mA supply current This high speed buffer may be used in a wide variety of applications in military, video and medical systems. A typical example is a general purpose op amp output current booster where the buffer must have sufficiently high bandwidth and low phase shift at the maximum frequency of the op amp. • Short circuit protected Elantec's products and facilities comply with MIL-I-45208A, and other applicable quality specifications. For information on Elantec's processing, see the Elantec document, QRA-1: Elantec's Processing, Monolithic Integrated Circuits. • No thermal runaway Ordering Information • Cable/line driver FN7020 • 70MHz bandwidth • 2000V/µs slew rate • Low bias current, 1µA typical • 100mA output current • Low cost • Stable with capacitive loads • Wide supply range ±5V to ±15V Applications • Op amp output current booster TEMP. RANGE PACKAGE PKG. NO. • A/D input buffer EL2001ACN 0°C to +75°C PDIP MDP0031 • Low standby current systems EL2001CM 0°C to +75°C 20-Pin SOL MDP0027 EL2001CN 0°C to +75°C PDIP MDP0031 PART NUMBER EL2001 Pinouts EL2001 (8-PIN PDIP, SO) TOP VIEW EL2001 (20-PIN SOL) TOP VIEW NOTE: Non-designated pins are no connects and are not electrically connected internally. Manufactured under U.S. Patent No. 4,833,424, 4,827,223 U.K. Patent No. 2217134 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2003. All Rights Reserved. Elantec is a registered trademark of Elantec Semiconductor, Inc. All other trademarks mentioned are the property of their respective owners. EL2001 Absolute Maximum Ratings (TA = 25°C) VS Supply Voltage (V+ - V-) . . . . . . . . . . . . . . . . . . . . ±18V or 36V VIN Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±15V or VS If the input exceeds the ratings shown (or the supplies) or if the input to output voltage exceeds ±7.5V then the input current must be limited to ±50 mA. See the applications section for more information. IIN Input Current (See above note) . . . . . . . . . . . . . . . . . . .±50 mA PD Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . See Curves Output Short Circuit Duration . . . . . . . . . . . . . . . . . . . . . Continuous A heat sink is required to keep the junction temperature below the absolute maximum when the output is short circuited. TA TJ TST Operating Temperature Range . . . . . . . . . . . . . 0°C to +75°C Operating Junction Temperature. . . . . . . . . . . . . . . . . . 150°C Storage Temperature . . . . . . . . . . . . . . . . . .-65°C to +150°C The maximum power dissipation depends on package type, ambient temperature and heat sinking. See the characteristic curves for more details. CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications VS = ±12V, RS = 50Ω, unless otherwise specified TEST CONDITIONS PARAMETER VOS DESCRIPTION Offset Voltage VIN LOAD TEMP MIN TYP MAX UNITS 0 ∞ 25°C -10 2 I mV TMIN, TMAX -15 +15 mV 25°C -30 +30 mV TMIN, TMAX -40 +40 mV 25°C -3 +3 µA TMIN, TMAX -6 +6 µA 25°C -5 +5 µA TMIN, TMAX -10 +10 µA 25° 1 TMIN, TMAX 0.5 25°C 0.990 TMIN, TMAX 0.985 25°C 0.83 TMIN, TMAX 0.80 25°C 0.82 TMIN, TMAX 0.79 25°C ±10 TMIN, TMAX ±9.5 0 IIN Input Current 0 0 RIN AV1 AV2 AV3 VO ROUT Input Resistance Voltage Gain Voltage Gain Voltage Gain with VS = ±5V Output Voltage Swing Output Resistance LIMITS ±12V ±12V ±10V ±3V ±12V ±2V ∞ ∞ ∞ 100Ω ∞ 100Ω 100Ω 100Ω 100Ω 25°C 2 1 1 8 MΩ 0.998 IS Output Current Supply Current ±12V 0 (Note 1) 0.93 ∞ ±100 TMIN, TMAX ±95 25°C 0.89 Supply Rejection (Note 2) 0 ∞ ±11 60 TMIN, TMAX 50 V V 15 Ω 18 Ω ±160 mA mA 1.3 25°C V/V V/V TMIN, TMAX PSRR V/V V/V 10 25°C V/V V/V TMIN, TMAX IOUT MΩ 75 2.0 mA 2.5 mA dB dB tR Rise Time 0.5V 100Ω 25°C 4.2 ns tD Propagation Delay 0.5V 100Ω 25°C 2.0 ns 2 EL2001 Electrical Specifications VS = ±12V, RS = 50Ω, unless otherwise specified (Continued) TEST CONDITIONS PARAMETER SR DESCRIPTION Slew Rate (Note 3) LIMITS VIN LOAD TEMP MIN TYP ±10V 100Ω 25°C 1200 2000 MAX NOTES: 1. Force the input to +12V and the output to +10V and measure the output current. Repeat with -12 VIN and -10V on the output. 2. VOS is measured at VS+ = +4.5V, VS- = -4.5V and at VS+ = +18V, VS- = -18V. Both supplies are changed simultaneously. 3. Slew rate is measured between VOUT = +5V and -5V. Typical Performance Curves Offset Voltage vs Temperature Voltage Gain vs Temperature Output Voltage Swing vs Temperature Supply Current vs Supply Voltage Voltage Gain vs Input Voltage Voltage Gain vs Source Resistance Input Bias Current vs Input Voltage ±Slew Rate vs Supply Voltage ±Slew Rate vs Capacitive Load 3 UNITS V/µs EL2001 Typical Performance Curves (Continued) Voltage Gain vs Frequency for Various Capacitive Loads; RL = 100Ω Voltage Gain vs Frequency for Various Capacitive Loads; RL = ∞ Phase Shift vs Frequency for Various Capacitive Loads -3dB Bandwidth vs Supply Voltage Power Supply Rejection Ratio vs Frequency Output Impedance vs Frequency Reverse Isolation vs Frequency Small Signal Output Resistance vs Output Current Voltage Gain vs Frequency for Various Resistive Loads 8-Pin Plastic DIP Maximum Power Dissipation vs Ambient Temperature 4 20-Pin SOL Maximum Power Dissipation vs Ambient Temperature Short Circuit Current vs Temperature EL2001 Typical Performance Curves (Continued) Application Information The EL2001 is a monolithic buffer amplifier built on Elantec's proprietary dielectric isolation process that produces NPN and PNP transistors with essentially identical DC and AC characteristics. The EL2001 takes full advantage of the complementary process with a unique circuit topology. Large Signal Response Elantec has applied for two patents based on the EL2001’s topology. The patents relate to the base drive and feedback mechanism in the buffer. This feedback makes 2000V/µs slew rates with 100Ω loads possible with very low supply current. Small Signal Response Power Supplies The EL2001 may be operated with single or split supplies with total voltage difference between 10V (±5V) and 36V (±18V). It is not necessary to use equal split value supplies. For example -5V and +12V would be excellent for signals from -2V to +9V. Bypass capacitors from each supply pin to ground are highly recommended to reduce supply ringing and the interference it can cause. At a minimum, 1µF tantalum capacitor with short pins should be used for both supplies. Burn-In Circuit Input Characteristics Simplified Schematic The input to the EL2001 looks like a resistance in parallel with about 3.5pF in addition to a DC bias current. The DC bias current is due to the miss-match in beta and collector current between the NPN and PNP transistors connected to the input pin. The bias current can be either positive or negative. The change in input current with input voltage (RIN) is affected by the output load, beta and the internal boost. RIN can actually appear negative over portions of the input range; typical input current curves are shown in the characteristic curves. Internal clamp diodes from the input to the output are provided. These diodes protect the transistor base emitter junctions and limit the boost current during slew to avoid saturation of internal transistors. The diodes begin conduction at about ±2.5V input to output differential. When that happens the input resistance drops dramatically. The diodes are rated at 50mA. When conducting they have a series resistance of about 20Ω. There is also 100Ω in series with the input that limits input current. Above ±7.5V differential input to output, additional series resistance should be added. Source Impedance The EL2001 has good input to output isolation. When the buffer is not used in a feedback loop, capactive and resistive sources up to 1Mb present no oscillation problems. Care must be used in board layout to minimize output to input coupling. CAUTION: When using high source impedances (RS > 100kΩ), significant gain errors can be observed due to output offset, load resistor, and the action of the boost circuit. See typical performance curves. 5 EL2001 EL2001 Macromodel *Connections: * * * * .subckt M2001 * Input Stage +input | +Vsupply | | -Vsupply | | | output | | | | 2 1 4 7 el 10 0 2 0 1.0 r1 10 0 1K rh 10 11 150 ch 11 0 9pF rc 11 12 100 cc 12 0 4pF e2 13 0 12 0 1.0 * Output stage q1 4 13 14 qp q2 1 13 15 qn q3 1 14 16 qn q4 4 15 19 qp r2 16 7 1 r3 19 7 1 i1 1 14 0.9mA i2 15 4 0.9mA * Bias Current iin+ 2 0 1uA * Models .model qn npn(is=5e-15 bf=150 rb=200 ptf=45 tf=0.1nS) .model qp pnp(is=5e-15 bf=150 rb=200 ptf=45 tf=0.1nS) .ends All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 6