Sample & Buy Product Folder Support & Community Tools & Software Technical Documents LM3444 SNVS682D – NOVEMBER 2010 – REVISED DECEMBER 2015 LM3444 AC-DC Offline LED Driver 1 Features 3 Description • • The LM3444 is an adaptive constant off-time AC/DC buck (step-down) constant current controller that provides a constant current for illuminating high power LEDs. The high-frequency capable architecture allows the use of small external passive components. A passive PFC circuit ensures good power factor by drawing current directly from the line for most of the cycle, and provides a constant positive voltage to the buck regulator. Additional features include thermal shutdown, current limit and VCC undervoltage lockout. The LM3444 is available in a low profile 10-pin VSSOP package or an 8-lead SOIC package. 1 • • • • • • • Application Voltage Range: 80 VAC to 277 VAC Capable of Controlling LED Currents Greater than 1 A Adjustable Switching Frequency Low Quiescent Current Adaptive Programmable Off-Time Allows for Constant Ripple Current Thermal Shutdown No Flicker at 120 Hz Low-Profile 10-Pin VSSOP Package or 8-Lead SOIC Package Patented Drive Architecture Device Information(1) PART NUMBER 2 Applications • • • LM3444 Solid State Lighting Industrial and Commercial Lighting Residential Lighting SPACE Typical LM3444 LED Driver Application Circuit V+ BODY SIZE (NOM) 3.00 mm × 3.00 mm SOIC (8) 3.91 mm × 4.90 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Efficiency vs Line Voltage VBUCK D3 PACKAGE VSSOP (10) 95.0 + D9 14 Series connected LEDs C10 D8 R2 C9 D4 Q1 + C12 VLED - R4 VLED- D2 VAC D1 D10 Q3 C5 L2 90.0 EFFICIENCY (%) C7 BR1 85.0 10 Series connected LEDs 80.0 LM3444 1 NC U1 NC 10 ICOLL 2 NC VCC 9 3 NC GATE 8 75.0 80 90 100 110 120 130 140 LINE VOLTAGE (VAC) 4 COFF ISNS 7 5 FILTER GND 6 Q2 R3 C4 C11 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LM3444 SNVS682D – NOVEMBER 2010 – REVISED DECEMBER 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 4 4 4 4 5 6 Absolute Maximum Ratings ..................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description .............................................. 8 7.1 Overview ................................................................... 8 7.2 Functional Block Diagram ......................................... 8 7.3 Feature Description................................................... 8 7.4 Device Functional Modes........................................ 13 8 Application and Implementation ........................ 14 8.1 Application Information............................................ 14 8.2 Typical Application ................................................. 20 9 Power Supply Recommendations...................... 25 10 Layout................................................................... 25 10.1 Layout Guidelines ................................................. 25 10.2 Layout Example .................................................... 25 11 Device and Documentation Support ................. 26 11.1 11.2 11.3 11.4 11.5 Device Support .................................................... Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 26 26 26 26 26 12 Mechanical, Packaging, and Orderable Information ........................................................... 26 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (May 2013) to Revision D • Added ESD Ratings table, Feature Description section, Device Functional Modes section, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section................................................................ 1 Changes from Revision B (May 2013) to Revision C • 2 Page Page Changed layout of National Data Sheet to TI format ........................................................................................................... 23 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: LM3444 LM3444 www.ti.com SNVS682D – NOVEMBER 2010 – REVISED DECEMBER 2015 5 Pin Configuration and Functions DGS Package 10-Pin VSSOP Top View D Package 8-Lead SOIC Top View NC 1 10 NC NC 2 9 VCC NC 3 8 GATE COFF 4 7 ISNS FILTER 5 6 GND NC 1 8 COFF FILTER 2 7 NC GND 3 6 VCC ISNS 4 5 GATE Pin Functions PIN I/O DESCRIPTION NAME VSSOP SOIC COFF 4 8 I OFF time setting pin. A user set current and capacitor connected from the output to this pin sets the constant OFF time of the switching controller. FILTER 5 2 I Filter input. A low pass filter tied to this pin can filter a PWM dimming signal to supply a DC voltage to control the LED current. Can also be used as an analog dimming input. If not used for dimming connect a 0.1-µF capacitor from this pin to ground. GATE 8 5 O Power MOSFET driver pin. This output provides the gate drive for the power switching MOSFET of the buck controller. GND 6 3 — Circuit ground connection ISNS 7 4 I 1, 2, 3, 10 1, 7 — No internal connection. Leave this pin open. 9 6 O Input voltage pin. This pin provides the power for the internal control circuitry and gate driver. NC VCC LED current sense pin. Connect a resistor from main switching MOSFET source, ISNS to GND to set the maximum LED current. Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: LM3444 3 LM3444 SNVS682D – NOVEMBER 2010 – REVISED DECEMBER 2015 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) (2) MIN MAX UNIT VCC and GATE to GND –0.3 14 V ISNS to GND –0.3 2.5 V FILTER and COFF to GND –0.3 7 V 60 mA COFF input current Continuous power dissipation (3) TJ Tstg (1) (2) (3) Internally limited Junction temperature 150 °C Maximum lead temperature (soldering) 260 °C 150 °C Storage temperature –65 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/Distributors for availability and specifications. Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 165°C (typical) and disengages at TJ = 145°C (typical). 6.2 ESD Ratings VALUE Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 V(ESD) (1) (2) Electrostatic discharge (1) UNIT ±2000 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) V ±1250 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions MIN MAX 8 13 V –40 125 °C VCC TJ Junction temperature UNIT 6.4 Thermal Information LM3444 THERMAL METRIC (1) DGS (VSSOP) D (SOIC) UNIT 10 PINS 8 PINS RθJA Junction-to-ambient thermal resistance 163.8 111.3 °C/W RθJC(top) Junction-to-case (top) thermal resistance 58.4 58.0 °C/W RθJB Junction-to-board thermal resistance 83.6 51.1 °C/W ψJT Junction-to-top characterization parameter 6.1 11.9 °C/W ψJB Junction-to-board characterization parameter 82.3 51.0 °C/W (1) 4 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: LM3444 LM3444 www.ti.com SNVS682D – NOVEMBER 2010 – REVISED DECEMBER 2015 6.5 Electrical Characteristics All typical limits are for TJ = 25°C and all maximum and minimum limits apply over the full operating temperature range (TJ = −40°C to 125°C). Minimum and maximum limits are specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following conditions apply: VCC = 12 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 1.58 2.25 mA 7.4 7.7 VCC SUPPLY IVCC Operating supply current Rising threshold VCC-UVLO Falling threshold 6 Hysterisis 6.4 V 1 COFF VCOFF Time-out threshold RCOFF Off timer sinking impedance tCOFF Restart timer 1.225 1.276 1.327 V 33 60 Ω 180 µs CURRENT LIMIT VISNS tISNS ISNS limit threshold 1.174 1.269 1.364 V Leading edge blanking time 125 ns Current limit reset delay 180 µs 33 ns ISNS limit to GATE delay ISNS = 0 to 1.75-V step CURRENT SENSE COMPARATOR VFILTER FILTER open circuit voltage 720 RFILTER FILTER impedance VOS Current sense comparator offset voltage 750 780 1.12 –4 mV MΩ 0.1 4 mV GATE DRIVE OUTPUT VDRVH GATE high saturation IGATE = 50 mA 0.24 0.5 VDRVL GATE low saturation IGATE = 100 mA 0.22 0.5 Peak souce current GATE = VCC/2 –0.77 Peak sink current GATE = VCC/2 0.88 Rise time Cload = 1 nF 15 Fall time Cload = 1 nF 15 IDRV tDV V A ns THERMAL SHUTDOWN TSD (1) Thermal shutdown temperature Thermal shutdown hysteresis See (1) 165 20 °C Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists, special care must be paid to thermal dissipation issues in board design. In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (RθJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (RθJA × PD-MAX). Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: LM3444 5 LM3444 SNVS682D – NOVEMBER 2010 – REVISED DECEMBER 2015 www.ti.com 6.6 Typical Characteristics 95.0 300k 14 Series connected LEDs 250k 7 LEDs in Series (VO = 24.5V) 90.0 EFFICIENCY (%) fSW (Hz) 200k 150k 100k 85.0 10 Series connected LEDs 80.0 50k C11 = 2.2 nF, R3 = 348 k: 0 80 90 100 110 120 130 75.0 80 140 90 LINE VOLTAGE (VAC) 100 110 120 130 140 LINE VOLTAGE (VAC) Figure 1. fSW vs Input Line Voltage Figure 2. Efficiency vs Input Line Voltage 8.0 200.0 UVLO (VCC) Rising 190.0 tON-MIN (ns) UVLO (V) 7.5 7.0 UVLO (VCC) Falling 180.0 170.0 6.5 160.0 6.0 -50 -25 0 25 50 75 150.0 -50 -25 100 125 150 TEMPERATURE (°C) 0 25 50 75 100 125 150 TEMPERATURE (°C) Figure 3. VCC UVLO vs Temperature Figure 4. Minimum On-Time (tON) vs Temperature 1.50 1.29 NORMALIZED SW FREQ Series connected LEDs VOFF(V) 1.28 1.27 OFF Threshold at C11 1.26 1.25 1.00 3 LEDs 5 LEDs 0.75 0.50 7 LEDs 9 LEDs 0.25 0 1.25 -50 -30 -10 10 30 50 70 90 110130150 50 100 150 200 VBUCK (V) TEMPERATURE (°C) Figure 5. Off Threshold (C11) vs Temperature 6 Figure 6. Normalized Variation in fSW Over VBUCK Voltage Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: LM3444 LM3444 www.ti.com SNVS682D – NOVEMBER 2010 – REVISED DECEMBER 2015 Typical Characteristics (continued) 15.0 100 units tested NUMBER OF UNITS Room (25°C) Hot (125°C) Cold (-40°C) 10.0 5.0 0.0 80 100 120 140 160 180 LEADING EDGE BLANKING (ns) Figure 7. Leading Edge Blanking Variation Over Temperature Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: LM3444 7 LM3444 SNVS682D – NOVEMBER 2010 – REVISED DECEMBER 2015 www.ti.com 7 Detailed Description 7.1 Overview The LM3444 device contains all the necessary circuitry to build a line-powered (mains powered) constant current LED driver. 7.2 Functional Block Diagram VCC INTERNAL REGULATORS LM3444 VCC UVLO MOSFET DRIVER THERMAL SHUTDOWN COFF GATE COFF 33Ö 1.276V S START Q R LATCH 1M PWM 750 mV CONTROLLER I-LIM 1.27V FILTER ISNS 1k LEADING EDGE BLANKING 125 ns PGND 7.3 Feature Description 7.3.1 Theory of Operation For an image of the LM3444 along with basic external circuitry, see Figure 8. 8 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: LM3444 LM3444 www.ti.com SNVS682D – NOVEMBER 2010 – REVISED DECEMBER 2015 Feature Description (continued) V+ VBUCK D3 C7 + D9 BR1 C10 D8 R2 C9 D4 + Q1 C12 VLED - R4 VLED- D2 VAC D1 D10 Q3 C5 L2 LM3444 1 NC U1 NC 10 ICOLL 2 NC VCC 9 3 NC GATE 8 4 COFF ISNS 7 5 FILTER GND 6 Q2 R3 C4 C11 Figure 8. LM3444 Schematic 7.3.2 Valley-Fill Circuit VBUCK supplies the power which drives the LED string. Diode D3 allows VBUCK to remain high while V+ cycles on and off. VBUCK has a relatively small hold capacitor C10 which reduces the voltage ripple when the valley fill capacitors are being charged. However, the network of diodes and capacitors shown between D3 and C10 make up a valley-fill circuit. The valley-fill circuit can be configured with two or three stages. The most common configuration is two stages. Figure 9 illustrates a two- and three-stage valley-fill circuit. Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: LM3444 9 LM3444 SNVS682D – NOVEMBER 2010 – REVISED DECEMBER 2015 www.ti.com Feature Description (continued) V+ VBUCK D3 C7 + VBUCK V+ D3 R6 C7 D9 + D8 D4 R8 C10 + C10 D8 R6 D9 D6 R8 + D5 R7 C9 C8 D4 D7 C9 + R7 Figure 9. Two and Three Stage Valley Fill Circuit The valley-fill circuit allows the buck regulator to draw power throughout a larger portion of the AC line. This allows the capacitance needed at VBUCK to be lower than if there were no valley-fill circuit, and adds passive power factor correction (PFC) to the application. 7.3.3 Valley-Fill Operation When the input line is high, power is derived directly through D3. The term input line is high is explained as follows. The valley-fill circuit charges capacitors C7 and C9 in series (Figure 10) when the input line is high. VBUCK V+ D3 + C7 + VBUCK 2 C10 D8 D4 + VBUCK 2 - + C9 Figure 10. Two Stage Valley-Fill Circuit When AC Line is High The peak voltage of a two-stage valley-fill capacitor is given by Equation 1. VVF-CAP = VAC-RMS 2 2 (1) As the AC line decreases from its peak value every cycle, there is a point where the voltage magnitude of the AC line is equal to the voltage that each capacitor is charged. At this point, diode D3 becomes reversed biased, and the capacitors are placed in parallel to each other (Figure 11), and VBUCK equals the capacitor voltage. 10 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: LM3444 LM3444 www.ti.com SNVS682D – NOVEMBER 2010 – REVISED DECEMBER 2015 Feature Description (continued) VBUCK V+ D3 C7 + + VBUCK D9 C10 D8 D4 + VBUCK - + C9 Figure 11. Two Stage Valley-Fill Circuit when AC Line is Low A three stage valley-fill circuit performs exactly the same as two-stage valley-fill circuit, except now three capacitors are charged in series when the line voltage decreases, as shown in Equation 2: VVF-CAP = VAC-RMS 2 3 (2) Diode D3 is reverse-biased and three capacitors are in parallel to each other. The valley-fill circuit can be optimized for power factor, voltage hold-up, and overall application size and cost. The LM3444 operates with a single-stage or a three-stage valley-fill circuit as well. Resistor R8 functions as a current limiting resistor during start-up, and during the transition from series to parallel connection. Resistors R6 and R7 are 1-MΩ bleeder resistors, and may or may not be necessary for each application. 7.3.4 Buck Converter The LM3444 is a buck controller that uses a proprietary constant off-time method to maintain constant current through a string of LEDs. While transistor Q2 is on, current ramps up through the inductor and LED string. A resistor R3 senses this current and this voltage is compared to the reference voltage at FILTER. When this sensed voltage is equal to the reference voltage, transistor Q2 is turned off and diode D10 conducts the current through the inductor and LEDs. Capacitor C12 eliminates most of the ripple current seen in the inductor. Resistor R4, capacitor C11, and transistor Q3 provide a linear current ramp that sets the constant off-time for a given output voltage. Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: LM3444 11 LM3444 SNVS682D – NOVEMBER 2010 – REVISED DECEMBER 2015 www.ti.com Feature Description (continued) VBUCK R4 C12 D10 Q3 L2 ICOLL LM3444 4 COFF GATE 8 ISNS 7 PGND 6 Q2 R3 C11 Figure 12. LM3444 Buck Regulation Circuit 7.3.5 Overview Of Constant Off-Time Control The conversion ratio of a buck converter is defined as given by Equation 3. VO tON = tON x fSW =D= tON + tOFF VIN (3) Constant off-time control architecture operates by simply defining the off-time and allowing the on-time, and therefore the switching frequency, to vary as either VIN or VO changes. The output voltage is equal to the LED string voltage (VLED), and should not change significantly for a given application. The input voltage or VBUCK in this analysis varies as the input line varies. The length of the on-time is determined by the sensed inductor current through a resistor to a voltage reference at a comparator. During the on-time, denoted by tON, MOSFET switch Q2 is on causing the inductor current to increase. During the on-time, current flows from VBUCK, through the LEDs, through L2, Q2, and finally through R3 to ground. At some point in time, the inductor current reaches a maximum (IL2-PK) determined by the voltage sensed at R3 and the ISNS pin. This sensed voltage across R3 is compared against the voltage of FILTER, at which point Q2 is turned off by the controller. 12 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: LM3444 LM3444 www.ti.com SNVS682D – NOVEMBER 2010 – REVISED DECEMBER 2015 Feature Description (continued) IL2-PK 'iL IAVE IL2-MIN IL2 (t) tON tOFF t Figure 13. Inductor Current Waveform in CCM During the off-period denoted by tOFF, the current through L2 continues to flow through the LEDs through D10. 7.3.6 Thermal Shutdown Thermal shutdown limits total power dissipation by turning off the output switch when the IC junction temperature exceeds 165°C. After thermal shutdown occurs, the output switch does not turn on until the junction temperature drops to approximately 145°C. 7.4 Device Functional Modes This device does not have any additional functional modes. Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: LM3444 13 LM3444 SNVS682D – NOVEMBER 2010 – REVISED DECEMBER 2015 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information 8.1.1 Determining Duty-Cycle (D) Equation 4 shows the duty-cycle (D). VLED VBUCK =D= tON tON + tOFF = tON x fSW (4) Equation 5 shows the duty-cycle with efficiency considered. VLED 1 u =D K VBUCK (5) For simplicity, choose efficiency from 75% to 85%. 8.1.2 Calculating Off-Time The off-time of the LM3444 is set by the user and remains fairly constant as long as the voltage of the LED stack remains constant. Calculating the off-time is the first step in determining the switching frequency of the converter, which is integral in determining some external component values. PNP transistor Q3, resistor R4, and the LED string voltage define a charging current into capacitor C11. A constant current into a capacitor creates a linear charging characteristic. dv i=C dt (6) Resistor R4, capacitor C11 and the current through resistor R4 (iCOLL), which is approximately equal to VLED/R4, are all fixed. Therefore, dv is fixed and linear, and dt (tOFF) can now be calculated as shown in Equation 7. R4 tOFF = C11 x 1.276V x VLED (7) Common equations for determining duty-cycle and switching frequency in any buck converter are shown in Equation 8. fSW = 1 tOFF + tON D= VLED tON = tON + tOFF VBUCK '¶ = tOFF tON + tOFF (8) Therefore, Equation 9 shows: fSW = 14 D 1-D , and fSW = tON tOFF (9) Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: LM3444 LM3444 www.ti.com SNVS682D – NOVEMBER 2010 – REVISED DECEMBER 2015 Application Information (continued) With efficiency of the buck converter in mind, Equation 10 shows: VLED VBUCK =KuD (10) Substituting and rearranging the equations, Equation 11 shows: fSW § ¨1 © = VLED · 1 u K VBUCK¸ ¹ tOFF (11) Off-time and switching frequency can now be calculated using the previous equations. 8.1.3 Setting the Switching Frequency Selecting the switching frequency for nominal operating conditions is based on tradeoffs between efficiency (better at low frequency) and solution size and cost (smaller at high frequency). The input voltage to the buck converter (VBUCK) changes with both line variations and over the course of each half-cycle of the input line voltage. The voltage across the LED string, however, remains constant, and therefore the off-time remains constant. The on-time, and therefore the switching frequency, varies as the VBUCK voltage changes with line voltage. A good design practice is to choose a desired nominal switching frequency knowing that the switching frequency decreases as the line voltage drops, and increases as the line voltage increases (Figure 14). 1.50 NORMALIZED SW FREQ Series connected LEDs 1.25 1.00 3 LEDs 5 LEDs 0.75 0.50 7 LEDs 9 LEDs 0.25 0 50 100 150 200 VBUCK (V) Figure 14. Graphical Illustration of Switching Frequency vs VBUCK The off-time of the LM3444 can be programmed for switching frequencies ranging from 30 kHz to over 1 MHz. A trade-off between efficiency and solution size must be considered when designing the LM3444 application. The maximum switching frequency attainable is limited only by the minimum on-time requirement (200 ns). Worst case scenario for minimum on time is when VBUCK is at its maximum voltage (AC high line) and the LED string voltage (VLED) is at its minimum value, as shown in Equation 12. VLED(MIN) 1 1 tON(MIN) = K u VBUCK(MAX) fSW (12) Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: LM3444 15 LM3444 SNVS682D – NOVEMBER 2010 – REVISED DECEMBER 2015 www.ti.com Application Information (continued) The maximum voltage seen by the Buck Converter is given by Equation 13. VBUCK(MAX) = VAC-RMS(MAX) x 2 (13) 8.1.4 Inductor Selection The controlled off-time architecture of the LM3444 regulates the average current through the inductor (L2), and therefore the LED string current. The input voltage to the buck converter (VBUCK) changes with line variations and over the course of each half-cycle of the input line voltage. The voltage across the LED string is relatively constant, and therefore the current through R4 is constant. This current sets the off-time of the converter and therefore the output volt-second product (VLED × off-time) remains constant. A constant volt-second product makes it possible to keep the ripple through the inductor constant as the voltage at VBUCK varies. VBUCK VLED C12 - D10 L2 VL2 Q2 R3 Figure 15. LM3444 External Components of the Buck Converter Use Equation 14 to calculate an ideal inductor. di Q=L dt (14) Given a fixed inductor value, L, Equation 14 states that the change in the inductor current over time is proportional to the voltage applied across the inductor. During the on-time, the voltage applied across the inductor is given in Equation 15. VL(ON-TIME) = VBUCK - (VLED + VDS(Q2) + IL2 × R3) (15) Because the voltage across the MOSFET switch (Q2) is relatively small, as is the voltage across sense resistor R3, we can approximately simplify this as shown in Equation 16, VL(ON-TIME) = VBUCK - VLED (16) During the off-time, the voltage seen by the inductor is given by Equation 17. VL(OFF-TIME) = VLED 16 (17) Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: LM3444 LM3444 www.ti.com SNVS682D – NOVEMBER 2010 – REVISED DECEMBER 2015 Application Information (continued) The value of VL(OFF-TIME) is relatively constant, because the LED stack voltage remains constant. If we rewrite the equation for an inductor inserting what we know about the circuit during the off-time, Equation 18 shows that we get: VL(OFF-TIME) = VLED = L x VL(OFF-TIME) = VLED = L x 'i 't (I(MAX) - I(MIN)) 't (18) Rearranging this gives Equation 19. 'i # tOFF x VLED L2 (19) From this, we can see that the ripple current (Δi) is proportional to off-time (tOFF) multiplied by a voltage, which is dominated by VLED divided by a constant (L2). These equations can be rearranged to calculate the desired value for inductor L2, as shown in Equation 20. L2 # tOFF x VLED 'i (20) The off time can be calculated using Equation 21: 1 VLED tOFF = 1 K u VBUCK fSW (21) Substituting toff in Equation 21 results in Equation 22: VLED 1 L2 = 1 VLED u K VBUCK fSW x 'i (22) See Typical Application to better understand the design process. 8.1.5 Setting the LED Current The LM3444 constant off-time control loop regulates the peak inductor current (IL2). The average inductor current equals the average LED current (IAVE). Therefore the average LED current is regulated by regulating the peak inductor current. IL2-PK 'iL IAVE IL2-MIN IL2 (t) tON tOFF t Figure 16. Inductor Current Waveform in CCM Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: LM3444 17 LM3444 SNVS682D – NOVEMBER 2010 – REVISED DECEMBER 2015 www.ti.com Application Information (continued) Knowing the desired average LED current, IAVE, and the nominal inductor current ripple, ΔiL, the peak current for an application running in continuous conduction mode (CCM) is defined in Equation 23. IL2-PK = IAVE + 'iL 2 (23) The LED current would then be calculated using Equation 24. IAVE(UNDIM) = IL2-PK(UNDIM) - 'iL 2 (24) This is important to calculate because this peak current multiplied by the sense resistor R3 determines when the internal comparator is tripped. The internal comparator turns the control MOSFET off once the peak sensed voltage reaches 750 mV. IL-PK(UNDIM) = 750 mV R3 (25) Current Limit: The trip voltage on the PWM comparator is 750 mV. However, if there is a short circuit or an excessive load on the output, higher than normal switch currents cause a voltage greater than 1.27 V on the ISNS pin which trip the I-LIM comparator. The I-LIM comparator resets the RS latch, turning off Q2. It also inhibits the Start Pulse Generator and the COFF comparator by holding the COFF pin low. A delay circuit prevents the start of another cycle for 180 µs. 8.1.6 Valley Fill Capacitors Determining voltage rating and capacitance value of the valley-fill capacitors: The maximum voltage seen by the valley-fill capacitors is calculated by Equation 26. VVF-CAP = VAC(MAX) 2 #stages (26) This is, of course, if the capacitors chosen have identical capacitance values and split the line voltage equally. Often a 20% difference in capacitance could be observed between like capacitors. Therefore a voltage rating margin of 25% to 50% should be considered. 8.1.7 Determining the Capacitance Value of the Valley-Fill Capacitors The valley-fill capacitors must be sized to supply energy to the buck converter (VBUCK) when the input line is less than its peak divided by the number of stages used in the valley fill (tX). The capacitance value must be calculated for the maximum LED current. 30° 150° tX VBUCK 8.33 ms 0° t 180° Figure 17. Two Stage Valley-Fill VBUCK Voltage 18 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: LM3444 LM3444 www.ti.com SNVS682D – NOVEMBER 2010 – REVISED DECEMBER 2015 Application Information (continued) From Figure 17 and the equation for current in a capacitor, i = C × dV/dt, the amount of capacitance needed at VBUCK is calculated as follows. At 60 Hz, and a valley-fill circuit of two stages, the hold-up time (tX) required at VBUCK is calculated as follows. The total angle of an AC half cycle is 180° and the total time of a half AC line cycle is 8.33 ms. When the angle of the AC waveform is at 30° and 150°, the voltage of the AC line is exactly ½ of its peak. With a two-stage valley-fill circuit, this is the point where the LED string switches from power being derived from AC line to power being derived from the hold up capacitors (C7 and C9). 60° out of 180° of the cycle or 1/3 of the cycle the power is derived from the hold up capacitors (1/3 × 8.33 ms = 2.78 ms). This is equal to the hold up time (dt) from the previous equation, and dv is the amount of voltage the circuit is allowed to droop. From Determining Maximum Number of Series Connected LEDs Allowed, we know the minimum VBUCK voltage is about 45 V for a 90-VAC to 135-VAC line. At 90-VAC low-line operating condition input, ½ of the peak voltage is 64 V. Thus, with some margin, the voltage at VBUCK can not droop more than about 15 V (dv). (i) is equal to (POUT/VBUCK), where POUT is equal to (VLED × ILED). Total capacitance (C7 in parallel with C9) can now be calculated. See Typical Application for further calculations of the valley-fill capacitors. 8.1.8 Determining Maximum Number of Series Connected LEDs Allowed The LM3444 is an off-line buck topology LED driver. A buck converter topology requires that the input voltage (VBUCK) of the output circuit must be greater than the voltage of the LED stack (VLED) for proper regulation. One must determine what the minimum voltage observed by the buck converter is before the maximum number of LEDs allowed can be determined. The following two variables must be determined to accomplish this: 1. AC line operating voltage. This is usually 90 VAC to 135 VAC for North America. Although the LM3444 can operate at much lower and higher input voltages, a range is needed to illustrate the design process. 2. The number of stages implemented in the valley-fill circuit (1, 2, or 3). In this example, the most common valley-fill circuit is used (two stages). VPEAK VAC t Figure 18. AC Line Figure 18 shows the AC waveform. One can easily see that the peak voltage (VPEAK) is always given by Equation 27. VAC-RMS-PK 2 (27) The voltage at VBUCK with a valley-fill stage of two looks similar to the waveforms in Figure 17. The purpose of the valley-fill circuit is to allow the buck converter to pull power directly off of the AC line when the line voltage is greater than its peak voltage divided by two (two-stage valley-fill circuit). During this time, the capacitors within the valley fill circuit (C7 and C8) are charged up to the peak of the AC line voltage. Once the line drops below its peak divided by two, the two capacitors are placed in parallel and deliver power to the buck converter. One can now see that if the peak of the AC line voltage is lowered due to variations in the line voltage, the DC offset (VDC) lowers. VDC is the lowest value that voltage VBUCK encounters. Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: LM3444 19 LM3444 SNVS682D – NOVEMBER 2010 – REVISED DECEMBER 2015 www.ti.com Application Information (continued) VBUCK(MIN) = VAC-RMS(MIN) 2 x SIN(T) #stages (28) Example: Line voltage = 90 VAC to 135 VAC Valley-fill = two stage VBUCK(MIN) = o 90 2 x SIN(135 ) = 45V 2 (29) Depending on what type and value of capacitors are used, some derating should be used for voltage droop when the capacitors are delivering power to the buck converter. With this derating, the lowest voltage the buck converter sees is about 42.5 V in this example. To determine how many LEDs can be driven, take the minimum voltage the buck converter sees (42.5 V) and divide it by the worst-case forward voltage drop of a single LED. Example: 42.5 V / 3.7 V = 11.5 LEDs (11 LEDs with margin) 8.1.9 Output Capacitor A capacitor placed in parallel with the LED or array of LEDs can be used to reduce the LED current ripple while keeping the same average current through both the inductor and the LED array. With a buck topology, the output inductance (L2) can now be lowered, making the magnetics smaller and less expensive. With a well designed converter, you can assume that all of the ripple is seen by the capacitor, and not the LEDs. One must ensure that the capacitor you choose can handle the RMS current of the inductor. See the manufacturer data sheets to ensure compliance. Usually an X5R or X7R capacitor from 1 µF and 10 µF of the proper voltage rating is sufficient. 8.1.10 Switching MOSFET The main switching MOSFET should be chosen with efficiency and robustness in mind. As shown in Equation 30, the maximum voltage across the switching MOSFET equals: VDS(MAX) = VAC-RMS(MAX) 2 (30) The average current rating should be greater than what is given in Equation 31. IDS-MAX = ILED(-AVE)(DMAX) (31) 8.1.11 Recirculating Diode The LM3444 buck converter requires a recirculating diode D10 (see Figure 8) to carry the inductor current during the MOSFET Q2 off-time. The most efficient choice for D10 is a diode with a low forward drop and near-zero reverse recovery time that can withstand a reverse voltage of the maximum voltage seen at VBUCK. For a common 110 VAC ± 20% line, the reverse voltage could be as high as 190 V, as shown in Equation 32. VD t VAC-RMS(MAX) 2 (32) As shown in Equation 33, the current rating must be at least: ID = (1 - DMIN) × ILED(AVE) (33) Or as shown in Equation 34: VLED(MIN) x ILED(AVE) ID = 1 VBUCK(MAX) (34) 8.2 Typical Application The following design example illustrates the process of calculating external component values. 20 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: LM3444 LM3444 www.ti.com SNVS682D – NOVEMBER 2010 – REVISED DECEMBER 2015 Typical Application (continued) TP3 VBUCK V+ D3 TP4 LED+ BR1 + R6 D9 C7 R8 D8 C10 C2 + L4 D4 R7 C9 VLED R4 C12 C15 L3 D10 V+ C1 TP5 LEDVLED- D12 Q3 R2 L5 TP14 Q1 D2 R10 L2 D1 C5 L1 ICOLL RT1 LM3444 F1 U1 1 NC NC 10 2 NC VCC 9 3 NC J1 VAC TP15 GATE 8 Q2 TP16 4 COFF ISNS 7 5 FLTR2 GND 6 R3 C4 C11 TP7-9 Figure 19. LM3444 Design Example 1 Input = 90 VAC to 135 VAC VLED = 7 × HB LED String Application at 400 mA Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: LM3444 21 LM3444 SNVS682D – NOVEMBER 2010 – REVISED DECEMBER 2015 www.ti.com Typical Application (continued) 8.2.1 Design Requirements Known: 1. Input voltage range (90 VAC to 135 VAC) 2. Number of LEDs in series = 7 3. Forward voltage drop of a single LED = 3.6 V 4. LED stack voltage = (7 × 3.6 V) = 25.2 V Choose: 1. Nominal switching frequency, fSW-TARGET = 350 kHz 2. ILED(AVE) = 400 mA 3. Δi (usually 15% to 30% of ILED(AVE)) = (0.30 × 400 mA) = 120 mA 4. Valley-fill stages (1, 2, or 3) = 2 5. Assumed minimum efficiency = 80% 8.2.2 Detailed Design Procedure Calculate: 1. Calculate minimum voltage VBUCK, as shown in Equation 35, which yields: VBUCK(MIN) = o 90 2 x SIN(135 ) = 45V 2 (35) 2. Calculate maximum voltage VBUCK, as shown in Equation 36, which yields: VBUCK(MAX) = 135 2 = 190V (36) 3. Calculate tOFF at VBUCK nominal line voltage, as given by Equation 37. 1 25.2V u 0.8 115 2 1 tOFF = (250 kHz) = 3.23 Ps (37) 4. Calculate tON(MIN) at high line to ensure that tON(MIN) > 200 ns, as given by Equation 38. 1 25.2V u 0.8 135 2 tON (MIN) = 1 u 3.23 Ps = 638 ns 1 25.2V u 0.8 135 2 (38) 5. Calculate C11 and R4 in steps 6 through 9. 6. Choose current through R4 (from 50 µA to 100 µA): 70 µA as given by Equation 39. VLED = 360 k: R4 = ICOLL 7. Use a standard value of 365 kΩ. 8. Calculate C11 as given by Equation 40. VLED tOFF C11 = = 175 pF R4 1.276 (39) (40) 9. Use standard value of 120 pF. 10. Calculate ripple current: 400 mA × 0.30 = 120 mA 11. Calculate inductor value at tOFF = 3 µs as given by Equation 41. 22 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: LM3444 LM3444 www.ti.com SNVS682D – NOVEMBER 2010 – REVISED DECEMBER 2015 Typical Application (continued) 25.2V 1 L2 = 1 25.2V u 0.8 115 2 (350 kHz x 0.1A) = 580 PH (41) 12. Choose C10: 1 µF, 200 V 13. Calculate valley-fill capacitor values: VAC low line = 90 VAC, VBUCK minimum equals 60 V. Set droop for 20-V maximum at full load and low line as shown in Equation 42. i=C dv dt where • • • • i equals POUT/VBUCK (270 mA) dV equals 20 V dt equals 2.77 ms CTOTAL equals 37 µF (42) Therefore, C7 = C9 = 22 µF 8.2.3 Application Curve 95.0 14 Series connected LEDs EFFICIENCY (%) 90.0 85.0 10 Series connected LEDs 80.0 75.0 80 90 100 110 120 130 140 LINE VOLTAGE (VAC) Figure 20. Efficiency vs Input Voltage Table 1. Bill of Materials QTY DESIGNATOR DESCRIPTION MANUFACTURER MANUFACTURER PART NUMBER LM3444MM 1 U1 IC, CTRLR, DRVR-LED, VSSOP TI 1 BR1 Bridge Rectifiier, SMT, 400 V, 800 mA DiodesInc HD04-T 1 L1 Common mode filter DIP4NS, 900 mA, 700 µH Panasonic ELF-11090E 1 L2 Inductor, SHLD, SMT, 1 A, 470 µH Coilcraft MSS1260-474-KLB 2 L3, L4 Diff mode inductor, 500 mA 1 mH Coilcraft MSS1260-105KL-KLB 1 L5 Bead Inductor, 160 Ω, 6 A Steward HI1206T161R-10 3 C1, C2, C15 Cap, Film, X2Y2, 12.5 MM, 250 VAC, 20%, 10 nF Panasonic ECQ-U2A103ML 1 C4 Cap, X7R, 0603, 16 V, 10%, 100 nF Murata GRM188R71C104KA01D 2 C5, C6 Cap, X5R, 1210, 25 V, 10%, 22 µF Murata GRM32ER61E226KE15L 2 C7, C9 Cap, AL, 200 V, 105C, 20%, 33 µF UCC EKXG201ELL330MK20S 1 C10 Cap, Film, 250 V, 5%, 10 nF Epcos B32521C3103J 1 C12 Cap, X7R, 1206, 50 V, 10%, 1 µF Kemet C1206F105K5RACTU Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: LM3444 23 LM3444 SNVS682D – NOVEMBER 2010 – REVISED DECEMBER 2015 www.ti.com Typical Application (continued) Table 1. Bill of Materials (continued) QTY DESIGNATOR DESCRIPTION MANUFACTURER MANUFACTURER PART NUMBER 1 C11 Cap, C0G, 0603, 100 V, 5%, 120 pF Murata GRM1885C2A121JA01D BZX84C15LT1G 24 1 D1 Diode, ZNR, SOT23, 15 V, 5% OnSemi 2 D2, D13 Diode, SCH, SOD123, 40 V, 120 mA NXP BAS40H 4 D3, D4, D8, D9 Diode, FR, SOD123, 200 V, 1 A Rohm RF071M2S 1 D10 Diode, FR, SMB, 400 V, 1 A OnSemi MURS140T3G 1 D12 TVS, VBR = 144 V Fairchild SMBJ130CA 1 R2 Resistor, 1206, 1%, 100 kΩ Panasonic ERJ-8ENF1003V 1 R3 Resistor, 1210, 5%, 1.8Ω Panasonic ERJ-14RQJ1R8U 1 R4 Resistor, 0603, 1%, 576 kΩ Panasonic ERJ-3EKF5763V 2 R6, R7 Resistor, 0805, 1%, 1 MΩ Rohm MCR10EZHF1004 2 R8, R10 Resistor, 1206, 0 Ω Yageo RC1206JR-070RL 1 RT1 Thermistor, 120 V, 1.1 A, 50 Ω at 25°C Thermometrics CL-140 2 Q1, Q2 XSTR, NFET, DPAK, 300 V, 4 A Fairchild FQD7N30TF 1 Q3 XSTR, PNP, SOT23, 300 V, 500 mA Fairchild MMBTA92 1 J1 Terminal Block 2 pos Phoenix Contact 1715721 1 F1 Fuse, 125 V, 1.25 A bel SSQ 1.25 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: LM3444 LM3444 www.ti.com SNVS682D – NOVEMBER 2010 – REVISED DECEMBER 2015 9 Power Supply Recommendations Use any AC power supply capable of the maximum application requirements for voltage and total power. 10 Layout 10.1 Layout Guidelines Keep the low power components for FILTER and COFF close to the LM3444 with short traces. The ISNS trace should also be as short and direct as possible. Keep the high current switching paths generated by R3, Q2, L2, and D10 as short as possible to minimize generated switching noise and improve EMI. 10.2 Layout Example RECTIFIED AC INPUT LED+ = VIA NC NC NC VCC NC GATE LED- COFF ISNS FLTR2 GND GND Figure 21. Layout Recommendation Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: LM3444 25 LM3444 SNVS682D – NOVEMBER 2010 – REVISED DECEMBER 2015 www.ti.com 11 Device and Documentation Support 11.1 Device Support 11.1.1 Third-Party Products Disclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE. 11.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. 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