ICST ICS8761CYT Low voltage, low skew, pci / pci-x clock generator Datasheet

ICS8761
Integrated
Circuit
Systems, Inc.
LOW VOLTAGE, LOW SKEW,
PCI / PCI-X CLOCK GENERATOR
GENERAL DESCRIPTION
FEATURES
The ICS8761 is a low voltage, low skew PCI /
PCI-X Clock Generator and a member of the
HiPerClockS™
HiPerClockS™ family of High Performance Clock
Solutions from ICS. The ICS8761 has a selectable
REF_CLK or crystal input. The REF_CLK input
accepts LVCMOS or LVTTL input levels. The ICS8761 has a
fully integrated PLL along with frequency configurable clock
and feedback outputs for multiplying and regenerating clocks
with “zero delay”. Using a 20MHz or 25MHz crystal or a
33.333MHz or 66.666MHz reference frequency, the ICS8761
will generate output frequencies of 33.333MHz, 66.666MHz,
100MHz and 133.333MHz simultaneously.
• Fully integrated PLL
ICS
• 17 LVCMOS/LVTTL outputs, 15Ω typical output impedance
• Selectable crystal oscillator interface or
LVCMOS/LVTTL REF_CLK
• Maximum output frequency: 166.67MHz
• Maximum crystal input frequency: 38MHz
• Maximum REF_CLK input frequency: 83.33MHz
• Individual banks with selectable output dividers for
generating 33.333MHz, 66.66MHz, 100MHz and
133.333MHz simultaneously
• Separate feedback control for generating PCI / PCI-X
frequencies from a 20MHz or 25MHz crystal or 33.333MHz
or 66.666MHz reference frequency
The low impedance LVCMOS/LVTTL outputs of the ICS8761
are designed to drive 50Ω series or parallel terminated
transmission lines.
• Cycle-to-cycle jitter: 70ps (maximum)
• Period jitter, RMS: 17ps (maximum)
• Output skew: 230ps (maximum)
• Bank skew: 40ps (maximum)
• Static phase offset: 0 ± 150ps (maximum)
• Full 3.3V or 3.3V core, 2.5V multiple output supply modes
BLOCK DIAGRAM
• 0°C to 85°C ambient operating temperature
OEA
MR
• Lead-Free package available
D_SELA0
D_SELA1
QA0
00
01
10
11
QD3
VDDOD
QD2
GND
QD1
QB2
XTAL2
FB_IN
QB3
V DD
5
44
V DD
XTAL_SEL
6
43
FBDIV_SEL0
PLL_SEL
7
42
FBDIV_SEL1
VDDA
8
41
MR
V DD
9
40
V DD
10
39
D_SELD0
11
38
D_SELD1
OEC
12
37
OED
OEA
13
36
OEB
D_SELA0
14
35
D_SELB0
D_SELA1
15
34
D_SELB1
QD0
QD1
QD2
GND
33
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
GND
GND
QB3
QC2 D_SELC0
QC3 D_SELC1
ICS8761
VDDOB
QC1
64-Lead LQFP
10mm x 10mm x 1.4mm package body
Y package
Top View
FB_OUT
FBDIV_SEL1
FBDIV_SEL0
8761CY
VDDOD
VDDOFB
45
GND
÷6
÷12
÷16
÷20
QD0
46
4
QD3
D_SELD1
D_SELD0
GND
3
QB2
11
QC3
XTAL1
GND
00
01
10
VDDOC
QB1
QB1
OED
QC2
FB_OUT
VDDOB
D_SELC1
D_SELC0
GND
47
QC0
00
01
10
11
QC1
2
D_SELB1
D_SELB0
OEC
VDDOC
GND
QB0
OEB
QB0
GND
10
11
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
QA3
FB_IN
PLL_SEL
1
VDDOA
00
01
REF_CLK
QA2
XTAL_SEL
QA3
GND
PLL
÷6
÷12
QA1
XTAL2
1
QA2
VDDOA
OSC
1
00
01
10
11
GND
0
XTAL1
÷3
÷4
QA0
0
QC0
PIN ASSIGNMENT
QA1
REF_CLK
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1
REV. C SEPTEMBER 7, 2004
ICS8761
Integrated
Circuit
Systems, Inc.
LOW VOLTAGE, LOW SKEW,
PCI / PCI-X CLOCK GENERATOR
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
1
REF_CLK
Input
2, 16, 17,
21, 25, 29,
33, 48, 52,
56, 60, 64
GND
Power
Power supply ground.
3, 4
XTAL1,
XTAL2
Input
Crystal oscillator interface. XTAL1 is the input. XTAL2 is the output.
5, 9, 40, 44
VDD
Power
Pulldown Reference clock input. LVCMOS / LVTTL interface levels.
Core supply pins.
6
XTAL_SEL
Input
Pullup
7
PLL_SEL
Input
Pullup
8
VDDA
Power
10, 11
D_SELC0,
D_SELC1
Input
Pulldown
12
OEC
Input
Pullup
13
OEA
Input
Pullup
Input
Pulldown
14, 15
18, 20,
22, 24
19, 23
26, 28,
30, 32
27, 31
34, 35
D_SELA0,
D_SELA1
QA0, QA1,
QA2, QA3
VDDOA
QB0, QB1,
QB2, QB3
VDDOB
D_SELB1,
D_SELB0
Selects between crystal oscillator or reference clock as the PLL
reference source. Selects XTAL inputs when HIGH. Selects REF_CLK
when LOW. LVCMOS / LVTTL interface levels.
Selects between PLL and bypass mode. When HIGH, selects PLL.
When LOW, selects reference clock. LVCMOS / LVTTL interface levels.
Analog supply pin. See Applications Note for filtering.
Output
Power
Output
Power
Input
Pulldown
36
OEB
Input
Pullup
37
OED
Input
Pullup
38, 39
D_SELD1,
D_SELD0
Input
Pulldown
41
MR
Input
Pulldown
42
FBDIV_SEL1
Input
Pulldown
43
FBDIV_SEL0
Input
Pullup
45
FB_IN
Input
Pulldown
8761CY
Description
Selects divide value for Bank C outputs as described in Table 3.
LVCMOS / LVTTL interface levels.
Determines state of Bank C outputs. When HIGH, outputs are enabled.
When LOW, outputs are disabled. LVCMOS / LVTTL interface levels.
Determines state of Bank A outputs. When HIGH, outputs are enabled.
When LOW, outputs are disabled. LVCMOS / LVTTL interface levels.
Selects divider value for Bank A outputs as described in Table 3.
LVCMOS / LVTTL interface levels.
Bank A clock outputs. 15Ω typical output impedance.
LVCMOS / LVTTL interface levels.
Output supply pins for Bank A outputs.
Bank B clock outputs. 15Ω typical output impedance.
LVCMOS / LVTTL interface levels.
Output supply pins for Bank B outputs.
Selects divider value for Bank B outputs as described in Table 3.
LVCMOS / LVTTL interface levels.
Determines state of Bank B outputs. When HIGH, outputs are enabled.
When LOW, outputs are disabled. LVCMOS / LVTTL interface levels.
Determines state of Bank D outputs. When HIGH, outputs are enabled.
When LOW, outputs are disabled. LVCMOS / LVTTL interface levels.
Selects divider value for Bank D outputs as described in Table 3.
LVCMOS / LVTTL interface levels.
Active HIGH Master reset. When logic HIGH, the internal dividers
are reset causing the outputs to go low. When logic LOW, the internal
dividers and the outputs are enabled.
LVCMOS / LVTTL interface levels.
Selects divider value for bank feedback output as described in Table 3.
LVCMOS / LVTTL interface levels.
Selects divider value for bank feedback output as described in Table 3.
LVCMOS / LVTTL interface levels.
Feedback input to phase detector for generating clocks with "zero
delay". LVCMOS / LVTTL interface levels.
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2
REV. C SEPTEMBER 7, 2004
ICS8761
Integrated
Circuit
Systems, Inc.
LOW VOLTAGE, LOW SKEW,
PCI / PCI-X CLOCK GENERATOR
Number
Name
46
VDDOFB
Power
Type
47
FB_OUT
Output
49, 51,
53, 55
50, 54
57, 59,
61, 63
58, 62
QD3, QD2,
QD1, QD0
VDDOD
QC3, QC2,
QC1, QC0
VDDOC
Description
Output supply pin for FB_Out output.
Feedback output. Connect to FB_IN. 15Ω typical output impedance.
LVCMOS / LVTTL interface levels.
Bank D clock outputs. 15Ω typical output impedance.
LVCMOS / LVTTL interface levels.
Output supply pins for Bank D outputs.
Bank C clock outputs. 15Ω typical output impedance.
LVCMOS / LVTTL interface levels.
Output supply pins for Bank C outputs.
Output
Power
Output
Power
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
CIN
Test Conditions
Minimum Typical
Maximum
Units
Input Capacitance
4
pF
RPULLUP
Input Pullup Resistor
51
KΩ
RPULLDOWN
Input Pulldown Resistor
51
KΩ
CPD
Power Dissipation Capacitance
(per output); NOTE 1
9
pF
11
pF
ROUT
Output Impedance
VDD, VDDA = 3.465V; VDDOx = 3.465V
VDD, VDDA = 3.465V; VDDOx = 2.625V
Ω
15
NOTE 1: VDDOx denotes VDDOA, VDDOB, VDDOC, VDDOD, VDDOFB.
TABLE 3A. OUTPUT CONTROL PIN FUNCTION TABLE
Inputs
Outputs
MR
OEA
OEB
OEC
OED
QA0:QA3
QB0:QB3
QC0:QC3
QD0:QD3
1
1
1
1
1
LOW
LOW
LOW
LOW
0
1
1
1
1
Active
Active
Active
Active
X
0
0
0
0
HiZ
HiZ
HiZ
HiZ
TABLE 3C. PLL INPUT FUNCTION TABLE
TABLE 3B. OPERATING MODE FUNCTION TABLE
Inputs
PLL_SEL
8761CY
Inputs
Operating Mode
XTAL_SEL
PLL Input
0
Bypass
0
REF_CLK
1
PLL
1
XTAL Oscillator
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3
REV. C SEPTEMBER 7, 2004
ICS8761
Integrated
Circuit
Systems, Inc.
LOW VOLTAGE, LOW SKEW,
PCI / PCI-X CLOCK GENERATOR
TABLE 3D. CONTROL FUNCTION TABLE
Outputs
Inputs
D_SELx1
D_SELx0
0
0
0
PLL_SEL =1
0
Reference
Frequency Range
(MHz)
41.6 - 83.33
FBDIV_SEL1 FBDIV_SEL0
Frequency
QX0:QX3
QX0:QX3
(MHz)
FB_OUT
(MHz)
x2
83.33 - 166.67
41.6 - 83.33
0
0
0
1
20.83 - 41.67
x4
83.33 - 166.67
20.83 - 41.67
0
0
1
0
15.62 - 31.25
x 5.33
83.33 - 166.67
15.62 - 31.25
0
0
1
1
12.5 - 25
x 6.67
83.33 - 166.67
12.5 - 25
0
1
0
0
41.6 - 83.33
x 1.5
62.4 - 125
41.6 - 83.33
0
1
0
1
20.83 - 41.67
x3
62.4 - 125
20.83 - 41.67
0
1
1
0
15.62 - 31.25
x4
62.4 - 125
15.62 - 31.25
0
1
1
1
12.5 - 25
x5
62.4 - 125
12.5 - 25
1
0
0
0
41.6 - 83.33
x1
41.6 - 83.33
41.6 - 83.33
1
0
0
1
20.83 - 41.67
x2
41.6 - 83.33
20.83 - 41.67
1
0
1
0
15.62 - 31.25
x 2.67
41.6 - 83.33
15.62 - 31.25
1
0
1
1
12.5 - 25
x 3.33
41.6 - 83.33
12.5 - 25
1
1
0
0
41.6 - 83.33
÷2
20.8 - 41.67
41.6 - 83.33
1
1
0
1
20.83 - 41.67
÷1
20.8 - 41.67
20.83 - 41.67
1
1
1
0
15.62 - 31.25
x 1.33
20.8 - 41.67
15.62 - 31.25
1
1
1
1
12.5 - 25
x 1.67
20.8 - 41.67
12.5 - 25
NOTE: D_SELX1 denotes D_SELA1, D_SELB1, D_SELC1, and D_SELD1. D_SELX0 denotes D_SELA0, D_SELB0,
D_SELC0, and D_SELD0. QX0:QX3 denotes QA0:QA3, QB0:QB3, QC0:QC3, and QD0:QD3.
TABLE 3E. CONTROL FUNCTION TABLE (PCI CONFIGURATION)
Outputs
Inputs
D_SELx1
D_SELx0
0
0
0
0
Reference Frequency
(MHz)
66.67
FBDIV_SEL1 FBDIV_SEL0
PLL_SEL = 1
QX0:QX3
x2
Frequency
QX0:QX3
FB_OUT
(MHz)
(MHz)
133
66.67
0
0
0
1
33.33
x4
133
0
0
1
0
25
x 5.33
133
33.33
25
0
0
1
1
20
x 6.67
133
20
0
1
0
0
66.67
x 1.5
100
66.67
0
1
0
1
33.33
x3
100
33.33
0
1
1
0
25
x4
100
25
0
1
1
1
20
x5
100
20
1
0
0
0
66.67
x1
66.67
66.67
1
0
0
1
33.33
x2
66.67
33.33
1
0
1
0
25
x 2.67
66.67
25
1
0
1
1
20
x 3.33
66.67
20
1
1
0
0
66.67
÷2
33.33
66.67
1
1
0
1
33.33
÷1
33.33
33.33
1
1
1
0
25
x 1.33
33.33
25
1
1
1
1
20
x 1.67
33.33
20
NOTE: D_SELx1 denotes D_SELA1, D_SELB1, D_SELC1, and D_SELD1. D_SELx0 denotes D_SELA0, D_SELB0,
D_SELC0, and D_SELD0. QX0:QX3 denotes QA0:QA3, QB0:QB3, QC0:QC3, and QD0:QD3.
8761CY
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4
REV. C SEPTEMBER 7, 2004
ICS8761
Integrated
Circuit
Systems, Inc.
LOW VOLTAGE, LOW SKEW,
PCI / PCI-X CLOCK GENERATOR
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
4.6V
Inputs, VI
-0.5V to VDD + 0.5 V
Outputs, VO
-0.5V to VDDOx + 0.5V
Package Thermal Impedance, θJA
41.1°C/W (0 lfpm)
Storage Temperature, TSTG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDOX = 3.3V±5%, TA = 0°C TO 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VDD
Core Supply Voltage
3.135
3.3
3.465
V
VDDA
Analog Supply Voltage
3.135
3.3
3.465
V
3.135
3.3
VDDOx
Output Supply Voltage; NOTE 1
3.465
V
IDD
Power Supply Current
175
mA
IDDA
Analog Supply Current
55
mA
25
mA
Maximum
Units
2
VDD + 0.3
V
2
VDD + 0.3
V
-0.3
0.8
V
-0.3
1.3
V
VDD = VIN = 3.465V
150
µA
VDD = VIN = 3.465V
5
µA
Output Supply Current; NOTE 2
IDDOx
NOTE 1: VDDOx denotes VDDOA, VDDOB, VDDOC, VDDOD, and VDDOFB.
NOTE 2: IDDOx denotes IDDOA, IDDOB, IDDOC, IDDOD, and IDDOFB.
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDOX = 3.3V±5%, TA = 0°C TO 85°C
Symbol
VIH
VIL
IIH
IIL
VOH
Parameter
Test Conditions
OEA:OED, XTAL_SEL, MR,
D_SELA0:D_SELD0, FB_IN,
Input
D_SELA1:D_SELD1, PLL_SEL,
High Voltage FBDIV_SEL0, FBDIV_SEL1
REF_CLK
OEA:OED, XTAL_SEL, MR,
D_SELA0:D_SELD0, FB_IN,
Input
Low Voltage D_SELA1, D_SELD1, PLL_SEL
REF_CLK
D_SELA0:D_SELD0, FB_IN, MR,
D_SELA1:D_SELD1, REF_CLK,
Input
FBDIV_SEL1
High Current
XTAL_SEL, PLL_SEL,
FBDIV_SEL0, OEA:OED
D_SELA0:D_SELD0, FB_IN, MR,
D_SELA1:D_SELD1, REF_CLK,
Input
FBDIV_SEL1
Low Current
XTAL_SEL, PLL_SEL,
FBDIV_SEL0, OEA:OED
VOL
Output Low Voltage; NOTE 1
Output Tristate Current Low
Typical
VDD = 3.465V,
VIN = 0V
-5
µA
VDD = 3.465V,
VIN = 0V
-150
µA
2.6
V
Output High Voltage; NOTE 1
IOZL
Minimum
0.5
-5
IOZH
Output Tristate Current High
NOTE 1: Outputs terminated with 50Ω to VDDOx/2. See Parameter Measurement Information section,
"3.3V Output Load Test Circuit".
8761CY
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5
V
µA
5
µA
REV. C SEPTEMBER 7, 2004
ICS8761
Integrated
Circuit
Systems, Inc.
LOW VOLTAGE, LOW SKEW,
PCI / PCI-X CLOCK GENERATOR
TABLE 5A. AC CHARACTERISTICS, VDD = VDDA = VDDOX = 3.3V±5%, TA = 0°C TO 85°C
Symbol
Parameter
fMAX
Output Frequency
t(Ø)
Static Phase Offset; NOTE 1, 7
t sk(b)
t sk(o)
Bank Skew; NOTE 2, 6
tjit(cc)
Test Conditions
Minimum
f = 50MHz
-150
Output Skew; NOTE 3, 6
f = 50MHz; NOTE 4, 7
f = 25MHz XTAL,
133.3MHz out
Cycle-to-Cycle Jitter; 6
tjit(per)
Period Jitter, RMS; NOTE 4, 6, 7, 8
tL
PLL Lock Time
tR
Output Rise Time
20% to 80%
tF
Output Fall Time
20% to 80%
Typical
Maximum
Units
166.67
MHz
150
ps
40
ps
230
ps
70
ps
190
ps
17
ps
1
ms
300
800
ps
300
800
ps
odc
Output Duty Cycle; NOTE 5, 7
45
55
NOTE 1: Defined as the time difference between the input reference clock and the average feedback input signal
when the PLL is locked and the input reference frequency is stable. Measured from VDD/2 of the input to
VDDOx/2 of the output.
NOTE 2: Defined as skew within a bank of outputs at the same voltages and with equal load conditions.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VDDOx/2.
NOTE 4: Jitter performance using LVCMOS inputs.
NOTE 5: Measured using REF_CLK. For XTAL input, refer to Application Note.
NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 7: Tested with D_SELXX =10 (divide by 6); FBDIV_SEL = 00 (divide by 6).
NOTE 8: This parameter is defined as an RMS value.
%
8761CY
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6
REV. C SEPTEMBER 7, 2004
ICS8761
Integrated
Circuit
Systems, Inc.
LOW VOLTAGE, LOW SKEW,
PCI / PCI-X CLOCK GENERATOR
TABLE 4C. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDO = 2.5V±5%, TA = 0°C TO 85°C
X
Symbol
Parameter
Minimum
Typical
Maximum
Units
VDD
Core Supply Voltage
Test Conditions
3.135
3.3
3.465
V
VDDA
Analog Supply Voltage
3.135
3.3
3.465
V
2.375
2.5
VDDOx
Output Supply Voltage; NOTE 1
2.625
V
IDD
Power Supply Current
160
mA
IDDA
Analog Supply Current
50
mA
210
mA
Output Supply Current; NOTE 2
IDDOx
NOTE 1: VDDOx denotes VDDOA, VDDOB, VDDOC, VDDOD, and VDDOFB.
NOTE 2: IDDOx denotes IDDOA, IDDOB, IDDOC, IDDOD, and IDDOFB.
TABLE 4D. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDO = 2.5V±5%, TA = 0°C TO 85°C
X
Symbol
VIH
VIL
IIH
IIL
Parameter
Test Conditions
OEA:OED, XTAL_SEL, MR,
D_SELA0:D_SELD0, FB_IN,
Input
D_SELA1:D_SELD1, PLL_SEL,
High Voltage FBDIV_SEL0, FBDIV_SEL1
REF_CLK
OEA:OED, XTAL_SEL, MR,
D_SELA0:D_SELD0, FB_IN,
Input
D_SELA1:D_SELD1, PLL_SEL,
Low Voltage FBDIV_SEL0, FBDIV_SEL1
REF_CLK
D_SELA0:D_SELD0, FB_IN, MR,
D_SELA1:D_SELD1, REF_CLK,
Input
FBDIV_SEL1
High Current
XTAL_SEL, PLL_SEL,
FBDIV_SEL0, OEA:OED
D_SELA0:D_SELD0, FB_IN, MR,
D_SELA1:D_SELD1, REF_CLK,
Input
FBDIV_SEL1
Low Current
XTAL_SEL, PLL_SEL,
FBDIV_SEL0, OEA:OED
VOH
Output High Voltage; NOTE 1
VOL
Output Low Voltage; NOTE 1
IOZL
Output Tristate Current Low
Minimum
Typical
Maximum
Units
2
VDD + 0.3
V
2
VDD + 0.3
V
-0.3
0.8
V
-0.3
1.3
V
VDD = VIN = 3.465V
150
µA
VDD = VIN = 3.465V
5
µA
VDD = 3.465V,
VIN = 0V
-5
µA
VDD = 3.465V,
VIN = 0V
-150
µA
1.8
-5
IOZH
Output Tristate Current High
NOTE 1: Outputs terminated with 50Ω to VDDOx/2. See Parameter Measurement Information section,
"3.3V/2.5V Output Load Test Circuit".
8761CY
V
0.5
www.icst.com/products/hiperclocks.html
7
V
µA
5
µA
REV. C SEPTEMBER 7, 2004
ICS8761
Integrated
Circuit
Systems, Inc.
LOW VOLTAGE, LOW SKEW,
PCI / PCI-X CLOCK GENERATOR
TABLE 5B. AC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDO = 2.5V±5%, TA = 0°C TO 85°C
X
Symbol
Parameter
fMAX
Output Frequency
t(Ø)
Static Phase Offset; NOTE 1, 7
t sk(b)
t sk(o)
Bank Skew; NOTE 2, 6
tjit(cc)
Test Conditions
Minimum
f = 50MHz
-350
Typical
Maximum
Units
166.67
MHz
Output Skew; NOTE 3, 6
f = 50MHz; NOTE 4, 7
f = 25MHz XTAL,
133.3MHz out
Cycle-to-Cycle Jitter; NOTE 6
tjit(per)
Period Jitter, RMS; NOTE 4, 6, 7, 8
tL
PLL Lock Time
tR
Output Rise Time
20% to 80%
tF
Output Fall Time
20% to 80%
20
ps
40
ps
230
ps
70
ps
190
ps
17
ps
1
ms
300
800
ps
300
800
ps
odc
Output Duty Cycle; NOTE 5, 7
45
55
NOTE 1: Defined as the time difference between the input reference clock and the average feedback input signal
when the PLL is locked and the input reference frequency is stable. Measured from VDD/2 of the input to
VDDOX/2 of the output.
NOTE 2: Defined as skew within a bank of outputs at the same voltages and with equal load conditions.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VDDOx/2.
NOTE 4: Jitter performance using LVCMOS inputs.
NOTE 5: Measured using REF_CLK. For XTAL input, refer to Application Note.
NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 7: Tested with D_SELXX =10 (divide by 6); FBDIV_SEL = 00 (divide by 6).
NOTE 8: This parameter is defined as an RMS value
%
TABLE 6. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Mode of Oscillation
Typical Maximum
Units
Fundamental
Frequency
10
38
Equivalent Series Resistance (ESR)
MHz
Ω
70
Shunt Capacitance
7
pF
TABLE 7. PLL INPUT REFERENCE CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 85°C
X
Symbol
Parameter
fREF
Reference Frequency
8761CY
Test Conditions
Minimum
10
www.icst.com/products/hiperclocks.html
8
Typical
Maximum
Units
83.33
MHz
REV. C SEPTEMBER 7, 2004
ICS8761
Integrated
Circuit
Systems, Inc.
LOW VOLTAGE, LOW SKEW,
PCI / PCI-X CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
1.65V±5%
2.05V±5% 1.25V±5%
SCOPE
VDD,
VDDA, VDDOx
Qx
LVCMOS
SCOPE
VDD,
VDDA
VDDOx
Qx
LVCMOS
GND
GND
-1.165V±5%
-1.25V±5%
3.3V OUTPUT LOAD AC TEST CIRCUIT
3.3V/2.5V OUTPUT LOAD AC TEST CIRCUIT
VDDO
2
V
DDOX
Qx
2
VDDO
2
V
DDOX
Qy
2
t sk(o)
Qy
t sk(o)
OUTPUT SKEW
BANK SKEW (Where X denotes outputs in the same Bank)
V
V
DDOX
DDOX
2
tcycle
2
tcycle n+1
➤
n
VDD
V
DDOX
2
➤
➤
QAx,
QBx,
QCx,
QDx
2
REF_CL:K
➤
VDD
2
FB_IN
t jit(cc) = tcycle n –tcycle n+1
➤ t (Ø)
➤
Qx
1000 Cycles
STATIC PHASE OFFSET
CYCLE-TO-CYCLE JITTER
QAx, QBx,
QCx, QDx,
FB_OUT
VDDOX
VDDOX
VDDOX
2
2
2
80%
t PW
t
R
t
F
t PW
t PERIOD
tPW & tPERIOD
8761CY
20%
20%
Clock Outputs
t PERIOD
odc =
80%
OUTPUT RISE/FALL TIME
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9
REV. C SEPTEMBER 7, 2004
ICS8761
Integrated
Circuit
Systems, Inc.
LOW VOLTAGE, LOW SKEW,
PCI / PCI-X CLOCK GENERATOR
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS8761 provides separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VDD, VDDA, and VDDOx
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10µF and a .01µF bypass
capacitor should be connected to each VDDA.
3.3V
VDD
.01µF
10Ω
VDDA
.01µF
10 µF
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS8761 crystal interface is shown in Figure 2. While layout
the PC Board, it is recommended to provide C1 and C2 spare
footprints for frequency fine tuning. For an 18pF parallel reso-
nant crystal, the C1 and C2 are expected to be ~10pF and ~5pF
respectively.
XTAL2
C1
SPARE
X1
18pF Parallel Cry stal
XTAL1
C2
SPARE
FIGURE 2. CRYSTAL INPUT INTERFACE
8761CY
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10
REV. C SEPTEMBER 7, 2004
ICS8761
Integrated
Circuit
Systems, Inc.
LOW VOLTAGE, LOW SKEW,
PCI / PCI-X CLOCK GENERATOR
SCHEMATIC EXAMPLE
Figure 3 shows a schematic example of the ICS8761. In this
example, the input is driven by an ICS HiPerClockS LVHSTL
driver. The decoupling capacitors should be physically located
near the power pin. For ICS8761, the unused clock outputs can
be left floating. The optional C1 and C2 are spare footprints for
frequency fine tuning.
Zo = 50
R1
36
VDDO
Receiv er
VDD
Zo = 50
R2
1K
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
1K
U1
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
X1
25MHz,18pF
R7
C2
SP
10
VDD
C16
C17
REF_CLK
GND
XTAL1
XTAL2
VDD
XTAL_SEL
PLL_SEL
VDDA
VDD
D_SELC0
D_SELC1
OEC
OEA
D_SELA0
D_SELA1
GND
Receiv er
GND
FB_OUT
VDDOFB
FB_IN
VDD
FBDIV_SEL0
FBDIV_SEL1
MR
VDD
D_SELD0
D_SELD1
OED
OEB
D_SELB0
D_SELB1
GND
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VDDO
VDD
Zo = 50
R3
GND
QA0
VDDOA
QA1
GND
QA2
VDDOA
QA3
GND
QB0
VDDOB
QB1
GND
QB2
VDDOB
QB3
10u
0.1u
36
GND
QC0
VDDOC
QC1
GND
QC2
VDDOC
QC3
GND
QD0
VDDOD
QD1
GND
QD2
VDDOD
QD3
R6
SP = Spare, Not Install
ICS8761
36
Receiv er
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
C1
SP
R5
VDDO
Zo = 50
R4
Logic Input Pin Examples
(U1,5)
VDD
Set Logic
Input to '1'
RU1
1K
VDD
Set Logic
Input to '0'
(U1,44)
(U1,40)
36
C6
C5
C4
C3
0.1u
0.1u
0.1u
0.1u
Receiv er
VDD=3.3V
VDDO=3.3V
RU2
SP
To Logic
Input pins
RD1
SP
(U1,9)
VDD
To Logic
Input pins
RD2
1K
(U1,23)
(U1,19)
VDDO
(U1,27)
(U1,31)
(U1,50)
(U1,54)
(U1,58)
(U1,62)
(U1,46)
C7
C8
C9
C10
C11
C12
C13
C14
C15
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
FIGURE 3. ICS8761 CLOCK GENERATOR SCHEMATIC EXAMPLE
8761CY
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11
REV. C SEPTEMBER 7, 2004
ICS8761
Integrated
Circuit
Systems, Inc.
LOW VOLTAGE, LOW SKEW,
PCI / PCI-X CLOCK GENERATOR
RELIABILITY INFORMATION
TABLE 8. θJAVS. AIR FLOW TABLE
FOR
64 LEAD TSSOP
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
58.8°C/W
41.1°C/W
48.5°C/W
35.8°C/W
43.2°C/W
33.6°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8761 is: 6040
8761CY
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12
REV. C SEPTEMBER 7, 2004
ICS8761
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - Y SUFFIX
LOW VOLTAGE, LOW SKEW,
PCI / PCI-X CLOCK GENERATOR
FOR
64 LEAD TSSOP
TABLE 9. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
SYMBOL
BCD
MINIMUM
NOMINAL
MAXIMUM
64
N
A
--
--
1.60
A1
0.05
--
0.15
A2
1.35
1.40
1.45
b
0.17
--
0.27
c
0.09
--
0.20
D
12.00 BASIC
D1
10.00 BASIC
D2
7.50 Ref.
E
12.00 BASIC
E1
10.00 BASIC
E2
7.50 Ref.
0.50 BASIC
e
L
0.45
--
0.75
θ
0°
--
7°
ccc
--
--
0.08
Reference Document: JEDEC Publication 95, MS-026
8761CY
www.icst.com/products/hiperclocks.html
13
REV. C SEPTEMBER 7, 2004
ICS8761
Integrated
Circuit
Systems, Inc.
LOW VOLTAGE, LOW SKEW,
PCI / PCI-X CLOCK GENERATOR
TABLE 10. ORDERING INFORMATION
Part/Order Number
Marking
Package
Count
Temperature
ICS8761CY
ICS8761CY
64 Lead LQFP
160 per tray
0°C to 85°C
ICS8761CYT
ICS8761CY
64 Lead LQFP on Tape and Reel
500
0°C to 85°C
ICS8761CYLN
ICS8761CYLN
160 per tray
0°C to 85°C
ICS8761CYLNT
ICS8761CYLN
500
0°C to 85°C
ICS8761CYLF
ICS8761CYLF
160 per tray
0°C to 85°C
ICS8761CYLFT
ICS8761CYLF
64 Lead "Lead-Free/Annealed" LQFP
64 Lead "Lead-Free/Annealed" LQFP
on Tape and Reel
64 Lead "Lead-Free" LQFP
64 Lead "Lead-Free" LQFP
on Tape and Reel
500
0°C to 85°C
The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for
use in life support devices or critical medical instruments.
8761CY
www.icst.com/products/hiperclocks.html
14
REV. C SEPTEMBER 7, 2004
ICS8761
Integrated
Circuit
Systems, Inc.
LOW VOLTAGE, LOW SKEW,
PCI / PCI-X CLOCK GENERATOR
REVISION HISTORY SHEET
Rev
Table
Page
A
T1
T1
2
2
T4B, T4D
6, 8
A
1
B
T3D
4
T5A, T5B
7, 9
T1
2
T5A, T5B
7, 9
B
10
8/15/02
Pin Description Table, pin 43 should be labeled at a PULL-UP instead of a
PULL-DOWN.
LVCMOS DC Characteristics table -in the IIH and IIL rows, FBDIV_SEL0 was
deleted from the "pulldown" row and was added to the "pullup" row.
Features section, changed max. output frequency from 200MHz to 183.3MHz,
and max. REF_CLK input frequency from 100MHz to 91.6MHz.
Control Function Table - revised Reference Frequency Range column and
Frequency columns to reflect the output frequency change.
11/05/02
11/06/02
AC Characteristics tables - changed Output Frequency from 200MHz max. to
183.3MHz max.
Pin Description Table, revised cr ystal description.
AC Characteristics tables - changed Period Jitter measurement to
Period Jitter, RMS and added NOTE 8.
1/20/03
Added Cr ystal information.
10
10
1
T3D
4
Adjusted Ref. Frequency Range and Frequency columns.
T4A
5
Changed IDD max. from 150mA to 175mA, IDDA max. from 50mA to 55mA, and
IDDO max. from 330mA to 25mA.
T5A & T5B
6&8
11
2
5, 7
B
C
1
10
14
Changed fMAX from 183.3MHz max. to 166.67MHz max.
Changed RMS tjit(per) from 20ps max. to 17ps max.
Features Section - added Lead-Free bullet.
Added Cr ystal Section.
Ordering Information Table - added Lead-Free/Annealed Par t Number.
C
14
Ordering Information Table - added Lead-Free Par t Number.
8761CY
Date
Added Schematic Example in the Application Information Section.
Pin Description Table - revised MR description.
Power Supply Tables - changed VDD parameter to read "Core Supply Voltage"
from "Positive Supply Voltage".
Deleted Cr ystal Input Interface section.
Updated Schematic Example diagram.
Updated Features to reflect T5A 3.3V AC Characteristics (see below).
T1
T4A, T4C
C
Description of Change
Pin Description Table, revised Master Reset description.
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15
3/25/03
4/10/03
8/2/04
8/7/04
REV. C SEPTEMBER 7, 2004
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