Ordering number : ENA1992 LV7109E Bi-CMOS IC AC Switch Europe SCART Standard http://onsemi.com Overview The LV7109E is a rationalized IC of AC switch LV7108 complying with the Europe SCART standard. Features and functions • Video/Audio cannal-SW • 6dB-VideoAmp • 6/12MHz/27MHz-LowPassFilter • 9ch VideoDriver (AV1/AV2/Line/RGB/Component) • V-Sync. Detection • 3ch Stereo Audio Input • 2ch Stereo Audio Output Specifications Absolute Maximum Ratings at Ta = 25°C Parameter Symbol Conditions Ratings Unit Maximum supply voltage 1 VCC1 max 6.0 Maximum supply voltage 2 VCC2 max 13.0 V V Recommended supply voltage 1 VCC1 5.0 V 12.0 V Recommended supply voltage 2 VCC2 Operating supply range 1 VCC1 opg 4.5 to 5.3 V Operating supply range 2 VCC2 opg 11.1 to 12.5 V Allowable power dissipation Pd max Operating temperature Topr * With specified substrate -20 to +75 1070 mW °C Storage temperature Tstg -40 to +150 °C * With specified substrate : 76.1mm × 114.3mm × 1.6mm, glass epoxy. Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Semiconductor Components Industries, LLC, 2013 July, 2013 N1611 SY PC 20110207-S00003 No.A1992-1/24 LV7109E Electrical Characteristics at Ta = 25°C, VCCV = 5.0V, VCCA = 12V Parameter Symbol Input Output point point Ratings Test condition min typ Unit max Current dissipation 1 (5V) ICC1 Non-signal 69.7 82.0 94.3 mA Current dissipation 2 ICC2 Non-signal 11.1 13.0 15.0 mA ICC3 Non-signal 7.7 9.0 10.4 mA VDCC AV1, AV2-OUT (Sync tip) 0.5 0.7 0.9 V (ALL5V) Current dissipation 3 (12V) Video CANAL SW part Output voltage 1 Voltage gain VGC Frequency characteristics 1 VFC1 VIN = 1Vp-p, f = 100kHz, AV1, AV2-OUT 38 Frequency characteristics 2 VFC2 5.5 6.0 6.5 dB -1.0 0.0 +1.0 dB -1.5 0.0 +1.5 dB VIN = Video : 1Vp-p -1 0 +1 % VIN = Video : 1Vp-p -1.5 VIN = 1Vp-p, f = 10MHz/100kHz 17 12 (P17, P19: Through) VIN = 1Vp-p, f = 6MHz/100kHz 40 (P38, P40: 6MHz-LPF) DG Differential gain DGC 19 DP Differential phase DPC 38 Cross talk between channel CTC Picture S/N VSNC Maximum output level 1 VOMAXC1 14 40 Selected input = GND 0 +1.5 °C -60 -50 dB -70 -65 Non-selected input = 1Vp-p, f = 4.43MHz VIN = Video (50%White) 17 12 Output level (Trough output) whose 19 14 linearity exceeds 1% dB 2.8 3.0 Vp-p 2.6 2.7 Vp-p Composite (Sync-Tip) 0.8 1.0 1.2 V V VIN = Linearity (lamp) signal Output level at linearity 1% Maximum output level 2 VOMAXC2 38 12 Output level (ENC output) whose linearity 40 14 exceeds 1% VIN = Linearity (lamp) signal Output level at linearity 1% Video INPUT SW part Output voltage 1 VDCI1 17, 19, 21 35 Output voltage 2 VDCI2 17, 19, 21 35 Y (Sync-Tip) 0.8 1.0 1.2 Output voltage 3 VDCI3 3 33 Chroma (Center) 1.8 2.1 2.4 V Voltage gain 1 VGI1 17, 19, 21 33 VIN = 1Vp-p, f = 100kHz, load = 10kΩ -0.5 0.0 +0.5 dB 3 35 Frequency characteristics VFI 17, 19, 21 33 VIN = 1Vp-p, f = 10MHz/100kHz -1.0 0.0 +1.0 dB 3 35 DG Differential Gain DGSW 17, 19, 21 35 VIN = Video :1Vp-p -1 0 +1 % DP Differential Phase DPSW 17, 19, 21 35 VIN = Video :1Vp-p -1.5 0 +1.5 °C Cross talk between channel CTAD 17, 19, 21 33 Selected input = GND -60 -50 dB 3 35 Non-selected input = 1Vp-p, f = 4.43MHz -66 -60 Picture S/N VSNC 17, 19, 21 35 VIN = Video (50%White) Maximum output level VOMAXSW 17, 19, 21 35 Output level (ENC output) whose linearity dB 1.8 2.0 Vp-p RGB (Pedestal) 0.6 0.8 1.0 V 0.5 0.7 0.9 V 1.7 2.0 2.3 V exceeds 1% VIN = Linearity (lamp) signal Output level at linearity 1% Video Driver part Output voltage 1 Output voltage 2 Output voltage 3 VDCD1 VDCD2 VDCD3 Output voltage 4 VDCD4 Voltage gain 1 VGD1 64, 46 6 1, 44 8 3, 42 10 40 16 CVBS (Sync tip) 27 Y (Sync tip) C, Pr, Pb (Center) 3 10 46 23 42 25 40 27 Y (Sync tip) 0.8 1.0 1.2 V 64, 46 6, 23 For VIN = 1Vp-p and f = 100kHz Line 5.5 6.0 6.5 dB 1, 44 8, 27 output only: 2 drives, Other outputs: 1drive 3, 42 10, 25 40, 38 12, 14, 16 Continued on next page. No.A1992-2/24 LV7109E Continued from preceding page. Parameter Frequency characteristics 1 Symbol VFD1 Input Output point point 46, 44, 42 6, 8, 10 40, 38 23, 27, 25 Ratings Test condition min VIN = 1Vp-p, f = 6MHz/100kHz when 6MHzLPF is selected -1.5 typ Unit max 0.0 +1.5 dB -35 -25 dB 0.0 +1.5 dB -40 -30 dB 0.0 +1.5 dB -40 -30 dB 0.0 +1.5 dB -40 -30 dB 20 35 ns 14 25 ns 10 18 ns 10 18 ns dB 12, 14 16 Frequency characteristics 2 Frequency characteristics 3 Frequency characteristics 4 Frequency characteristics 5 Frequency characteristics 6 Frequency characteristics 7 VFD2 VFD3 VFD4 VFD5 VFD6 VFD7 46 6 f = 27MHz/100kHz when 6MHzLPF is 44 8 selected 42 10 46 23 f = 12MHz/100kHz when 12MHzLPF is 44 27 selected 42 25 46 23 f = 54MHz/100kHz when 12MHzLPF is 44 27 selected 42 25 46 23 f = 13.5MHz/100kHz when 13.5MHzLPF 42 25 is selected 46 23 f = 74MHz/100kHz when 13.5MHzLPF is 42 25 selected 44 27 f = 25MHz/100kHz when 27MHzLPF is -1.5 -1.5 -1.5 selected Frequency characteristics 8 VFD8 44 27 f = 74MHz/100kHz when 27MHzLPF is selected Group delay 1 VGDD1 46, 44, 42 6, 8, 10 40, 38 23, 27, 25 f = 6MHz/100kHz when 6MHzLPF is selected 12, 14 16 Group delay 2 Group delay 3 Group delay 4 VGDD2 VGDD3 VGDD4 46 23 f = 12MHz/100kHz when 12MHzLPF is 44 27 selected 42 25 46 23 f = 27MHz/100kHz when 13.5MHzLPF is 42 25 selected 44 27 f = 27MHz/100kHz when 27MHzLPF is selected Mute attenuation VMUD ALL VIN = 1Vp-p, f=4.43MHz -60 -50 DG Differential gain DG1 ALL VIN = Video : 1Vp-p -1 0 +1 % DP Differential phase DP1 ALL VIN = Video : 1Vp-p -1.5 0 +1.5 °C Cross talk between channel CTD ALL VIN = 1Vp-p, f=4.43MHz Driver output terminated with 75Ω -60 -50 dB Picture S/N VSND ALL VIN = Video (50%White) -70 -65 Maximum output level 1 VOMAXD1 Maximum output level 2 VOMAXD2 64, 46 6 Output level (RGB) whose linearity 1, 44 8 exceeds 1% 3, 42 10 VIN = Linearity (lamp) signal Output level at linearity 1% 16 Output level (brightness, CVBS) whose 27 linearity exceeds 1% 40 dB 2.5 2.7 Vp-p 2.6 2.8 Vp-p 2.0 2.5 Vp-p VIN = Linearity (lamp) signal Output level at linearity 1% Maximum output level 3 VOMAXD3 46 23 Output level (color difference) whose 42 25 linearity exceeds 1% VIN = sin 10kHz Output level at linearity 1% Sync-SEP part V.SYNC output VVSH 17, 19, 21 34 4.3 4.7 5.0 V VVSL 17, 19, 21 34 0.0 0.3 0.6 V TDVS 17, 19, 21 34 Note 2) 7 15 25 μs TWVS 17, 19, 21 34 VIN = PAL Video : 1Vp-p Note 2) 125 155 185 μs High voltage V.SYNC output Low voltage V.SYNC output delay time V.SYNC output pulse width Note 2) When pin 10 is open Continued on next page. No.A1992-3/24 LV7109E Continued from preceding page. Parameter Symbol Input Output point point Ratings Test condition min typ Unit max Audio canal switches part Maximum output level VOMAXC AV1, AV2-OUT (L, R) 2.2 2.5 Vrms -1.5 0.0 +1.5 dB 0.003 0.01 % -100 -80 dBV -90 -75 dB Output level at f = 1kHz, THD = 1% BW = 400 to 30kHz Channel balance CVSW Total harmonic distortion THDAC Output noise voltage VNAC Mute attenuation VMUAC Input impedance ZIN Cross talk between channel CTSW VIN = 2Vrms, f = 1kHz Lch Gain-Rch Gain R-Ch. R-Ch. 49, 50, 51 58, 61 Rg = 0Ω, BW = JIS-A L-Ch. L-Ch. VIN = 2Vrms, f = 1kHz, BW = JIS-A 54, 55, 56 59, 62 20log (VOUT/VIN) 80 VIN = 2Vrms, f = 1kHz and selctors Output off set voltage VIN = 2Vrms, f = 1kHz, BW = 400 to 30kHz 100 120 kΩ -110 -80 dB 0 +20 mV Rg = 0Ω, BW = JIS-A Off set voltage at the time of VOFSET -20 changeover SW. External control part I2C-BUS High level input VIH voltage I2C-BUS Low level input VIL voltage FSS output H voltage 36 2.5 VCC5 V GND 0.8 V 37 36 37 VHFSS 7 Serial control select FSS OUT H, 10.6 11.1 11.6 V 5.5 6.3 7.0 V 0.0 0.1 0.5 V 1.0 ms load = 10kΩ external output resistor 470 recommended FSS output M voltage VMFSS 7 Serial control select FSS OUT M, load = 10kΩ external output resistor 470 recommended FSS output L voltage VLFSS 7 Serial control select FSS OUT, load = 10kΩ FSS risinge time TFSSLH 7 FB output H voltage VHFB 18 Serial control select FB OUT H, 3.0 4.0 5.0 V 0.0 0.2 0.4 V 0.0 0.5 V 1.0 3.0 V load = 150Ω FB output L voltage VLFB 18 Serial control select FB OUT L, load = 150Ω FB external control L range VLFBIN 20 18 Pin 20 input voltage range at which the pin 18 output becomes “L”. FB external control H range VHFBIN 20 18 Pin 20 input voltage range at which the pin 18 output becomes “H”. External control output H VEXTH 26 2kΩ load for data 1 4.0 4.5 5.0 V VEXTL 26 2kΩ load for data 0 0.0 0.3 1.0 V 2.3 2.5 2.7 V 8.7 9.0 9.3 V 4.3 4.5 4.7 V voltage External control output L voltage Internal reference regulator REG2.5V VREG25 2 31 REG9.0V VREG90 52 57 VRE4.5 VREG45 48 No.A1992-4/24 LV7109E Package Dimensions unit : mm (typ) 3159A 33 32 64 17 14.0 49 1 17.2 48 0.8 17.2 14.0 16 0.35 0.8 0.15 0.1 3.0max (2.7) (1.0) SANYO : QIP64E(14X14) AudioPower Supply Block Diagram A-DAC_R_IN 49 VCC12V_A 29 REG9V_AR 52 R-ch Input Bias 100kΩ 100kΩ R-ch Circuit Power Supply 4.5V-Ref. Buffer Switch Buf. Mute AV2_R_OUT 58 Switch Buf. Mute AV1_R_OUT 61 Switch Buf. Mute AV2_L_OUT 59 Switch Buf. Mute AV1_L_OUT 62 Buf. R-ch Output Ref. VCC5V_ALL 28 AV1_R_IN 51 100kΩ 9V-Reg. Buf. REF4.5V 48 AV2_R_IN 50 Power Mute Buf. REG9V_AL 57 L-ch Output Ref. 9V-Reg. L-ch Circuit Power Supply Buffer 100kΩ Buf. L-ch Input Bias 100kΩ 100kΩ 54 A-DAC_L_IN 55 AV2_L_IN 56 AV1_L_IN No.A1992-5/24 LV7109E Video Power Supply Block Diagram The thick line indicates the circuit operative in the power save mode. Applied power to VCC5_All, VCC5V_SW and VCC_LOGIC only in the power save mode. VCC5V_VD VCC5V_RGB 9 24 Input Bias/Clamp Low Pass Filter 6dB. Switch DR. RGB/ Component GND_VD 22 GND_RGB 11 VCC5V_VL VCC5V_VC 4 13 Input Bias/Clamp Low Pass Filter 6dB. Switch DR. Line Output Input Bias/Clamp Low Pass Filter 6dB. Switch DR. Canal AV1/AV2 GND_VC GND_VL 15 5 VCC5V_ALL 28 Input Bias/Clamp 0dB Switch ADC Output VCC5V_SW 43 V-Sync. Detector 34 V-Sync.Output GND_SW 41 VCC12V_A 29 FB Control Canal FB FB Output FSS Control Canal FSS FSS Output 7 18 VCC5V_LOGIC 30 36 Serial 37 EXT-CTL Serial Control 26 GND_LOGIC 39 No.A1992-6/24 1kΩ 11 0.1μF 15 0.1μF 7 75Ω 8 680Ω 7 11 75Ω 8 6dB 0.1μF FSS OUT 6dB 6 9 15 75Ω 10 6dB 12M/13.5M 5 11 19 75Ω 12 6dB VCC5V_VC 4 6M 13 19 Mute Mute AV1_V a a: 0V b: 4V GND_VL 17 Clamp 75Ω 18 Drv 1000μF 19 20 21 22 23 24 25 26 PY_OUT(Component) PR_OUT(Component) 75Ω 75Ω 75Ω 16 16 AV2_V/Y_IN 20 AV2_FB_IN AV1_V_IN 20 AV1_FB_OUT 0.1μF 75Ω 0.1μF 0.1μF AV3_V_IN PB_OUT(Component) GND_VD + 330μF VCC5V_VD + 330μF EXT_CTL1 + 75Ω VCC5V_ALL 28 27 VCC12V_A 29 1000μF VCC5V_LOGIC 0.01μF 30 31 REG2.5V_ALL 32 Sync._Sep._Filter 33pF Clamp 75Ω 16 + 6dB 6dB Clamp SV13a SV11a EXTCTL1 6dB REG SV12a cd ae bcdf ae bcdf Serial V_OUT(Line) 15 AV2_V/Y 75Ω 14 6dB 3 f bcde a SV14 LPF f Mute b c d e AV3_V b 2 REG Mute 6dB 1 f bcde a Serial Mute Clamp 6M SV16 Clamp/ Bias f c Mute b d e a 64 Mute 0.1μF 12M/13.5M a c bed SV1 Mute 7 Mute a b c def SV2 Mute SV11b a SV12b AV1_V SV13b AV2_V/Y GND_AL SA1L SV6 SV4 Mute Mute Clamp Buf + 62 10μF AV2_B AV2_G AV2_R/C ENC_R ENC_G ENC_B SV3 SV7 V-Sync. Sep. V-Sync. Sep. 33 34 35 AV3_V AV2_B_IN 3 SA1R SA2L ENC_C ENC_Y+C ENC_Y 63 Buf + 61 1kΩ 10μF AV1_L_OUT 1 10μF Buf 6M GND_AR 1kΩ 60 + 59 12M/27M AV1_R_OUT 3 1kΩ 10μF AV2_L_OUT c SA2R abde Buf SV5 + 36 Serial Control 37 c + 58 SA2L SA1L 6M Bias 38 abde 1 a b,c b,d,e Mute a b,c d,e Mute + 39 Mute Mute 10μF REG Bias Bias Bias SA2R SA1R 6M Clamp 40 c d + 57 56 55 54 a b,c b,d,e Mute a b,c d,e Mute 41 0.1μF b REG9V_AL 1μF 1μF 1μF 53 REG Bias Bias Bias Clamp/ Bias 42 0.1μF Mute AV2_R_OUT 6 AV1_L_IN 51 50 49 + 52 10μF GND_REG AV2_L_IN 6 1μF 1μF REG9V_AR A-DAC_L_IN 2 AV1_R_IN 2 1μF ENC_B_IN Clamp ENC_G_IN AV2_R_IN GND_REF 43 ENC_R_IN Clamp/ Bias 44 VCC5V_SW 45 GND_V_SW REF 46 0.1μF ENC_Y_IN A-DAC_R_IN 47 0.1μF GND_LOGIC 48 22μF 0.1μF 180kΩ + REF4.5V ENC_C_IN a b c d Mute SCL_IN cd Mute SDA_IN b a Mute 0dB Mute Y/V_ADC ENC_Y ENC_PY ENC_PR ENC_PB LPF V-Sync._OUT LPF 0dB LPF C_ADC LPF 0.1μF Audio_Mute_Filter 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 AV1_V_IN AV1_FB_OUT AV2_V/Y_IN AV2_FB_IN AV3_V_IN GND_VD PB_OUT (Component) VCC5V_VD PR_OUT (Component) EXT_CTL1 PY_OUT (Component) VCC5V_ALL VCC12V_A VCC5V_LOGIC REG2.5V_ALL Sync_Sep._Filter AV2_G_IN REG2.5V AV2_R/C_IN GND_VC VCC5V_VC AV1_B_OUT AV1_FSS_OUT AV1_G_OUT VCC5V_RGB AV1_R/C_OUT GND_RGB AV2_V_OUT VCC5V_VL AV1_V/Y_OUT GND_VL V_OUT (Line) 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 A-DAC_R_IN AV2_R_IN AV1_R_IN REG9V_AR GND_REG A-DAC_L_IN AV2_L_IN AV1_L_IN REG9V_AL AV2_R_OUT AV2_L_OUT GND_AR AV1_R_OUT AV1_L_OUT GND_AL AV2_B_IN C_ADC V-Sync._OUT Y/V_ADC SDA_IN SCL_IN ENC_C_IN GND_LOGIC ENC_Y_IN GND_V_SW ENC_R_IN VCC5V_SW ENC_G_IN GND_REF ENC_B_IN Audio_Mute_Filter REF4.5V Marks of switches are assigned alphabetically from LSB. ex.) assign 3bit register a=000, b=001, c=010, d=011, e=100, f=101 Pin List Bold parts are for Always Power ON X SCART PIN X LV7109 PIN (always Power ON) X LV7109 PIN (for Power Save) LV7109E Block Diagram a AV1_V\Y_OUT VCC5V_VL VCC5V_VL AV2_V_OUT VCC5V_RGB AV1_R/C_OUT AV1_G_OUT AV1_FSS_OUT AV1_B_OUT GND_VC AV2_R/C_IN REG2.5V AV2_G_IN No.A1992-7/24 75Ω 10μF + T65 T60A T60 0.22μF T61A T61 0.22μF T74A T74 4.7μF + 10kΩ 0.1μF T5 T71A T71 4.7μF + 10kΩ T72A T72 4.7μF + 10kΩ T73A T73 4.7μF + 10kΩ 100kΩ 1kΩ 100kΩ 1kΩ 100kΩ 1kΩ T64A T64 0.22μF 75Ω VCC5V_VC GND_VC AV2_R/C_IN REG 2.5V AV2_G_IN 75Ω AV1_B_OUT 0.1μF 150Ω T27 7 AV1_FSS_OUT 6 10Ω T17 8 AV1_G_OUT 0.01μF T12 150Ω 9 VCC5V_RGB 5 T9 150Ω 10 AV1_R/C_OUT 4 11 GND_RGB 3 T28 150Ω 12 13 AV2_V_OUT 0.1μF T1 VCC5V_VL 2 T26 150Ω 14 AV1_V_OUT T100 33 VCC_ALL5V 28 VCC12V_A 29 VCC_LOGIC 30 REG2.5V_ALL 31 32 SYNC_SEP_LPF 15 T23 1000μF 150Ω + 16 AV1_V_IN 17 AV1_FB_OUT 18 AV2_V/Y_IN 19 AV2_FB_IN 20 AV3_V_IN 21 GND_VD 22 B-Y_OUT(component) 23 VCC5V_VD 24 R-Y_OUT(component) 25 EXT_CTL1 26 V_OUT(Line) T3 LV7109E T81 10kΩ Y_OUT(component) 27 GND_VL 1 AV2_B_IN 64 63 GND_AL 62 AV1_L_OUT 61 AV1_R_OUT 60 GND_AR 59 AV2_L_OUT 58 AV2_R_OUT 57 REG9V_AL 56 AV1_L_IN 55 AV2_L_IN 54 A-DAC_L_IN 53 GND_REG 52 REG9V_AR Audio_Mute_Filte 10μF + ENC_B/B-Y_IN 51 AV1_R_IN GND_REF T57 ENC_G/Y_IN T52A T52 0.22μF VCC5V_VSW 100kΩ 50 AV2_R_IN ENC_R/R-Y_IN 1kΩ T53A T53 0.22μF GND_VSW 100kΩ 1kΩ REF4.5V 49 A-DAC_R_IN 34 T82 35 T83 36 37 T91 10kΩ 38 10kΩ 39 3mA 40 T93 0.1μF ENC_Y_IN 41 180kΩ 75Ω GND_LOGIC 42 0.1μF ENC_C_IN 43 T95 75Ω SCL_IN 44 0.1μF SDA_IN 45 T97 75Ω Y/V_ADC 46 0.1μF V-Sync_OUT 47 T99 75Ω C_ADC 100kΩ T56 T56A 0.22μF T16 0.1μF SERIAL CLOCK 1kΩ 48 + 75Ω 0.1μF SERIAL DATA T49 22μF 10kΩ T33 T34 T31 T32 T37 T11 0.01μF 0.1μF 0.1μF 0.1μF 75Ω 150Ω 75Ω 75Ω 75Ω 330μF 150Ω + 330μF 150Ω + 2kΩ 1000μF 150Ω + + T13 T7 0.01μF 47μF T14 T2 T10 12V + 0.01μF + 47μF 5V + LV7109E Test Circuit No.A1992-8/24 LV7109E LV7109E Serial Control Table ADDRESS SV1 Group 1 0000 0001 VIDEO CANAL-SW VIDEO * indicates initial. 8 7 6 5 4 3 2 1 Symbol Input 0 0 0 a P19 AV2_V/Y_IN 0 0 1 b - ENC_Y+C_MIX 0 1 0 C P40 ENC_Y 0 1 1 d - MUTE 1 0 0 e - MUTE 1 0 1 f - MUTE 1 1 X - - PROHIBIT 0 0 0 a P17 AV1_V_IN 0 0 1 b - MUTE 0 1 0 c - ENC_Y+C_MIX 0 1 1 d 1 0 0 e MUTE 1 0 1 and after - PROHIBIT Output * P10: AV1_R/C_OUT * P12: AV2_V_OUT SV2 MUTE 0 0 a P17 AV1_V_IN 0 1 b P19 AV2_V/Y_IN 1 0 c - N/A 1 1 d - N/A a P21 AV3_V_IN 0 1 b - N/A 1 0 C 1 1 d - SV5/6 MIX 0 0 0 a - MUTE 0 0 1 b - MUTE MUTE 0 1 0 c P19 AV2_V/Y_IN AV2_R/C_IN 0 1 1 d - MUTE MUTE 1 0 0 e - MUTE MUTE and 1 0 1 after - - PROHIBIT PROHIBIT 0 0 a SV5 Y 0 1 b SV4 Composit Video 1 0 c - MUTE 1 1 d - MUTE * SV3 ADDRESS SV4 8 7 6 5 4 3 2 1 Symbol 0 0 Input Output SV4 Group 2 0000 0010 SV7 VIDEO INPUT-SW * MUTE Y+C MIX SV7 P33: C_ADC * P35: Y/V_ADC SV3 ADDRESS Remarks According to SV3 control SV2 SV16 Note 1) Remarks 0 - - THROUGH 1 - - CLAMP input * * 8 7 6 5 4 3 2 1 Symbol 12/27MHz LPF SW Input Output Remarks 0 - x = 12MHz 1 - x = 27MHz 0 - According to G3D3-5 control 1 - Switch of SV11b-13b set to “f” * RGB output SV11a SV12a SV13a 0 0 0 a - MUTE P40 ENC_Y_IN - MUTE 0 0 1 b 0 1 0 c P42 ENC_R_IN P44 ENC_G_IN P46 ENC_B_IN P42 ENC_R_IN P44 ENC_G_IN P46 ENC_B_IN 0 1 1 d P42 ENC_R_IN P44 ENC_G_IN P46 ENC_B_IN 1 0 0 e - MUTE - MUTE - MUTE 1 0 1 f P42 ENC_R_IN P44 ENC_G_IN P46 ENC_B_IN f: AV2_RGB (EXTERNAL) * a: ENC_Y * b: Component (× MLPF) P25: PR_OUT P27: PY_OUT P23: PB_OUT c: Component (× MLPF) d: Component (× MLPF) e: mute f: Component (× MLPF) Group 3 0000 0011 1 1 X - - PROHIBIT - PROHIBIT - PROHIBIT 0 0 0 a P42 ENC_R_IN P44 ENC_G_IN P46 ENC_B_IN a: ENC_RGB (6MLPF) VIDEO OTHER-1 0 0 1 b - MUTE - MUTE - MUTE b: mute 0 1 0 c P38 ENC_C_IN - MUTE - MUTE 0 1 1 d - MUTE - MUTE - MUTE 1 0 0 e - MUTE - MUTE - MUTE 1 0 1 f P3 AV2_R/C_IN P1 AV2_G_IN P64 AV2_B_IN - PROHIBIT - PROHIBIT SV11b SV12b SV13b * effective at G3D2 = “0” - - PROHIBIT 0 1 1 X a - ENC_Y+C 1 b - MUTE 0 a - - - - 1 - - SV14 P10: AV1_R/C_OUT P8: AV1_G_OUT P6: AV1_B_OUT * c: ENC_C d: mute e: mute f: AV2_RGB (EXTERNAL) P16: V_OUT (Line) * N/A SV16 Note 1) b - - 0 - - THROUGH 1 - - BIAS input * * Note 1) G2D8/G3D8 = “11” is prohibited. Follow the AV2 (16) FB_IN (Pin32) control in case of THROUGH. AV2_16pin SV16 H a : Clamp input (RGB) L b : Bias input (Y+C) No.A1992-9/24 LV7109E * indicates initial. ADDRESS 8 7 6 5 4 3 2 1 Symbol Input 0 a - N/A - N/A 1 b - N/A - N/A 0 a - N/A - N/A 1 b - N/A - N/A 0 0 a - 0V 0 1 b - 5V 1 0 c P20 THROUGH 1 1 d P20 THROUGH Output Remarks * N/A * N/A Group 4 0000 0100 VIDEO & AUDIO OTHER-1 FB AV1 (16) Note 2) P18: AV1_FB_OUT FSS AV1 (8) 0 0 - - LOW (0.5V) 0 1 - - MID (6.0V) * * P7: AV1_FSS_OUT 1 0 - - HIGH (11.0V) 1 1 - - HIGH (11.0V) 0 - - - 1 - - - 0 - - THROUGH 1 - - MUTE * N/A A-MUTE P58,59,61,62 output MUTE * Note 2) Same polarity as the AV2 (16) FB_IN (Pin20) control in case of THROUGH. ADDRESS 8 7 6 5 4 3 2 1 Symbol Input 0 0 0 a P55 AV2_L_IN P50 AV2_R_IN 0 0 1 b P54 A-DAC_L_IN P49 A-DAC_R_IN 0 1 0 c P54 A-DAC_L_IN P49 A-DAC_R_IN 0 1 1 d - MUTE - MUTE Output * P62: AV1_L_OUT P61: AV1_R_OUT SA1L/R 1 0 0 e - MUTE - MUTE and after 1 0 1 f - PROHIBIT - PROHIBIT 0 0 0 a P56 AV1_L_IN P51 AV1_R_IN 0 0 1 b - MUTE - MUTE 0 1 0 c P54 A-DAC_L_IN P49 A-DAC_R_IN 0 1 1 d - MUTE - MUTE 1 0 0 e - MUTE - MUTE 1 0 1 and after - - PROHIBIT - PROHIBIT 0 0 a - N/A - N/A 0 1 b - N/A - N/A 1 0 c - N/A - N/A 1 1 d - N/A - N/A Group 5 0000 0101 AUDIO CANAL-SW Remarks * P59: AV2_L_OUT P58: AV2_R_OUT SA2L/R N/A ADDRESS 8 7 6 5 4 3 2 1 Symbol * Input 0 0 0 a - N/A - N/A 0 0 1 b - N/A - N/A 0 1 0 c - N/A - N/A 0 1 1 d - N/A - N/A 1 0 0 e - N/A - N/A 1 0 1 - - PROHIBIT - PROHIBIT 0 a - N/A 1 b - N/A 0 0 a - N/A 0 1 b - N/A 1 0 c - N/A Output Remarks * N/A and after Group 6 0000 0110 N/A * N/A * N/A - - PROHIBIT 0 0 1 1 a - N/A 0 1 b - N/A 1 0 c - N/A 1 1 - - PROHIBIT * N/A ADDRESS 8 7 6 5 4 3 2 1 Symbol Input 0 0 0 0 0 0 - - N/A 0 0 1 1 0 0 - - N/A 1 1 1 1 1 1 - - N/A Other than above - - PROHIBIT Output Remarks N/A Group 7 0000 0111 0 - - L 1 - - H - P42 ENC_R_IN * General purpose OUT1 * P26: EXT_CTL1 EXT-CTL1 - Changeover of VIDEO input 0 BIAS/CLAMP 1 - - - - - - ENC_B_IN Input changeover - BIAS input P44 CLAMP input ENC_G_IN P46 BIAS input Component - CLAMP input CLAMP input CLAMP input RGB * No.A1992-10/24 LV7109E * indicates initial. ADDRESS 8 7 6 5 4 3 2 1 Symbol Input 0 0 0 0 0 0 - - N/A 0 0 1 1 0 0 - - N/A 1 1 1 1 1 1 - - N/A Other than above - - PROHIBIT 0 - - N/A 1 - - N/A 0 - - N/A 1 - - N/A Output Remarks N/A Group 8 0000 1000 N/A * * N/A * N/A Cautions for Use 1. Drive capacity of video driver Line outputs can drive two systems through capacitive coupling. Component outputs can drive one systems through capacitive coupling. Scart output can drive one system only through DC coupling. 2. Audio Mute This IC incorporates a mute transistor to reduce the POP noise of audio output when power is turned ON/OFF. Mute control can be made by serial control. 3. Resistor to limit the Audio input When the large signal is input in the input pin with power OFF, cross-talke between input and output occurs through the protective diode and parasitic elements. Because of the structure of LSI, such cross-talke is difficult to avoid. If cross-talk at a time of power OFF presents a problem, the cross-talk amount can be reduced by inserting the limiting resistor in the input. In this case, the input signal level changes depending on the resistance value. Determine the constant while taking both the cross-talk amount and input level into account. 4. Pin treatment when external control is not to be used When external control pins (Pins 26) are not used, pull-down to GND is recommended. 5. Audio 9V_REG pin external capacitance Use the Audio 9V_REG pins (pins 52 and 57) external capacitance of 10μF or more and with the equivalent series resistance component of 7Ω or less. 6. Power application and disconnection sequences The recommended power application sequence to this IC is VCC_ALL5V (Pin28) → VCC5V (Pins 5, 9, 13, 24, 30 and 43), VCC12V (Pin29). (No particular order is established between VCC5V and VCC12V.) It is recommended to reverse the above sequence when power supply is turned OFF. No.A1992-11/24 LV7109E Serial Control Specification 1. Slave address LSB MSB 1 0 0 1 0 1 0 0 Slave receiver One-way communication (this IC is dedicated to receive) 2. DATA TRANSFER MANUAL : [1] is High level. [0] is Low level. I2C-BUS control system is adopted in SW LSI. SW LSI is controlled by SCL (Serial Clock) and SDA (Serial Data) At first, please set up the START condition*1 by these two terminals (SCL and SDA). And next, please input the 8bits data, which should be synchronized with SCL into SDA terminal. Still more, please give priority to high rank bit at data transfer order (MSB→LSB). The 9th bit is called as ACK (Acknowledge), SW LSI sends [0] to the SDA terminal during SCL [1] period. So, please open the port of microprocessor during this period. LV7107M adopt auto-increment, so you input only first group-address and you can transfer data in order. As thus the Data transfer Stop condition*2 is finished. *1 SDA rise up during SCI is [1] *2 SDA fall down during SCL is [1] 3. TRANSFER DATA FORMAT The transfer data is composed by START condition, Slave address, Group address*4, data, and STOP condition. After setting up the START condition, please transfer the Slave Address (regulated as “1001000” in SW LSI). Group and next control data (Please see the Fig.1) Slave Address is composed by 7bits, and this bit 8th bit*5 should be set as [0]. The both of Group address and control data are composed by 8bits, and the one control action is defined with combination of these two data. And if you want to control 2 or more groups at the same mode, you can realize it by sending some control data together. The data makes meaning with all bits, so you cannot stop the sending until all data transfer is over. But LV7107M adopt auto-increment, for example you can stop to transfer STOP condition after group 2 data. If you want to stop transfer action, please transfer the STOP condition without fail. *4 There are 8 control groups. *5 This 8th bit called as R/W bit, and this bit shows the data transmission direction. [0] means send mode (accept mode with SW LSI) and [1] means accept mode (send mode with SW LSI) fundamentally. But SW LSI is not equipped with such a data out function, please keep this bit as [0]. Fig. 1 DATA STRUCTURE START condition Start condition Slave address R/W ACK Group address Acknowledge ACK Control data ACK ..... STOP condition Stop condition No.A1992-12/24 LV7109E 4. INITIALIZE AND OTHERS SW LSI is initialized as the following mode for circuit protection. Please see “SERIAL CONTROL TABLE”. Characteristics of the SDA and SCL 1/0 stages for SW LSI Parameter Symbol Min Max Unit LOW level input voltage VIL 0 0.8 V HIGH level input voltage VIH 3.0 5.0 V LOW level output current IOL 3.0 mA SCL clock frequency fSCL 400 kHz Set-up time for a repeated START condition tSU : STA Hold time START condition. After this period, the first clock pulse is generated. LOW period of the SCL clock Rise time of both SDA and SDL signals tR 0.6 μs tHD : STA 0.6 μs tLOW 1.3 0 μs 0.3 μs μs HIGH period of the SCL clock tHIGH Fall time of both SDA and SDL signals tF 0.6 0 0.3 μs Data hold time: tHD : DAT 0 0.9 μs Data set-up time tSU : DAT 100 ns Set-up time for STOP condition tSU : STO 0.6 μs BUS fredd time between a STOP and START condition tBUF 1.3 μs Fig.2 Definition of timing. tHIGH tR tF SCL 37pin tSU:STA tHD:STA tLOW tHD:DAT tSU:DAT tSU:STO tBUF SDA 36pin No.A1992-13/24 LV7109E Pin Function Pin No. Pin name P1 AV2_G_IN DC voltage Signal wave form Input/Output form Note 1.6Vdc +Green 1kΩ 4kΩ 0.7Vp-p 4kΩ 300Ω 300Ω 1.6Vdc 1 P2 REG2.5V 2.5Vdc DC 10pF 50Ω 50Ω 300Ω 2 6.8kΩ 22.8kΩ 13kΩ 18.5kΩ 18.5kΩ 30kΩ P3 AV2_R/C_IN 910Ω 23kΩ 1.6Vdc +Red 1kΩ 0.7Vp-p 4kΩ 1.6Vdc 4kΩ 2.1Vdc +Chroma 20kΩ 300Ω 300Ω 0.7Vp-p 2.1Vdc 3 P4 GND_VC P5 VCC5V_VC P6 AV1_B_OUT 0.5V +Blue 2kΩ 100Ω 10.7kΩ 1.25pF 200Ω 1.4Vp-p 3.3pF 0.5Vdc 6 10kΩ 1.25pF Continued on next page. No.A1992-14/24 LV7109E Continued from preceding page. Pin No. Pin name P7 AV1_FSS_OUT DC voltage Signal wave form Low : 0.5V Input/Output form Note DC Mid : 6.0V High : 11.1V 7 100kΩ P8 AV1_G_OUT 0.5Vdc +Green 2kΩ 100Ω 10.7kΩ 1.25pF 200Ω 1.4Vp-p 3.3pF 0.5Vdc 8 10kΩ 1.25pF P9 VCC_RGB P10 AV1_R/C_OUT 0.5Vdc +Red 1.4Vp-p 2kΩ 100Ω 0.5Vdc 3.3pF 1.7Vdc +Chroma 10.7kΩ 1.25pF 200Ω 10 10kΩ 1.4Vp-p 1.25pF 1.7Vdc P11 GND_RGB P12 AV2_V_OUT 0.5Vdc +Video 2kΩ 100Ω 10.7kΩ 1.25pF 200Ω 2.0Vp-p 3.3pF 0.5Vdc P13 12 10kΩ 1.25pF VCC5V_VL Continued on next page. No.A1992-15/24 LV7109E Continued from preceding page. Pin No. Pin name P14 AV1_V/Y_OUT DC voltage Signal wave form Input/Output form Note 0.5Vdc +Video 2.0Vp-p 2kΩ 100Ω 10.7kΩ 1.25pF 200Ω 0.5Vdc 14 3.3pF 0.5Vdc +Y 10kΩ 1.25pF 2.0Vp-p 0.5Vdc P15 P16 GND_VL V_OUT 0.7Vdc (Line_OUT) +CVBS 2kΩ 100Ω 10.4kΩ 3pF 100Ω 2.0Vp-p 16 3pF 10kΩ 0.7Vdc P17 AV1_V_IN 3pF 100kΩ 1.6Vdc +CVBS 1kΩ 4kΩ 1.0Vp-p 4kΩ 300Ω 300Ω 1.6Vdc 17 P18 AV1_FB_OUT Low : 0V High : 4.0V 10Ω Through : 0/4.0V 4.0Vp-p 1kΩ 18 1kΩ 100kΩ 0Vdc 1kΩ 1kΩ Continued on next page. No.A1992-16/24 LV7109E Continued from preceding page. Pin No. Pin name P19 AV2_V/Y_IN DC voltage Signal wave form Input/Output form Note 1.6Vdc +CVBS 1kΩ 1.0Vp-p 4kΩ 1.6Vdc 4kΩ 1.6Vdc 300Ω 300Ω +Y 1.0Vp-p 1.6Vdc P20 AV1_FB_IN 19 Low : 0V High : 2V 2Vdc 1kΩ 20 0Vdc P21 AV3_V_IN 1.6Vdc +CVBS 1kΩ 4kΩ 1.0Vp-p 4kΩ 300Ω 300Ω 1.6Vdc 21 P22 P23 GND_VD PB_OUT 1.7V (Component) +Pb 2kΩ 1.4Vp-p 100Ω 1.7Vdc 3.3pF 10.7kΩ 1.25pF 200Ω 10kΩ 1.25pF P24 23 100kΩ VCC5V_VD Continued on next page. No.A1992-17/24 LV7109E Continued from preceding page. Pin No. Pin name P25 PR_OUT 1.7V DC voltage (Component) +Pr Signal wave form Input/Output form Note 2kΩ 1.4Vp-p 100Ω 1.7Vdc 3.3pF 10.7kΩ 1.25pF 200Ω 25 10kΩ 100kΩ 1.25pF P26 EXT-CTL1 Low : 0V (OUT) High : 5V 26 P27 PY_OUT (Component) 0.7Vdc +Py 5kΩ 2.0Vp-p 27 0.7Vdc P28 VCC5V_ALL P29 VCC12V_A P30 VCC5V_LOGIC P31 REG2.5V_ALL 2.5Vdc DC 10pF 50Ω 300Ω 50Ω 31 6.8kΩ 22.8kΩ 13kΩ 30kΩ P32 SYNC_SEP _FILTER 18.5kΩ 18.5kΩ 910Ω 23kΩ 2.2Vdc +Y 32 500Ω 1.0Vp-p 40kΩ 500Ω 2.2Vdc 8pF Continued on next page. No.A1992-18/24 LV7109E Continued from preceding page. Pin No. Pin name P33 ADC_C_OUT DC voltage Signal wave form Input/Output form Note 2.1Vdc +Chroma 500Ω 0.7Vp-p 33 2.1Vdc P34 V_SYNC_OUT Low : 0.3V High : 4.7V 300Ω 4.7Vdc 34 300Ω 0.3Vdc P35 ADC_V/Y_OUT 1.0Vdc +CVBS 500Ω 1.0Vp-p 1.0Vdc 35 1.0Vdc +Y 1.0Vp-p 1.0Vdc P36 SDA_IN 2 I C DATA ACK_OUT 30kΩ 500Ω 36 P37 SCL_IN I2C CLOCK 30kΩ 500Ω 37 Continued on next page. No.A1992-19/24 LV7109E Continued from preceding page. Pin No. Pin name P38 ENC_C_IN DC voltage Signal wave form Input/Output form Note 2.1Vdc +Chroma 4kΩ 0.7Vp-p 4kΩ 2.1dc 20.3kΩ 300Ω 38 P39 GNG_LOGIC P40 ENC_Y_IN 1.6Vdc +Y 1kΩ 4kΩ 1.0Vp-p 4kΩ 300Ω 300Ω 1.6Vdc 40 P41 GND_VSW P42 ENC_R/PR_IN 1.6Vdc +Red 1kΩ 0.7Vp-p 4kΩ 1.6Vdc 4kΩ 2.1Vdc +Pr 20kΩ 300Ω 300Ω 0.7Vp-p 2.1Vdc 42 P43 VCC5V_SW P44 ENC_G/PY_IN 1.6Vdc +Green 0.7Vp-p 1kΩ 4kΩ 1.6Vdc 4kΩ 1.6Vdc 300Ω 300Ω +Py 1.0Vp-p 1.6Vdc P45 44 GNG_REF Continued on next page. No.A1992-20/24 LV7109E Continued from preceding page. Pin No. Pin name P46 ENC_B/PB_IN DC voltage Signal wave form Input/Output form Note 1.6Vdc +Blue 1kΩ 0.7Vp-p 4kΩ 1.6Vdc 4kΩ 2.1Vdc +Pb 20kΩ 300Ω 300Ω 0.7Vp-p 2.1Vdc 46 P47 Audio_Mute_Filter 140kΩ 500Ω 47 60kΩ P48 REF4.5V 4.5Vdc DC 52 60kΩ 1kΩ 48 60kΩ P49 A-DAC_R_IN 4.5Vdc 4.5V +Right 5.6Vp-p-MAX 100kΩ 1kΩ 4.5Vdc P50 AV2_R_IN 49 4.5Vdc 4.5V +Right 5.6Vp-p-MAX 100kΩ 1kΩ 4.5Vdc 50 Continued on next page. No.A1992-21/24 LV7109E Continued from preceding page. Pin No. Pin name P51 AV1_R_IN DC voltage Signal wave form Input/Output form 4.5Vdc Note 4.5V +Right 5.6Vp-p-MAX 100kΩ 1kΩ 51 4.5Vdc P52 REG9V_AR 9Vdc DC 50Ω 100Ω 52 141kΩ 23kΩ P53 GND_REG P54 A-DAC_L_IN 4.5Vdc 4.5V +Left 5.6Vp-p-MAX 100kΩ 1kΩ 4.5Vdc P55 AV2_L_IN 54 4.5Vdc 4.5V +Left 5.6Vp-p-MAX 100kΩ 1kΩ 4.5Vdc P56 AV1_L_IN 55 4.5Vdc 4.5V +Left 5.6Vp-p-MAX 100kΩ 1kΩ 4.5Vdc 56 Continued on next page. No.A1992-22/24 LV7109E Continued from preceding page. Pin No. Pin name P57 REG9V_AL DC voltage Signal wave form 9Vdc Input/Output form Note DC 50Ω 100Ω 57 141kΩ 23kΩ P58 AV2_R_OUT 4.5Vdc 4.5V +Right 5.6Vp-p-MAX 20kΩ 4.5Vdc P59 AV2_L_OUT 700Ω 100Ω 58 4.5Vdc 4.5V +Left 5.6Vp-p-MAX 20kΩ 4.5Vdc P60 GND_AR P61 AV1_R_OUT 700Ω 100Ω 59 4.5Vdc 4.5V +Right 5.6Vp-p-MAX 20kΩ 4.5Vdc P62 AV1_L_OUT 700Ω 100Ω 61 4.5Vdc 4.5V +Left 5.6Vp-p-MAX 20kΩ 4.5Vdc P63 700Ω 100Ω 62 GND_AL Continued on next page. No.A1992-23/24 LV7109E Continued from preceding page. Pin No. Pin name P64 AV2_B_IN DC voltage Signal wave form Input/Output form Note 1.6Vdc +Blue 1kΩ 4kΩ 0.7Vp-p 4kΩ 300Ω 300Ω 1.6Vdc 64 ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. 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This literature is subject to all applicable copyright laws and is not for resale in any manner. PS No.A1992-24/24