ICST ICS873990AYT Low voltage, lvcmos/ crystal-to-lvpecl/ecl clock generator Datasheet

ICS873990
Integrated
Circuit
Systems, Inc.
LOW VOLTAGE, LVCMOS/
CRYSTAL-TO-LVPECL/ECL CLOCK GENERATOR
GENERAL DESCRIPTION
FEATURES
The ICS873990 is a low voltage, low skew, 3.3V
LVPECL/ECL Clock Generator and a member
HiPerClockS™
of the HiPerClockS™ family of High Performance
Clock Solutions from ICS. The ICS873990 has
two selectable clock inputs. The XTAL1 and
XTAL2 are used to interface to a crystal and the TEST_CLK
pin can accept a LVCMOS or LVTTL input. This device has a
fully integrated PLL along with frequency configurable outputs. An external feedback input and output regenerates
clocks with “zero delay”.
• 14 differential LVPECL outputs
ICS
• Selectable crystal oscillator interface or TEST_CLK inputs
• TEST_CLK accepts the following input levels:
LVCMOS, LVTTL
• Output frequency: 400MHz (maximum)
• Crystal input frequency range: 10MHz to 25MHz
• VCO range: 200MHz to 800MHz
• Output skew: 250ps (maximum)
The four independent banks of outputs each have their own
output dividers, which allow the device to generate a multitude of different bank frequency ratios and output-to-input
frequency ratios. The output frequency range is 25MHz to
400MHz and the input frequency range is 6.25MHz to
125MHz. The PLL_SEL input can be used to bypass the PLL
for test and system debug purposes. In bypass mode, the
input clock is routed around the PLL and into the internal output dividers.
• Cycle-to-cyle jitter: ±50ps (typical)
• LVPECL mode operating voltage supply range:
VCC = 3.135V to 3.465V, VEE = 0V
• ECL mode operating voltage supply range:
VCC = 0V, VEE = -3.465V to -3.135V
• 0°C to 70°C ambient operating temperature
• Industrial temperature available upon request
The ICS873990 also has a SYNC output which can be used
for system synchronization purposes. It monitors Bank A and
Bank C outputs for coincident rising edges and signals a pulse
per the timing diagrams in this data sheet. This feature is used
primarily in applications where Bank A and Bank C are running at different frequencies, and is particularly useful when
they are running at non-integer multiples of each other.
• Lead-Free package fully RoHS compliant
nQB3
nQC2
QC2
VCCO
nQB0
QB0
FSEL2
nQB1
QB1
FSEL1
FSEL3
QC1
QB3
41
25
nQC1
VCCO
42
24
QC0
nQA0
43
23
nQC0
QA0
44
22
V CCO
nQA1
45
21
QD1
QA1
46
20
nQD1
nQA2
47
19
QD0
QA2
48
18
nQD0
nQA3
49
17
V CCO
QA3
50
16
QFB
SYNC_SEL
51
15
nQFB
VCO_SEL
52
1
V CCA
nEXT_FB
EXT_FB
FSEL_FB0
V CC
FSEL_FB1
XTAL_OUT
6
XTAL_IN
5
TEST_CLK
4
FSEL_FB2
2 3
14
7 8 9 10 11 12 13
REF_SEL
ICS873990
PLL_EN
VEE
2. Zero Delay Buffer: Fan out up to thirteen 100MHz copies
from a reference clock to multiple processing units on an
embedded system.
39 38 37 36 35 34 33 32 31 30 29 28 27
26
40
MR
1. Line Card Multiplier: Multiply 19.44MHz from a back-plane
to 77.76MHz on the line card ASIC and Serdes.
nQB2
Example Applications:
QB2
FSEL0
PIN ASSIGNMENT
52-Lead LQFP
10mm x 10mm x 1.4mm package body
Y package
Top View
873990AY
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REV. B
JUNE 13, 2005
Integrated
Circuit
Systems, Inc.
ICS873990
LOW VOLTAGE, LVCMOS/
CRYSTAL-TO-LVPECL/ECL CLOCK GENERATOR
BLOCK DIAGRAM
VCO_SEL Pulldown
PLL_EN Pulldown
QA0
nQA0
REF_SEL Pulldown
TEST_CLK Pulldown
XTAL_IN
XTAL_OUT
EXT_FB
QA1
XTAL
OSC
nQA1
PHASE
DETECTOR
QA2
nQA2
VCO
QA3
nQA3
LPF
nEXT_FB
QB0
nQB0
MR Pulldown
QB1
nQB1
FREQUENCY
GENERATOR
FSEL_0:3 Pulldown
QB2
nQB2
SYNC
QB3
nQB3
QC0
FSEL_FB0:2 Pulldown
nQC0
QC1
nQC1
QC2
nQC2
QD0
nQD0
SYNC_SEL Pulldown
QD1
nQD1
QFB
nQFB
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REV. B
JUNE 13, 2005
ICS873990
Integrated
Circuit
Systems, Inc.
LOW VOLTAGE, LVCMOS/
CRYSTAL-TO-LVPECL/ECL CLOCK GENERATOR
TABLE 1. PIN DESCRIPTIONS
Number
Name
1
VEE
Power
2
MR
Input
3
PLL_EN
Input
4
REF_SEL
Input
5
6
7
8
11
FSEL_FB2
FSEL_FB1
FSEL_FB0
TEST_CLK
XTAL_IN,
XTAL_OUT
VCC
Power
12
EXT_FB
Input
13
nEXT_FB
Input
14
15,
16
17, 22, 30, 42
VCCA
nQFB,
QFB
VCCO
Power
Output
Power
Output supply pins.
18, 19
nQD0, QD0
Output
Differential output pair. LVPECL interface levels.
9, 10
Type
Description
Negative supply pin.
Active High Master Reset. When logic HIGH, the internal dividers are
reset causing the true outputs (Qx) to go low and the inver ted outputs
Pulldown
(nQx) to go high. When logic LOW, the internal dividers and the
outputs are enabled. LVCMOS/LVTTL interface levels.
PLL enable pin. When logic LOW, PLL is enabled. When logic HIGH,
Pulldown
PLL is in bypass mode. LVCMOS/LVTTL interface levels.
Selects between the different reference inputs as the PLL reference
Pulldown source. When logic LOW, selects cr ystal inputs. When logic HIGH,
selects TEST_CLK. LVCMOS/LVTTL interface levels.
Input
Pulldown Feedback frequency select pins. LVCMOS/LVTTL interface levels.
Input
Pulldown LVCMOS/LVTTL test clock input.
Cr ystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the
output.
Core supply pin.
Input
Pulldown External feedback input.
Pullup/ External feedback input. V /2 default when left floating.
CC
Pulldown
Analog supply pin.
Differential feedback output pair. LVPECL interface levels.
20, 21
nQD1, QD1
Output
Differential output pair. LVPECL interface levels.
23, 24
nQC0, QC0
Output
Differential output pair. LVPECL interface levels.
25, 26
27
33
36
39
28, 29
nQC1, QC1
FSEL3
FSEL2
FSEL1
FSEL0
nQC2, QC2
Output
Differential output pair. LVPECL interface levels.
Output
Differential output pair. LVPECL interface levels.
31, 32
nQB0, QB0
Output
Differential output pair. LVPECL interface levels.
Input
Pulldown Frequency select pins. LVCMOS/LVTTL interface levels.
34, 35
nQB1, QB1
Output
Differential output pair. LVPECL interface levels.
37, 38
nQB2, QB2
Output
Differential output pair. LVPECL interface levels.
40, 41
nQB3, QB3
Output
Differential output pair. LVPECL interface levels.
43, 44
nQA0, QA0
Output
Differential output pair. LVPECL interface levels.
45, 46
nQA1, QA1
Output
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
47, 48
nQA2, QA2
Output
49, 50
nQA3, QA3
Output
51
SYNC_SEL
Input
52
VCO_SEL
Input
Differential output pair. LVPECL interface levels.
Sync output select pin. When LOW, the SYNC output follows the
Pulldown
timing diagram (page 5). When HIGH, QD output follows QC output.
Pulldown Selects VCO range. LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
873990AY
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REV. B
JUNE 13, 2005
ICS873990
Integrated
Circuit
Systems, Inc.
LOW VOLTAGE, LVCMOS/
CRYSTAL-TO-LVPECL/ECL CLOCK GENERATOR
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum Typical
Maximum
Units
CIN
Input Capacitance
4
pF
RPULLDOWN
Input Pulldown Resistor
51
kΩ
RPULLup
Input Pullup Resistor
51
kΩ
TABLE 3A. SELECT PIN FUNCTION TABLE
Inputs
FSEL3
FSEL2
TABLE 3B. FEEDBACK CONTROL FUNCTION TABLE
Inputs
Outputs
FSEL1
FSEL0
QAx
QBx
Outputs
QCx
FSEL_FB2
FSEL_FB1
FSEL_FB0
QFB
0
0
0
0
÷2
÷2
÷2
0
0
0
÷2
0
0
0
1
÷2
÷2
÷4
0
0
1
÷4
0
0
1
0
÷2
÷4
÷4
0
1
0
÷6
1
1
÷8
0
0
1
1
÷2
÷2
÷6
0
0
1
0
0
÷2
÷6
÷6
1
0
0
÷8
0
1
÷16
0
1
0
1
÷2
÷4
÷6
1
0
1
1
0
÷2
÷4
÷8
1
1
0
÷24
0
1
1
1
÷2
÷6
÷8
1
1
1
÷32
1
0
0
0
÷2
÷2
÷8
1
0
0
1
÷2
÷8
÷8
1
0
1
0
÷4
÷4
÷6
1
0
1
1
÷4
÷6
÷6
1
1
0
0
÷4
÷6
÷8
1
1
0
1
÷6
÷6
÷8
1
1
1
0
÷6
÷8
÷8
1
1
1
1
÷8
÷8
÷8
TABLE 3C. INPUT CONTROL FUNCTION TABLE
Control Input Pin
Logic 0
Logic 1
PLL_EN
Enables PLL
Bypasses PLL
VCO_SEL
fVCO
fVCO/2
REF_SEL
Selects XTAL
Selects TEST_CLK
MR
---
Resets outputs
SYNC_SEL
Selects outputs
Match QC Outputs
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REV. B
JUNE 13, 2005
Integrated
Circuit
Systems, Inc.
ICS873990
LOW VOLTAGE, LVCMOS/
CRYSTAL-TO-LVPECL/ECL CLOCK GENERATOR
1:1 Mode
QA
QC
SYNC (QD)
2:1 Mode
QA
QC
SYNC (QD)
3:1 Mode
QA
QC
SYNC (QD)
3:2 Mode
QA
QC
SYNC (QD)
4:3 Mode
QA
QC
SYNC (QD)
FIGURE 1. TIMING DIAGRAMS
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REV. B
JUNE 13, 2005
ICS873990
Integrated
Circuit
Systems, Inc.
LOW VOLTAGE, LVCMOS/
CRYSTAL-TO-LVPECL/ECL CLOCK GENERATOR
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC
NOTE: Stresses beyond those listed under Absolute Maximum
Ratings may cause permanent damage to the device. These
4.6V
Inputs, VI
-0.5V to VCC + 0.5 V
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
Package Thermal Impedance, θJA
42.3°C/W (0 lfpm)
ratings are stress specifications only. Functional operation of
product at these conditions or any conditions beyond those listed
in the DC Characteristics or AC Characteristics is not implied.
Exposure to absolute maxi-mum rating conditions for extended
Storage Temperature, TSTG
-65°C to 150°C
periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V ± 5%, VEE = 0V, TA = 0°C TO 70°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VCC
Core Supply Voltage
3.135
VCCA
Analog Supply Voltage
3.135
3.3
3.465
V
3.3
3.465
3.135
3.3
VCCO
Output Supply Voltage
3.465
V
ICC
Power Supply Current
150
mA
ICCA
Analog Supply Current
15
mA
ICCO
Output Supply Current
95
mA
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V ± 5%, VEE = 0V, TA = 0°C TO 70°C
Symbol
VIH
VIL
Parameter
Input
High Voltage
Input
Low Voltage
Test Conditions
Minimum
REF_SEL, SYNC_SEL,
FSEL_FB0:FB2, PLL_EN,
FSEL0:3, MR, VCO_SEL
TEST_CLK
REF_SEL, SYNC_SEL,
FSEL_FB0:FB2, PLL_EN,
FSEL0:3, MR, VCO_SEL
TEST_CLK
IIH
Input High Current
VCC = VIN = 3.465V
IIL
Input Low Current
VIN = 0V, VCC = 3.465V
Typical
Maximum
Units
2
VCC + 0.3
V
2
VCC + 0.3
V
-0.3
0.8
V
-0.3
1.3
V
15 0
µA
-5
µA
TABLE 4B. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V ± 5%, VEE = 0V, TA = 0°C TO 70°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VOH
Output High Voltage, NOTE 1
VCC - 1.4
VCC - 0.9
V
VOL
Output Low Voltage, NOTE 1
VCC - 2.0
VCC - 1.7
V
VSWING
Peak-to-Peak Output Voltage Swing
0.6
1.0
V
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Mode of Oscillation
Typical Maximum
Units
Fundamental
Frequency
25
MHz
Equivalent Series Resistance (ESR)
50
Ω
Shunt Capacitance
7
pF
Drive Level
1
mW
873990AY
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REV. B
JUNE 13, 2005
ICS873990
Integrated
Circuit
Systems, Inc.
LOW VOLTAGE, LVCMOS/
CRYSTAL-TO-LVPECL/ECL CLOCK GENERATOR
TABLE 6. PLL INPUT REFERENCE CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
t R / tR
Input Rise/Fall Time
Test Conditions
Reference Frequency
VCO_SEL = 0
fREF
Reference Frequency
VCO_SEL = 1
fREFDC
Minimum
Typical
TEST_CLK
Maximum
Units
3
ns
Feedback ÷ 6
66.66
133.33
MHz
Feedback ÷ 8
50
100
MHz
Feedback ÷ 16
25
50
MHz
Feedback ÷ 24
16.66
33.33
MHz
Feedback ÷ 32
12.5
25
MHz
Feedback ÷ 4
50
100
MHz
Feedback ÷ 6
33.33
66.66
MHz
Feedback ÷ 8
25
50
MHz
Feedback ÷ 16
12.5
25
MHz
Feedback ÷ 24
8.33
16.66
MHz
Feedback ÷ 32
6.25
12.5
MHz
25
75
%
Maximum
Units
400
MHz
0
ps
250
ps
350
ps
Reference Input Duty Cycle
NOTE: These parameters are guaranteed by design, but not tested in production.
TABLE 7. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V ± 5%, TA = 0°C TO 70°C
Symbol
Parameter
fMAX
Output Frequency
Static Phase Offset;
TEST_CLK
NOTE 1, 5
Output Skew; NOTE 2, 3
t(Ø)
tsk(o)
t sk(w)
tjit(cc)
Test Conditions
Minimum
-240
Typical
120
Multiple Frequency Skew; NOTE 3, 6
Cycle-to-Cycle Jitter; NOTE 3
f VCO
PLL VCO Lock Range; NOTE 4
t LOCK
PLL Lock Time
tR / tF
Output Rise/Fall Time
±50
ps
VCO_SEL = 0
400
800
MHz
VCO_SEL = 1
200
400
MHz
10
ms
20% to 80%
0.2
1
ns
odc
Output Duty Cycle
45
55
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Defined as the time difference between the input reference clock and the average feedback input signal
when the PLL is locked and the input reference frequency is stable.
NOTE 2:Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: When VCO_SEL = 0, the PLL will be unstable with feedback configurations of ÷2, ÷4 and some ÷6.
When VCO_SEL = 1, the PLL will be unstable with a feedback configuration of ÷2.
NOTE 5: Static phase offset is specified for an input frequency of 50MHz with feedback in ÷8.
NOTE 6: Defined as skew across banks of outputs switching in the same direction operating at different frequencies
with the same supply voltages and equal load conditions. Measured at VCCO/2.
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REV. B
%
JUNE 13, 2005
ICS873990
Integrated
Circuit
Systems, Inc.
LOW VOLTAGE, LVCMOS/
CRYSTAL-TO-LVPECL/ECL CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
2V
VCC ,
VCCA, VCCO
Qx
nQx
SCOPE
Qx
LVPECL
nQy
nQx
VEE
Qy
tsk(o)
-1.3V ± -0.165V
OUTPUT LOAD AC TEST CIRCUIT
OUTPUT SKEW
nQFB,
nQAx:nQDx
VOH
nQFB,
nQAx:nQDx
VOH
➤ t(Ø)
tcycle
➤
n
tcycle n+1
➤
VOL
➤
QFB,
QAx:QDx
QFB,
QAx:QDx
➤
VOL
➤
TEST_CLK
t jit(cc) = tcycle n –tcycle n+1
1000 Cycles
STATIC PHASE OFFSET
CYCLE-TO-CYCLE JITTER
nQFB,
nQAx:nQDx
nQxx
QFB,
QAx:QDx
Qxx
t PW
t
nQyy
Qyy
odc =
tsk(ω)
t PW
x 100%
t PERIOD
MULTIPLE FREQUENCY SKEW
80%
PERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
80%
VSW I N G
Clock
Outputs
20%
20%
tR
tF
OUTPUT RISE/FALL TIME
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REV. B
JUNE 13, 2005
ICS873990
Integrated
Circuit
Systems, Inc.
LOW VOLTAGE, LVCMOS/
CRYSTAL-TO-LVPECL/ECL CLOCK GENERATOR
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS873990 provides separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VCC, VCCA, and VCCO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 2 illustrates how
a 10Ω resistor along with a 10μF and a .01μF bypass
capacitor should be connected to each VCCA pin.
3.3V
VCC
.01μF
10Ω
VCCA
.01μF
10μF
FIGURE 2. POWER SUPPLY FILTERING
TERMINATION FOR 3.3V LVPECL OUTPUTS
50Ω transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion. Figures 3A and 3B show two different layouts which
are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
3.3V
Zo = 50Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
FOUT
50Ω
1
RTT =
Z
((VOH + VOL) / (VCC – 2)) – 2 o
FIN
50Ω
Zo = 50Ω
VCC - 2V
RTT
84Ω
FIGURE 3A. LVPECL OUTPUT TERMINATION
873990AY
125Ω
84Ω
FIGURE 3B. LVPECL OUTPUT TERMINATION
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REV. B
JUNE 13, 2005
ICS873990
Integrated
Circuit
Systems, Inc.
LOW VOLTAGE, LVCMOS/
CRYSTAL-TO-LVPECL/ECL CLOCK GENERATOR
CRYSTAL INPUT INTERFACE
The ICS873990 has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown
in Figure 4 below were determined using a 25MHz, 18pF par-
allel resonant crystal and were chosen to minimize the ppm
error. The optimum C1 and C2 values can be slightly adjusted
for different board layouts.
XTAL_OUT
C1
22p
X1
18pF Parallel Crystal
XTAL_IN
C2
22p
Figure 4. CRYSTAL INPUt INTERFACE
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REV. B
JUNE 13, 2005
ICS873990
Integrated
Circuit
Systems, Inc.
LOW VOLTAGE, LVCMOS/
CRYSTAL-TO-LVPECL/ECL CLOCK GENERATOR
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS873990.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS873990 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 165mA = 571.7mW
Power (outputs)MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 14 * 30mW = 420mW
Total Power_MAX (3.465V, with all outputs switching) = 571.7mW + 420mW = 991.7mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 47.1°C/W per Table 8 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.992W * 47.1°C/W = 116.7°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 8. THERMAL RESISTANCE θJA
FOR
52-PIN LQFP, FORCED CONVECTION
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
58.0°C/W
42.3°C/W
47.1°C/W
36.4°C/W
500
42.0°C/W
34.0°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
873990AY
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REV. B
JUNE 13, 2005
ICS873990
Integrated
Circuit
Systems, Inc.
LOW VOLTAGE, LVCMOS/
CRYSTAL-TO-LVPECL/ECL CLOCK GENERATOR
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 5.
VCCO
Q1
VOUT
RL
50
VCCO - 2V
FIGURE 5. LVPECL DRIVER CIRCUIT
TERMINATION
AND
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CCO
•
For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.9V
(V
CCO_MAX
•
-V
OH_MAX
) = 0.9V
For logic low, VOUT = V
=V
OL_MAX
(V
CCO_MAX
-V
OL_MAX
CCO_MAX
– 1.7V
) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
– (V
CCO_MAX
- 2V))/R ] * (V
CCO_MAX
L
-V
OH_MAX
) = [(2V - (V
CCO_MAX
))/R ] * (V
-V
OH_MAX
CCO_MAX
L
-V
)=
OH_MAX
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
Pd_L = [(V
OL_MAX
– (V
CCO_MAX
- 2V))/R ] * (V
L
CCO_MAX
-V
OL_MAX
) = [(2V - (V
CCO_MAX
-V
OL_MAX
))/R ] * (V
L
CCO_MAX
-V
OL_MAX
)=
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
873990AY
www.icst.com/products/hiperclocks.html
12
REV. B
JUNE 13, 2005
ICS873990
Integrated
Circuit
Systems, Inc.
LOW VOLTAGE, LVCMOS/
CRYSTAL-TO-LVPECL/ECL CLOCK GENERATOR
RELIABILITY INFORMATION
TABLE 9.
θJAVS. AIR FLOW TABLE FOR 52 LEAD LQFP
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
58.0°C/W
42.3°C/W
47.1°C/W
36.4°C/W
42.0°C/W
34.0°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS873990 is: 5788
Pin compatible with the MPC990
873990AY
www.icst.com/products/hiperclocks.html
13
REV. B
JUNE 13, 2005
ICS873990
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - Y SUFFIX
LOW VOLTAGE, LVCMOS/
CRYSTAL-TO-LVPECL/ECL CLOCK GENERATOR
FOR
52 LEAD LQFP
TABLE 10. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
SYMBOL
BCC
MINIMUM
NOMINAL
MAXIMUM
52
N
A
--
--
1.60
A1
A2
0.05
--
0.15
1.35
1.40
1.45
b
0.22
0.32
0.38
c
0.09
--
0.20
D
12.00 BASIC
D1
10.00 BASIC
E
12.00 BASIC
E1
10.00 BASIC
e
0.65 BASIC
L
0.45
--
0.75
θ
0°
--
7°
ccc
--
--
0.08
Reference Document: JEDEC Publication 95, MS-026
873990AY
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14
REV. B
JUNE 13, 2005
ICS873990
Integrated
Circuit
Systems, Inc.
LOW VOLTAGE, LVCMOS/
CRYSTAL-TO-LVPECL/ECL CLOCK GENERATOR
TABLE 11. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
ICS873990AY
ICS873990AY
52 Lead LQFP
tray
0°C to 70°C
ICS873990AYT
ICS873990AY
52 Lead LQFP
500 tape & reel
0°C to 70°C
ICS873990AYLF
TBD
52 Lead "Lead-Free" LQFP
tray
0°C to 70°C
ICS873990AYLFT
TBD
52 Lead "Lead-Free" LQFP
500 tape & reel
0°C to 70°C
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
873990AY
www.icst.com/products/hiperclocks.html
15
REV. B
JUNE 13, 2005
Integrated
Circuit
Systems, Inc.
ICS873990
LOW VOLTAGE, LVCMOS/
CRYSTAL-TO-LVPECL/ECL CLOCK GENERATOR
REVISION HISTORY SHEET
Rev
Table
B
T5
T11
873990AY
Page
1
6
15
Description of Change
Features Section - added Lead-Free bullet.
Cr ystal Characteristics - added Drive Level.
Ordering Information Table - added Lead-Free par t number and note.
www.icst.com/products/hiperclocks.html
16
Date
6/13/05
REV. B
JUNE 13, 2005
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