TI LVC2952A Octal bus transceiver and register with 3-state output Datasheet

SN74LVC2952A
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
www.ti.com
SCAS311I – JANUARY 1993 – REVISED MARCH 2005
FEATURES
•
•
•
•
•
•
•
•
•
Operates From 1.65 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Max tpd of 8.2 ns at 3.3 V
Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
>2 V at VCC = 3.3 V, TA = 25°C
Supports Mixed-Mode Signal Operation on All
Ports (5-V Input/Output Voltage With
3.3-V VCC)
Ioff Supports Partial-Power-Down Mode
Operation
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 1000-V Charged-Device Model (C101)
DB, DW, NS, OR PW PACKAGE
(TOP VIEW)
B8
B7
B6
B5
B4
B3
B2
B1
OEAB
CLKAB
CLKENAB
GND
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
VCC
A8
A7
A6
A5
A4
A3
A2
A1
OEBA
CLKBA
CLKENBA
DESCRIPTION/ORDERING INFORMATION
This octal bus transceiver and register is designed for 1.65-V to 3.6-V VCC operation.
The SN74LVC2952A consists of two 8-bit back-to-back registers that store data flowing in both directions
between two bidirectional buses. Data on the A or B bus is stored in the registers on the low-to-high transition of
the clock (CLKAB or CLKBA) input, provided that the clock-enable (CLKENAB or CLKENBA) input is low. Taking
the output-enable (OEAB or OEBA) input low accesses the data on either port.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
PACKAGE (1)
TA
Reel of 2000
SN74LVC2952ADWR
SOP – NS
Reel of 2000
SN74LVC2952ANSR
LVC2952A
SSOP – DB
Reel of 2000
SN74LVC2952ADBR
LE952A
Tube of 60
SN74LVC2952APW
Reel of 2000
SN74LVC2952APWR
Reel of 250
SN74LVC2952APWT
TSSOP – PW
(1)
TOP-SIDE MARKING
SN74LVC2952ADW
SOIC – DW
–40°C to 85°C
ORDERABLE PART NUMBER
Tube of 25
LVC2952A
LE952A
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1993–2005, Texas Instruments Incorporated
SN74LVC2952A
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
www.ti.com
SCAS311I – JANUARY 1993 – REVISED MARCH 2005
FUNCTION TABLE (1)
INPUTS
(1)
(2)
CLKENAB
CLKAB
OEAB
A
OUTPUT
B
H
X
L
X
B0 (2)
X
H or L
L
X
B0 (2)
L
↑
L
L
L
L
↑
L
H
H
X
X
H
X
Z
A-to-B data flow is shown; B-to-A data flow is similar, but uses
CLKENBA, CLKBA, and OEBA.
Level of B before the indicated steady-state input conditions were
established
LOGIC DIAGRAM (POSITIVE LOGIC)
CLKENAB
CLKAB
OEAB
CLKENBA
CLKBA
OEBA
11
10
9
13
14
15
C1
A1
16
8
1D
C1
1D
To Seven Other Channels
2
B1
SN74LVC2952A
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
www.ti.com
Absolute Maximum Ratings
SCAS311I – JANUARY 1993 – REVISED MARCH 2005
(1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VCC
Supply voltage range
–0.5
6.5
V
VI
Input voltage range (2)
–0.5
6.5
V
–0.5
6.5
V
–0.5
VCC + 0.5
state (2)
UNIT
VO
Voltage range applied to any output in the high-impedance or power-off
VO
Voltage range applied to any output in the high or low state (2) (3)
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
±100
mA
Continuous current through VCC or GND
θJA
Package thermal impedance (4)
Tstg
(1)
(2)
(3)
(4)
DB package
63
DW package
46
NS package
65
PW package
88
Storage temperature range
–65
V
°C/W
°C
150
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
The value of VCC is provided in the recommended operating conditions table.
The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions (1)
VCC
Supply voltage
VIH
High-level input voltage
Operating
Data retention only
VCC = 1.65 V to 1.95 V
MIN
MAX
1.65
3.6
1.5
Low-level input voltage
VI
Input voltage
VO
Output voltage
1.7
VCC = 2.7 V to 3.6 V
2
High-level output current
0.35 × VCC
0.7
VCC = 2.7 V to 3.6 V
0.8
0
5.5
High or low state
0
VCC
3-state
0
5.5
Low-level output current
∆t/∆v
Input transition rise or fall rate
TA
Operating free-air temperature
(1)
V
V
V
–4
VCC = 2.3 V
–8
VCC = 2.7 V
–12
VCC = 3 V
–24
VCC = 1.65 V
IOL
V
VCC = 2.3 V to 2.7 V
VCC = 1.65 V
IOH
V
0.65 × VCC
VCC = 2.3 V to 2.7 V
VCC = 1.65 V to 1.95 V
VIL
UNIT
mA
4
VCC = 2.3 V
8
VCC = 2.7 V
12
VCC = 3 V
24
–40
mA
10
ns/V
85
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3
SN74LVC2952A
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
www.ti.com
SCAS311I – JANUARY 1993 – REVISED MARCH 2005
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
IOH = –100 µA
VOH
1.65 V to 3.6 V
1.2
IOH = –8 mA
2.3 V
1.7
2.7 V
2.2
3V
2.4
IOH = –24 mA
3V
2.2
IOL = 100 µA
1.65 V to 3.6 V
0.2
IOL = 4 mA
1.65 V
0.45
IOL = 8 mA
2.3 V
0.7
IOL = 12 mA
2.7 V
0.4
3V
0.55
Control inputs VI = 0 to 5.5 V
UNIT
VCC – 0.2
1.65 V
IOL = 24 mA
II
TYP (1) MAX
IOH = –4 mA
IOH = –12 mA
VOL
MIN
V
V
3.6 V
±5
µA
Ioff
VI or VO = 5.5 V
0
±10
µA
IOZ (2)
VO = 0 to 5.5 V
3.6 V
±10
µA
VI = VCC or GND
ICC
3.6 V ≤ VI ≤ 5.5 V (3)
∆ICC
IO = 0
10
3.6 V
One input at VCC – 0.6 V, Other inputs at VCC or GND
10
2.7 V to 3.6 V
500
µA
µA
Ci
Control inputs VI = VCC or GND
3.3 V
5
pF
Cio
A or B ports
3.3 V
8.5
pF
(1)
(2)
(3)
VO = VCC or GND
All typical values are at VCC = 3.3 V, TA = 25°C.
For I/O ports, the parameter IOZ includes the input leakage current.
This applies in the disabled state only.
Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
VCC = 1.8 V
± 0.15 V
MIN
Clock frequency
tw
Pulse duration, CLK high or low
Setup time
th
Hold time
(1)
4
MIN
(1)
fclock
tsu
MAX
VCC = 2.5 V
± 0.2 V
MAX
VCC = 2.7 V
MIN
(1)
MAX
VCC = 3.3 V
± 0.3 V
MIN
150
150
(1)
(1)
3.3
3.3
Data before CLK high
(1)
(1)
1.7
1.3
CLKEN before CLK high
(1)
(1)
1.3
1.1
Data after CLK high
(1)
(1)
1.8
1.1
CLKEN after CLK high
(1)
(1)
1.4
1.1
This information was not available at the time of publication.
UNIT
MAX
MHz
ns
ns
ns
SN74LVC2952A
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
www.ti.com
SCAS311I – JANUARY 1993 – REVISED MARCH 2005
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 1.8 V
± 0.15 V
MIN
MAX
VCC = 2.5 V
± 0.2 V
MIN
MAX
MIN
MAX
MIN
(1)
tpd
CLKAB or CLKBA
B or A
(1)
(1)
(1)
(1)
8.8
1
8.2
ns
ten
OE
A or B
(1)
(1)
(1)
(1)
9
1
7.8
ns
A or B
(1)
(1)
(1)
(1)
8.8
1
7.8
ns
1
ns
OE
150
150
MHz
tsk(o)
(1)
UNIT
MAX
fmax
tdis
(1)
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
This information was not available at the time of publication.
Operating Characteristics
TA = 25°C
PARAMETER
Cpd
(1)
Power dissipation capacitance Outputs enabled
per transceiver
Outputs disabled
TEST
CONDITIONS
f = 10 MHz
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
TYP
TYP
TYP
(1)
(1)
79
(1)
(1)
41
UNIT
pF
This information was not available at the time of publication.
5
SN74LVC2952A
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
www.ti.com
SCAS311I – JANUARY 1993 – REVISED MARCH 2005
PARAMETER MEASUREMENT INFORMATION
VLOAD
S1
RL
From Output
Under Test
CL
(see Note A)
Open
GND
RL
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
2.7 V
3.3 V ± 0.3 V
VI
tr/tf
VCC
VCC
2.7 V
2.7 V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
V∆
VCC/2
VCC/2
1.5 V
1.5 V
2 × VCC
2 × VCC
6V
6V
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tw
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
tPLH
VM
VM
VOL
tPHL
VM
VM
0V
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
tPLZ
VLOAD/2
VM
tPZH
VOH
Output
VM
tPZL
tPHL
VOH
Output
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
VM
VOH − V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
6
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN74LVC2952ADBLE
OBSOLETE
SSOP
DB
24
SN74LVC2952ADBR
ACTIVE
SSOP
DB
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC2952ADBRE4
ACTIVE
SSOP
DB
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC2952ADGVR
OBSOLETE
TVSOP
DGV
24
TBD
Call TI
SN74LVC2952ADW
ACTIVE
SOIC
DW
24
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC2952ADWE4
ACTIVE
SOIC
DW
24
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC2952ADWR
ACTIVE
SOIC
DW
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC2952ADWRE4
ACTIVE
SOIC
DW
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC2952ANSR
ACTIVE
SO
NS
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC2952ANSRE4
ACTIVE
SO
NS
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC2952APW
ACTIVE
TSSOP
PW
24
60
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC2952APWE4
ACTIVE
TSSOP
PW
24
60
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC2952APWLE
OBSOLETE
TSSOP
PW
24
SN74LVC2952APWR
ACTIVE
TSSOP
PW
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC2952APWRE4
ACTIVE
TSSOP
PW
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC2952APWT
ACTIVE
TSSOP
PW
24
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC2952APWTE4
ACTIVE
TSSOP
PW
24
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TBD
TBD
Lead/Ball Finish
Call TI
Call TI
MSL Peak Temp (3)
Call TI
Call TI
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,40
0,23
0,13
24
13
0,07 M
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–8°
1
0,75
0,50
12
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,08
14
16
20
24
38
48
56
A MAX
3,70
3,70
5,10
5,10
7,90
9,80
11,40
A MIN
3,50
3,50
4,90
4,90
7,70
9,60
11,20
DIM
4073251/E 08/00
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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