TI1 ADS58C28 Dual channel if receiver with snrboost 3g Datasheet

ADS58C28
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SBAS509B – JUNE 2010 – REVISED OCTOBER 2010
Dual Channel IF Receiver with SNRBoost3G
Check for Samples: ADS58C28
FEATURES
DESCRIPTION
•
•
The ADS58C28 is a dual-channel, 11-bit
analog-to-digital converter (ADC) with sampling rates
up to 200MSPS. The device uses innovative design
techniques to achieve high dynamic performance,
while consuming extremely low power at 1.8V supply.
This architecture makes it well-suited for multi-carrier,
wide bandwidth communications applications.
1
23
•
•
•
•
•
•
•
Maximum Sample Rate: 200MSPS
High Dynamic Performance:
– 83dBc SFDR at 140MHz
– 72.5dBFS SNR with 60MHz BW Using
SNRBoost3G Technology
SNRBoost3G Highlights:
– Supports Wide Bandwidth (up to 60MHz)
– Programmable Bandwidths:
20MHz, 30MHz, and 40MHz
– Flat Noise Floor within the Band
– Independent SNRBoost3G Coefficients for
Both Channels
Output Interface:
– Double Data Rate (DDR) LVDS with
Programmable Swing and Strength:
– Standard Swing: 350mV
– Low Swing: 200mV
– Default Strength: 100Ω termination
– 2x Strength: 50Ω termination
– Compatible with GC6016
– 1.8V Parallel CMOS Interface Also
Supported
Ultralow Power with Single 1.8V Supply:
– 470mW Total Power
– 710mW Total Power (200MSPS) with
SNRBoost3G on Both Channels
Programmable Gain up to 6dB for
SNR/SFDR Trade-off
DC Offset Correction
Supports Low Input Clock Amplitude
Package: QFN-64 (9mm × 9mm)
The ADS58C28 uses third-generation SNRBoost3G
technology to overcome SNR limitation as a result of
quantization noise (for bandwidths less than Nyquist,
fS/2). Enhancements in the SNRBoost3G technology
allow support for SNR improvements over wide
bandwidths (up to 60MHz). In addition, separate
SNRBoost3G coefficients can also be programmed for
each channel.
The device has a digital gain function that can be
used to improve SFDR performance at lower
full-scale input ranges. It includes a dc offset
correction loop that can be used to cancel the ADC
offset. The digital outputs of all channels are output
as double data rate (DDR) low-voltage differential
signaling (LVDS) together with an LVDS clock output.
The low data rate of this interface (400MBPS at
200MSPS sample rate) makes it possible to use
low-cost
field-programmable
gate
array
(FPGA)-based receivers. The strength of the LVDS
output buffers can be increased to support 50Ω
differential termination. This increase allows the
output clock signal to be connected to two separate
receiver chips with an effective 50Ω termination (such
as the two clock ports of the GC5330). The same
digital output pins can also be configured as a parallel
1.8V CMOS interface.
The device includes internal references while the
traditional reference pins and associated decoupling
capacitors have been eliminated. The ADS58C28 is
specified over the industrial temperature range
(–40°C to +85°C).
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments Incorporated.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated
ADS58C28
SBAS509B – JUNE 2010 – REVISED OCTOBER 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION (1)
PRODUCT
ADS58C28
(1)
(2)
PACKAGELEAD
PACKAGE
DESIGNATOR
QFN-64
RGC
SPECIFIED
TEMPERATURE
RANGE
–40°C to +85°C
ECO PLAN (2)
GREEN (RoHS, no
Sb/Br)
LEAD/BALL
FINISH
Cu/NiPdAu
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT MEDIA
ADS58C28IRGC
Tape and reel
ADS58C28IRGC
Tape and reel
AZ58C28
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
Eco Plan is the planned eco-friendly classification. Green (RoHS, no Sb/Br): TI defines Green to mean Pb-Free (RoHS compatible) and
free of Bromine- (Br) and Antimony- (Sb) based flame retardants. Refer to the Quality and Lead-Free (Pb-Free) Data web site for more
information.
The ADS58C28 is pin-compatible with the previous generation ADS62C17 converter; this architecture enables
easy migration. However, there are some important differences between the generations, summarized in Table 1.
Table 1. Migrating from the ADS62C17
ADS62C17
ADS58C28
PINS
Pin 22 is NC (not connected)
Pin 22 is AVDD
Pins 38 and 58 are DRVDD
Pins 38 and 58 are NC (do not connect pins)
Pins 39 and 59 are DRGND
Pins 39 and 59 are NC (do not connect pins)
SUPPLY
AVDD is 3.3V
AVDD is 1.8V
DRVDD is 1.8V
No change
INPUT COMMON-MODE VOLTAGE
CM is 1.5V
CM is 0.95V
SERIAL INTERFACE
Protocol: 8-bit register address and 8-bit register data
No change in protocol
New serial register map
PARALLEL CONFIGURATION
SCLK pin controls internal and external reference mode
SCLK pin enables low-speed mode
EXTERNAL REFERENCE
Supported
2
Not supported
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ABSOLUTE MAXIMUM RATINGS (1)
ADS58C28
MIN
MAX
Supply voltage range, AVDD
–0.3
2.1
V
Supply voltage range, DRVDD
–0.3
2.1
V
Voltage between AGND and DRGND
–0.3
0.3
V
Voltage between AVDD to DRVDD (when AVDD leads DRVDD)
–2.4
2.4
V
Voltage between DRVDD to AVDD (when DRVDD leads AVDD)
–2.4
2.4
V
–0.3
Minimum
(1.9, AVDD + 0.3)
V
(2)
–0.3
AVDD + 0.3
V
RESET, SCLK, SDATA, SEN,
CTRL1, CTRL2, CTRL3
–0.3
+3.9
V
+85
°C
+125
°C
INP, INM
Voltage applied to input pins
CLKP, CLKM
Operating free-air temperature range, TA
–40
Operating junction temperature range, TJ
Storage temperature range, Tstg
–65
+150
°C
2
kV
ESD, Human body model (HBM)
(1)
(2)
UNIT
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
When AVDD is turned off, it is recommended to switch off the input clock (or ensure the voltage on CLKP, CLKM is less than |0.3V|.
This prevents the ESD protection diodes at the clock input pins from turning on.
THERMAL INFORMATION
ADS58C28
THERMAL METRIC (1)
RGC
UNITS
64 PINS
qJA
Junction-to-ambient thermal resistance
23.9
qJCtop
Junction-to-case (top) thermal resistance
10.9
qJB
Junction-to-board thermal resistance
4.3
yJT
Junction-to-top characterization parameter
0.1
yJB
Junction-to-board characterization parameter
4.4
qJCbot
Junction-to-case (bottom) thermal resistance
0.6
(1)
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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RECOMMENDED OPERATING CONDITIONS
Over operating free-air temperature range, unless otherwise noted.
MIN
NOM
MAX
UNIT
Analog supply voltage, AVDD
1.75
1.8
1.9
V
Digital supply voltage, DRVDD
1.7
1.8
1.9
V
SUPPLIES
ANALOG INPUTS
Default, SNRBoost3G disabled
Differential input voltage range
3G
SNRBoost
enabled
2
VPP
1.6
VPP
VCM (1) ± 0.05
Input common-mode voltage
V
Maximum analog input frequency with 2VPP input amplitude (2)
400
MHz
Maximum analog input frequency with 1VPP input amplitude (2)
600
MHz
CLOCK INPUT
Default after reset LOW SPEED mode disabled
Input clock sample rate (3)
> 80
200
1
80
LOW SPEED mode enabled
Sine wave, ac-coupled
Input clock amplitude differential
(VCLKP – VCLKM)
0.2
1.5
VPP
LVPECL, ac-coupled
1.6
VPP
LVDS, ac-coupled
0.7
VPP
LVCMOS, single-ended, ac-coupled
Input clock duty cycle
MSPS
1.8
V
Default after reset LOW SPEED mode disabled
35
50
65
%
LOW SPEED mode enabled
40
50
60
%
DIGITAL OUTPUTS
Maximum external load capacitance from each output pin to DRGND, CLOAD
Differential load resistance between the LVDS output pairs (LVDS mode), RLOAD
HIGH-PERFORMANCE MODES
10
pF
100
Ω
(4) (5)
High-performance mode
Set this register bit to get best performance across Register address = 03h,
sample clock and input signal frequencies
data = 03h
High-frequency mode
Set these register bits for high input signal
frequencies (> 200MHz)
Register address = 4Ah,
data = 01h
Register address = 58h,
data = 01h
Operating free-air temperature, TA
(1)
(2)
(3)
(4)
(5)
4
–40
+85
°C
VCM, typically 0.95V, is the voltage measured on the VCM pin when the input clock is switched off.
See the Theory of Operation section in the Application Information
See description for LOW SPEED mode in the Serial Interface Configuration section.
It is recommended to use these modes to obtain best performance.
See the Serial Interface Configuration section for details on register programming.
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SBAS509B – JUNE 2010 – REVISED OCTOBER 2010
ELECTRICAL CHARACTERISTICS
Typical values are at +25°C, AVDD = 1.8V, DRVDD = 1.8V, sampling frequency = 200MSPS, 50% clock duty cycle, –1dBFS
differential analog input, and LVDS and CMOS interfaces, unless otherwise noted.
Minimum and maximum values are across the full temperature range: TMIN = –40°C to TMAX = +85°C, AVDD = 1.8V, and
DRVDD = 1.8V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RESOLUTION
Resolution
11
Bits
ANALOG INPUTS
Differential input voltage range
2
VPP
0.75
kΩ
Differential input capacitance
(at 200MHz, see Figure 56)
3.7
pF
Analog input bandwidth
550
MHz
Analog input common-mode current
(per input pin of each channel)
1.5
µA/MSPS
VCM common-mode voltage output
0.95
Differential input resistance
(at 200MHz, see Figure 55)
VCM output current capability
V
4
mA
POWER SUPPLY
IAVDD
IDRVDD
Analog supply current
Output buffer supply current LVDS interface
350mV LVDS swing with 100Ω
external termination after reset
141
163
mA
120
130
mA
Analog power
254
Digital power LVDS interface
216
Global power-down
mW
mW
15
mW
0.6
LSB
1.5
LSB
15
mV
2
%FS
±1
%FS
DC ACCURACY
DNL
Differential nonlinearity
fIN = 170MHz
–0.6
INL
Integral nonlinearity
fIN = 170MHz
–1.5
Offset error
Specified across devices and
channels within a device
–15
0.3
There are two sources of gain error: internal reference inaccuracy and channel gain error
Gain error as a result of internal reference
inaccuracy alone
Specified across devices and
channels within a device
Gain error of channel alone (1)
Specified across devices and
channels within a device
Channel gain error temperature coefficient
(1)
–2
±0.1
0.002
Δ%/°C
Specified by design and characterization; not tested in production.
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ELECTRICAL CHARACTERISTICS
Typical values are at +25°C, AVDD = 1.8V, DRVDD = 1.8V, sampling frequency = 200MSPS, 50% clock duty cycle, –1dBFS
differential analog input, SNRBoost3G disabled, and LVDS and CMOS interfaces, unless otherwise noted.
Minimum and maximum values are across the full temperature range: TMIN = –40°C to TMAX = +85°C, AVDD = 1.8V, and
DRVDD = 1.8V.
PARAMETER
SNR
Signal-to-noise ratio,
LVDS
TEST CONDITIONS
MIN
fIN = 20MHz
fIN = 100MHz
66.4
fIN = 170MHz
65
fIN = 100MHz
fIN = 100MHz
84
70.5
80
fIN = 100MHz
81
69.5
82
fIN = 100MHz
85
70.5
86
fIN = 100MHz
86
Worst Spur
Other than second and third
harmonics
70.5
fIN = 20MHz
dBc
85
90
fIN = 100MHz
89
fIN = 170MHz
74.5
IMD
Two-tone intermodulation distortion
F1 = 185MHz, F2 = 190MHz, each tone at –7dBFS
Input overload recovery
Recovery to within 1% (of final value) for 6dB overload
with sine wave input
Crosstalk
With a full-scale 170MHz signal on aggressor and a full-scale
20MHz signal on victim
PSRR
AC power-supply rejection ratio
For 50mVPP signal on AVDD supply
6
dBc
79
fIN = 20MHz
fIN = 170MHz
dBc
78
fIN = 20MHz
fIN = 170MHz
dBc
80
fIN = 20MHz
fIN = 170MHz
HD3
Third-harmonic distortion
dBFS
65.8
82
fIN = 170MHz
HD2
Second-harmonic distortion
dBFS
66
66.3
64.5
fIN = 20MHz
THD
Total harmonic distortion
UNITS
66.7
fIN = 170MHz
SFDR
Spurious-free dynamic range
MAX
66.8
fIN = 20MHz
SINAD
Signal-to-noise and distortion ratio
TYP
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dBc
88
83
dBFS
1
Clock
cycles
96
20
dB
dB
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DIGITAL CHARACTERISTICS
The DC specifications refer to the condition where the digital outputs are not switching, but are permanently at valid logic
level 0 or 1. AVDD = 1.8V and DRVDD = 1.8V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL INPUTS—RESET, SCLK, SDATA, SEN, CTRL1, CTRL2, and CTRL3
High-level input voltage
RESET, SCLK, SDATA and SEN support
1.8V and 3.3V CMOS logic levels.
Low-level input voltage
1.3
V
0.4
V
High-level input
current
SDATA, SCLK (1)
VHIGH = 1.8V
10
µA
SEN (2)
VHIGH = 1.8V
0
µA
Low-level input
current
SDATA, SCLK
VLOW = 0V
0
µA
SEN
VLOW = 0V
–10
µA
DRVDD
V
DIGITAL OUTPUTS—CMOS INTERFACE (CHx_Dn, SDOUT)
High-level output voltage
DRVDD – 0.1
Low-level output voltage
0
0.1
V
DIGITAL OUTPUTS—LVDS INTERFACE (CHxP/M, CLKOUTP/M)
VODH, High-level output voltage (3)
VODL, Low-level output voltage
(3)
Standard swing LVDS
270
350
430
mV
Standard swing LVDS
–430
–350
–270
mV
VODH, High-level output voltage (3)
Low swing LVDS (4)
200
VODL, Low-level output voltage (3)
Low swing LVDS (4)
–200
VOCM, Output common-mode voltage
(1)
(2)
(3)
(4)
0.9
1.05
mV
mV
1.25
V
SDATA and SCLK have an internal 150kΩ pull-down resistor.
SEN has an internal 150kΩ pull-up resistor to AVDD.
With external 100Ω termination.
See the LVDS Output Data and Clock Buffers section.
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Table 2. SNR Enhancement with SNRBoost3G Enabled (1)
SNR WITHIN SPECIFIED BANDWIDTH (dBFS)
BANDWIDTH
(MHz)
IN DEFAULT MODE
(SNRBoost3G Disabled)
MIN
(1)
(2)
(3)
TYP
MAX
WITH SNRBoost3G ENABLED (2) (3)
MIN
TYP
60
68.3
69.7
72.5
40
70
71.8
74
30
71.1
72.8
74.7
20
72.5
74.4
76
MAX
3G
SNRBoost bathtub centered at (3/4) × fS, –2dBFS input applied at fIN = 140MHz, sampling
frequency = 200MSPS.
Using suitable filters. See note on SNRBoost3G in the SNR Enhancement Using SNRBoost section.
Specified by characterization.
CHAn_P
CHBn_P
Logic 0
VODL = -350mV
Logic 1
(1)
VODH = +350mV
(1)
CHAn_M
CHBn_M
VOCM
GND
(1) With external 100Ω termination.
Figure 1. LVDS Voltage Levels
8
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PIN CONFIGURATION (LVDS MODE)
49 DRGND
50 CHA6_M
51 CHA6_P
52 CHA8_M
53 CHA8_P
54 CHA10_M
55 CHA10_P
56 CLKOUTM
57 CLKOUTP
58 NC
59 NC
60 NC
61 NC
62 CHB0_M
63 CHB0_P
64 SDOUT
RGC PACKAGE(1)
QFN-64
(TOP VIEW)
DRVDD
1
48
DRVDD
CHB2_M
2
47
CHA4_P
CHB2_P
3
46
CHA4_M
CHB4_M
4
45
CHA2_P
CHB4_P
5
44
CHA2_M
CHB6_M
6
43
CHA0_P
CHB6_P
7
42
CHA0_M
CHB8_M
8
41
NC
CHB8_P
9
40
NC
CHB10_M 10
39
NC
CHB10_P 11
38
NC
RESET 12
37
CTRL3
SCLK 13
36
CTRL2
SDATA 14
35
CTRL1
SEN 15
34
AVDD
AVDD 16
33
AVDD
AGND 32
AGND 31
INA_M 30
INA_P 29
AGND 28
AGND 27
CLKM 26
CLKP 25
AGND 24
CM 23
AVDD 22
AGND 21
INB_M 20
INB_P 19
AGND 18
AGND 17
Thermal Pad
(Connected to DRGND)
(2) The PowerPAD™ is connected to DRGND.
(3) NC = no connection.
Figure 2. ADS58C28 LVDS Pinout
Pin Assignments (LVDS Mode)
PIN NAME
PIN NUMBER
# OF
PINS
AVDD
16, 22, 33, 34
4
Input
Analog power supply
AGND
17, 18, 21, 24, 27, 28,
31, 32
8
Input
Analog ground
FUNCTION
DESCRIPTION
CLK_P
25
1
Input
Differential clock positive input
CLK_M
26
1
Input
Differential clock negative input
INA_P
29
1
Input
Differential analog positive input, channel A
INA_M
30
1
Input
Differential analog negative input, channel A
INB_P
19
1
Input
Differential analog positive input, channel B
INB_M
20
1
Input
Differential analog negative input, channel B
CM
23
1
Output
This pin outputs the common-mode voltage (0.95V) that can be used externally to bias
the analog input pins
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Pin Assignments (LVDS Mode) (continued)
PIN NAME
PIN NUMBER
# OF
PINS
FUNCTION
DESCRIPTION
RESET
12
1
Input
Serial interface RESET input.
When using the serial interface mode, the internal registers must be initialized through a
hardware RESET by applying a high pulse on this pin or by using the software reset
option; refer to the Serial Interface Configuration section.
In parallel interface mode, the RESET pin must be permanently tied high. SCLK and
SEN are used as parallel control pins in this mode. This pin has an internal 100kΩ
pull-down resistor.
SCLK
13
1
Input
This pin functions as a serial interface clock input when RESET is low. It controls the
low-speed mode selection when RESET is tied high; see Table 6 for detailed
information. This pin has an internal 100kΩ pull-down resistor.
SDATA
14
1
Input
Serial interface data input; this pin has an internal 100kΩ pull-down resistor.
SEN
15
1
Input
This pin functions as a serial interface enable input when RESET is low. It controls the
output interface and data format selection when RESET is tied high; see Table 7 for
detailed information. This pin has an internal 150kΩ pull-up resistor to AVDD.
SDOUT
64
1
Output
This pin functions as a serial interface register readout when the READOUT bit is
enabled. When READOUT = 0, this pin forces a logic low and is not put in 3-state.
CTRL1
35
1
Input
Digital control input pins. Together, they control the SNRBoost3G, power-down, and
multiplexed modes.
CTRL2
36
1
Input
Digital control input pins. Together, they control the SNRBoost3G, power-down, and
multiplexed modes.
CTRL3
37
1
Input
Digital control input pins. Together, they control the SNRBoost3G, power-down, and
multiplexed modes.
CLKOUT_P
57
1
Output
Differential output clock, true
CLKOUT_M
56
1
Output
Differential output clock, complement
CHA0_P,
CHA0_M
Refer to Figure 2
2
Output
Channel A differential output data pair, 0 and D0 multiplexed
CHA2_P,
CHA2_M
Refer to Figure 2
2
Output
Channel A differential output data D1 and D2 (multiplexed and true)
CHA4_P,
CHA4_M
Refer to Figure 2
2
Output
Channel A differential output data D3 and D4 (multiplexed and true)
CHA6_P,
CHA6_M
Refer to Figure 2
2
Output
Channel A differential output data D5 and D6 (multiplexed and true)
CHA8_P,
CHA8_M
Refer to Figure 2
2
Output
Channel A differential output data D7 and D8 (multiplexed and true)
CHA10_P,
CHA10_M
Refer to Figure 2
2
Output
Channel A differential output data D9 and D10 (multiplexed and true)
CHB0_P,
CHB0_M
Refer to Figure 2
2
Output
Channel B differential output data pair, 0 and D0 multiplexed
CHB2_P,
CHB2_M
Refer to Figure 2
2
Output
Channel B differential output data D1 and D2 (multiplexed and true)
CHB4_P,
CHB4_M
Refer to Figure 2
2
Output
Channel B differential output data D3 and D4 (multiplexed and true)
CHB6_P,
CHB6_M
Refer to Figure 2
2
Output
Channel B differential output data D5 and D6 (multiplexed and true)
CHB8_P,
CHB8_M
Refer to Figure 2
2
Output
Channel B differential output data D7 and D8 (multiplexed and true)
CHB10_P,
CHB10_M
Refer to Figure 2
2
Output
Channel B differential output data D9 and D10 (multiplexed and true)
10
DRVDD
1, 48
2
Input
Output buffer supply
DRGND
49, PAD
2
Input
Output buffer ground
NC
Refer to Figure 2
1
—
Do not connect
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PIN CONFIGURATION (CMOS MODE)
49 DRGND
50 CHA_D5
51 CHA_D6
52 CHA_D7
53 CHA_D8
54 CHA_D9
55 CHA_D10
56 NC
57 CLKOUTP
58 NC
59 NC
60 NC
61 NC
62 NC
63 CHB_D0
64 SDOUT
RGC PACKAGE(3)
QFN-64
(TOP VIEW)
DRVDD
1
48
DRVDD
CHB_D1
2
47
CHA_D4
CHB_D2
3
46
CHA_D3
CHB_D3
4
45
CHA_D2
CHB_D4
5
44
CHA_D1
CHB_D5
6
43
CHA_D0
CHB_D6
7
42
NC
CHB_D7
8
41
NC
CHB_D8
9
40
NC
CHB_D9 10
39
NC
CHB_D10 11
38
NC
RESET 12
37
CTRL3
SCLK 13
36
CTRL2
SDATA 14
35
CTRL1
SEN 15
34
AVDD
AVDD 16
33
AVDD
AGND 32
AGND 31
INA_M 30
INA_P 29
AGND 28
AGND 27
CLKM 26
CLKP 25
AGND 24
CM 23
AVDD 22
AGND 21
INB_M 20
INB_P 19
AGND 18
AGND 17
Thermal Pad
(Connected to DRGND)
(4) The PowerPAD is connected to DRGND.
(5) NC = no connection.
Figure 3. ADS58C28 CMOS Pinout
Pin Assignments (CMOS Mode)
PIN NAME
PIN NUMBER
# OF
PINS
AVDD
16, 22, 33, 34
4
Input
Analog power supply
AGND
17, 18, 21, 24, 27, 28,
31, 32
8
Input
Analog ground
FUNCTION
DESCRIPTION
CLK_P
25
1
Input
Differential clock positive input
CLK_M
26
1
Input
Differential clock negative input
INA_P
29
1
Input
Differential analog positive input, channel A
INA_M
30
1
Input
Differential analog negative input, channel A
INB_P
19
1
Input
Differential analog positive input, channel B
INB_M
20
1
Input
Differential analog negative input, channel B
CM
23
1
Output
This pin outputs the common-mode voltage (0.95V) that can be used externally to bias
the analog input pins
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Pin Assignments (CMOS Mode) (continued)
PIN NAME
12
PIN NUMBER
# OF
PINS
FUNCTION
DESCRIPTION
RESET
12
1
Input
Serial interface RESET input.
When using the serial interface mode, the internal registers must be initialized through a
hardware RESET by applying a high pulse on this pin or by using the software reset
option; refer to the Serial Interface Configuration section.
In parallel interface mode, the RESET pin must be permanently tied high. SDATA and
SEN are used as parallel control pins in this mode. This pin has an internal 100kΩ
pull-down resistor.
SCLK
13
1
Input
This pin functions as a serial interface clock input when RESET is low. It controls the
low-speed mode when RESET is tied high; see Table 6 for detailed information. This pin
has an internal 100kΩ pull-down resistor.
SDATA
14
1
Input
Serial interface data input; this pin has an internal 100kΩ pull-down resistor.
SEN
15
1
Input
This pin functions as a serial interface enable input when RESET is low. It controls the
output interface and data format selection when RESET is tied high; see Table 7 for
detailed information. This pin has an internal 150kΩ pull-up resistor to AVDD.
SDOUT
64
1
Output
CTRL1
35
1
Input
Digital control input pins. Together, they control various power-down modes.
CTRL2
36
1
Input
Digital control input pins. Together, they control various power-down modes.
CTRL3
37
1
Input
Digital control input pins. Together, they control various power-down modes.
CLKOUT
57
1
Output
CMOS output clock
CHA_D0 to
CHA_D10
Refer to Figure 3
11
Output
Channel A ADC output data bits, CMOS levels
CHB_D0 to
CHB_D10
Refer to Figure 3
11
Output
Channel B ADC output data bits, CMOS levels
This pin functions as a serial interface register readout when the READOUT bit is
enabled. When READOUT = 0, this pin forces a logic low and is not put in 3-state.
DRVDD
1, 48
2
Input
Output buffer supply
DRGND
49, PAD
2
Input
Output buffer ground
NC
Refer to Figure 3
1
—
Do not connect
UNUSED
56
1
—
This pin is not used in the CMOS interface
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FUNCTIONAL BLOCK DIAGRAM
AGND
AVDD
DRVDD
DRGND
CHB0_P
Channel B
CHB0_M
CHB2_P
CHB2_M
Digital Processing
Block
INB_P
INB_M
14-Bit
ADC
SNRBoost
CHB4_P
CHB4_M
DDR
Serializer
3G
11
CHB6_P
CHB6_M
CHB8_P
CHB8_M
CHB10_P
CHB10_M
CLK_P
CLKOUT_P
Output
Clock Buffer
CLOCKGEN
CLK_M
CLKOUT_M
CHA0_P
Channel A
CHA0_M
CHA2_P
CHA2_M
Digital Processing
Block
INA_P
INA_M
14-Bit
ADC
SNRBoost
CHA4_P
CHA4_M
DDR
Serializer
3G
11
CHA6_P
CHA6_M
CHA8_P
CHA8_M
CHA10_P
CHA10_M
CM
Control
Interface
Reference
SDOUT
SEN
SDATA
SCLK
RESET
CTRL3
CTRL1
CTRL2
ADS58C28
Figure 4. ADS58C28 Block Diagram (LVDS Interface)
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TIMING CHARACTERISTICS: LVDS AND CMOS MODES (1)
Typical values are at +25°C, AVDD = 1.8 V, DRVDD = 1.8 V, sampling frequency = 200MSPS, sine wave input clock,
CLOAD = 5pF (2), and RLOAD = 100Ω (3), unless otherwise noted.
Minimum and maximum values are across the full temperature range: TMIN = –40°C to TMAX = +85°C, AVDD = 1.8V, and
DRVDD = 1.7V to 1.9V.
PARAMETER
tA
TEST CONDITIONS
Aperture delay
tJ
Aperture delay matching
Between the two channels of the same device
Variation of aperture delay
Between two devices at the same temperature and
DRVDD supply
MIN
TYP
MAX
0.5
0.8
1.1
Aperture jitter
Wakeup time
ADC latency (4)
Time to valid data after coming out of STANDBY
mode
Time to valid data after coming out of GLOBAL
power-down mode
UNIT
ns
±70
ps
±150
ps
140
fS rms
50
100
µs
100
500
µs
Default latency after reset, DIGITAL MODE1 = 0,
DIGITAL MODE2 = 0
16
Clock
cycles
SNRBoost3G only enabled, DIGITAL MODE1 = 0,
DIGITAL MODE2 = 1
17
Clock
cycles
SNRBoost3G, gain and offset corr enabled, DIGITAL
MODE1 = 1, DIGITAL MODE2 = 0 or 1
24
Clock
cycles
DDR LVDS MODE (5)
Data setup time (6)
Data valid (6) to zero-crossing of CLKOUTP
1.05
1.5
ns
tH
Data hold time (6)
Zero-crossing of CLKOUTP to data becoming
invalid (6)
0.35
0.6
ns
tPDI
Clock propagation delay
Input clock rising edge cross-over to output clock
rising edge cross-over
1MSPS ≤ Sampling frequency ≤ 200MSPS
5.1
6.4
LVDS bit clock duty cycle
Duty cycle of differential clock,
(CLKOUTP-CLKOUTM)
1MSPS ≤ Sampling frequency ≤ 200MSPS
50%
tRISE,
tFALL
Data rise time,
Data fall time
Rise time measured from –100mV to +100mV
Fall time measured from +100mV to –100mV
1MSPS ≤ Sampling frequency ≤ 200MSPS
0.13
ns
tCLKRISE,
tCLKFALL
Output clock rise time,
Output clock fall time
Rise time measured from –100mV to +100mV
Fall time measured from +100mV to –100mV
1MSPS ≤ Sampling frequency ≤ 200MSPS
0.13
ns
0.06
tSU
7.7
ns
PARALLEL CMOS MODE
tSTART
Input clock to data delay
Input clock rising edge crossover to start of data valid
tDV
Data valid time
Time interval of data valid
Output clock duty cycle
Duty cycle of output clock, CLKOUT
1MSPS ≤ Sampling frequency ≤ 150MSPS (7)
tRISE ,
tFALL
Data rise time,
Data fall time
tCLKRISE,
tCLKFALL
Output clock rise time
Output clock fall time
(1)
(2)
(3)
(4)
(5)
(6)
(7)
14
3.1
1.5
ns
3.6
ns
44
%
Rise time measured from 20% to 80% of DRVDD
Fall time measured from 80% to 20% of DRVDD
1 ≤ Sampling frequency ≤ 200MSPS
1
ns
Rise time measured from 20% to 80% of DRVDD
Fall time measured from 80% to 20% of DRVDD
1 ≤ Sampling frequency ≤ 150MSPS
1
ns
Timing parameters are ensured by design and characterization and not tested in production.
CLOAD is the effective external single-ended load capacitance between each output pin and ground
RLOAD is the differential load resistance between the LVDS output pair.
At higher frequencies, tPDI is greater than one clock period and overall latency = ADC latency + 1.
Measurements are done with a transmission line of 100Ω characteristic impedance between the device and the load. Setup and hold
time specifications take into account the effect of jitter on the output data and clock.
Data valid refers to a logic high of +100mV and a logic low of –100mV.
In CMOS mode, the output clock should be used only up to 150MSPS. See Figure 69 for a simple capture scheme above 150MSPS.
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Table 3. LVDS Timings at Lower Sampling Frequencies
SAMPLING
FREQUENCY
(MSPS)
MIN
TYP
185
1.1
170
1.3
150
125
(1)
SETUP TIME (ns)
tPDI, CLOCK PROPAGATION
DELAY (ns) (1)
HOLD TIME (ns)
MAX
MIN
TYP
1.7
0.35
1.9
0.35
1.7
2.3
2.3
3
MAX
MIN
TYP
MAX
0.6
5.1
6.4
7.7
0.6
5.1
6.4
7.7
0.35
0.6
5.1
6.4
7.7
0.35
0.6
5.1
6.4
7.7
At higher frequencies, tPDI is greater than one clock period and overall latency = ADC latency + 1.
Table 4. CMOS Timings at Lower Sampling Frequencies
TIMINGS SPECIFIED WITH RESPECT TO CLKOUT
SAMPLING
FREQUENCY
(MSPS)
tPDI, CLOCK PROPAGATION
DELAY (ns) (1)
HOLD TIME (ns)
MIN
TYP
MIN
TYP
MIN
TYP
MAX
1.2
2.6
2.1
2.8
5.5
7
8.5
125
2
3.2
2.8
3.5
5.5
7
8.5
105
2.8
4
3.5
4.2
5.5
7
8.5
80
4.3
5.5
5
5.7
5.5
7
8.5
150
(1)
SETUP TIME (ns)
MAX
MAX
At higher frequencies, tPDI is greater than one clock period and overall latency = ADC latency + 1.
N+3
N+2
N+1
Sample N
N+4
N + 18
N + 17
N + 16
Input Signal
tA
CLKP
Input Clock
CLKM
CLKOUTM
CLKOUTP
tPDI
tH
16 Clock Cycles
DDR LVDS
(1)
tSU
(2)
Output Data
(CHx_P, CHx_M)
O
E
O
O
E
N - 16
E
N - 15
O
E
N - 14
O
O
E
N - 13
E
N - 12
O
E
N-1
O
E
N
O
E
O
E
O
N+1
tPDI
CLKOUT
tSU
Parallel CMOS
16 Clock Cycles
Output Data
N - 16
N - 15
N - 14
(1)
N - 13
tH
N-1
N
N+1
(1) ADC latency after reset; at higher frequencies, tPDI is greater than one clock period and overall latency = ADC latency + 1.
(2) E = even bits (D0, D2, D4, etc.); O = odd bits (D1, D3, D5, etc.).
Figure 5. Latency Diagram
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CLKP
Input
Clock
CLKM
tPDI
CLKOUTP
Output
Clock
CLKOUTM
tSU
CHx_P
CHx_M
Output
Data Pair
tSU
tH
Dn
(1)
tH
Dn + 1
(1)
(1) Dn = bits D0, D2, D4, etc.
(2) Dn + 1 = bits D1, D3, D5, etc.
Figure 6. LVDS Mode Timing
CLKM
Input
Clock
CLKP
tPDI
Output
Clock
CLKOUT
tSU
Output
Data
CHx_Dn
tH
Dn
(1)
CLKM
Input
Clock
CLKP
tSTART
Output
Data
CHx_Dn
tDV
Dn
(1)
(1) Dn = bits D0, D1, D2, etc. of channels A and B.
Figure 7. CMOS Mode Timing
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DEVICE CONFIGURATION
The ADS58C28 can be configured independently using either parallel interface control or serial interface
programming.
PARALLEL CONFIGURATION ONLY
To put the device into parallel configuration mode, keep RESET tied high (AVDD). Then, use the SEN, SCLK,
CTRL1, CTRL2, and CTRL3 pins to directly control certain modes of the ADC. The device can be easily
configured by connecting the parallel pins to the correct voltage levels (as described in Table 5 to Table 8).
There is no need to apply a reset and SDATA can be connected to ground.
In this mode, SEN and SCLK function as parallel interface control pins. Some frequently-used functions can be
controlled using these pins. Table 5 describes the modes controlled by the parallel pins.
Table 5. Parallel Pin Definition
PIN
CONTROL MODE
SCLK
Low-speed mode selection
SEN
Output data format and output interface selection
CTRL1
CTRL2
Together, these pins control the SNRBoost3G and power-down modes.
CTRL3
SERIAL INTERFACE CONFIGURATION ONLY
To exercise this mode, the serial registers must first be reset to the default values and the RESET pin must be
kept low. SEN, SDATA, and SCLK function as serial interface pins in this mode and can be used to access the
internal registers of the ADC. The registers can be reset either by applying a pulse on the RESET pin or by
setting the RESET bit high. The Serial Register Map section describes the register programming and the register
reset process in more detail.
USING BOTH SERIAL INTERFACE AND PARALLEL CONTROLS
For increased flexibility, a combination of serial interface registers and parallel pin controls (CTRL1 to CTRL3)
can also be used to configure the device. To enable this flexibility, keep RESET low. The parallel interface
control pins CTRL1 to CTRL3 are available. After power-up, the device is automatically configured according to
the voltage settings on these pins (see Table 8). SEN, SDATA, and SCLK function as serial interface digital pins
and are used to access the internal registers of the ADC. The registers must first be reset to the default values
either by applying a pulse on the RESET pin or by setting the RESET bit to '1'. After reset, the RESET pin must
be kept low. The Serial Register Map section describes register programming and the register reset process in
more detail.
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DETAILS OF PARALLEL CONFIGURATION ONLY
The functions controlled by each parallel pin are described in Table 6, Table 7, and Table 8. A simple way of
configuring the parallel pins is shown in Figure 8.
Table 6. SCLK Control Pin
VOLTAGE APPLIED ON SCLK
DESCRIPTION
0V to 0.9V
Low-speed mode is disabled
0.9V to AVDD
Low-speed mode is enabled
Table 7. SEN Control Pin
VOLTAGE APPLIED ON SEN
DESCRIPTION
0
(+50mV/–0mV)
Twos complement and parallel CMOS output
(3/8) AVDD
(±50mV)
Offset binary and parallel CMOS output
(5/8) 2AVDD
(±50mV)
Offset binary and DDR LVDS output
AVDD
(+0mV/–50mV)
Twos complement and DDR LVDS output
Table 8. CTRL1, CTRL2, and CTRL3 Pins
CTRL1
CTRL2
CTRL3
DESCRIPTION
Low
Low
Low
Normal operation; SNRBoost3G disabled for both
channels
Low
Low
High
SNRBoost3G enabled for channel B
Low
High
Low
SNRBoost3G enabled for channel A
Low
High
High
SNRBoost3G enabled for channel A and B
High
Low
Low
Global power-down
High
Low
High
Channel A powered down, channel B is active
High
High
Low
Do not use
High
High
High
MUX mode of operation, channel A and B data are
multiplexed and output on the CHB_D[10:0] pins.
AVDD
(5/8) AVDD
3R
(5/8) AVDD
GND
AVDD
2R
(3/8) AVDD
3R
(3/8) AVDD
To Parallel Pin
Figure 8. Simple Scheme to Configure the Parallel Pins
18
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DETAILS OF SERIAL INTERFACE
The ADC has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial
interface enable), SCLK (serial interface clock), and SDATA (serial interface data) pins. Serial shift of bits into the
device is enabled when SEN is low. Serial data SDATA are latched at every SCLK falling edge when SEN is
active (low). The serial data are loaded into the register at every 16th SCLK falling edge when SEN is low. When
the word length exceeds a multiple of 16 bits, the excess bits are ignored. Data can be loaded in multiples of
16-bit words within a single active SEN pulse. The first eight bits form the register address and the remaining
eight bits are the register data. The interface can work with SCLK frequencies from 20MHz down to very low
speeds (of a few hertz) and also with non-50% SCLK duty cycle.
Register Initialization
After power-up, the internal registers must be initialized to the default values. This initialization can be
accomplished in one of two ways:
1. Either through hardware reset by applying a high pulse on the RESET pin (of width greater than 10ns), as
shown in Figure 9; or
2. By applying a software reset. When using the serial interface, set the RESET bit (D7 in register 00h) high.
This setting initializes the internal registers to the default values and then self-resets the RESET bit low. In
this case, the RESET pin is kept low.
Register Address
SDATA
A6
A7
A5
A4
A3
Register Data
A2
A1
A0
D7
D6
D5
tSCLK
D4
D3
D2
D1
D0
tDH
tDSU
SCLK
tSLOADS
tSLOADH
SEN
RESET
Figure 9. Serial Interface Timing
Table 9. Serial Interface Timing Characteristics (1)
PARAMETER
MIN
TYP
UNIT
20
MHz
SCLK frequency (equal to 1/tSCLK)
tSLOADS
SEN to SCLK setup time
25
ns
tSLOADH
SCLK to SEN hold time
25
ns
tDSU
SDATA setup time
25
ns
tDH
SDATA hold time
25
ns
(1)
> DC
MAX
fSCLK
Typical values at +25°C; minimum and maximum values across the full temperature range: TMIN = –40°C to TMAX = +85°C,
AVDD = 1.8V, and DRVDD = 1.8V, unless otherwise noted.
Serial Register Readout
The device includes a mode where the contents of the internal registers can be read back. This readback mode
may be useful as a diagnostic check to verify the serial interface communication between the external controller
and the ADC.
1. Set the READOUT register bit to '1'. This setting disables any further writes to the registers.
2. Initiate a serial interface cycle specifying the address of the register (A7 to A0) whose content has to be
read.
3. The device outputs the contents (D7 to D0) of the selected register on the SDOUT pin (pin 64).
4. The external controller can latch the contents at the SCLK falling edge.
5. To enable register writes, reset the READOUT register bit to '0'.
The serial register readout works with both CMOS and LVDS interfaces on pin 64.
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When READOUT is disabled, the SDOUT pin is in a high-impedance mode. If serial readout is not used, the
SDOUT pin must float.
Register Address A[7:0] = 00h
0
SDATA
0
0
0
0
Register Data D[7:0] = 01h
0
0
0
0
0
0
0
0
0
0
1
SCLK
SEN
The SDOUT pin is in a high-impedance state.
SDOUT
a) Enable serial readout (READOUT = 1)
Register Address A[7:0] = 45h
SDATA
A6
A7
A5
A4
A3
A2
Register Data D[7:0] = XX (don’t care)
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
1
0
0
SCLK
SEN
SDOUT
The SDOUT pin functions as serial readout (READOUT = 1).
b) Read contents of Register 45h. This register has been initialized with 04h (device is put into global power-down mode.)
(1) The SDOUT pin functions as a serial readout (READOUT = 1).
Figure 10. Serial Readout Timing Diagram
Table 10. Reset Timing (Only when Serial Interface is Used) (1)
PARAMETER
CONDITIONS
MIN
t1
Power-on delay
Delay from AVDD and DRVDD power-up to active RESET
pulse
t2
Reset pulse width
Active RESET signal pulse width
t3
Register write delay
Delay from RESET disable to SEN active
(1)
20
TYP
MAX
UNIT
1
ms
10
ns
1
100
µs
ns
Typical values at +25°C; minimum and maximum values across the full temperature range: TMIN = –40°C to TMAX = +85°C, unless
otherwise noted.
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Power Supply
AVDD, DRVDD
t1
RESET
t2
t3
SEN
NOTE: A high pulse on the RESET pin is required in the serial interface mode when initialized through a hardware reset. For parallel
interface operation, RESET must be permanently tied high.
Figure 11. Reset Timing Diagram
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SERIAL REGISTER MAP
Table 11 summarizes the functions supported by the serial interface.
Table 11. Serial Interface Register Map (1)
REGISTER
ADDRESS
REGISTER DATA
A[7:0] (Hex)
D7
D6
D5
D4
D3
D2
D1
D0
00
0
0
0
0
0
0
RESET
READOUT
0
0
0
0
0
0
0
0
01
03
LVDS SWING
25
CH A GAIN
0
28
0
CH A
SNRBoost3G
ON
0
29
0
0
0
0
0
DATA FORMAT
CH B GAIN
0
0
0
0
0
0
0
CH B TEST PATTERNS
CH B SNRBoost3G FILTER NUMBER
2D
0
2E
0
CH B
SNRBoost3G
ON
0
0
0
0
0
0
3D
0
0
ENABLE
OFFSET
CORR
0
0
0
0
0
3F
0
0
40
CUSTOM PATTERN D[10:5]
CUSTOM PATTERN D[4:0]
41
LVDS CMOS
CMOS CLKOUT STRENGTH
0
0
0
0
0
0
0
0
0
0
42
0
0
0
0
DIGITAL
MODE 1
44
0
0
0
0
0
0
0
DIGITAL
MODE 2
45
STBY
LVDS
CLKOUT
STRENGTH
LVDS DATA
STRENGTH
0
0
PDN GLOBAL
0
0
4A
0
0
0
0
0
0
0
HIGH FREQ
MODE CH B
58
0
0
0
0
0
0
0
HIGH FREQ
MODE CH A
BF
CH A OFFSET PEDESTAL
0
0
0
0
0
C1
CH B OFFSET PEDESTAL
0
0
0
0
0
0
0
CF
FREEZE
OFFSET
CORR
0
DB
0
0
0
0
0
0
0
LOW SPEED
MODE CH B
EA
OVERRIDE
SNRBoost3G
PINS
0
0
0
0
0
0
0
EF
0
0
0
EN LOW
SPEED MODE
0
0
0
0
F1
0
0
0
0
0
0
EN LVDS SWING
0
LOW SPEED
MODE CH A
0
0
F2
22
CH A TEST PATTERNS
CH A SNRBoost3G FILTER NUMBER
26
2B
(1)
0
HIGH PERF MODE
0
0
OFFSET CORR TIME CONSTANT
0
0
All registers default to '0' after reset.
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DESCRIPTION OF SERIAL REGISTERS
Register Address 00h (Default = 00h)
7
6
5
4
3
2
1
0
0
0
0
0
0
0
RESET
READOUT
Bits[7:2]
Always write '0'
Bit 1
RESET: Software reset applied
This bit resets all internal registers to the default values and self-clears to 0 (default = 1).
Bit 0
READOUT: Serial readout
This bit sets the serial readout of the registers.
0 = Serial readout of registers disabled; the SDOUT pin is placed in a high-impedance state.
1 = Serial readout enabled; the SDOUT pin functions as a serial data readout with CMOS logic
levels running from the DRVDD supply. See the Serial Register Readout section.
Register Address 01h (Default = 00h)
7
6
5
4
3
2
LVDS SWING
Bits[7:2]
1
0
0
0
LVDS SWING: LVDS swing programmability
These bits program the LVDS swing. Set the EN LVDS SWING bit to '1' before programming
swing.
000000 = Default LVDS swing; ±350mV with external 100Ω termination
011011 = LVDS swing increases to ±410mV
110010 = LVDS swing increases to ±465mV
010100 = LVDS swing increases to ±570mV
111110 = LVDS swing increases to ±200mV
001111 = LVDS swing increases to ±125mV
Bits[1:0]
Always write '0'
Register Address 03h (Default = 00h)
7
6
5
4
3
2
1
0
0
0
0
0
0
HIGH PERF MODE
Bits[7:2]
Always write '0'
Bits[1:0]
HIGH PERF MODE: High-performance mode
0
These bits enable LVDS swing control using the LVDS SWING register bits.
00 = Default performance
01 = Do not use
10 = Do not use
11 = Obtain best performance across sample clock and input signal frequencies
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Register Address 25h (Default = 00h)
7
6
5
4
3
CH A GAIN
Bits[7:4]
2
0
1
0
CH A TEST PATTERNS
CH A GAIN: Channel A gain programmability
These bits set the gain programmability in 0.5dB steps for channel A.
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
=
=
=
=
=
=
=
=
=
=
=
=
=
0dB gain (default after reset)
0.5dB gain
1dB gain
1.5dB gain
2dB gain
2.5dB gain
3dB gain
3.5dB gain
4dB gain
4.5dB gain
5dB gain
5.5dB gain
6dB gain
Bit 3
Always write '0'
Bits[2:0]
CH A TEST PATTERNS: Channel A data capture
These bits verify data capture for channel A; see Table 12.
000 = Normal operation
001 = Outputs all 0s
010 = Outputs all 1s
011 = Outputs toggle pattern; D[10:0] output data are an alternating sequence of 10101010101 and
01010101010
100 = Outputs digital ramp; output data increments by 1LSB (11 bits) every eighth clock cycle from
code 0 to code 2047
101 = Outputs custom pattern; use registers 3Fh and 40h to set the custom pattern
110 = Unused
111 = Unused
Register Address 26h (Default = 00h)
7
6
5
4
3
2
1
0
CH A SNRBoost3G FILTER NUMBER
0
Bit 7
Always write '0'
Bits[6:0]
CH A SNRBoost3G FILTER NUMBER: Channel A SNRBoost3G filter selection
These bits select any one of 55 SNRBoost3G filters for channel A only after selecting the
appropriate mode from Table 12; refer to the SNR Enhancement Using SNRBoost section.
Register Address 28h (Default = 00h)
7
6
5
4
3
2
1
0
0
CH A SNRBoost3G ON
0
0
0
0
0
0
Bit 7
Always write '0'
Bit 6
CH A SNRBoost3G ON: Channel A SNRBoost3G setting
This bit sets the SNRBoost3G for channel A
0 = SNRBoost3G for channel A is off
1 = SNRBoost3G for channel A is on
Bits[5:0]
24
Always write '0'
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Register Address 29h (Default = 00h)
7
6
5
0
0
0
4
3
DATA FORMAT
Bits[7:5]
Always write '0'
Bits[4:3]
DATA FORMAT: Data format selection
00
01
10
11
Bits[2:0]
=
=
=
=
2
1
0
0
0
0
2
1
0
Twos complement
Twos complement
Twos complement
Offset binary
Always write '0'
Register Address 2Bh (Default = 00h)
7
6
5
4
CH B GAIN
Bits[7:4]
3
0
CH B TEST PATTERNS
CH B GAIN: Channel B gain programmability
These bits set the gain programmability in 0.5dB steps for channel B.
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
=
=
=
=
=
=
=
=
=
=
=
=
=
0dB gain (default after reset)
0.5dB gain
1dB gain
1.5dB gain
2dB gain
2.5dB gain
3dB gain
3.5dB gain
4dB gain
4.5dB gain
5dB gain
5.5dB gain
6dB gain
Bit 3
Always write '0'
Bits[2:0]
CH B TEST PATTERNS: Channel B data capture
These bits verify data capture for channel B; see Table 12.
000 = Normal operation
001 = Outputs all 0s
010 = Outputs all 1s
011 = Outputs toggle pattern; D[10:0] output data are an alternating sequence of 10101010101 and
01010101010
100 = Outputs digital ramp; output data increments by 1LSB (11 bits) every eighth clock cycle from
code 0 to code 2047
101 = Outputs custom pattern; use registers 3Fh and 40h to set the custom pattern
110 = Unused
111 = Unused
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Register Address 2Dh (Default = 00h)
7
6
5
4
3
2
1
0
CH B SNRBoost3G FILTER NUMBER
0
Bit 7
Always write '0'
Bits[6:0]
CH B SNRBoost3G FILTER NUMBER: Channel B SNRBoost3G filter selection
These bits select any one of 55 SNRBoost3G filters for channel B only after selecting the
appropriate mode from Table 12; refer to the SNR Enhancement Using SNRBoost section.
Register Address 2Eh (Default = 00h)
7
6
5
4
3
2
1
0
0
CH B SNRBoost3G ON
0
0
0
0
0
0
Bit 7
Always write '0'
Bit 6
CH B SNRBoost3G ON: Channel B SNRBoost3G setting
This bit sets the SNRBoost3G for channel B
0 = SNRBoost3G for channel B is off
1 = SNRBoost3G for channel B is on
Bits[5:0]
Always write '0'
Register Address 3Dh (Default = 00h)
7
6
5
4
3
2
1
0
0
0
ENABLE OFFSET CORR
0
0
0
0
0
Bits[7:6]
Always write '0'
Bit 5
ENABLE OFFSET CORR: Offset correction setting
This bit sets the offset correction; see Table 12.
0 = Offset correction disabled
1 = Offset correction enabled
Bits[4:0]
Always write '0'
Register Address 3Fh (Default = 00h)
7
0
6
5
4
3
2
1
0
0
CUSTOM
PATTERN D10
CUSTOM
PATTERN D9
CUSTOM
PATTERN D8
CUSTOM
PATTERN D7
CUSTOM
PATTERN D6
CUSTOM
PATTERN D5
Bits[7:6]
Always write '0'
Bits[7:0]
CUSTOM PATTERN D[10:5]
These are the six custom pattern upper bits available at output instead of ADC data.
Register Address 40h (Default = 00h)
7
6
5
4
3
2
1
0
CUSTOM
PATTERN D4
CUSTOM
PATTERN D3
CUSTOM
PATTERN D2
CUSTOM
PATTERN D1
CUSTOM
PATTERN D0
0
0
0
Bits[7:3]
CUSTOM PATTERN D[4:0]
These are the five lower custom pattern bits available at output instead of ADC data.
Bits[2:0]
26
Always write '0'
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Register Address 41h (Default = 00h)
7
6
5
LVDS CMOS
Bits[7:6]
4
CMOS CLKOUT STRENGTH
3
2
1
0
0
0
0
0
LVDS CMOS: Interface selection
These bits select the interface.
00 = DDR LVDS interface
01 = Parallel CMOS interface
10 = Parallel CMOS interface
11 = Parallel CMOS interface
Bits[5:4]
CMOS CLKOUT STRENGTH
These bits control the strength of the CMOS output clock.
00 = Maximum strength (recommended)
01 = Medium strength
10 = Low strength
11 = Very low strength
Bits[3:0]
Always write '0'
Register Address 42h (Default = 00h)
7
6
5
4
3
2
1
0
0
0
0
0
DIGITAL MODE 1
0
0
0
Bits[7:4]
Always write '0'
Bit 3
DIGITAL MODE 1
See Table 12.
Bits[2:0]
Always write '0'
Register Address 44h (Default = 00h)
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
DIGITAL MODE 2
Bits[7:1]
Always write '0'
Bit 0
DIGITAL MODE 2
Refer to the Digital Functions section.
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Register Address 45h (Default = 00h)
7
6
5
4
3
2
1
0
STBY
LVDS CLKOUT
STRENGTH
LVDS DATA
STRENGTH
0
0
PDN GLOBAL
0
0
Bit 7
STBY: Standby setting
0 = Normal operation
1 = Both channels are put in standby; wakeup time from this mode is fast (typically 50µs).
Bit 6
LVDS CLKOUT STRENGTH: LVDS output clock buffer strength setting
0 = LVDS output clock buffer at default strength to be used with 100Ω external termination
1 = LVDS output clock buffer has double strength to be used with 50Ω external termination
Bit 5
LVDS DATA STRENGTH
0 = All LVDS data buffers at default strength to be used with 100Ω external termination
1 = All LVDS data buffers have double strength to be used with 50Ω external termination
Bits[4:3]
Always write '0'
Bit 2
PDN GLOBAL
0 = Normal operation
1 = Total power down; all ADC channels, internal references, and output buffers are powered
down. Wakeup time from this mode is slow (typically 100µs).
Bits[1:0]
Always write '0'
Register Address 4Ah (Default = 00h)
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
HIGH FREQ MODE CH B
Bits[7:1]
Always write '0'
Bit 0
HIGH FREQ MODE CH B: Channel B high-frequency mode selection
This bit configures the high-frequency mode for channel B. This bit is recommended for high input
signal frequencies greater than 200MHz.
0 = Default performance after reset
1 = Set this bit for each channel for high input frequencies
Register Address 58h (Default = 00h)
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
HIGH FREQ MODE CH A
Bits[7:1]
Always write '0'
Bit 0
HIGH FREQ MODE CH A: Channel A high-frequency mode selection
This bit configures the high-frequency mode for channel A. This bit is recommended for high input
signal frequencies greater than 200MHz.
0 = Default performance after reset
1 = Set this bit for each channel for high input frequencies
28
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Register Address BFh (Default = 00h)
7
6
5
CH A OFFSET PEDESTAL
Bits[7:5]
4
3
2
1
0
0
0
0
0
0
CH A OFFSET PEDESTAL: Channel A offset pedestal selection
When the offset correction is enabled, the final converged value after the offset is corrected is the
ADC midcode value. A pedestal can be added to the final converged value by programming these
bits. See the Offset Correction section. Channels can be independently programmed for different
offset pedestals by choosing the relevant register address.
100
011
010
001
000
111
110
101
Bits[4:0]
=
=
=
=
=
=
=
=
Pedestal
Pedestal
Pedestal
Pedestal
Pedestal
Pedestal
Pedestal
Pedestal
is 4LSB
is 3LSB
is 2LSB
is 1LSB
is 0LSB
is –1LSB
is –2LSB
is –3LSB
Always write '0'
Register Address C1h (Default = 00h)
7
6
5
CH B OFFSET PEDESTAL
Bits[7:5]
4
3
2
1
0
0
0
0
0
0
CH B OFFSET PEDESTAL: Channel B offset pedestal selection
When the offset correction is enabled, the final converged value after the offset is corrected is the
ADC midcode value. A pedestal can be added to the final converged value by programming these
bits. See the Offset Correction section. Channels can be independently programmed for different
offset pedestals by choosing the relevant register address.
100
011
010
001
000
111
110
101
Bits[4:0]
=
=
=
=
=
=
=
=
Pedestal
Pedestal
Pedestal
Pedestal
Pedestal
Pedestal
Pedestal
Pedestal
is 4LSB
is 3LSB
is 2LSB
is 1LSB
is 0LSB
is –1LSB
is –2LSB
is –3LSB
Always write '0'
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Register Address CFh (Default = 00h)
7
6
FREEZE OFFSET CORR
0
Bit 7
5
4
3
2
OFFSET CORR TIME CONSTANT
1
0
0
0
FREEZE OFFSET CORR: Freeze offset correction setting
This bit sets the freeze offset correction estimation.
0 = Estimation of offset correction is not frozen (the EN OFFSET CORR bit must be set)
1 = Estimation of offset correction is frozen (the EN OFFSET CORR bit must be set); when frozen,
the last estimated value is used for offset correction of every clock cycle. See the Offset Correction
section.
Bit 6
Always write '0'
Bits[5:2]
OFFSET CORR TIME CONSTANT
The offset correction loop time constant in number of clock cycles. Refer to the Offset Correction
section.
Bits[1:0]
Always write '0'
Register Address DBh (Default = 00h)
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
LOW SPEED MODE CH B
Bits[7:1]
Always write '0'
Bit 0
LOW SPEED MODE CH B: Channel B low-speed mode enable
This bit enables the low-speed mode for channel B. Set the EN LOW SPEED MODE bit to '1'
before using this bit.
0 = Low-speed mode is disabled for channel B
1 = Low-speed mode is enabled for channel B
Register Address EAh (Default = 00h)
7
6
5
4
3
2
1
0
OVERRIDE SNRBoost3G PINS
0
0
0
0
0
0
0
OVERRIDE SNRBoost3G PINS
Bit 7
Refer to the SNR Enhancement Using SNRBoost section.
Bits[6:0]
Always write '0'
Register Address EFh (Default = 00h)
7
6
5
4
3
2
1
0
0
0
0
EN LOW SPEED MODE
0
0
0
0
Bits[7:5]
Always write '0'
Bit 4
EN LOW SPEED MODE: Enable control of low-speed mode through serial register bits
This bit enables the control of the low-speed mode using the ENABLE LOW SPEED MODE CH B
and ENABLE LOW SPEED MODE CH A register bits.
0 = Low-speed mode is controlled by dc voltage on the SCLK pin
1 = Low-speed mode is controlled by serial register bits
Bits[3:0]
30
Always write '0'
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Register Address F1h (Default = 00h)
7
6
5
4
3
2
1
0
0
0
0
0
0
EN LVDS SWING
Bits[7:2]
Always write '0'
Bits[1:0]
EN LVDS SWING: LVDS swing enable
0
These bits enable LVDS swing control using the LVDS SWING register bits.
00 = LVDS swing control using the LVDS SWING register bits is disabled
01 = Do not use
10 = Do not use
11 = LVDS swing control using the LVDS SWING register bits is enabled
Register Address F2h (Default = 00h)
7
6
5
4
3
2
1
0
0
0
0
0
LOW SPEED MODE CH A
0
0
0
Bits[7:4]
Always write '0'
Bit 3
LOW SPEED MODE CH A: Channel A low-speed mode enable
This bit enables the low-speed mode for channel A. Set the EN LOW SPEED MODE bit to '1'
before using this bit.
0 = Low-speed mode is disabled for channel A
1 = Low-speed mode is enabled for channel A
Bits[2:0]
Always write '0'
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TYPICAL CHARACTERISTICS
All graphs are at +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock. 1.5VPP
differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, High Perf Mode disabled, 0dB gain, DDR
LVDS output interface, and 32k point FFT, unless otherwise noted.
FFT FOR 20MHz INPUT SIGNAL
FFT FOR 170MHz INPUT SIGNAL
0
0
SFDR = 84dBc
SNR = 66.9dBFS
SINAD = 66.8dBFS
THD = 82dBc
−10
−20
−30
−30
−40
−40
Amplitude (dB)
Amplitude (dB)
−20
−50
−60
−70
−50
−60
−70
−80
−80
−90
−90
−100
−100
−110
−110
−120
0
10
20
30
40
50
60
70
80
90
SFDR = 80.5dBc
SNR = 65.8dBFS
SINAD = 65.6dBFS
THD = 78.7dBc
−10
−120
100
0
10
20
30
40
50
60
Frequency (MHz)
Frequency (MHz)
Figure 12.
Figure 13.
70
80
90
100
FFT FOR 270MHz INPUT SIGNAL
0
SFDR = 73.1dBc
SNR = 65.9dBFS
SINAD = 65.1dBFS
THD = −72dBc
−10
−20
−30
Amplitude (dB)
−40
−50
−60
−70
−80
−90
−100
−110
−120
0
10
20
30
40
50
60
70
80
90
100
Frequency (MHz)
Figure 14.
32
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TYPICAL CHARACTERISTICS (continued)
All graphs are at +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock. 1.5VPP
differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, High Perf Mode disabled, 0dB gain, DDR
LVDS output interface, and 32k point FFT, unless otherwise noted.
FFT FOR TWO-TONE INPUT SIGNAL
FFT FOR TWO-TONE INPUT SIGNAL
0
0
Each Tone at −7dBFS Amplitude
fIN1 = 185.1MHz
fIN2 = 190.1MHz
Two-Tone IMD = 86.5dBFS
SFDR = 92dBFS
−10
−20
−30
−20
−30
−40
Amplitude (dB)
Amplitude (dB)
−40
−50
−60
−70
−60
−70
−80
−90
−90
−100
−100
−110
−110
0
10
20
30
40
50
60
70
80
90
−120
100
10
20
30
40
50
60
70
80
Frequency (MHz)
Figure 15.
Figure 16.
FFT WITH SNRBoost3G ENABLED
(60MHz Bandwidth)
FFT WITH SNRBoost3G ENABLED
(60MHz Bandwidth)
90
100
0
AIN = −36dBFS
fIN = 140MHz
fS = 185MSPS
Over 60MHz BW
17M to 77M
SNR = 75.3dBFS
SINAD = 75.3dBFS
SFDR = 58.2dBc
SNRBoost Filter #40
−20
−30
−40
−50
−20
−30
−40
−60
−70
−50
−60
−70
−80
−80
−90
−90
−100
−100
−110
−110
0
10
20
30
40
50
60
70
80
AIN = −2dBFS
fIN = 140MHz
fS = 185MSPS
Over 60MHz BW
17M to 77M
SNR = 72.2dBFS
SINAD = 72dBFS
SFDR = 88.4dBc
SNRBoost Filter #40
−10
Amplitude (dB)
−10
−120
0
Frequency (MHz)
0
Amplitude (dB)
−50
−80
−120
Each Tone at −36dBFS
fIN1 = 185.1MHz
fIN2 = 190.1MHz
Two-Tone IMD = 93.2dBFS
SFDR = 102.5dBFS
−10
90
−120
0
10
20
30
40
50
Frequency (MHz)
Frequency (MHz)
Figure 17.
Figure 18.
60
70
80
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TYPICAL CHARACTERISTICS (continued)
All graphs are at +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock. 1.5VPP
differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, High Perf Mode disabled, 0dB gain, DDR
LVDS output interface, and 32k point FFT, unless otherwise noted.
FFT WITH SNRBoost3G ENABLED
(40MHz Bandwidth)
FFT WITH SNRBoost3G ENABLED
(40MHz Bandwidth)
0
0
AIN = −36dBFS
fIN = 140MHz
fS = 185MSPS
Over 40MHz BW
26M to 66M
SNR = 77.6dBFS
SINAD = 81.5dBFS
SFDR = 57.6dBc
SNRBoost Filter #30
−20
−30
Amplitude (dB)
−40
−50
−20
−30
−40
−60
−70
−70
−90
−90
−100
−100
−110
−110
0
10
20
30
40
50
60
70
80
−120
90
10
20
30
40
50
60
70
Frequency (MHz)
Figure 19.
Figure 20.
FFT WITH SNRBoost3G ENABLED
(30MHz Bandwidth)
FFT WITH SNRBoost3G ENABLED
(30MHz Bandwidth)
80
90
0
AIN = −36dBFS
fIN = 140MHz
fS = 185MSPS
Over 30MHz BW
32M to 62M
SNR = 77.2dBFS
SINAD = 77.2dBFS
SFDR = 57.9dBc
SNRBoost Filter #24
−30
−40
−50
−20
−30
−40
−60
−70
−50
−60
−70
−80
−80
−90
−90
−100
−100
−110
−110
0
10
20
30
40
50
60
70
80
AIN = −2dBFS
fIN = 140MHz
fS = 185MSPS
Over 30MHz BW
32M to 62M
SNR = 74.1dBFS
SINAD = 74dBFS
SFDR = 88.5dBc
SNRBoost Filter #24
−10
Amplitude (dB)
−20
−120
0
Frequency (MHz)
−10
Amplitude (dB)
−60
−80
0
34
−50
−80
−120
AIN = −2dBFS
fIN = 140MHz
fS = 185MSPS
Over 40MHz BW
26M to 66M
SNR = 74dBFS
SINAD = 73.8dBFS
SFDR = 93.6dBc
SNRBoost Filter #30
−10
Amplitude (dB)
−10
90
−120
0
10
20
30
40
50
Frequency (MHz)
Frequency (MHz)
Figure 21.
Figure 22.
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70
80
90
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TYPICAL CHARACTERISTICS (continued)
All graphs are at +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock. 1.5VPP
differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, High Perf Mode disabled, 0dB gain, DDR
LVDS output interface, and 32k point FFT, unless otherwise noted.
FFT WITH SNRBoost3G ENABLED
(20MHz Bandwidth)
FFT WITH SNRBoost3G ENABLED
(20MHz Bandwidth)
0
0
AIN = −36dBFS
fIN = 140MHz
fS = 185MSPS
Over 20MHz BW
36M to 56M
SNR = 80.5dBFS
SINAD = 80.2dBFS
SFDR = 81.3dBc
SNRBoost Filter #14
−20
−30
Amplitude (dB)
−40
−50
−20
−30
−40
−60
−70
−50
−60
−70
−80
−80
−90
−90
−100
−100
−110
−110
−120
0
10
20
30
40
50
60
70
80
AIN = −2dBFS
fIN = 140MHz
fS = 185MSPS
Over 20MHz BW
36M to 56M
SNR = 75.9dBFS
SINAD = 75.7dBFS
SFDR = 87.9dBc
SNRBoost Filter #14
−10
Amplitude (dB)
−10
−120
90
0
20
30
40
50
60
70
80
90
Frequency (MHz)
Figure 23.
Figure 24.
TIME DOMAIN WAVEFORM OF UNWRAP SIGNAL
DISABLED
TIME DOMAIN WAVEFORM OF UNWRAP SIGNAL
ENABLED
2048
2048
Fs = 185MSPS
Fin = 150MHz
Fs = 185MSPS
Fin = 150MHz
1792
1792
1536
1536
Output Code (LSB)
Output Code (LSB)
10
Frequency (MHz)
1280
1024
768
1280
1024
768
512
512
256
256
0
0
4000
8000 12000 16000 20000 24000 28000 32000
0
0
4000
8000 12000 16000 20000 24000 28000 32000
Sample Number
Sample Number
Figure 25.
Figure 26.
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TYPICAL CHARACTERISTICS (continued)
All graphs are at +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock. 1.5VPP
differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, High Perf Mode disabled, 0dB gain, DDR
LVDS output interface, and 32k point FFT, unless otherwise noted.
SFDR vs INPUT FREQUENCY
SNR vs INPUT FREQUENCY
67
95
Gain 0dB
Gain 6dB
Gain 0dB
Gain 6dB
90
66
85
SNR (dBFS)
SFDR (dBc)
80
75
70
65
64
65
63
60
55
0
50
100
150
200
250
300
350
400
450
62
500
0
50
100
150
Input Frequency (MHz)
200
250
300
350
400
450
500
Input Frequency (MHz)
Figure 27.
Figure 28.
SFDR ACROSS GAIN AND INPUT FREQUENCY
SINAD ACROSS GAIN AND INPUT FREQUENCY
68
92
88
66
84
SINAD (dBFS)
SFDR (dBc)
80
76
72
68
170MHz
220MHz
300MHz
400MHz
500MHz
64
60
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
64
62
170MHz
220MHz
300MHz
400MHz
500MHz
60
6
58
0
0.5
Gain (dB)
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
Gain (dB)
Figure 29.
36
1
Figure 30.
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TYPICAL CHARACTERISTICS (continued)
All graphs are at +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock. 1.5VPP
differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, High Perf Mode disabled, 0dB gain, DDR
LVDS output interface, and 32k point FFT, unless otherwise noted.
PERFORMANCE ACROSS INPUT AMPLITUDE
WITH SNRBoost3G ENABLED
69
110
80
120
In−Band SFDR (dBc)
In−Band SFDR (dBFS)
In−Band SNR
68
110
90
67
100
78
80
66
90
77
70
65
80
76
60
64
70
75
50
63
60
74
40
62
50
73
61
40
60
30
−55 −50 −45 −40 −35 −30 −25 −20 −15 −10
SFDR (dBc)
SFDR (dBFS)
SNR
20
−55 −50 −45 −40 −35 −30 −25 −20 −15 −10
−5
0
72
Input Frequency = 40MHz
60M Bandwidth
Amplitude (dBFS)
−5
0
71
Amplitude (dBFS)
Figure 31.
Figure 32.
PERFORMANCE ACROSS INPUT AMPLITUDE
WITH SNRBoost3G DISABLED
PERFORMANCE ACROSS INPUT AMPLITUDE
WITH SNRBoost3G ENABLED
69
110
79
120
Input Frequency = 150MHz
In−Band SFDR (dBc)
In−Band SFDR (dBFS)
In−Band SNR
68
110
90
67
100
77
80
66
90
76
70
65
80
75
60
64
70
74
50
63
60
73
40
62
50
72
61
40
60
30
−55 −50 −45 −40 −35 −30 −25 −20 −15 −10
SFDR (dBc)
SFDR (dBFS)
SNR
30
20
−55 −50 −45 −40 −35 −30 −25 −20 −15 −10
−5
0
SFDR (dBc,dBFS)
100
SNR (dBFS)
SFDR (dBc,dBFS)
79
78
71
Input Frequency =150MHz
60M Bandwidth
−5
SNR (dBFS)
30
SFDR (dBc,dBFS)
100
SNR (dBFS)
SFDR (dBc,dBFS)
Input Frequency = 40MHz
SNR (dBFS)
PERFORMANCE ACROSS INPUT AMPLITUDE
WITH SNRBoost3G DISABLED
0
70
Amplitude (dBFS)
Amplitude (dBFS)
Figure 33.
Figure 34.
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TYPICAL CHARACTERISTICS (continued)
All graphs are at +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock. 1.5VPP
differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, High Perf Mode disabled, 0dB gain, DDR
LVDS output interface, and 32k point FFT, unless otherwise noted.
SFDR
SNR
66.8
90
SFDR
SNR
88
67.2
86
66.6
87
67.1
84
66.5
86
67
82
66.4
85
66.9
80
66.3
84
66.8
78
66.2
83
66.7
76
66.1
82
66.6
74
66
66.5
72
81
SFDR (dBc)
88
SNR (dBFS)
67.3
89
SFDR (dBc)
PERFORMANCE vs INPUT COMMON-MODE VOLTAGE
67.4
66.7
65.9
Input Frequency = 40MHz
80
0.8
0.85
0.9
0.95
1
Input Frequency = 150MHz
66.4
1.1
1.05
SNR (dBFS)
PERFORMANCE vs INPUT COMMON-MODE VOLTAGE
90
70
0.8
0.85
0.9
0.95
1
65.8
1.1
1.05
Input Common-Mode Voltage (V)
Input Common-Mode Voltage (V)
Figure 35.
Figure 36.
SFDR ACROSS TEMPERATURE vs AVDD SUPPLY
SNR ACROSS TEMPERATURE vs AVDD SUPPLY
92
67
90
66.7
88
66.4
86
66.1
SNR (dBFS)
SFDR (dBc)
84
82
80
65.8
65.5
65.2
78
76
74
72
70
−40
AVDD = 1.65
AVDD = 1.7
AVDD = 1.75
AVDD = 1.8
AVDD = 1.85
AVDD = 1.9
AVDD = 1.95
−15
64.9
64.6
64.3
Input Frequency = 150MHz
10
35
60
85
64
−40
Temperature (°C)
−15
Input Frequency = 150MHz
10
35
60
85
Temperature (°C)
Figure 37.
38
AVDD = 1.65
AVDD = 1.7
AVDD = 1.75
AVDD = 1.8
AVDD = 1.85
AVDD = 1.9
AVDD = 1.95
Figure 38.
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TYPICAL CHARACTERISTICS (continued)
All graphs are at +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock. 1.5VPP
differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, High Perf Mode disabled, 0dB gain, DDR
LVDS output interface, and 32k point FFT, unless otherwise noted.
PERFORMANCE ACROSS INPUT CLOCK AMPLITUDE
69
68.5
86
68
85
67.5
84
67
83
66.5
82
66
81
65.5
SFDR (dBc)
87
SNR (dBFS)
72
90
71
88
70
86
69
84
68
82
67
80
66
78
65
76
64
74
80
1.65
1.70
1.75
1.80
1.85
1.90
65
1.95
72
63
SFDR
SNR
Input Frequency = 150MHz
0
0.3
Input Frequency = 40MHz
0.6
DRVDD Supply (V)
0.9
1.5
1.8
2.1
62
2.4
Differential Clock Amplitude (VPP)
Figure 39.
Figure 40.
PERFORMANCE ACROSS INPUT CLOCK AMPLITUDE
PERFORMANCE ACROSS INPUT CLOCK DUTY CYCLE
70
90
SFDR
SNR
88
1.2
THD
SNR
69
86
68
84
67
82
66
80
65
78
64
76
63
74
62
72
61
68
82
67.5
81.5
67
66.5
THD (dBc)
80.5
SNR (dBFS)
SFDR (dBc)
81
66
80
65.5
79.5
65
79
64.5
78.5
Input Frequency = 150MHz
70
0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
60
2.4
SNR (dBFS)
SFDR (dBc)
SNR
SFDR
92
SNR (dBFS)
PERFORMANCE ACROSS DRVDD SUPPLY VOLTAGE
88
Input Frequency = 10MHz
78
25
30
35
40
45
50
55
60
65
70
75
64
Input Clock Duty Cycle (%)
Differential Clock Amplitude (VPP)
Figure 41.
Figure 42.
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TYPICAL CHARACTERISTICS (continued)
All graphs are at +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock. 1.5VPP
differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, High Perf Mode disabled, 0dB gain, DDR
LVDS output interface, and 32k point FFT, unless otherwise noted.
ANALOG POWER vs SAMPLING FREQUENCY
DIGITAL POWER vs SAMPLING FREQUENCY
270
550
AVDD = 1.8V
Input Frequency = 2.5MHz
250
230
450
400
DRVDD Power (mW)
Analog Power (mW)
210
190
170
150
130
350
300
250
200
110
90
150
70
100
50
Default
Digital Mode Enabled
20M/30M BW SNRBoost Enabled
40M BW SNRBoost Enabled
60M BW SNRBoost Enabled
500
0
25
50
75
100
125
150
175
50
200
0
25
50
Sampling Speed (MSPS)
75
CMRR OVER FREQUENCY
-20
−20
-40
Amplitude (dBFS)
CMRR (dB)
−10
−30
fIN (40MHz)
-60
−40
-80
−50
-100
150
200
250
300
fIN - fCM
(30MHz)
fCM
(10MHz)
fIN + fCM (30MHz)
-120
0
Frequency of Input Common−Mode Signal (MHz)
Figure 45.
40
200
fIN = 40MHz
fCM = 10MHz, 50mVPP
SFDR = 79.36dBFS
Amplitude (fCM) = -91dBFS
Amplitude (fIN + fCM) = -87.2dBFS
Amplitude (fIN - fCM) = -91dBFS
Input Frequency = 40MHz
50mVPP Signal Superimposed
on Input Common−Mode Voltage 0.95V
100
175
CMRR SPECTRUM
0
50
150
Figure 44.
0
0
125
Sampling Speed (MSPS)
Figure 43.
−60
100
10
20
30
40
50
60
70
80
90
100
Frequency (MHz)
Figure 46.
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TYPICAL CHARACTERISTICS (continued)
All graphs are at +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock. 1.5VPP
differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, High Perf Mode disabled, 0dB gain, DDR
LVDS output interface, and 32k point FFT, unless otherwise noted.
PSRR OVER FREQUENCY
ZOOMED VIEW OF PSRR SPECTRUM
0
0
fIN = 40MHz
fPSRR = 1MHz, 50mVPP
Amplitude (fIN) = -1dBFS
Amplitude (fPSRR) = -90.36dBFS
Amplitude (fIN + fP) = -57.26dBFS
Amplitude (fIN - fP) = -57.74dBFS
Input Frequency = 40MHz
50mVpp Signal
Superimposed on AVDD
−10
-20
−20
fIN + fPSRR
(41MHz)
-40
Amplitude (dB)
PSRR (dB)
−30
−40
−50
fIN (40MHz)
-60
fIN - fPSRR (39MHz)
-80
fPSRR (1MHz)
−60
-100
−70
−80
0
25
50
-120
75 100 125 150 175 200 225 250 275 300
0
10
5
15
Frequency of Signal on Supply (MHz)
20
25
30
35
40
45
50
Frequency (MHz)
Figure 47.
Figure 48.
CROSSTALK
120
Full−Scale Signal Applied on Aggressor Channel
−1dBFS, 20MHz Signal Applied on the Victim Channel
110
Crosstalk (dB)
100
90
80
70
60
50
0
50
100
150
200
250
300
Frequency of Aggressor Channel (MHz)
Figure 49.
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TYPICAL CHARACTERISTICS: Contour
All graphs are at +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock. 1.5VPP
differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, High Perf Mode disabled, 0dB gain, DDR
LVDS output interface, and 32k point FFT, unless otherwise noted.
SPURIOUS-FREE DYNAMIC RANGE (0dB Gain)
200
85
81
85
77
Sampling Frequency (MSPS)
180
68
73
81
160
85
85
140
89
77
68
73
120
89
85
100
85
81
85
80
73
89
68
77
65
10
50
100
150
200
250
300
350
400
450
500
Input Frequency (MHz)
65
70
75
80
85
90
SFDR (dBc)
Figure 50.
SPURIOUS-FREE DYNAMIC RANGE (6dB Gain)
200
86
82
82
180
Sampling Frequency (MSPS)
74
78
82
86
160
78
86
74
140
82
86
120
86
74
100
78
86
80
82
86
65
10
50
100
70
150
75
200
250
300
Input Frequency (MHz)
80
350
400
85
450
500
90
SFDR (dBc)
Figure 51.
42
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TYPICAL CHARACTERISTICS: Contour (continued)
All graphs are at +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock. 1.5VPP
differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, High Perf Mode disabled, 0dB gain, DDR
LVDS output interface, and 32k point FFT, unless otherwise noted.
SIGNAL-TO-NOISE RATIO (0dB Gain)
200
66.5
65.5
66
Sampling Frequency (MSPS)
180
64.5
160
140
66.5
66
64.5
120
65.5
100
64.5
66
63.5
63.5
66.5
80
62.5
65.5
66
65
10
50
100
150
200
250
300
350
400
450
500
Input Frequency (MHz)
62
63
64
65
66
67
SNR (dBFS)
Figure 52.
SIGNAL-TO-NOISE RATIO (6dB Gain)
200
63.6
64.5
64.2
63
Sampling Frequency (MSPS)
180
64.5
160
64.2
140
63.6
64.2
64.5
64.8
120
63.6
63
100
63
80
62.4
62.4
64.8
64.2
64.5
61.8
63.6
65
10
50
61.5
100
150
62
200
62.5
250
300
Input Frequency (MHz)
63
63.5
350
400
64
450
64.5
500
65
SNR (dBFS)
Figure 53.
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APPLICATION INFORMATION
THEORY OF OPERATION
The ADS58C28 is a dual-channel, 11-bit, analog-to-digital converter (ADC) with sampling rates up to 200MSPS.
At every rising edge of the input clock, the analog input signal of each channel is simultaneously sampled. The
sampled signal in each channel is converted by a pipeline of low-resolution stages. In each stage, the sampled
and held signal is converted by a high-speed, low-resolution, flash sub-ADC. The difference (residue) between
the stage input and the quantized equivalent is gained and propagates to the next stage. At every clock, each
succeeding stage resolves the sampled input with greater accuracy. The digital outputs from all stages are
combined in a digital correction logic block and are processed digitally to create the final code, after a data
latency of 16 clock cycles. The digital output is available as either DDR LVDS or parallel CMOS and coded in
either straight offset binary or binary twos complement format.
ANALOG INPUT
The analog input consists of a switched-capacitor based, differential sample-and-hold architecture. This
differential topology results in very good ac performance even for high input frequencies at high sampling rates.
The IN_P and IN_M pins must be externally biased around a common-mode voltage of 0.95V, available on the
VCM pin. For a full-scale differential input, each input pin (IN_P and IN_M) must swing symmetrically between
VCM + 0.5V and VCM – 0.5V, resulting in a 2VPP differential input swing. The input sampling circuit has a high
3dB bandwidth that extends up to 550MHz (measured from the input pins to the sampled voltage).
Sampling
Switch
LPKG
2nH
IN_P
10W
CBOND
1pF
100W
RESR
200W
IN_M
10W
CBOND
1pF
CPAR2
1pF
RON
15W
CSAMP
2pF
3pF
3pF
LPKG
2nH
Sampling
Capacitor
RCR Filter
CPAR1
0.5pF
RON
15W
100W
RON
15W
CPAR2
1pF
RESR
200W
CSAMP
2pF
Sampling
Capacitor
Sampling
Switch
Figure 54. Analog Input Equivalent Circuit
44
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Drive Circuit Requirements
For optimum performance, the analog inputs must be driven differentially. This operation improves the
common-mode noise immunity and even-order harmonic rejection. A 5Ω to 15Ω resistor in series with each input
pin is recommended to damp out ringing caused by package parasitics.
SFDR performance can be limited as a result of several reasons, including the effects of sampling glitches;
nonlinearity of the sampling circuit; and nonlinearity of the quantizer that follows the sampling circuit. Depending
on the input frequency, sample rate, and input amplitude, one of these factors plays a dominant part in limiting
performance. At very high input frequencies (greater than approximately 300MHz), SFDR is determined largely
by the device sampling circuit nonlinearity. At low input amplitudes, the quantizer nonlinearity usually limits
performance.
Glitches are caused by the opening and closing of the sampling switches. The driving circuit should present a
low source impedance to absorb these glitches. Otherwise, glitches could limit performance, primarily at low
input frequencies (up to approximately 200MHz). It is also necessary to present low impedance (less than 50Ω)
for the common-mode switching currents. This configuration can be achieved by using two resistors from each
input terminated to the common-mode voltage (VCM).
The device includes an internal R-C filter from each input to ground. The purpose of this filter is to absorb the
sampling glitches inside the device itself. The cutoff frequency of the R-C filter involves a trade-off. A lower cutoff
frequency (larger C) absorbs glitches better, but it reduces the input bandwidth. On the other hand, with a higher
cutoff frequency (smaller C), bandwidth support is maximized. However, the sampling glitches now must be
supplied by the external drive circuit. This tradeoff has limitations as a result of the presence of the package
bond-wire inductance.
In the ADS58C28, the R-C component values have been optimized while supporting high input bandwidth (up to
550MHz). However, in applications with input frequencies up to 200MHz to 300MHz, the filtering of the glitches
can be improved further using an external R-C-R filter; see Figure 57 and Figure 58.
In addition, the drive circuit may have to be designed to provide a low insertion loss over the desired frequency
range and matched impedance to the source. Furthermore, the ADC input impedance must be considered.
Figure 55 and Figure 56 show the impedance (ZIN = RIN || CIN) looking into the ADC input pins.
5.0
Differential Input Capacitance (pF)
Differential Input Resistance (kW)
100.00
10.00
1.00
0.10
0.01
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0
0.1
Input Frequency (GHz)
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
Input Frequency (GHz)
Figure 55. ADC Analog Input Resistance (RIN)
Across Frequency
Figure 56. ADC Analog Input Capacitance (CIN)
Across Frequency
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Driving Circuit
Two example driving circuit configurations are shown in Figure 57 and Figure 58—one optimized for low
bandwidth (low input frequencies) and the other one for high bandwidth to support higher input frequencies. Note
that both of the drive circuits have been terminated by 50Ω near the ADC side. The termination is accomplished
by a 25Ω resistor from each input to the 0.95V common-mode (VCM) from the device. This allows the analog
inputs to be biased around the required common-mode voltage.
The mismatch in the transformer parasitic capacitance (between the windings) results in degraded even-order
harmonic performance. Connecting two identical RF transformers back-to-back helps minimize this mismatch;
good performance is obtained for high-frequency input signals. An additional termination resistor pair may be
required between the two transformers, as shown in Figure 57, Figure 58, and Figure 59. The center point of this
termination is connected to ground to improve the balance between the P and M sides. The values of the
terminations between the transformers and on the secondary side must be chosen to obtain an effective 50Ω (in
the case of 50Ω source impedance).
0.1mF
T1
15W
INx_P
T2
0.1mF
0.1mF
25W
25W
3.3pF
25W
RIN
CIN
25W
INx_M
1:1
1:1
15W
0.1mF
VCM
ADS58C28
Figure 57. Drive Circuit with Low Bandwidth (for Low Input Frequencies)
0.1mF
T1
5W
INx_P
T2
0.1mF
0.1mF
25W
50W
3.3pF
25W
RIN
CIN
50W
INx_M
1:1
1:1
5W
0.1mF
VCM
ADS58C28
Figure 58. Drive Circuit with High Bandwidth (for High Input Frequencies)
0.1mF
T1
5W
T2
INx_P
0.1mF
0.1mF
25W
RIN
CIN
25W
INx_M
1:1
1:1
0.1mF
5W
VCM
ADS58C28
Figure 59. Drive Circuit with Very High Bandwidth (Greater than 300MHz)
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All of these examples show 1:1 transformers being used with a 50Ω source. As explained in the Drive Circuit
Requirements section, this configuration helps to present a low source impedance to absorb the sampling
glitches. With a 1:4 transformer, the source impedance is 200Ω. Higher impedance can lead to degradation in
performance, compared to the case with 1:1 transformers. For applications where only a band of frequencies are
used, the drive circuit can be tuned to present a low impedance for the sampling glitches. Figure 60 shows an
example with a 1:4 transformer, tuned for a band of approximately 150MHz.
5W
T1
Band-Pass
or
Low-Pass
Filter
Differential
Input Signal
0.1mF
INx_P
100W
RIN
CIN
100W
INx_M
1:4
5W
VCM
ADS58C28
Figure 60. Drive Circuit with a 1:4 Transformer
CLOCK INPUT
The ADS58C28 clock inputs can be driven differentially (sine, LVPECL, or LVDS) or single-ended (LVCMOS),
with little or no difference in performance between them. The common-mode voltage of the clock inputs is set to
VCM using internal 5kΩ resistors. This setting allows the use of transformer-coupled drive circuits for sine-wave
clock or ac-coupling for LVPECL and LVDS clock sources. Figure 61 shows a circuit for the internal clock buffer.
Clock Buffer
LPKG
2nH
20W
CLK_P
CBOND
1pF
RESR
100W
LPKG
2nH
5kW
2pF
20W
CEQ
CEQ
VCM
5kW
CLK_M
CBOND
1pF
RESR
100W
NOTE: CEQ is 1pF to 3pF and is the equivalent input capacitance of the clock buffer.
Figure 61. Internal Clock Buffer
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A single-ended CMOS clock can be ac-coupled to the CLK_P input, with CLK_M connected to ground with a
0.1mF capacitor, as shown in Figure 62. For best performance, the clock inputs must be driven differentially,
thereby reducing susceptibility to common-mode noise. For high input frequency sampling, it is recommended to
use a clock source with very low jitter. Band-pass filtering of the clock source can help reduce the effects of jitter.
There is no change in performance with a non-50% duty cycle clock input. Figure 63 shows a differential circuit.
CMOS
Clock Input
0.1mF
0.1mF
CLK_P
CLK_P
Differential Sine-Wave,
PECL, or LVDS
Clock Input
VCM
0.1mF
0.1mF
CLK_M
CLK_M
Figure 62. Single-Ended Clock Driving Circuit
Figure 63. Differential Clock Driving Circuit
DIGITAL FUNCTIONS
The device has several useful digital functions such as test patterns, gain, offset correction, and SNRBoost3G. All
of these functions can be controlled using two control bits (DIGITAL MODE 1 and DIGITAL MODE 2), as shown
in Table 12.
Table 12. Digital Functions Control Bits
DIGITAL MODE 1
DIGITAL MODE 2
0
0
Default
DESCRIPTION
0
1
SNRBoost3G enabled, test patterns, gain, and offset correction disabled
1
0
SNRBoost3G, test patterns, gain, and offset correction enabled
1
1
SNRBoost3G, test patterns, gain, and offset correction enabled
SNR ENHANCEMENT USING SNRBoost3G
SNRBoost3G technology makes it possible to overcome SNR limitations resulting from quantization noise. Using
SNRBoost3G, enhanced SNR can be obtained for any bandwidth (less than Nyquist or fS/2; see Table 5). SNR
improvement is achieved without affecting the default harmonic performance.
The ADS58C28 uses third-generation SNRBoost technology (SNRBoost3G) to achieve SNR enhancement over
very wide bandwidths (up to 60MHz). When SNRBoost3G is enabled, the noise floor in the spectrum acquires a
typical bathtub shape. The special feature of SNRBoost3G is the nearly flat noise floor within the entire band of
the bathtub.
The position of the center of the bathtub and its bandwidth are programmable; the available bandwidths are
60MHz, 40MHz, 30MHz, and 20MHz. Several center frequency options are available for each bandwidth. The
ADS58C28 includes 55 pre-programmed combinations of center frequency and bandwidth. Any one of these
combinations can be selected by programming the Ch SNRBoost3G Filter Number register bits. Each channel can
be programmed with independent center frequency and bandwidths.
One of the characteristics of SNRBoost3G is that the bandwidth scales with the sampling frequency. 60MHz and
40MHz bandwidths are achieved at a sampling rate of 184MHz; at higher sample rates, even higher bandwidths
are possible. The lower 30MHz and 20MHz bandwidths are achieved at a sample rate of 200MHz; at lower
sample rates, the achieved bandwidth is lower. Table 14 shows all combinations of center frequency for each
bandwidth, specified as fractions of the sample rate. By positioning the bathtub within the desired signal band,
SNR improvement can be achieved. Note that as the bandwidth increases, the amount of SNR improvement
reduces. After reset, the SNRBoost3G function is disabled.
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To use SNRBoost3G with control pins, follow this exact sequence:
Select and Enable the SNRBoost3G Filter
1. First, disable the DIGITAL MODE 1 and DIGITAL MODE 2 bits (set to '0').
2. Next, select the appropriate SNRBoost3G filter, using the Ch SNRBoost3G Filter number register bits.
3. Finally, set the DIGITAL MODE 2 bit (set to '1').
Turn On/Off SNRBoost3G
1. Use the CTRL1, CTRL2, and CTRL3 pins to dynamically turn on/off the SNRBoost3G for each pair of
channels.
To use SNRBoost3G without using control pins follow this exact sequence:
Select and Enable the SNRBoost3G Filter
1. First, disable the DIGITAL MODE 1 and DIGITAL MODE 2 bits (set to '0').
2. Next, select the appropriate SNRBoost3G filter using the Ch SNRBoost Filter number register bits.
3. Then set the DIGITAL MODE 2 bit (set to '1').
4. Finally, set the SNRBoost3G pin override bit (OVERRIDE SNRBoost PINS).
Turn On/Off SNRBoost3G
1. Turn on and off the SNRBoost3G for each channel using the SNRBoost CH A ON and SNRBoost CH B ON
register bits.
NOTE
To use a different SNRBoost3G filter, it is required to follow all the above steps in the exact
order specified. Not following this order can result in incorrect operation of the
SNRBoost3G filter. To turn on and off the filter without changing the filter number, simply
follow the steps under the Turn On/Off SNRBoost3G outline.
Table 13 describes the SNRBoost3G control when used with the CTRL pins.
Table 13. SNRBoost3G Control Using Pins CTRL1, CTRL2, and CTRL3
CTRL1
CTRL2
CTRL3
DESCRIPTION
Low
Low
Low
Normal operation; SNRBoost3G disabled for both channels
Low
Low
High
SNRBoost3G enabled for channel B
Low
High
Low
SNRBoost3G enabled for channel A
Low
High
High
SNRBoost3G enabled for channels A and B
High
Low
Low
Global power-down
High
Low
High
Channel A standby
High
High
Low
Do not use
High
High
High
MUX mode of operation, channels A and B data are multiplexed and
output on pins CHB_D[10:0].
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Table 14. Complete List of SNRBoost3G Modes (fS = Sampling Frequency in MSPS)
50
SNRBoost3G FILTER NUMBER
BANDWIDTH OF THE BATHTUB (MHz)
CENTER FREQUENCY OF THE BATHTUB
(MHz)
0
25 × (fS/200)
15 × (fS/200)
1
20 × (fS/200)
30 × (fS/200)
2
20 × (fS/200)
35 × (fS/200)
3
20 × (fS/200)
42 × (fS/200)
4
20 × (fS/200)
50 × (fS/200)
5
20 × (fS/200)
58 × (fS/200)
6
20 × (fS/200)
65 × (fS/200)
7
20 × (fS/200)
75 × (fS/200)
8
20 × (fS/200)
85 × (fS/200)
9
25 × (fS/200)
87.5 × (fS/200)
10
25 × (fS/200)
15 × (fS/200)
11
20 × (fS/200)
25 × (fS/200)
12
20 × (fS/200)
35 × (fS/200)
13
20 × (fS/200)
42 × (fS/200)
14
20 × (fS/200)
50 × (fS/200)
15
20 × (fS/200)
58 × (fS/200)
16
20 × (fS/200)
65 × (fS/200)
17
20 × (fS/200)
75 × (fS/200)
18
25 × (fS/200)
82.5 × (fS/200)
19
25 × (fS/200)
87.5 × (fS/200)
20
25 × (fS/200)
15 × (fS/200)
21
30 × (fS/200)
30 × (fS/200)
22
30 × (fS/200)
35 × (fS/200)
23
30 × (fS/200)
45 × (fS/200)
24
30 × (fS/200)
55 × (fS/200)
25
30 × (fS/200)
65 × (fS/200)
26
30 × (fS/200)
70 × (fS/200)
27
30 × (fS/200)
80 × (fS/200)
28
30 × (fS/200)
85 × (fS/200)
29
25 × (fS/200)
87.5 × (fS/200)
30
40 × (fS/184)
46 × (fS/184)
31
40 × (fS/184)
72 × (fS/184)
32
40 × (fS/184)
20 × (fS/184)
33
40 × (fS/184)
40 × (fS/184)
34
40 × (fS/184)
39.5 × (fS/184)
35
40 × (fS/184)
33.5 × (fS/184)
36
40 × (fS/184)
27 × (fS/184)
37
40 × (fS/184)
53 × (fS/184)
38
40 × (fS/184)
59 × (fS/184)
39
40 × (fS/184)
65.5 × (fS/184)
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Table 14. Complete List of SNRBoost3G Modes (fS = Sampling Frequency in MSPS) (continued)
SNRBoost3G FILTER NUMBER
BANDWIDTH OF THE BATHTUB (MHz)
CENTER FREQUENCY OF THE BATHTUB
(MHz)
40
60 × (fS/184)
46 × (fS/184)
41
60 × (fS/184)
46 × (fS/184)
42
60 × (fS/184)
30 × (fS/184)
43
60 × (fS/184)
30 × (fS/184)
44
60 × (fS/184)
62 × (fS/184)
45
60 × (fS/184)
62 × (fS/184)
46
60 × (fS/184)
40.5 × (fS/184)
47
60 × (fS/184)
40.5 × (fS/184)
48
60 × (fS/184)
37 × (fS/184)
49
60 × (fS/184)
37 × (fS/184)
50
60 × (fS/184)
53 × (fS/184)
51
60 × (fS/184)
50 × (fS/184)
52
60 × (fS/184)
54 × (fS/184)
53
58 × (fS/184)
58 × (fS/184)
54
60 × (fS/184)
62 × (fS/184)
GAIN FOR SFDR/SNR TRADE-OFF
The ADS58C28 includes gain settings that can be used to get improved SFDR performance. The gain is
programmable from 0dB to 6dB (in 0.5dB steps) using the GAIN register bits. For each gain setting, the analog
input full-scale range scales proportionally, as shown in Table 15.
The SFDR improvement is achieved at the expense of SNR; for each gain setting, the SNR degrades
approximately between 0.5dB and 1dB. The SNR degradation is reduced at high input frequencies. As a result,
the gain is very useful at high input frequencies because the SFDR improvement is significant with marginal
degradation in SNR. Therefore, the gain can be used as a trade-off between SFDR and SNR.
After a reset, the gain function is disabled. To use gain:
• First, program the DIGITAL MODE 1 and DIGITAL MODE 2 bits (see Table 12) to enable the gain function.
• This setting enables the gain and puts the device in a 0dB gain mode.
• For other gain settings, program the GAIN register bits.
Table 15. Full-Scale Range Across Gains
GAIN (dB)
TYPE
0
Default after reset
FULL-SCALE (VPP)
2
1
Fine adjust, programmable
1.78
2
Fine adjust, programmable
1.59
3
Fine adjust, programmable
1.42
4
Fine adjust, programmable
1.26
5
Fine adjust, programmable
1.12
6
Fine adjust, programmable
1
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OFFSET CORRECTION
The ADS58C28 has an internal offset corretion algorithm that estimates and corrects dc offset up to ±10mV. The
correction can be enabled using the ENABLE OFFSET CORR serial register bit. Once enabled, the algorithm
estimates the channel offset and applies the correction every clock cycle. The time constant of the correction
loop is a function of the sampling clock frequency. The time constant can be controlled using the OFFSET CORR
TIME CONSTANT register bits, as described in Table 16.
Table 16. Time Constant of Offset Correction Algorithm
(1)
OFFSET CORR TIME CONSTANT
TIME CONSTANT, TCCLK
(Number of Clock Cycles)
TIME CONSTANT, TCCLK × 1/fS (sec) (1)
0000
1M
5ms
0001
2M
10ms
0010
4M
21ms
0011
8M
42ms
0100
16M
84ms
0101
32M
168ms
0110
64M
336ms
0111
128M
671ms
1000
256M
1.3s
1001
512M
2.7s
1010
1024M
5.4s
1011
2048M
10.7s
1100
Reserved
—
1101
Reserved
—
1110
Reserved
—
1111
Reserved
—
Sampling frequency, fS = 200MSPS.
After the offset is estimated, the correction can be frozen by setting FREEZE OFFSET CORR = 1. Once frozen,
the last estimated value is used for the offset correction of every clock cycle. Note that offset correction is
disabled by default after reset.
After a reset, the offset correction is disabled. To use offset correction:
• First, program the DIGITAL MODE 1 and DIGITAL MODE 2 bits (see Table 12) to enable the correction.
• Then set ENABLE OFFSET CORR to '1' and program the required time constant.
DIGITAL OUTPUT INFORMATION
The ADS58C28 provides 11-bit digital data for each channel and a common output clock synchronized with the
data.
Output Interface
Two output interface options are available: double data rate (DDR) LVDS and parallel CMOS. They can be
selected using the LVDS CMOS serial interface register bit .
DDR LVDS Outputs
In this mode, the data bits and clock are output using low-voltage differential signal (LVDS) levels. Two data bits
are multiplexed and output on each LVDS differential pair.
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Pins
CLKOUTP
CLKOUTM
CHx0_P
LVDS Buffers
CHx0_M
CHx2_P
CHx2_M
CHx4_P
11-Bit
ADC Data
CHx4_M
CHx6_P
CHx6_M
CHx8_P
CHx8_M
CHx10_P
CHx10_M
ADS58C28
NOTE: X = channels A and B.
Figure 64. DDR LVDS Interface
CLKOUTM
CLKOUTP
CHA0,
CHB0
0
D0
0
D0
CHA2,
CHB2
D1
D2
D1
D2
CHA4,
CHB4
D3
D4
D3
D4
CHA6,
CHB6
D5
D6
D5
D6
CHA8,
CHB8
D7
D8
D7
D8
CHA10,
CHB10
D9
D10
D9
D10
Sample N
Sample N + 1
Figure 65. DDR LVDS Interface Timing Diagram
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LVDS Output Data and Clock Buffers
The equivalent circuit of each LVDS output buffer is shown in Figure 66. After reset, the buffer presents an
output impedance of 100Ω to match with the external 100Ω termination.
The VDIFF voltage is nominally 350mV, resulting in an output swing of ±350mV with 100Ω external termination.
The VDIFF voltage is programmable using the LVDS SWING register bits from ±125mV to ±570mV.
Additionally, a mode exists to double the strength of the LVDS buffer to support 50Ω differential termination. This
mode can be used when the output LVDS signal is routed to two separate receiver chips, each using a 100Ω
termination. The mode can be enabled using the LVDS DATA STRENGTH and LVDS CLKOUT STRENGTH
register bits for data and output clock buffers, respectively.
The buffer output impedance behaves in the same way as a source-side series termination. By absorbing
reflections from the receiver end, it helps to improve signal integrity.
VDIFF
High
Low
OUTP
External
100W Load
OUTM
VCM
ROUT
VDIFF
High
Low
Figure 66. LVDS Buffer Equivalent Circuit
CHA Data[10:0]
Receiver Chip #1
(for Example GC5330)
CHB Data[10:0]
CLKIN1
100W
CLKOUTP
CLKOUTM
CLKIN2
100W
CHC Data[10:0]
CHD Data[10:0]
Receiver Chip #2
ADS58C28
Make LVDS CLKOUT STRENGTH = 1
Figure 67. LVDS Strength Doubling (Example Application)
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Parallel CMOS Interface
In the CMOS mode, each data bit is output on separate pins as CMOS voltage level, every clock cycle. The
rising edge of the output clock CLKOUT can be used to latch data in the receiver.
Switching noise (caused by CMOS output data transitions) can couple into the analog inputs and degrade the
SNR. The coupling and SNR degradation increases as the output buffer drive is made stronger. To minimize this
effect, the CMOS output buffers are designed with controlled drive strength. The default drive strength ensures
wide data stable window provided the data outputs have minimal load capacitance. It is recommended to use
short traces (1 to 2 inches or 25,4mm to 50,8mm) terminated with not more than 5pF load capacitance.
For sampling frequencies greater than 150MSPS, it is recommended to use an external clock to capture data.
The delay from input clock to output data and the data valid times are specified for the higher sampling
frequencies. These timings can be used to delay the input clock appropriately and use it to capture the data.
CLKOUT
CMOS Output Buffers
CHx_D0
CHx_D1
CHx_D2
¼
¼
11-Bit
ADC Data
(1)
CHx_D9
CHx_D10
ADS58C28
NOTE: X = channels A and B.
Figure 68. CMOS Interface
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Use External Clock Buffer
(> 150MSPS)
Input Clock
Receiver (FPGA, ASIC, etc.)
Flip-Flops
CLKOUT
CMOS Output Buffers
CHx_D0
CHx_D1
CHx_D2
CLKIN
D0_In
D1_In
D2_In
11-Bit ADC Data
CHx_D9
CHx_D10
D12_In
D13_In
ADS58C28
Use short traces between
ADC output and receiver pins (1 to 2 inches).
Figure 69. Data Capture with CMOS Interface
CMOS Interface Power Dissipation
With CMOS outputs, the DRVDD current scales with the sampling frequency and the load capacitance on every
output pin. The maximum DRVDD current occurs when each output bit toggles between 0 and 1 every clock
cycle. In actual applications, this condition is unlikely to occur. The actual DRVDD current would be determined
by the average number of output bits switching, which is a function of the sampling frequency and the nature of
the analog input signal.
Digital current as a result of CMOS output switching = CL × DRVDD × (N × FAVG),
where CL = load capacitance, N × FAVG = average number of output bits switching.
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Multiplexed Mode of Operation
In this mode, the digital outputs of both channels are multiplexed and output on a single bus (CHB_D[10:0] pins),
as shown in Figure 70. Any unused channel output pins (CHA_Dn) are forced low and are not put in a
high-impedance state. Because the output data rate on the channel B bus is effectively doubled, this mode is
recommended only for low sampling frequencies (< 75MSPS). This mode can be enabled using the
POWER-DOWN MODE register bits or using the CTRL[3:1] parallel pins. Note that setup and hold timings in this
mode are different compared to the default CMOS mode.
CLKM
Input
Clock
CLKP
tPDI
Output
Clock
CLKOUT
tSU
Output
Data
CHB_Dn
(2)
CHA_Dn
(1)
tH
CHB_Dn
(1)
CHA_Dn
(1)
(1) Dn = Bits D0, D1, D2, etc.
(2) In multiplexed mode, both channel outputs come on channel B output pins.
Figure 70. ADS58C28 MUX Mode Timing Diagram
Output Data Format
Two output data formats are supported: twos complement and offset binary. They can be selected using the
DATA FORMAT CHx serial interface register bit.
In the event of an input voltage overdrive, the digital outputs go to the appropriate full-scale level. For a positive
overdrive, the output code is 7FFh in offset binary output format, and 3FFh in twos complement output format.
For a negative input overdrive, the output code is 0000h in offset binary output format and 400h in twos
complement output format.
BOARD DESIGN CONSIDERATIONS
Grounding
A single ground plane is sufficient to give good performance, provided the analog, digital, and clock sections of
the board are cleanly partitioned. See the EVM User Guide for details on layout and grounding.
Exposed Pad
In addition to providing a path for heat dissipation, the PowerPAD is also electrically internally connected to the
digital ground. Therefore, it is necessary to solder the exposed pad to the ground plane for best thermal and
electrical performance. For detailed information, see application notes.
DEFINITION OF SPECIFICATIONS
Analog Bandwidth – The analog input frequency at which the power of the fundamental is reduced by 3 dB with
respect to the low-frequency value.
Aperture Delay – The delay in time between the rising edge of the input sampling clock and the actual time at
which the sampling occurs. This delay is different across channels. The maximum variation is specified as
aperture delay variation (channel-to-channel).
Aperture Uncertainty (Jitter) – The sample-to-sample variation in aperture delay.
Clock Pulse Width/Duty Cycle – The duty cycle of a clock signal is the ratio of the time the clock signal remains
at a logic high (clock pulse width) to the period of the clock signal. Duty cycle is typically expressed as a
percentage. A perfect differential sine-wave clock results in a 50% duty cycle.
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Maximum Conversion Rate – The maximum sampling rate at which specified operation is given. All parametric
testing is performed at this sampling rate unless otherwise noted.
Minimum Conversion Rate – The minimum sampling rate at which the ADC functions.
Differential Nonlinearity (DNL) – An ideal ADC exhibits code transitions at analog input values spaced exactly
1 LSB apart. The DNL is the deviation of any single step from this ideal value, measured in units of LSBs.
Integral Nonlinearity (INL) – The INL is the deviation of the ADC transfer function from a best fit line determined
by a least squares curve fit of that transfer function, measured in units of LSBs.
Gain Error – Gain error is the deviation of the ADC actual input full-scale range from its ideal value. The gain
error is given as a percentage of the ideal input full-scale range. Gain error has two components: error as a
result of reference inaccuracy and error as a result of the channel. Both errors are specified independently as
EGREF and EGCHAN.
To a first-order approximation, the total gain error is ETOTAL ~ EGREF + EGCHAN.
For example, if ETOTAL = ±0.5%, the full-scale input varies from (1 – 0.5/100) x FSideal to (1 + 0.5/100) x FSideal.
Offset Error – The offset error is the difference, given in number of LSBs, between the ADC actual average idle
channel output code and the ideal average idle channel output code. This quantity is often mapped into millivolts.
Temperature Drift – The temperature drift coefficient (with respect to gain error and offset error) specifies the
change per degree Celsius of the parameter from TMIN to TMAX. It is calculated by dividing the maximum deviation
of the parameter across the TMIN to TMAX range by the difference TMAX – TMIN.
Signal-to-Noise Ratio – SNR is the ratio of the power of the fundamental (PS) to the noise floor power (PN),
excluding the power at dc and the first nine harmonics.
SNR = 10Log10
PS
PN
(1)
SNR is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the
reference, or dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter
full-scale range.
Signal-to-Noise and Distortion (SINAD) – SINAD is the ratio of the power of the fundamental (PS) to the power
of all the other spectral components including noise (PN) and distortion (PD), but excluding dc.
SINAD = 10Log10
PS
PN + PD
(2)
SINAD is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the
reference, or dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter
full-scale range.
58
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Effective Number of Bits (ENOB) – ENOB is a measure of the converter performance as compared to the
theoretical limit based on quantization noise.
ENOB =
SINAD - 1.76
6.02
(3)
Total Harmonic Distortion (THD) – THD is the ratio of the power of the fundamental (PS) to the power of the
first nine harmonics (PD).
THD = 10Log10
PS
PN
(4)
THD is typically given in units of dBc (dB to carrier).
Spurious-Free Dynamic Range (SFDR) – The ratio of the power of the fundamental to the highest other
spectral component (either spur or harmonic). SFDR is typically given in units of dBc (dB to carrier).
Two-Tone Intermodulation Distortion – IMD3 is the ratio of the power of the fundamental (at frequencies f1
and f2) to the power of the worst spectral component at either frequency 2f1 – f2 or 2f2 – f1. IMD3 is either given
in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB
to full-scale) when the power of the fundamental is extrapolated to the converter full-scale range.
DC Power-Supply Rejection Ratio (DC PSRR) – DC PSSR is the ratio of the change in offset error to a change
in analog supply voltage. The dc PSRR is typically given in units of mV/V.
AC Power-Supply Rejection Ratio (AC PSRR) – AC PSRR is the measure of rejection of variations in the
supply voltage by the ADC. If ΔVSUP is the change in supply voltage and ΔVOUT is the resultant change of the
ADC output code (referred to the input), then:
DVOUT
PSRR = 20Log 10
(Expressed in dBc)
DVSUP
(5)
Voltage Overload Recovery – The number of clock cycles taken to recover to less than 1% error after an
overload on the analog inputs. This is tested by separately applying a sine wave signal with 6 dB positive and
negative overload. The deviation of the first few samples after the overload (from the expected values) is noted.
Common-Mode Rejection Ratio (CMRR) – CMRR is the measure of rejection of variation in the analog input
common-mode by the ADC. If ΔVCM_IN is the change in the common-mode voltage of the input pins and ΔVOUT is
the resulting change of the ADC output code (referred to the input), then:
DVOUT
CMRR = 20Log10
(Expressed in dBc)
DVCM
(6)
Crosstalk (only for multi-channel ADCs) – This is a measure of the internal coupling of a signal from an
adjacent channel into the channel of interest. It is specified separately for coupling from the immediate
neighboring channel (near-channel) and for coupling from channel across the package (far-channel). It is usually
measured by applying a full-scale signal in the adjacent channel. Crosstalk is the ratio of the power of the
coupling signal (as measured at the output of the channel of interest) to the power of the signal applied at the
adjacent channel input. It is typically expressed in dBc.
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REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (October 2010) to Revision B
•
60
Page
Updated Figure 44 .............................................................................................................................................................. 40
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PACKAGE OPTION ADDENDUM
www.ti.com
7-Apr-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ADS58C28IRGCR
ACTIVE
VQFN
RGC
64
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
AZ58C28
ADS58C28IRGCT
ACTIVE
VQFN
RGC
64
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
AZ58C28
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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7-Apr-2016
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Mar-2014
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
ADS58C28IRGCR
VQFN
RGC
64
2000
330.0
16.4
9.3
9.3
1.5
12.0
16.0
Q2
ADS58C28IRGCT
VQFN
RGC
64
250
180.0
16.4
9.3
9.3
1.5
12.0
16.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Mar-2014
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ADS58C28IRGCR
VQFN
RGC
64
2000
336.6
336.6
28.6
ADS58C28IRGCT
VQFN
RGC
64
250
213.0
191.0
55.0
Pack Materials-Page 2
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