Holtek HT9200A Dtmf generator Datasheet

HT9200A/HT9200B
DTMF Generators
Features
· Operating voltage: 2.5V~5.5V
· Low total harmonic distortion
· Serial mode for the HT9200A
· 3.58MHz crystal or ceramic resonator
· Serial/parallel mode for the HT9200B
· HT9200A: 8-pin DIP/SOP package
HT9200B: 14-pin SOP package
· Low standby current
General Description
The HT9200A/B tone generators are designed for MCU
interfaces. They can be instructed by a MCU to generate 16 dual tones and 8 single tones from the DTMF pin.
The HT9200A provides a serial mode whereas the
HT9200B contains a selectable serial/parallel mode interface for various applications such as security systems, home automation, remote control through
telephone lines, communication systems, etc.
Selection Table
Function
Operating
Voltage
OSC
Frequency
HT9200A
2.5V~5.5V
HT9200B
2.5V~5.5V
Part No.
Interface
Package
3.58MHz
Serial
8 DIP/SOP
3.58MHz
Serial/Parallel
14 SOP
Block Diagram
3 .5 8 M H z
C r y s ta l/R e s o n a to r
O s c illa to r
X 1
X 2
D A T A
S e r ia l D a ta
In p u t C ir c u it
C L K
D T M F
G e n e ra to r
C o n tro l
C ir c u it
C E
S /P
D T M F
P a r a l l e lD a t a
I n p u tC ir c u it
D 3
D 2
D 1
D 0
C E
X 2
1
1 4
2
1 3
D T M F
X 1
3
1 2
D A T A
Pin Assignment
C E
X 2
1
8
V D D
V S S
4
1 1
C L K
2
7
D T M F
N C
5
1 0
X 1
3
6
D A T A
D 0
6
9
S /P
D 3
V S S
4
5
C L K
D 1
7
8
D 2
H T 9 2 0 0 A
8 D IP -A /S O P -A
Rev. 1.40
V D D
H T 9 2 0 0 B
1 4 S O P -A
1
August 30, 2004
HT9200A/HT9200B
Pad Coordinates
Pad Assignment
X 2
1
C E
V D D
1 3
1 2
1 1
(0 ,0 )
X 1
1 0
2
Pad
No.
X
Y
Pad
No.
X
1
-553.30
430.40
8
553.30
-523.50
2
-553.30
-133.50
9
553.30
-190.30
3
-553.30
-328.50
10
553.30
4.70
4
-553.30
-523.50
11
553.30
340.30
5
-220.10
-523.50
12
374.90
523.50
6
-25.10
-523.50
13
-279.30
523.50
7
308.10
-523.50
D T M F
D A T A
C L K
9
3
V S S
D 0
4
5
6
7
8
D 1
D 2
D 3
S /P
Unit: mm
Y
Chip size: 1460 ´ 1470 (mm)2
* The IC substrate should be connected to VSS in the PCB layout artwork.
Pin Description
I/O
Internal
Connection
CE
I
CMOS IN
Chip enable, active low.
No internal pull-high resistor.
X2
O
Oscillator
X1
I
The system oscillator consists of an inverter, a bias resistor, and the required load
capacitor on chip.
The oscillator function can be implemented by Connect a standard 3.579545MHz
crystal to the X1 and X2 terminals.
Pin Name
Description
VSS
¾
¾
Negative power suppl, ground
NC
¾
¾
No connection
D0~D3
I
CMOS IN
Pull-high
or Floating
Data inputs for the parallel mode
When the IC is operating in the serial mode, the data input terminals (D0~D3) are
included with a pull-high resistor. When the IC is operating in the parallel mode,
these pins become floating.
S/P
I
CMOS IN
Operation mode selection input
S/P=²H²: Parallel mode
S/P=²L²: Serial mode
CLK
I
CMOS IN
Pull-high
or Floating
Data synchronous clock input for the serial mode
When the IC is operating in the parallel mode, the input terminal (CLK) is included
with a pull-high resistor. When the IC is operating in the serial mode, this pin becomes floating.
DATA
I
CMOS IN
Pull-high
or Floating
Data input terminal for the serial mode
When the IC is operating in the parallel mode, the input terminal (DATA) is included
with a pull-high resistor. When the IC is operating in the serial mode, this pin becomes floating.
DTMF
O
CMOS OUT
VDD
¾
¾
Rev. 1.40
Output terminal of the DTMF signal
Positive power supply, 2.5V~5.5V for normal operation
2
August 30, 2004
HT9200A/HT9200B
Approximate Internal Connection Circuits
C M O S IN
P u ll- h ig h
V
C M O S O U T
V
D D
C M O S IN (F o r D 0 ~ D 3 ,
C L K , D A T A )
V
D D
C M O S IN
D D
O S C IL L A T O R
X 1
2 0 p F
X 2
1 0 M
1 0 p F
E N
Absolute Maximum Ratings
Supply Voltage ..............................VSS-0.3V to VSS+6V
Storage Temperature ............................-50°C to 125°C
Input Voltage ................................VSS-0.3 to VDD+0.3V
Operating Temperature...........................-20°C to 75°C
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
Electrical Characteristics
Symbol
Parameter
VDD
Operating Voltage
IDD
Operating Current
Ta=25°C
Test Conditions
VDD
Conditions
¾
¾
2.5V
5.0V
S/P=VDD,D0~D3=VSS,
CE=VSS, No load
Min.
Typ.
Max.
Unit
2.5
¾
5.5
V
¾
240
2500
¾
950
3000
mA
VIL
²Low² Input Voltage
¾
¾
VSS
¾
0.2VDD
V
VIH
²High² Input Voltage
¾
¾
0.8VDD
¾
VDD
V
Standby Current
¾
¾
1
ISTB
¾
¾
2
120
180
270
45
68
100
¾
tUP+6
tUP+8
ms
0.45VDD
¾
0.75VDD
V
2.5V
S/P=VDD,CE=VDD, no load
5.0V
RP
2.5V
Pull-high Resistance
5.0V
VOL=0V
mA
kW
tDE
DTMF Output Delay Time
(Parallel Mode)
VTDC
DTMF Output DC Level
2.5V~
DTMF Output
5.5V
ITOL
DTMF Sink Current
2.5V
VDTMF=0.5V
-0.1
¾
¾
mA
VTAC
DTMF Output AC Level
2.5V
Row group, RL=5kW
0.12
0.15
0.18
Vrms
ACR
Column Pre-emphasis
2.5V
Row group=0dB
1
2
3
dB
RL
DTMF Output Load
2.5V
tHD £-23dB
5
¾
¾
kW
Rev. 1.40
¾
5V
3
August 30, 2004
HT9200A/HT9200B
Symbol
Parameter
tHD
Tone Signal Distortion
fCLK
Clock Input Rate (Serial
Mode)
tUP
Oscillator Starting Time
(When CE is low)
fOSC
System Frequency
Rev. 1.40
Test Conditions
VDD
2.5V
Conditions
RL=5kW
Min.
Typ.
Max.
Unit
¾
-30
-23
dB
¾
¾
¾
100
500
kHz
5.0V
The time from CE falling
edge to normal oscillator
operation
¾
¾
10
ms
3.5759
3.5795
3.5831
MHz
¾
Crystal=3.5795MHz
4
August 30, 2004
HT9200A/HT9200B
Functional Description
bits, the D0(LSB) is the first received bit. The
HT9200A/B will latch data on the falling edge of the
clock (CLK pin). The relationship between the digital
codes and the tone output frequency is shown in Table
1. As for the control timing diagram, refer to Figure 1.
The HT9200A/B are DTMF generators for MCU interfaces. They are controlled by a MCU in the serial mode
or the parallel mode (for the HT9200B only).
Serial Mode (HT9200A/B)
The HT9200A/B employ a data input, a 5-bit code, and a
synchronous clock to transmit a DTMF signal. Every
digit of a phone number to be transmitted is selected by
a series of inputs which consist of 5-bit data. Of the 5
When the system is operating in the serial mode a
pull-high resistor is attached to D0~D3 (for parallel
mode) on the input terminal.
Table 1: Digits vs. Input Data vs. Tone Output Frequency (Serial Mode)
Digit
D4
D3
D2
D1
D0
Tone Output
Frequency (Hz)
697+1209
1
0
0
0
0
1
2
0
0
0
1
0
697+1336
3
0
0
0
1
1
697+1477
4
0
0
1
0
0
770+1209
5
0
0
1
0
1
770+1336
6
0
0
1
1
0
770+1477
7
0
0
1
1
1
852+1209
8
0
1
0
0
0
852+1336
9
0
1
0
0
1
852+1477
0
0
1
0
1
0
941+1336
*
0
1
0
1
1
941+1209
#
A
0
1
1
0
0
941+1477
0
1
1
0
1
697+1633
B
0
1
1
1
0
770+1633
C
0
1
1
1
1
852+1633
D
0
0
0
0
0
941+1633
¾
1
0
0
0
0
697
¾
1
0
0
0
1
770
¾
1
0
0
1
0
852
¾
1
0
0
1
1
941
¾
1
0
1
0
0
1209
¾
1
0
1
0
1
1336
¾
1
0
1
1
0
1477
¾
1
0
1
1
1
1633
DTMF OFF
1
1
1
1
1
¾
Note: The codes not listed in Table 1 are not used D4 is MSB
Rev. 1.40
5
August 30, 2004
HT9200A/HT9200B
The TDE time (about 6ms) will be delayed from the CE falling edge to the DTMF signal output.
For the HT9200B, the S/P pin has to be connected low for
serial mode operation.
The relationship between the digital codes and the tone
output frequency is illustrated in Table 2. As for the control
timing diagram, see Figure 2.
Parallel Mode (HT9200B)
The HT9200B provides four data inputs D0~D3 to generate their corresponding DTMF signals. The S/P has to be
connected high to select the parallel operation mode.
Then the input data codes should be determined. Finally,
the CE is connected low to transmit the DTMF signal from
the DTMF pin.
When the system is operating in the parallel mode,
D0~D3 are all in the floating state. Thus, these data input pins should not float.
S /P
X 2
( O s c illa to r )
tU
P
C E
C L K
L S B
M S B
L S B
M S B
L S B
D A T A
1
D ig it 1
D ig it 2
M S B
1
1
1
1
S to p c o d e
D T M F
D ig it 1
D T M F s ig n a l
D ig it 2
D T M F s ig n a l
Figure 1
Table 2: Digits vs. Input Data vs. Tone Output Frequency (Parallel Mode)
Digit
D3
D2
D1
D0
Tone Output
Frequency (Hz)
1
0
0
0
1
697+1209
2
0
0
1
0
697+1336
3
0
0
1
1
697+1477
4
0
1
0
0
770+1209
5
0
1
0
1
770+1336
6
0
1
1
0
770+1477
7
0
1
1
1
852+1209
8
1
0
0
0
852+1336
9
1
0
0
1
852+1477
0
1
0
1
0
941+1336
*
1
0
1
1
941+1209
#
1
1
0
0
941+1477
A
1
1
0
1
697+1633
B
1
1
1
0
770+1633
C
1
1
1
1
852+1633
D
0
0
0
0
941+1633
Rev. 1.40
6
August 30, 2004
HT9200A/HT9200B
S /P
X 2
( O s c illa to r )
C E
D 0 ~ D 3
D T M F
tD
tD
E
N o te : T h e d a ta ( D 0 ~ D 3 ) s h o u ld b e r e a d y b e fo r e th e C E
E
b e c o m e s lo w .
Figure 2
Tone Frequency
Output Frequency (Hz)
%Error
Specified
Actual
697
699
+0.29%
770
766
–0.52%
852
847
–0.59%
941
948
+0.74%
1209
1215
+0.50%
1336
1332
–0.30%
1477
1472
–0.34%
% Error does not contain the crystal frequency drift
Rev. 1.40
7
August 30, 2004
HT9200A/HT9200B
Application Circuits
Serial Mode
V
V
D D
V D D
C E
3 .5 7 9 5 4 5 M H z
1
2
C L K
V S S
D A T A
2 0 p F
3
4
2 0 p F
M C U
C E
X 2
X 1
V S S
V D
D T M
D A T
C L
D D
8
D
7
T o n e
O u tp u t
F
A
K
6
5
H T 9 2 0 0 A
Serial/Parallel Mode
V
V
D D
V D D
V S S
V S S
C E
D 0
D 1
D 2
D 3
S /P
C L K
D A T A
3 .5 7 9 5 4 5 M H z 1
2 0 p F
2
3
4
2 0 p F
Rev. 1.40
V D D
X 2
D T M F
X 1
D A T A
V S S
5
6
7
M C U
C E
1 4
1 3
1 2
N C
D 0
D 3
D 1
D 2
T o n e
O u tp u t
1 1
C L K
S /P
D D
1 0
9
8
H T 9 2 0 0 B
8
August 30, 2004
HT9200A/HT9200B
Package Information
8-pin DIP (300mil) Outline Dimensions
A
8
B
5
4
1
H
C
D
=
G
E
I
F
Symbol
A
Rev. 1.40
Dimensions in mil
Min.
Nom.
Max.
355
¾
375
B
240
¾
260
C
125
¾
135
D
125
¾
145
E
16
¾
20
F
50
¾
70
G
¾
100
¾
H
295
¾
315
I
335
¾
375
a
0°
¾
15°
9
August 30, 2004
HT9200A/HT9200B
8-pin SOP (150mil) Outline Dimensions
5
8
A
B
4
1
C
C '
G
H
D
E
Symbol
Rev. 1.40
=
F
Dimensions in mil
Min.
Nom.
Max.
A
228
¾
244
B
149
¾
157
C
14
¾
20
C¢
189
¾
197
D
53
¾
69
E
¾
50
¾
F
4
¾
10
G
22
¾
28
H
4
¾
12
a
0°
¾
10°
10
August 30, 2004
HT9200A/HT9200B
14-pin SOP (150mil) Outline Dimensions
8
1 4
A
B
7
1
C
C '
G
H
D
E
Symbol
Rev. 1.40
=
F
Dimensions in mil
Min.
Nom.
Max.
A
228
¾
244
B
149
¾
157
C
14
¾
20
C¢
336
¾
344
D
53
¾
69
E
¾
50
¾
F
4
¾
10
G
22
¾
28
H
4
¾
12
a
0°
¾
10°
11
August 30, 2004
HT9200A/HT9200B
Product Tape and Reel Specifications
Reel Dimensions
D
T 2
A
C
B
T 1
SOP 8N
Symbol
Description
Dimensions in mm
A
Reel Outer Diameter
330±1.0
B
Reel Inner Diameter
62±1.5
C
Spindle Hole Diameter
13.0+0.5
-0.2
D
Key Slit Width
2.0±0.15
T1
Space Between Flange
12.8+0.3
-0.2
T2
Reel Thickness
18.2±0.2
SOP 14N
Symbol
Description
Dimensions in mm
A
Reel Outer Diameter
330±1.0
B
Reel Inner Diameter
62±1.5
C
Spindle Hole Diameter
13.0+0.5
-0.2
D
Key Slit Width
2.0±0.5
T1
Space Between Flange
16.8+0.3
-0.2
T2
Reel Thickness
22.2±0.2
Rev. 1.40
12
August 30, 2004
HT9200A/HT9200B
Carrier Tape Dimensions
P 0
D
P 1
t
E
F
W
C
D 1
B 0
P
K 0
A 0
SOP 8N
Symbol
Description
Dimensions in mm
W
Carrier Tape Width
12.0+0.3
-0.1
P
Cavity Pitch
8.0±0.1
E
Perforation Position
1.75±0.1
F
Cavity to Perforation (Width Direction)
5.5±0.1
D
Perforation Diameter
1.55±0.1
D1
Cavity Hole Diameter
1.5+0.25
P0
Perforation Pitch
4.0±0.1
P1
Cavity to Perforation (Length Direction)
2.0±0.1
A0
Cavity Length
6.4±0.1
B0
Cavity Width
5.20±0.1
K0
Cavity Depth
2.1±0.1
t
Carrier Tape Thickness
0.3±0.05
C
Cover Tape Width
9.3
SOP 14N
Symbol
Description
Dimensions in mm
16.0+0.3
-0.1
W
Carrier Tape Width
P
Cavity Pitch
8.0±0.1
E
Perforation Position
1.75±0.1
F
Cavity to Perforation (Width Direction)
7.5±0.1
D
Perforation Diameter
1.5+0.1
D1
Cavity Hole Diameter
1.5+0.25
P0
Perforation Pitch
4.0±0.1
P1
Cavity to Perforation (Length Direction)
2.0±0.1
A0
Cavity Length
6.5±0.1
B0
Cavity Width
9.5±0.1
K0
Cavity Depth
2.1±0.1
t
Carrier Tape Thickness
0.3±0.05
C
Cover Tape Width
Rev. 1.40
13.3
13
August 30, 2004
HT9200A/HT9200B
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Fax: 886-3-563-1189
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Copyright Ó 2004 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 1.40
14
August 30, 2004
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