Intersil ISL6146D Low voltage or-ing fet controller Datasheet

Low Voltage OR-ing FET Controller
ISL6146
Features
The ISL6146 represents a family of OR-ing MOSFET controllers
capable of OR-ing voltages from 1V to 18V. Together with suitably
sized N-channel power MOSFETs, the ISL6146 increases power
distribution efficiency when replacing a power OR-ing diode in high
current applications. It provides gate drive voltage for the
MOSFET(s) with a fully integrated charge pump.
• OR-ing Down to 1V and Up to 20V with ISL6146A, ISL6146B,
ISL6146D and ISL6146E
The ISL6146 allows users to adjust with external resistor(s) the
VOUT - VIN trip point, which adjusts the control sensitivity to system
power supply noise. An open drain FAULT pin will indicate if a
conditional or FET fault has occurred.
The ISL6146A and ISL6146B are optimized for very low voltage
operation, down to 1V with an additional independent bias of 3V
or greater.
The ISL6146C provides a voltage compliant mode of operation
down to 3V with programmable Undervoltage Lock Out and
Overvoltage Protection threshold levels
The ISL6146D and ISL6146E are like the ISL6146A and ISL6146B
respectively but do not have conduction state reporting via the
fault output.
TABLE 1. KEY DIFFERENCES BETWEEN PARTS IN FAMILY
PART NUMBER
KEY DIFFERENCES
• Programmable Voltage Compliant Operation with ISL6146C
• VIN Hot Swap Transient Protection Rating to +24V
• High Speed Comparator Provides Fast <0.3µs Turn-off in
Response to Shorts on Sourcing Supply
• Fastest Reverse Current Fault Isolation with 6A Turn-off
Current
• Very Smooth Switching Transition
• Internal Charge Pump to Drive N-channel MOSFET
• User Programmable VIN - VOUT Vth for Noise Immunity
• Open Drain FAULT Output with Delay
- Short between any two of the OR-ing FET Terminals
- GATE Voltage and Excessive FET VDS
- Power-Good Indicator (ISL6146C)
• MSOP and DFN Package Options
Applications
• N+1 Industrial and Telecom Power Distribution Systems
ISL6146A
Separate BIAS and VIN with Active High Enable
ISL6146B
Separate BIAS and VIN with Active Low Enable
• Low Voltage Processor and Memory
ISL6146C
VIN with OVP/UVLO Inputs
• Storage and Datacom Systems
ISL6146D
ISL6146A wo Conduction Monitor & Reporting
ISL6146E
ISL6146B wo Conduction Monitor & Reporting
+
Q1
+
VOLTAGE
DC/DC
(3V - 20V)
VIN GATE VOUT
BIAS
ADJ
ISL6146B
FLT
GND
EN
Q2
+
VOLTAGE
DC/DC
(3V - 20V)
VIN GATE VOUT
VOUT
BIAS
ADJ
ISL6146B
FLT
GND
EN
-
FIGURE 1. TYPICAL APPLICATION
April 26, 2013
FN7667.4
1
• Uninterruptable Power Supplies
C
O
M
M
O
N
P
O
W
E
R
GATE FAST OFF, ~200ns FALL TIME
~70ns FROM 20V TO 12.6V ACROSS 57nF
GATE OUTPUT SINKING ~ 6A
B
U
S
+C
O
M
M
O
N
P
O
W
E
R
B
U
S
FIGURE 2. ISL6146 GATE HIGH CURRENT PULL-DOWN
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2011-2013. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL6146
Block Diagram
FAULT DIAGNOSTIC
1. VIN - VOUT > 570mV
2. GATE - VIN < 220mV (A,B,C only)
Q-PUMP
BIAS
+
VIN
VDS FORWARD
REGULATOR
+
-
GATE
19mV
VOUT
REVERSE DETECTION
57mV COMPARATOR
+
+
-
EN/EN
ENABLE
EN
ENABLE
*
4A
+
+
UVLO
8mA
ADJ
FLT
3. TEMP > +150°C
4. VBIAS < POR (ISL6146A/B/D/E)
5. VIN OR VOUT < POR (ISL6146C)
6. VIN < VOUT
7. Gate to Drain and Gate to Source Shorts
HIGH SPEED
COMPARATOR
+
-
OVP
VREF
+
ISL6146A/B/D/E
+
-
* Connected to BIAS on ISL6146A/B/D/E
VREF
Connected to VOUT on ISL6146C
ISL6146C
Pin Configuration
ISL6146A, ISL6146B, ISL6146D, ISL6146E
GATE
1
8
VOUT
VIN
2
7
ADJ
BIAS
3
6
FAULT
4
5
GND
EN ISL6146A/D
EN ISL6146B/E
ISL6146
(8 LD MSOP/DFN)
TOP VIEW
ISL6146C
GATE
1
8
VOUT
VIN
2
7
ADJ
UVLO
3
6
FAULT
OVP
4
5
GND
EPAD on DFN only, connect to GND
Pin Descriptions
MSOP/
DFN
SYMBOL
DESCRIPTION
1
GATE
Gate Drive output to the external N-Channel MOSFET generated by the IC internal charge pump. Gate turn-on time is typically
<1ms. Allows active control of external N-Channel FET gate to perform OR-ing function.
The GATE drive is between VIN + 7V at VIN = 3.3V and VIN +12V at VIN = 18V.
2
VIN
Connected to the sourcing supply side (OR-ing MOSFET Source), this pin serves as the sense pin to determine the OR’d
supply voltage. The OR-ing MOSFET will be turned off when VIN becomes lower than VOUT by a value more than the externally
set threshold or the defaulted internal threshold. Range: 0V to 24V
3
ISL6146A
ISL6146B
ISL6146D
ISL6146E
BIAS
Primary bias pin. Connected to an independent voltage supply greater than or equal to 3V and greater than VIN.
Range: 3.0 to 24V
3
ISL6146C
UVLO
Programmable UVLO protection to prevent premature turn-on prior to VIN being adequately biased. Range: 0V to 24V
4
ISL6146A
ISL6146D
EN
Active high enable input to turn on the FET. Internally pulled low to GND through 2MΩ.
Range: 0V to 24V
2
FN7667.4
April 26, 2013
ISL6146
Pin Descriptions
MSOP/
DFN
(Continued)
SYMBOL
DESCRIPTION
4
ISL6146B
ISL6146E
EN
Active low enable input to turn on the FET. Internally pulled high to BIAS through 2MΩ. Range: 0 to 24V
4
ISL6146C
OVP
Programmable OV protection to prevent continued operation when the monitored voltage is too high. A back-to-back FET
configuration must be employed to implement the OVP capability. Range: 0V to 24V
5
GND
Chip ground reference.
6
FAULT
Open-Drain pull-down fault indicating output with internal on chip filtering (TFLT). The ISL6146 fault detection circuitry pulls
down this pin to GND as it detects a fault or a disabled input (EN = ‘0’ or EN = ‘1’).
Different types of faults and their detection mechanisms are discussed in more detail on page 17. These faults include:
a. GATE is OFF (GATE < VIN +0.2V) when enabled [this condition is not reported on the ISL6146D and ISL6146E]
b. VIN-VOUT > 0.57V when ON.
c. FET G-D or G-S or D-S shorts.
d. VIN < PORL2H
e. VIN < VOUT
f. Over-Temperature
Range: 0 to VOUT
7
ADJ
Resistor programmable VIN - VOUT Voltage Threshold (Vth) of the High Speed Comparator. This pin is either directly
connected to VOUT or can be connected through a 5kΩ to 100kΩ resistor to GND. Allows for adjusting the voltage difference
threshold to prevent unintended turn-off of the pass FET due to normal system voltage fluctuations.
Range: 0.4 to VOUT
8
VOUT
The second sensing node for external FET control and connected to the Load side (OR-ing MOSFET Drain). This is the
common connection point for multiple paralleled supplies. VOUT is compared to VIN to determine when the OR-ing FET has
to be turned off. Range: 0V to 24V
PAD
Thermal Pad Connect to GND
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
TEMP RANGE
(°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
ISL6146AFUZ
6146A
-40 to +125
8 Ld MSOP
M8.118
ISL6146AFUZ-T
6146A
-40 to +125
8 Ld MSOP Tape and Reel
M8.118
ISL6146AFUZ-T7A
6146A
-40 to +125
8 Ld MSOP Tape and Reel
M8.118
ISL6146AFUZ-TK
6146A
-40 to +125
8 Ld MSOP Tape and Reel
M8.118
ISL6146AFRZ
46AF
-40 to +125
8 Ld 3x3 DFN
L8.3x3J
ISL6146AFRZ-T
46AF
-40 to +125
8 Ld 3x3 DFN Tape and Reel
L8.3x3J
ISL6146AFRZ-T7A
46AF
-40 to +125
8 Ld 3x3 DFN Tape and Reel
L8.3x3J
ISL6146AFRZ-TK
46AF
-40 to +125
8 Ld 3x3 DFN Tape and Reel
L8.3x3J
ISL6146BFUZ
6146B
-40 to +125
8 Ld MSOP
M8.118
ISL6146BFUZ-T
6146B
-40 to +125
8 Ld MSOP Tape and Reel
M8.118
ISL6146BFUZ-T7A
6146B
-40 to +125
8 Ld MSOP Tape and Reel
M8.118
ISL6146BFUZ-TK
6146B
-40 to +125
8 Ld MSOP Tape and Reel
M8.118
ISL6146BFRZ
46BF
-40 to +125
8 Ld 3x3 DFN
L8.3x3J
ISL6146BFRZ-T
46BF
-40 to +125
8 Ld 3x3 DFN Tape and Reel
L8.3x3J
ISL6146BFRZ-T7A
46BF
-40 to +125
8 Ld 3x3 DFN Tape and Reel
L8.3x3J
ISL6146BFRZ-TK
46BF
-40 to +125
8 Ld 3x3 DFN Tape and Reel
L8.3x3J
ISL6146CFUZ
6146C
-40 to +125
8 Ld MSOP
M8.118
3
FN7667.4
April 26, 2013
ISL6146
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
(Continued)
PART
MARKING
TEMP RANGE
(°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
ISL6146CFUZ-T
6146C
-40 to +125
8 Ld MSOP Tape and Reel
M8.118
ISL6146CFUZ-T7A
6146C
-40 to +125
8 Ld MSOP Tape and Reel
M8.118
ISL6146CFUZ-TK
6146C
-40 to +125
8 Ld MSOP Tape and Reel
M8.118
ISL6146CFRZ
46CF
-40 to +125
8 Ld 3x3 DFN
L8.3x3J
ISL6146CFRZ-T
46CF
-40 to +125
8 Ld 3x3 DFN Tape and Reel
L8.3x3J
ISL6146CFRZ-T7A
46CF
-40 to +125
8 Ld 3x3 DFN Tape and Reel
L8.3x3J
ISL6146CFRZ-TK
46CF
-40 to +125
8 Ld 3x3 DFN Tape and Reel
L8.3x3J
ISL6146DFUZ
6146D
-40 to +125
8 Ld MSOP
M8.118
ISL6146DFUZ-T
6146D
-40 to +125
8 Ld MSOP Tape and Reel
M8.118
ISL6146DFUZ-T7A
6146D
-40 to +125
8 Ld MSOP Tape and Reel
M8.118
ISL6146DFUZ-TK
6146D
-40 to +125
8 Ld MSOP Tape and Reel
M8.118
ISL6146DFRZ
46DF
-40 to +125
8 Ld 3x3 DFN
L8.3x3J
ISL6146DFRZ-T
46DF
-40 to +125
8 Ld 3x3 DFN Tape and Reel
L8.3x3J
ISL6146DFRZ-T7A
46DF
-40 to +125
8 Ld 3x3 DFN Tape and Reel
L8.3x3J
ISL6146DFRZ-TK
46DF
-40 to +125
8 Ld 3x3 DFN Tape and Reel
L8.3x3J
ISL6146EFUZ
6146E
-40 to +125
8 Ld MSOP
M8.118
ISL6146EFUZ-T
6146E
-40 to +125
8 Ld MSOP Tape and Reel
M8.118
ISL6146EFUZ-T7A
6146E
-40 to +125
8 Ld MSOP Tape and Reel
M8.118
ISL6146EFUZ-TK
6146E
-40 to +125
8 Ld MSOP Tape and Reel
M8.118
ISL6146EFRZ
46EF
-40 to +125
8 Ld 3x3 DFN
L8.3x3J
ISL6146EFRZ-T
46EF
-40 to +125
8 Ld 3x3 DFN Tape and Reel
L8.3x3J
ISL6146EFRZ-T7A
46EF
-40 to +125
8 Ld 3x3 DFN Tape and Reel
L8.3x3J
ISL6146EFRZ-TK
46EF
-40 to +125
8 Ld 3x3 DFN Tape and Reel
L8.3x3J
ISL6146AEVAL1Z
ISL6146A Evaluation Board (If desired with ISL6146D, please contact support)
ISL6146BEVAL1Z
ISL6146B Evaluation Board (If desired with ISL6146E, please contact support)
ISL6146CEVAL1Z
ISL6146C Evaluation Board
ISL6146DEVAL1Z
1 pair of ISL6146D Mini Development Boards (If desired with ISL6146A, please contact support)
ISL6146EEVAL1Z
1 pair of ISL6146E Mini Development Boards (If desired with ISL6146B, please contact support)
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL6146. For more information on MSL please see techbrief TB363.
4
FN7667.4
April 26, 2013
ISL6146
Table of Contents
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Typical Performance Curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Power-Up Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Typical Applications Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
ISL6146 Evaluation Platforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Description and Use of the Evaluation Boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
L8.3x3J. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
M8.118 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
5
FN7667.4
April 26, 2013
ISL6146
Absolute Maximum Ratings
Thermal Information
BIAS, VIN, VOUT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +24V
GATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 40V
EN, EN, UVLO, OVP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +24V
ADJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VOUT
FAULT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VOUT
ESD Rating
Human Body Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . .2.5kV
Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . 250V
Latch Up (Tested per JESD-78B; Class 2, Level A) . . . . . . . . . . . . . . 100mA
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
MSOP Package (Notes 4, 7) . . . . . . . . . . . .
140
41
DFN Package (Notes 5, 6) . . . . . . . . . . . . . .
46
5
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Recommended Operating Conditions
Bias Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3V to +20V
OR’d Supply Voltage Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1V to BIAS
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
5. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
6. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
7. For θJC, the “case temp” location is taken at the package top center
Electrical Specifications
temperature range, -40°C to +125°C.
SYMBOL
VCC = BIAS = 12V, unless otherwise stated. TA = +25°C to +85°C. Boldface limits apply over the operating
PARAMETERS
TEST CONDITIONS
MIN
(Note 8)
TYP
MAX
(Note 8)
UNITS
1.9
2.5
2.95
V
BIAS
PORL2H
PORHYS
POR Rising
BIAS Rising, GATE Rising
POR Hysteresis
189
mV
IBIAS_en_18
ISL6146A/B/D/E BIAS Current
BIAS, VIN = 18V, ADJ, VOUT = 16.98V, enabled
3.6
5
mA
IVIN_en_18
ISL6146A/B/D/E VIN Current
BIAS, VIN = 18V, ADJ, VOUT = 16.98V, enabled
25
40
µA
IVIN_en_18
ISL6146C VIN Current
VIN = 18V, ADJ, VOUT = 16.98V, enabled
3
4.5
mA
IVOUT_en_18
ISL6146A/B/D/E VOUT Current
BIAS, VIN = 18V, VOUT = 16.98V, enabled
14
20
µA
VOUT_en_18
ISL6146C VOUT Current
VIN = 18V, VOUT = 16.98V, enabled
400
500
µA
IBIAS_den_18
ISL6146A/B/D/E BIAS Current
BIAS, VIN = 18V, ADJ, VOUT = 16.98V, disabled
1.7
3
mA
IVIN_den_18
ISL6146A/B/D/E VIN Current
BIAS, VIN = 18V, ADJ, VOUT = 16.98V, disabled
27
37
µA
IVIN_den_18
ISL6146C VIN Current
VIN = 18V, ADJ, VOUT = 16.98V, disabled
1.3
1.5
mA
IVOUT_den_18 ISL6146A/B/D/E VOUT Current
BIAS, VIN = 18V, VOUT = 16.98V, disabled
14
20
µA
IVOUT_den_18 ISL6146C VOUT Current
VIN = 18V, VOUT = 16.98V, disabled
385
500
µA
BIAS to GATE Delay
BIAS > PORL2H to GATE Rising
150
210
µs
VGH_3
Charge Pump Voltage
VIN, BIAS = 3V VIN - VOUT > VFWD_VR
VIN+5V
VIN +7V
VIN+10.5V
V
VGH_12
Charge Pump Voltage
VIN, BIAS = 12V VIN - VOUT > VFWD_VR
VIN+9V
VIN +10V
VIN+17.5V
V
VGH_18
VIN+9V
VIN +10V
VIN+18V
V
0
0.1
V
13
mA
tBIAS2GTE
GATE
Charge Pump Voltage
VIN, BIAS = 18V VIN - VOUT > VFWD_VR
VGL
Low Voltage Level
VIN - VOUT < 0V
IPDL
Low Pull-Down Current
VIN = 12V, VOUT = 12.2V ADJ = 11V
5
8.4
IPDH
High Pull-Down Current
VIN falling from 12V to 10V in 2µs
3.5
6.5
ttoff
Fast Turn-off Time
VIN = VBIAS = 12V, VGATE = 18V to 10V,
CGATE = 57nF
6
65
A
130
ns
FN7667.4
April 26, 2013
ISL6146
Electrical Specifications
VCC = BIAS = 12V, unless otherwise stated. TA = +25°C to +85°C. Boldface limits apply over the operating
temperature range, -40°C to +125°C. (Continued)
SYMBOL
PARAMETERS
TEST CONDITIONS
MIN
(Note 8)
TYP
MAX
(Note 8)
UNITS
80
µs
ttoffs
Slow Turn-off Time
VIN = VBIAS = 12V, VGATE = 18V to 10V,
CGATE = 57nF
58
ION
Turn-On Current
BIAS = 12V, VG = 0V
1
mA
BIAS = 12V, VG = 20V
0.15
mA
VVG_FLTr
GATE to VIN Rising Fault Voltage
GATE > VIN, enabled, FLT output is high.
(Does not apply to ISL6146D and ISL6146E)
320
440
560
mV
VVG_FLTf
GATE to VIN Falling Fault Voltage
GATE > VIN, enabled, FLT output is low.
(Does not apply to ISL6146D and ISL6146E)
140
220
300
mV
CONTROL AND REGULATION I/O
VRr
Reverse Voltage Detection
Rising VOUT Threshold
VOUT rising
35
57
79
mV
VRf
Reverse Voltage Detection
Falling VOUT Threshold
VOUT falling
10
30
51
mV
tRs
Reverse Voltage Detection Response
Time
VFWD_VR
Amplifier Forward Voltage Regulation
VOS_HS
VTH(HS5k)
VTH(HS100k)
tHSpd
10
ISL6146 controls voltage across FET VDS to
VFWD_VR during static forward operation at loads
resulting in Id*rDS(ON) < VFWD_VR
HS Comparator Input Offset Voltage
ADJ Adjust Threshold with 5k to GND
RADJ = 5kΩ to GND
ADJ Adjust Threshold with 100k to GND RADJ = 100kΩ to GND
HS Comparator Response Time
11
19
28
mV
-14
0.7
14
mV
0.57
0.8
1.1
V
10
40
95
mV
VOUT > VIN, 1ns transition, 5V differential
VFWD_FLT
VIN to VOUT Forward Fault Voltage
VIN > VOUT, GATE is fully on, FLT output is low
VFWD_FLT_HYS
VIN to VOUT Forward Fault Voltage
Hysteresis
VIN > VOUT, GATE is fully on, FLT output is high
IFLT_SINK
FAULT Sink Current
BIAS = 18V FAULT = 0.5V, VIN < VOUT, VGATE = VGL
IFLT_LEAK
FAULT Leakage Current
FAULT = “VFLT_H”, VIN > VOUT, VGATE = VIN + VGQP
tFLT_L2H
FAULT Low to High Delay
tFLT_H2L
FAULT High to Low Delay
µs
170
330
450
ns
570
mV
44
mV
9
mA
FAULT OUTPUT
5
0.04
10
µA
GATE = VGQP to FAULT output is high
10
23
µs
GATE = VIN to FAULT output is low
1.7
3
µs
606
631
mV
ENABLE UVLO/OVP/ADJ INPUTS
VthRa
VthR_hysa
VthFb
VthF_hysb
VthFc
VthF_hysc
VthRc
ISL6146A/D EN Rising Vth
580
ISL6146A/D EN Vth Hysteresis
ISL6146B/E EN Falling Vth
-90
580
ISL6146B/E EN Vth Hysteresis
ISL6146C OVP Falling Vth
631
+90
580
ISL6146C OVP Vth Hysteresis
ISL6146C UVLO Rising Vth
606
mV
606
mV
631
+90
580
606
mV
mV
mV
631
mV
VthR_hysc
ISL6146C UVLO Vth Hysteresis
-90
tEN2GTER
EN/UVLO Rising to GATE Rising Delay
10
12
µs
EN/OVP Falling to GATE Rising Delay
9
12
µs
7
mV
FN7667.4
April 26, 2013
ISL6146
Electrical Specifications
VCC = BIAS = 12V, unless otherwise stated. TA = +25°C to +85°C. Boldface limits apply over the operating
temperature range, -40°C to +125°C. (Continued)
SYMBOL
tEN2GTEF
PARAMETERS
TEST CONDITIONS
MIN
(Note 8)
TYP
MAX
(Note 8)
UNITS
EN/UVLO Falling to GATE Falling Delay
2
4
µs
EN/OVP Rising to GATE Falling Delay
2
4
µs
Ren_h
ENABLE Pull-Down Resistor
ISL6146A, ISL6146D
2
MΩ
Ren_l
ENABLE Pull-Up Resistor
ISL6146B, ISL6146E
2
MΩ
Vadj
ADJ Pin Voltage
RADJ 5kΩ to 100kΩ
0.4
V
Radj
ADJ Pull-Up Resistor
Internal ADJ Pull-up Resistor to VOUT
3.85
MΩ
OTS
Over-Temperature Sense
Fault signals in operation
140
°C
20
°C
Fault signals upon enabling
125
°C
OTSHYS
HTS
Over-Temperature Sense Hysteresis
High Temperature Sense
NOTE:
8. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
8
FN7667.4
April 26, 2013
ISL6146
Typical Performance Curves
4.0
3.0
2.0
18V DISABLED
12V DISABLED
3V DISABLED
35
12V ENABLED
30
3V ENABLED
25
20
18V DISABLED
12V DISABLED
3V DISABLED
VOUT CURRENT
15
1.5
1.0
18V ENABLED
VIN CURRENT
VIN/VOUT CURRENT (mA)
IBIAS/IVIN CURRENT (mA)
3.5
2.5
40
18V ENABLED
12V ENABLED
3V ENABLED
-40
25
85
TEMPERATURE (°C)
10
125
FIGURE 3. ISL6146A/B/D/E BIAS AND ISL6146C VIN CURRENT vs
TEMPERATURE
-40
25
85
TEMPERATURE (°C)
125
FIGURE 4. ISL6146A/B/C/D/E VIN AND VOUT CURRENT vs
TEMPERATURE
35
2.60
BIAS = 18V
2.55
2.50
BIAS = 12V
25
POR Vth RISING
2.45
VPOR Vth (V)
HARD ON GATE VOLTAGE (V)
30
20
15
BIAS = 3V
10
2.40
2.35
2.30
2.25
POR Vth FALLING
2.20
2.15
5
2.10
0
-40
25
85
2.05
125
-40
TEMPERATURE (°C)
25
85
125
TEMPERATURE (°C)
FIGURE 5. GATE VOLTAGE vs TEMPERATURE
FIGURE 6. POR Vth RISING AND FALLING VOLTAGE
0.74
0.70
0.72
0.65
EN DEASSERT RISING Vth
0.70
EN ASSERT RISING Vth
0.68
0.55
EN Vth (V)
EN Vth (V)
0.60
EN DEASSERT FALLING Vth
0.50
0.66
0.64
0.62
0.60
EN ASSERT FALLING Vth
0.58
0.45
0.56
0.40
0.54
-40
25
85
TEMPERATURE (°C)
FIGURE 7. ISL6146A/D EN Vth vs TEMPERATURE
9
125
-40
25
85
125
TEMPERATURE (°C)
FIGURE 8. ISL6146B/E EN Vth vs TEMPERATURE
FN7667.4
April 26, 2013
ISL6146
Typical Performance Curves (Continued)
750
1.3
VG = 0V
OVP RISING
GATE TURN-ON CURRENT (mA)
OVP AND UVLO Vth (mV)
700
650
600
UVLO RISING AND OVP FALLING
550
500
1.1
0.9
0.7
0.5
0.3
UVLO FALLING
450
-40
25
85
TEMPERATURE (°C)
0.1
125
7.0
10
6.5
9
6.0
5.5
5.0
4.5
4.0
3.5
3.0
8
7
6
5
4
3
2
-40
25
85
TEMPERATURE (°C)
0
125
FIGURE 11. GATE HARD TURN-OFF CURRENT
-40
25
85
TEMPERATURE (°C)
125
FIGURE 12. GATE SLOW TURN-OFF CURRENT
56.0
45
55.5
40
55.0
RESPONSE TIME (µs)
REVERSE DETECTION VOLTAGE (mV)
125
1
2.5
2.0
25
85
TEMPERATURE (°C)
FIGURE 10. GATE TURN-ON CURRENT VIN = 12V
GATE PULL-DOWN CURRENT (mA)
GATE PULL-DOWN CURRENT (A)
FIGURE 9. ISL6146C UVLO/OVP Vth vs TEMPERATURE
-40
54.5
54.0
53.5
35
30
25
53.0
20
52.5
52.0
-40
25
85
TEMPERATURE (°C)
125
FIGURE 13. INCREASING REVERSE VOLTAGE DETECTION Vth
10
15
-40
25
85
TEMPERATURE (°C)
125
FIGURE 14. REVERSE VOLTAGE RESPONSE TIME
FN7667.4
April 26, 2013
ISL6146
Typical Performance Curves (Continued)
3
300
280
260
RESPONSE TIME (ns)
OFFSET VOLTAGE (mV)
2
1
0
-1
240
220
200
180
160
140
-2
120
-3
-40
25
85
TEMPERATURE (°C)
100
125
FIGURE 15. HIGH SPEED COMPARATOR OFFSET VOLTAGE
700
1.000
600
0.999
RELATIVE %
HS COMP ADJUST VTH (mV)
1.001
RADJ TO GND = 5kΩ
500
400
300
200
0.998
0.997
0.996
0.995
RADJ TO GND = 100kΩ
100
-40
25
85
TEMPERATURE (°C)
0.994
125
FIGURE 17. HS COMPARATOR ADJUSTABLE Vth
0.993
3
12
BIAS VOLTAGE (V)
18
FIGURE 18. EN/EN/OVP/UVLO Vth DELTA vs BIAS VOLTAGE
NORMALIZED TO BIAS = 12V
21.0
465
20.8
460
20.6
VIN - VOUT FAULT VTH (mV)
VIN TO VOUT FWD VOLTAGE REG (mV)
125
1.002
800
20.4
20.2
20.0
19.8
19.6
19.4
455
450
445
440
435
430
425
19.2
19.0
25
85
TEMPERATURE (°C)
FIGURE 16. HIGH SPEED COMPARATOR RESPONSE TIME
900
0
-40
-40
25
85
TEMPERATURE (°C)
FIGURE 19. FORWARD VOLTAGE REGULATION
11
125
420
-40
25
85
TEMPERATURE (°C)
125
FIGURE 20. VIN TO VOUT FORWARD FAULT VOLTAGE
FN7667.4
April 26, 2013
ISL6146
Typical Performance Curves (Continued)
GATE 2
GATE1
GATE 2
GATE1
IIN2
IIN1
IIN1
IIN2
FIGURE 21. ISL6146C SLOW RAMP CONNECT 12V OR-ing
GATE1
GATE 2
FIGURE 22. ISL6146C SLOW RAMP DISCONNECT 12V OR-ing
GATE 2
GATE1
IIN2
IIN1
IIN2
IIN1
FIGURE 23. ISL6146C HOT SWAP CONNECT 12V OR-ing
FIGURE 24. ISL6146C HOT DISCONNECT 12V OR-ing
GATE
GATE
EN/UVLO
EN/UVLO
FIGURE 25. ISL6146A/D EN/ISL6146C UVLO TO GATE ON DELAY
12
FIGURE 26. ISL6146A/D EN/ISL6146C UVLO TO GATE OFF DELAY
FN7667.4
April 26, 2013
ISL6146
Typical Performance Curves (Continued)
GATE
GATE
EN
EN
FIGURE 27. ISL6146B/E EN TO GATE ON DELAY
FIGURE 28. ISL6146B/E EN TO GATE OFF DELAY
GATE
OVP
OVP
GATE
FIGURE 29. ISL6146C OVP TO GATE ON DELAY
VIN RISING THROUGH BOTH THE PROGRAMMED UVLO
AND OVP LEVELS. GATE TURNS-ON AS VIN EXCEEDS 10V
THEN TURNS-OFF AS VIN EXCEEDS 15V
FIGURE 30. ISL6146C OVP TO GATE OFF DELAY
VIN FALLING THROUGH BOTH THE PROGRAMMED OVP
AND UVLO LEVELS. GATE TURNS-ON AS VIN > 13V THEN
TURNS-OFF AS VIN > 8.3V
VIN
GATE
FIGURE 31. ISL6146C RISING VIN, UVLO AND OVP FUNCTION
13
GATE
VIN
FIGURE 32. ISL6146C FALLING, VIN OVP AND UVLO FUNCTION
FN7667.4
April 26, 2013
ISL6146
Typical Performance Curves (Continued)
VIN RISING TO <2.5V WHEN
GATE BECOMES ACTIVE
GGATE
AT E
VIN
V IN
VOUT
VO
UT
GATE
VIN
FIGURE 33. BACK-TO-BACK FET TURN_ON DETAIL
GATE FAST OFF, ~200ns FALL TIME
~70ns FROM 20V TO 12.6V ACROSS 57nF
GATE OUTPUT SINKING ~ 6A
FIGURE 34. ISL6146 RISING POR Vth
VOUT
HIGH SPEED COMPARATOR Vth = VOS(HS)
GATE1
VIN1 SHORTED
TO GND
GATE2
FIGURE 35. FAST GATE TURN-OFF WITH 57nF GATE
VOUT
HIGH SPEED COMPARATOR Vth = 800mV
GATE1
FIGURE 36. RESPONSE TO VIN SHORTED TO GND WITH ADJ
SHORTED TO VOUT
VOUT
HIGH SPEED COMPARATOR Vth = 40mV
GATE1
VIN1 SHORTED
TO GND
VIN1 SHORTED
TO GND
GATE2
GATE2
FIGURE 37. RESPONSE TO VIN SHORTED TO GND WITH
ADJ 5kΩ TO GND
14
FIGURE 38. RESPONSE TO VIN SHORTED TO GND WITH
ADJ 100kΩ TO GND
FN7667.4
April 26, 2013
ISL6146
Typical Performance Curves (Continued)
VIN
VIN
VOUT
FLT
GATE
VIN - VOUT
FIGURE 40. FAULT ASSERTING VIN TO VOUT > VFWD_FLT
35
40
30
35
25
% OF DISTRIBUTION
% OF DISTRIBUTION
FIGURE 39. VIN HOT SWAPPED TO GATE WITH BIAS = 12V NO LOAD
20
15
10
25
20
15
10
5
0
30
5
-1
0
1
2
3
4
5
HS COMP ADJUST VTH (mV)
6
7
FIGURE 41. HIGH SPEED COMPARATOR OFFSET VOLTAGE
DISTRIBUTION
0
17
18
19
20
VFWD_VR (mV)
21
22
FIGURE 42. FORWARD REGULATION VOLTAGE DISTRIBUTION
40
35
+
VDS
% OF DISTRIBUTION
30
0V
VR
25
tHSpd
20
15
20V
VGATE
10
5
0
12.6V
50
52
54
56
58
60
62
64
66
68
VRr (mV)
FIGURE 43. REVERSE DETECTION RISING VOLTAGE DISTRIBUTION
15
VBIAS = VIN = 12V
tOFF
FIGURE 44. FAST RAMP REVERSE PROTECTION TIMING DIAGRAM
FN7667.4
April 26, 2013
ISL6146
Typical Performance Curves (Continued)
FLT
FLT
GATE
GATE
VIN
VIN
FIGURE 45. ISL6146A FLT RESPONSE TO NON-CONDUCTION
16
FIGURE 46. ISL6146D FLT RESPONSE TO NON-CONDUCTION
FN7667.4
April 26, 2013
ISL6146
Functional Description
Functional Overview
In a redundant power distribution system, similar potential and
parallel power supplies each contribute to the load current
through various active and passive current sharing schemes.
Typically OR-ing power diodes are used to protect against reverse
current flow in the event that one of the power supplies falls
below the common bus voltage or develops a catastrophic
failure. However, using a discrete OR-ing diode solution has some
significant drawbacks. The primary downside is the increased
power dissipation loss in the OR-ing diodes as system power
requirements increase. At the lowest voltages where the ISL6146
is designed for use, the voltage distribution losses across an
OR-ing diode can be a significant percentage, in some cases
approaching 70%. Another disadvantage when using an OR-ing
diode is failure to detect a shorted or opened current path, which
jeopardizes system power availability and reliability. An open
diode may reduce the system to a single point of failure while a
shorted diode eliminates the system’s power protection.
Using an active OR-ing FET controller, such as the ISL6146, helps
with these potential issues. The use of a low on-resistance FET as
the OR-ing component allows for a more efficient system design
as the voltage across the FET is much lower than that across a
forward biased diode. Additionally, the ISL6146 has a dedicated
fault (FAULT) output pin that indicates when there is a conditional
or FET fault short providing the diagnostic capability that a diode
is unable to.
The ISL6146 is designed to OR together voltages as low as 1V
when supplied with a separate bias supply of 3V or greater.
Otherwise, the ISL6146 is designed to be biased from and OR
voltages across the 3V to 20V nominal supply range.
In a single FET configuration as voltage is first applied to a VIN
pin, the FET body diode conducts providing all the ISL6146s
connected on a common bus circuit, bias via the VOUT pins. As
individual power supply voltages ramp up in excess of the rising
POR threshold, the ISL6146’s internal charge pump activates to
provide a floating gate drive voltage for the external N-channel
OR-ing MOSFET, thus turning the FETs on once VIN > VOUT. The
ISL6146 continuously monitors the drain and source of the
OR-ing FET and provides a reverse voltage (N-channel MOSFET
VOUT - VIN) detection threshold (VR) that, when exceeded,
indicates a reverse current condition. Once this threshold is
exceeded, the ISL6146 turns off the OR-ing FET by pulling down
the GATE pin to GND. The ISL6146 also provides high speed
VOUT > VIN transient protection as in the case of a catastrophic
VIN failure. The ISL6146 additionally provides for adjustment of
the VIN - VOUT reverse voltage Vth(VR Vth) via the ADJ pin of the
ISL6146 with an external resistor to GND. This allows adjusting
the VIN - VOUT voltage threshold level to compensate for normal
system voltage fluctuations, thus eliminating unnecessary
reaction by the ISL6146.
The total VIN - VOUT VR Vth is the sum of both the internal offset
and the external programmed VR Vth.
17
In the event of a VOUT > VIN condition, the ISL6146 responds
either with a high or low current pull-down on the GATE pin
depending on whether the High Speed comparator (HSCOMP)
has been activated or not. The HSCOMP determines if the VR
occurred within 1μs, by continuously monitoring the FET VDS and
if so, the high pull-down current is used to turn off the OR-ing FET.
In the event of a falling VIN transition in <1μs, (i.e., a catastrophic
failure of the power source) the HSCOMP protects the common
bus from the individual faulted power supply short by turning off
the shorted supply’s OR-ing MOSFET in less than 300ns, ensuring
the integrity of the common bus voltage from reverse current to
the damaged supply.
Once the correct VIN > VOUT relationship is established again, the
ISL6146 again turns on the FET.
The FAULT pin is an open drain, active low output indicating that
a fault or specific condition has occurred, these include:
• GATE is OFF (GATE < VIN+0.2V). Lack of conduction, not a fault,
just not on. ISL6146D and ISL6146E do not respond to this
condition
• Faults resulting in VIN - VOUT > 0.57V when ON
• An open FET resulting in body diode conduction
• Excessive current through FET
• FET Faults monitored and reported include
- G-D, gate unable to drive to Q-pump voltage
- G-S, gate unable to drive to Q-pump voltage
- D-S shorts, when GATE is OFF VDS < 2V
- VIN < POR
- Missing VIN
- VIN shorted to GND
On the ISL6146C version, a conditional fault is also signalled if
the VIN is not within the programmed UVLO and OVP levels.
The ISL6146 has an on-chip over-temperature fault threshold of
~+140°C with a 20°C hysteresis. Although the ISL6146 itself
produces little heat, it senses the environment in which it is,
likely including a close by FET.
The ISL6146A/D and ISL6146B/E are functional variants with an
enabling input of either polarity. This feature is used when the
need to interrupt the current path via signaling is necessary. This
is accomplished by implementing two FETs in series so that there
is a body diode positioned to block current in either direction.
This functionality is considered an additional enhancement to
the OR-ing diode it replaces.
The ISL6146C employs the use of a programmable Undervoltage
Lock Out (UVLO) and a programmable Overvoltage Protection (OVP)
input. This allows the GATE to only turn-on when the monitored
voltage is between the programmed lower and upper levels. This
application would use the back-to-back FET configuration. In the
event that the current path does not need to be interrupted then the
EN, UVLO and OVP inputs can all be overridden.
The ISL6146D and ISL6146E are variants of the ISL6146A and
ISL6146B respectively, the difference being the former do not
respond to a nonconduction condition (when enabled and
VIN>VOUT, the GATE is not on) unlike the latter that do signal
a fault.
FN7667.4
April 26, 2013
ISL6146
Applications Information
Power-Up Considerations
BIAS AND VIN CONSTRAINTS
Upon power-up when the VIN supply is separate from the BIAS
supply, the BIAS voltage must be greater or equal to the VIN
voltage at all times.
When using a single supply for both the ISL6146 bias and the
OR-ing supply, the VIN and BIAS pins can be configured with a low
value resistor between the two pins to provide some isolation and
decoupling to support the chip bias even as the OR’d supply
experiences voltage droops and surges. Although not necessary
to do so, it is a best design practice for particularly noisy
environments.
FET TO IC LAYOUT RECOMMENDATIONS
Connections from the FET(s) to the ISL6146 VIN and VOUT pins
must be Kelvin in nature and as close to the FET drain and source
PCB pads as possible to eliminate any trace resistance errors
that can occur with high currents. This connection placement is
most critical to providing the most accurate voltage sensing
particularly when the back-to-back FET configuration is used.
Likewise, connections from OVP, UVLO and ADJ are also critical to
optimize accuracy.
ADJUSTING THE HS COMPARATOR REVERSE VOLTAGE
THRESHOLD
The ISL6146 allows adjustment of the HS Comparator reverse
voltage detection threshold (VR Vth), the difference in VOUT - VIN.
There are two valid ADJ pin configurations:
1. ADJ connected to VOUT: This makes the HS comparator
threshold equal to the intrinsic error in the HS comparator
input. This is the default condition and the most likely used
configuration.
2. A single resistor is connected from ADJ pin to ground:
Making the HS comparator threshold = VOUT - 4k/RADJ.
So, for a 100kΩ REXT, HS Comparator threshold = 40mV below
VOUT and for a 5kΩ REXT HS comparator threshold = ~ 800mV
below VOUT.
The recommended resistor range is 5kΩ to 100kΩ for this
voltage adjustment.
At power-up, the HS comparator threshold is default set to the
internal device error first, and then released to the user
programmed threshold after the related circuits are ready. It
takes ~20μs for the circuit to switch from the default setting to
the user programmed threshold after a POR startup.
The current out of the ADJ pin with a resistor to GND is equal to
0.4V/REXT.
BACK-TO-BACK FET CONFIGURATION
When using the back-to-back FET configuration, the FET choice
must be such that the voltage across both FETs at full current
loading be less than the minimum forward voltage fault
threshold of 400mV to avoid unintended fault notification.
In this configuration, it may be tempting to use the enable inputs
to force a path by switching between the two as opposed to
having both paths on, and having the higher voltage source
provide current. The problem with that is the timing of the FETs
on and off, so that excessive VOUT voltage droop is not introduced
if the turn-off happens faster, or before the (or a slower) turn-on
momentarily leaves the load with an inadequate power
connection.
Typical Applications Circuits
There are four basic configurations that the ISL6146 can be
used in:
1. For voltages >3V where the BIAS and VIN are common
2. For a very low OR-ing voltage, <3V operation, BIAS >3V
3. For a voltage window compliant operation and,
4. For a signaled operation where the current path is controlled
by an input signal or minimum voltage condition.
Each of these configurations can be tailored for the High Speed
Comparator (HS COMP) reverse threshold via the ADJ input being
connected either to VOUT or to GND via a resistor as previously
explained. Additionally, the voltage window is adjustable for both
a minimum and maximum operating voltage via the UVLO and
OVP inputs and a resistor divider also explained earlier. Also,
soft-start and turn-on and turn-off characteristics can be tailored
to suit.
The three evaluation platforms provided demonstrate the four
basic configurations and provide for the additional tailoring of
the various performance characteristics.
BIAS
VOLTAGE
>3V
+
Q1
C
O
M
M
O
N
+
VERY LOW
VOLTAGE
DC - DC
(1V-3V)
VIN
BIAS
EN
GATE
VOUT
P
O
W
E
R
ADJ
ISL6146A
FLT
B
U
S
GND
-
+
Q2
C
O
M
M
O
N
+
VIN
VERY LOW
VOLTAGE
DC - DC
(1V-3V)
GATE
BIAS
VOUT
P
O
W
E
R
ADJ
ISL6146A
FLT
B
U
S
EN
GND
FIGURE 47. LOW VOLTAGE APPLICATION DIAGRAM
18
FN7667.4
April 26, 2013
ISL6146
The Figure 1 circuit shown on page 1 is the basic circuit used for
OR-ing voltages >3V to 20V.
The ISL6146A application shown in Figure 47 is the configuration
for OR-ing very low voltages of 1V to 3V. Additionally, this
application shows the utilization of the ADJ input with a single
resistor tied to GND. This provides the user a programmable level
of VOUT > VIN before the High Speed (HS) Comparator is activated
and the GATE output is pulled down to allow for normal voltage
fluctuations in the system.
Notice that in both of these circuits, the EN or EN inputs are
defaulted to enabled and have no current path on/off control.
Failure to do so correctly will result in only body diode conduction
and a resulting fault indication.
The VIN and VOUT to FET and GND to ADJ connections are drawn
to emphasize the Kelvin connection necessary to correctly
monitor the voltage across the FET, and for the VR Vth monitor to
eliminate any stray resistance effects.
Q1
Q2
VOUT
GATE
UVLO
VOLTAGE
DC - DC
3V-20V
ADJ
ISL6146C
FLT
OVP
P
O
W
E
R
-
+
Q4
C
O
M
M
O
N
+
VIN
VOLTAGE
DC - DC
3V-20V
GATE
UVLO
VOUT
ADJ
ISL6146C
FLT
OVP
GND
P
O
W
E
R
B
U
S
-
FIGURE 48. TYPICAL ISL6146C APPLICATION DIAGRAM
The ISL6146C application shown in Figure 48 is limited to the 3V
to 20V VIN range and must implement the back-to-back FET
configuration to utilize the UVLO and OVP inputs and capabilities.
As the VIN voltage rises above the minimum programmed
voltage, the related OR-ing FETs will turn on and stay on until
either the minimum voltage requirement is no longer met or the
VIN voltage exceeds its programmed maximum. The minimum
and maximum programmed voltage levels are done with the
resistor divider on the UVLO and OVP pins. These levels should be
programmed to take into account conduction path losses to the
load in addition to the IC operational constraints.
When using the back-to-back FET configuration, the user must
chose FETs to ensure (2rDS(ON) + PCB IR) ILOAD < 0.5V to avoid
tripping the VIN - VOUT > 0.5V when ON fault.
19
Q2
+
C
O
M
M
O
N
+
VERY LOW
VOLTAGE
DC - DC
(1V-BIAS)
VIN
VOUT
GATE
BIAS
P
O
W
E
R
ADJ
ISL6146A/B
FLT
GND
EN/EN
-
ENABLED
WHEN
SIGNALED
B
U
S
+
Q3
Q4
C
O
M
M
O
N
+
GATE
VIN
C
O
M
M
O
N
B
U
S
GND
Q3
Q1
+
+
VIN
DISTRIBUTED
VOLTAGE
>3V
VERY LOW
VOLTAGE
DC - DC
(1V-BIAS)
VOUT
BIAS
P
O
W
E
R
ADJ
ISL6146A/B
GND
-
FLT
EN/EN
ENABLED
WHEN
SIGNALED
B
U
S
FIGURE 49. CONTROLLED ON/OFF APPLICATION DIAGRAM
The application diagram in Figure 49 shows the ISL6146A or
ISL6146B utilizing the EN or EN pin as a signalled input to open
or close the conduction path from power supply to load. This
feature can be implemented on OR-ing 1V to 20V but is shown
for OR-ing <3V.
The enable input signaling can be simultaneous across the N+1
number of ISL6146s used.
Although not needed for thermal relief, connect the DFN EPAD
to GND.
SWITCH-OVER CIRCUITS
Switch over applications are different than OR-ing applications in
that, the former are looking for the presence of or a condition of
a preferred supply in order to switch to it. Whereas true OR-ing
consists of a redundant N+1 configuration with no preferred
source.
The following 2 circuits are simple single ISL6146 switchover
circuits optimized for situations particular to the VBATT and VEXT
voltages relative to each other. Figure 50 shows an ISL6146B
switchover circuit where VEXT, when present, is the preferred
source and VBATT could be lesser or greater than VEXT. This circuit
senses the presence of the preferred voltage supply to a
programmable threshold level that when exceeded, VEXT is
passed to the output as VBATT is disconnected from the output.
R1 & R2 program the VEXT level that must be preset for the
preferred voltage to be passed to the output.
Q3 is necessary if VBATT can ever exceed VEXT to prevent current
from flowing into VEXT when present. The body diode of Q3
FN7667.4
April 26, 2013
ISL6146
prevents that when Q1 is on regardless of the VBATT voltage.
The ISL6146 bias is pulled from the common drain node to
ensure an always adequate bias from either source when the
other is absent
Q1
VEXT
3.3V - 24V
SWITCHED
OUTPUT
Q2
Use when VBATT > VEXT
Q3 disconnects VBATT from
output when GATE is off.
Q3
VBATT
3.3V-20V
All of the scope shots were taken with a 5A load and 100µF of
bulk load capacitance.
Figure 52 is a ISL6146A switchover circuit to use where the
preferred VEXT source is always greater than the VBATT. Because
this is so, there is no need for a 3rd FET for blocking as in
Figure 50. Additionally, the preferred VEXT source when present
or at a programmed minimum threshold voltage via R1 and R2
divider will turn on Q2/turn-off Q1 but when absent or not
minimally adequate, will do the opposite. In this circuit, with the
ISL6146A not connected to the battery, and thus no constant IVIN
load on it, which allows for longer battery life.
Bias voltage is pulled from the common output to ensure an
always adequate IC bias from either source.
VIN
GATE
FLT
BIAS
R1
ISL6146B
EN
VOUT
GND
Q1
VBATT
ADJ
SWITCHED
OUTPUT
R3
Use when VBATT < VEXT
Q2
R2
VEXT
FIGURE 50. ISL6146B EXTERNAL SWITCHOVER SCHEMATIC
Figure 51 shows operational scope shots of the above circuit.
VIN
GATE
FLT
BIAS
R1
BATT SUPPLY
EXT SUPPLY
ISL6146A
EN
VOUT
ADJ
GND
R2
VOUT
FIGURE 53. ISL6146A EXTERNAL SWITCHOVER SCHEMATIC
GATE
BATT SUPPLY
EXT SUPPLY
VOUT
FIGURE 51. EXTERNAL SUPPLY < BATT SUPPLY CONNECTED
BATT SUPPLY
GATE
EXT SUPPLY
VOUT
FIGURE 54. EXTERNAL SUPPLY > BATT SUPPLY CONNECTED
GATE
FIGURE 52. EXTERNAL SUPPLY < BATT SUPPLY DISCONNECTED
20
FN7667.4
April 26, 2013
ISL6146
BATT SUPPLY
EXT SUPPLY
Figures 56 through 61 illustrate the three ISL6146 evaluation
boards for the three typical applications in photograph and
schematic form.
There are also 2 mini development boards named
ISL6146DEVAL1 and ISL6146EEVAL1. These boards are
provided as a matching pair of either the ISL6146D or ISL6146E
part type directly from the website or with either the ISL6146A or
ISL6146B installed from the factory (contact support if desired).
The small size (1” x 0.5”) is suitable for adding into an existing
circuit using another OR-ing FET controller. These small and
simple boards have only the necessary components for its
implementation utilizing the already present MOSFET(s) in the
circuit it is being added to.
VOUT
GATE
FIGURE 55. EXTERNAL SUPPLY > BATT SUPPLY DISCONNECTED
ISL6146 Evaluation Platforms
Description and Use of the Evaluation Boards
The three ISL6146 evaluation boards are used to demonstrate
the four application configurations discussed earlier. All the
boards have ADJ shorted to VOUT with the PCB layout having the
component footprints to insert a resistor of choice between ADJ
and GND to adjust the HS COMP Vth. Likewise, the VIN is
connected to BIAS but these can be separated to provide an
adequate BIAS voltage when OR-ing <3V supplies or if providing
a separate from VIN voltage to BIAS.
The mini evaluation circuit is designed to give the user the
flexibility in either defaulting or signaling the enable ON or to use
a VIN voltage threshold to turn-on the IC function.
Provided are access to the IC VIN, GATE and VOUT pins for best
practices connections to the MOSFET(s) along with adjustable HS
Vth via the ADJ pin and the FAULT output.
The mini evaluation circuit is documented in Figures 62 & 63 and
Table 2.
The ISL6146AEVAL1Z is configured to have a 8.5V minimum
turn-on threshold with a 1.2V hysteresis.
The ISL6146BEVAL1Z is configured as a minimally featured
maximum performance OR-ing FET controller for 3V to 20V.
The ISL6146CEVAL1Z is configured to operate with a 10.8V lower
turn on threshold and 14.9V upper turn-off threshold.
All three boards are equipped with 50A capable FETs for high
current evaluations and with a minimum of VIN and VOUT bulk
capacitance likely to be found in any power system design.
After determining the BIAS source along with VIN voltage criteria
and configuring the evaluation board if necessary, for the
application to be evaluated the board is ready for power.
Apply the BIAS voltage first (via the test points labeled BIAS), if
separate from VIN, then the VIN voltage. Monitor the provided
test points for device performance with current loads up to 50A.
21
FN7667.4
April 26, 2013
ISL6146
FIGURE 56. ISL6146AEVAL1Z
FIGURE 57. ISL6146AEVAL1Z SCHEMATIC
FIGURE 58. ISL6146BEVAL1Z
FIGURE 59. ISL6146BEVAL1Z SCHEMATIC
22
FN7667.4
April 26, 2013
ISL6146
FIGURE 60. ISL6146CEVAL1Z
FIGURE 61. ISL6146CEVAL1Z SCHEMATIC
Dimensions are
1” x 0.5” (25.4mm x 12.7mm)
FIGURE 62. ISL6146DEVAL1Z
23
FIGURE 63. ISL6146EDEV1Z SCHEMATIC (Mini-eval)
FN7667.4
April 26, 2013
ISL6146
TABLE 2. ISL6146xEVALZ BOM
REFERENCE DESIGNATOR
VALUE
DESCRIPTION
MANUFACTURER
PART NUMBER
ISL6146AEVAL1Z
U1, U2
Q1, Q2, Q11, Q12
ISL6146A OR-ing FET Controller
Intersil
30V, 50A FET
Various
R1, 11
66.5kΩ
RES, SMD, 0603, 1%
Generic
R2, R12, R6, R16
4.99kΩ
RES, SMD, 0603, 1%
Generic
R3, R13
10Ω
RES, SMD, 0603, 1%
Generic
R4, R14
0Ω
RES, SMD, 0603, 1%
Generic
R5, R15
DNP
RES, SMD, 0603, 1%
Generic
R7, R17
10kΩ
RES, SMD, 0603, 1%
Generic
C1, C11, C5 C15
100µF
Alum. Elect SMD Cap
Generic
C2, C3, C12 C13
1µF
CAP, SMD, 0603, 50V, 10%
Generic
C4, C14
DNP
CAP, SMD, 0603, 50V, 10%
Generic
Test Point
Generic
Banana Jack
Generic
ISL6146B OR-ing FET Controller
Intersil
30V, 50A FET
Various
TPx
Jx
ISL6146AFUZ
ISL6146BEVAL1Z
U1, U2
Q1, Q11
R4, R14
4.99kΩ
RES, SMD, 0603, 1%
Generic
R1, R10
10Ω
RES, SMD, 0603, 1%
Generic
R2, R12
0Ω
RES, SMD, 0603, 1%
Generic
R3, R13
DNP
RES, SMD, 0603, 1%
Generic
R5, R15
10kΩ
RES, SMD, 0603, 1%
Generic
C1, C11, C5 C15
100µF
Alum. Elect SMD Cap
Generic
C2, C3, C12 C13
1µF
CAP, SMD, 0603, 50V, 10%
Generic
C4, C14
DNP
CAP, SMD, 0603, 50V, 10%
Generic
Test Point
Generic
Banana Jack
Generic
ISL6146C OR-ing FET Controller
Intersil
TPx
Jx
ISL6146BFUZ
ISL6146CEVAL1Z
U1, U2
Q1, Q2, Q11, Q12
30V, 50A FET
Various
R1, 11
93.1kΩ
RES, SMD, 0603, 1%
Generic
R2, R12
1.4kΩ
RES, SMD, 0603, 1%
Generic
R3, R13
4.53kΩ
RES, SMD, 0603, 1%
Generic
R4, R14
0Ω
RES, SMD, 0603, 1%
Generic
R5, R15
DNP
RES, SMD, 0603, 1%
Generic
R6, R16
4.99kΩ
RES, SMD, 0603, 1%
Generic
R7, R17
10kΩ
RES, SMD, 0603, 1%
Generic
C1, C11, C3 C13
100µF
C2, C12
1µF
TPx
Jx
24
Alum. Elect SMD Cap
Generic
CAP, SMD, 0603, 50V, 10%
Generic
Test Point
Generic
Banana Jack
Generic
ISL6146CFUZ
FN7667.4
April 26, 2013
ISL6146
TABLE 2. ISL6146xEVALZ BOM (Continued)
REFERENCE DESIGNATOR
VALUE
DESCRIPTION
MANUFACTURER
PART NUMBER
ISL6146DEVAL1Z
ISL6146D OR-ing FET Controller
Intersil
R1, R2, R3
U1
DNP
RES, SMD, 0603, 1%
Generic
R4
4.99kΩ
RES, SMD, 0603, 1%
Generic
R5
10kΩ
RES, SMD, 0603, 1%
Generic
C1, C2
1µF
CAP, SMD, 0603, 50V, 10%
Generic
ISL6146E OR-ing FET Controller
Intersil
ISL6146DFUZ
ISL6146EEVAL1Z
U1
R1, R2, R3
DNP
RES, SMD, 0603, 1%
Generic
R4
4.99kΩ
RES, SMD, 0603, 1%
Generic
R5
10kΩ
RES, SMD, 0603, 1%
Generic
C1, C2
1µF
CAP, SMD, 0603, 50V, 10%
Generic
25
ISL6146EFUZ
FN7667.4
April 26, 2013
ISL6146
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision.
DATE
REVISION
CHANGE
April 3, 2013
FN7667.4
Added ISL6146DEVAL1Z and ISL6146EEVAL1Z related information. Figurers 62 and 63. Corrected labels in
Figure 61.
September 27, 2012
FN7667.3
Added tape and reel parts to Ordering Information table for ISL6146A/B/C/D/E products.
Thermal Information - removed Pb-Free Reflow link
June 18, 2012
FN7667.2
Added ISL6146D and ISL6146E. References to these products added throughout the datasheet. Added Figures
45 & 46 to illustrate the fault differences between ISL6146A/B and ISL6146D/E. Moved Figure 50 and revised
the related text on page 20 before the evaluation board section. Added Figures 51 - 55 and related text on
page 20 to page 21.
February 27, 2012
FN7667.1
Removed note “MSOP packaged parts to be released soon” from “Ordering Information” on page 3. Added
FIgures 42 & 43 on page 15.
December 16, 2011
FN7667.0
Initial Release
About Intersil
Intersil Corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management
semiconductors. The company's products address some of the largest markets within the industrial and infrastructure, personal
computing and high-end consumer markets. For more information about Intersil, visit our website at www.intersil.com.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting
www.intersil.com/en/support/ask-an-expert.html. Reliability reports are also available from our website at
http://www.intersil.com/en/support/qualandreliability.html#reliability
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
26
FN7667.4
April 26, 2013
ISL6146
Package Outline Drawing
L8.3x3J
8 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE
Rev 0 9/09
2X 1.950
3.00
B
0.15
5
8
3.00
(4X)
6X 0.65
A
1.64 +0.10/ - 0.15
6
PIN 1
INDEX AREA
6
PIN #1 INDEX AREA
4
1
4
8X 0.30
8X 0.400 ± 0.10
TOP VIEW
0.10 M C A B
2.38
+0.10/ - 0.15
BOTTOM VIEW
SEE DETAIL "X"
( 2.38 )
( 1.95)
0.10 C
Max 1.00
C
0.08 C
SIDE VIEW
( 8X 0.60)
(1.64)
( 2.80 )
PIN 1
C
0 . 2 REF
5
(6x 0.65)
0 . 00 MIN.
0 . 05 MAX.
( 8 X 0.30)
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6.
27
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
FN7667.4
April 26, 2013
ISL6146
Package Outline Drawing
M8.118
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
Rev 4, 7/11
5
3.0±0.05
A
DETAIL "X"
D
8
1.10 MAX
SIDE VIEW 2
0.09 - 0.20
4.9±0.15
3.0±0.05
5
0.95 REF
PIN# 1 ID
1
2
B
0.65 BSC
GAUGE
PLANE
TOP VIEW
0.55 ± 0.15
0.25
3°±3°
0.85±010
H
DETAIL "X"
C
SEATING PLANE
0.25 - 0.36
0.08 M C A-B D
0.10 ± 0.05
0.10 C
SIDE VIEW 1
(5.80)
NOTES:
(4.40)
(3.00)
1. Dimensions are in millimeters.
(0.65)
(0.40)
(1.40)
TYPICAL RECOMMENDED LAND PATTERN
28
2. Dimensioning and tolerancing conform to JEDEC MO-187-AA
and AMSEY14.5m-1994.
3. Plastic or metal protrusions of 0.15mm max per side are not
included.
4. Plastic interlead protrusions of 0.15mm max per side are not
included.
5. Dimensions are measured at Datum Plane "H".
6. Dimensions in ( ) are for reference only.
FN7667.4
April 26, 2013