SEMICONDUCTOR TECHNICAL DATA " " ! # L SUFFIX CERAMIC CASE 726 CMOS MSI (Low–Power Complementary MOS) The MC14544B BCD–to–seven segment latch/decoder/driver is designed for use with liquid crystal readouts, and is constructed with complementary MOS (CMOS) enhancement mode devices. The circuit provides the functions of a 4–bit storage latch and an 8421 BCD–to–seven segment decoder and driver. The device has the capability to invert the logic levels of the output combination. The phase (Ph), blanking (BI), and latch disable (LD) inputs are used to reverse the truth table phase, blank the display, and store a BCD code, respectively. For liquid crystal (LC) readouts, a square wave is applied to the Ph input of the circuit and the electrically common backplane of the display. The outputs of the circuit are connected directly to the segments of the LC readout. The Ripple Blanking Input (RBI) and the Ripple Blanking Output (RBO) can be used to suppress either leading or trailing zeroes. For other types of readouts, such as light–emitting diode (LED), incandescent, gas discharge, and fluorescent readouts, connection diagrams are given on this data sheet. Applications include instrument (e.g., counter, DVM etc.) display driver, computer/calculator display driver, cockpit display driver, and various clock, watch, and timer uses. • • • • • • • Latch Storage of Code Blanking Input Readout Blanking on All Illegal Input Combinations Direct LED (Common Anode or Cathode) Driving Capability Supply Voltage Range = 3.0 V to 18 V Capability for Suppression of Non–significant zero Capable of Driving Two Low–power TTL Loads, One Low–power Schottky TTL Load or Two HTL Loads Over the Rated Temperature Range ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ P SUFFIX PLASTIC CASE 707 ORDERING INFORMATION MC14XXXBCP MC14XXXBCL TA = – 55° to 125°C for all packages. PIN ASSIGNMENT LD 1 18 VDD C 2 17 f B 3 16 g D 4 15 e A 5 14 d PH 6 13 c BI 7 12 b RBO 8 11 a VSS 9 10 RBI MAXIMUM RATINGS* (Voltages referenced to VSS) Rating DC Supply Voltage Input Voltage, All Inputs Symbol Value Unit VDD – 0.5 to + 18 V Vin – 0.5 to VDD + 0.5 V DC Input Current per Pin Iin ± 10 mAdc Operating Temperature Range TA – 55 to + 125 _C Power Dissipation, per Package† PD 500 mW Storage Temperature Range Tstg – 65 to + 150 _C Maximum Continuous Output Drive Current (Source or Sink) per Output IOHmax IOLmax 10 mAdc Maximum Continuous Output Power* (Source or Sink) per Output POHmax POLmax 70 mW * POHmax = IOH (VOH – VDD) and POLmax = IOL (VOL – VSS) * Maximum Ratings are those values beyond which damage to the device may occur. †Temperature Derating: Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C Plastic Ceramic a f g e b c d DISPLAY 0 1 2 3 4 5 6 7 8 9 This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. v v REV 3 1/94 MOTOROLA Motorola, Inc. 1995 CMOS LOGIC DATA MC14544B 1 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) Characteristic Output Voltage Vin = VDD or 0 Symbol – 55_C 25_C 125_C VDD Vdc Min Max Min Typ # Max Min Max Unit “0” Level VOL 5.0 10 15 — — — 0.05 0.05 0.05 — — — 0 0 0 0.05 0.05 0.05 — — — 0.05 0.05 0.05 Vdc “1” Level VOH 5.0 10 15 4.95 9.95 14.95 — — — 4.95 9.95 14.95 5.0 10 15 — — — 4.95 9.95 14.95 — — — Vdc 5.0 10 15 — — — 1.5 3.0 4.0 — — — 2.25 4.50 6.75 1.5 3.0 4.0 — — — 1.5 3.0 4.0 5.0 10 15 3.5 7.0 11 — — — 3.5 7.0 11 2.75 5.50 8.25 — — — 3.5 7.0 11 — — — 5.0 5.0 10 10 15 – 3.0 – 0.64 — – 1.6 – 4.2 — — — — — – 2.4 – 0.51 — – 1.3 – 3.4 – 4.2 – 0.88 – 10.1 – 2.25 – 8.8 — — — — — – 1.7 – 0.36 — – 0.9 – 2.4 — — — — IOL 5.0 10 10 15 0.64 1.6 — 4.2 — — — — 0.51 1.3 — 3.4 0.88 2.25 10.1 8.8 — — — — 0.36 0.9 — 2.4 — — — mAdc Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc Input Capacitance Cin — — — — 5.0 7.5 — — pF Quiescent Current (Per Package) Vin = 0 or VDD, Iout = 0 µA IDD 5.0 10 15 — — — 5.0 10 20 — — — 0.005 0.010 0.015 5.0 10 20 — — — 150 300 600 µAdc Total Supply Current**† (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) IT 5.0 10 15 Vin = 0 or VDD Input Voltage # “0” Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) VIL “1” Level VIH (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 0.5 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 9.5 Vdc) (VOL = 1.5 Vdc) Vdc Vdc IOH Source Sink mAdc IT = (1.6 µA/kHz) f + IDD IT = (3.1 µA/kHz) f + IDD IT = (4.7 µA/kHz )f + IDD µAdc #Noise immunity specified for worst–case input combination. Noise Margin for both “1” and “0” level = 1.0 V min @ VDD = 5.0 V = 2.0 V min @ VDD = 10 V = 2.5 V min @ VDD = 15 V †To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + 3.5 x 10–3 (CL – 50) VDDf where: IT is in µA (per package), CL in pF, VDD in V, and f in kHz is input frequency. * The formulas given are for the typical characteristics only at 25_C. MC14544B 2 MOTOROLA CMOS LOGIC DATA ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C) Characteristic Symbol Output Rise Time tTLH = (3.0 ns/pF) CL + 30 ns tTLH = (1.5 ns/pF) CL + 15 ns tTLH = (1.1 ns/pF) CL + 10 ns tTLH Output Fall Time tTHL = (1.5 ns/pF) CL + 25 ns tTHL = (0.75 ns/pF) CL + 12.5 ns tTHL = (0.55 ns/pF) CL + 12.5 ns tTHL Turn–Off Delay Time tPLH = (1.7 ns/pF) CL + 520 ns tPLH = (0.66 ns/pF) CL + 217 ns tPLH = (0.5 ns/pF) CL + 160 ns tPLH Turn–On Delay Time tPHL = (1.7 ns/pF) CL + 420 ns tPHL = (0.66 ns/pF) CL + 172 ns tPHL = (0.5 ns/pF) CL + 130 ns tPHL VDD Min Typ Max 5.0 10 15 — — — 100 50 40 200 100 80 5.0 10 15 — — — 100 50 40 200 100 80 5.0 10 15 — — — 605 250 185 1210 500 370 5.0 10 15 — — — 505 205 155 1650 660 495 Unit ns ns ns ns Setup Time tsu 5.0 10 15 0 0 0 – 40 – 15 – 10 — — — ns Hold Time th 5.0 10 15 80 30 20 40 15 10 — — — ns tWH 5.0 10 15 250 100 80 125 50 40 — — — ns Latch Disable Pulse Width (Strobing Data) * The formulas given are for the typical characteristics only. LOGIC DIAGRAM BI 7 VDD = PIN 18 VSS = PIN 9 11 a A 5 12 b 13 c B 3 14 d 15 e C 2 17 f 16 g D 4 LD 1 RBI 10 MOTOROLA CMOS LOGIC DATA 8 RBO 6 PHASE MC14544B 3 CONNECTIONS TO VARIOUS DISPLAY READOUTS LIQUID CRYSTAL (LC) READOUT MC14544B OUTPUT Ph INCANDESCENT READOUT APPROPRIATE VOLTAGE ONE OF SEVEN SEGMENTS COMMON BACKPLANE MC14544B OUTPUT Ph SQUARE WAVE (VSS TO VDD) VSS LIGHT EMITTING DIODE (LED) READOUT COMMON CATHODE LED GAS DISCHARGE READOUT COMMON ANODE LED MC14544B OUTPUT Ph APPROPRIATE VOLTAGE VDD MC14544B OUTPUT Ph MC14544B OUTPUT Ph VSS VDD NOTE: Bipolar transistors may be added for gain (for VDD v 10 V or Iout ≥ 10 mA). VSS TRUTH TABLE Inputs Outputs RBI LD BI Ph* D C B A RBO a b c d e f g Display X X 1 0 X X X X # 0 0 0 0 0 0 0 Blank 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 0 Blank 0 X X X X X 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0 0 0 0 0 1 1 0 1 1 1 1 1 0 1 0 1 1 1 0 1 1 0 1 0 1 0 0 0 0 0 0 1 1 0 1 1 1 1 1 2 3 4 5 X X X X X 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 1 1 0 0 1 0 1 0 1 0 0 0 0 0 0 1 1 1 1 0 0 1 1 1 0 1 0 1 1 0 1 0 1 1 0 1 0 1 0 0 1 0 1 1 0 1 0 1 1 0 6 7 8 9 Blank X X X X X 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 1 1 1 1 1 0 0 1 1 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Blank Blank Blank Blank Blank X 0 0 0 X X X X # ** ** † † † 1 † Inverse of Output Combinations Above Display as above MC14544B 4 † X = Don’t Care †Above Combinations * For liquid crystal readouts, apply a square wave to Ph. For common cathode LED readouts, select Ph = 0. For common anode LED readouts, select Ph = 1. ** Depends upon the BCD Code previously applied when LD = 1. # RBO = RBI (A B C D) MOTOROLA CMOS LOGIC DATA 24 VDD = 15 Vdc VDD = 5.0 Vdc POHmax = 70 mWdc IOL , SINK CURRENT (mAdc) IOH, SOURCE CURRENT (mAdc) 0 – 6.0 VDD = 10 Vdc – 12 – 18 18 VDD = 10 Vdc 12 6.0 VDD = 15 Vdc – 24 – 16 POLmax = 70 mWdc VDD = 5.0 Vdc VSS = 0 Vdc VSS = 0 Vdc 0 – 12 – 8.0 – 4.0 (VOH – VDD), SOURCE DEVICE VOLTAGE (Vdc) 0 0 4.0 8.0 12 (VOL – VSS), SINK DEVICE VOLTAGE (Vdc) Figure 1. Typical Output Source Characteristics 16 Figure 2. Typical Output Sink Characteristics (a) Inputs D, Ph, and BI low, and Inputs A, B, and LD high. 20 ns 20 ns 90% 10% C VDD 50% VSS tPLH tPHL 90% 50% g VOH 10% VOL tTLH tTHL (b) Inputs D, Ph, and BI low, and Inputs A and B high. 20 ns 90% 10% LD VSS tsu Inputs BI and Ph low, and Inputs D and LD high. f in respect to a system clock. C VDD 50% th 50% 50% VDD VSS All outputs connected to respective CL loads. 20 ns A, B, AND C 10% 20 ns 90% 50% 1 2f 50% DUTY CYCLE ANY OUTPUT VOH VDD VSS VOH VOL Figure 3. Dynamic Power Dissipation Signal Waveforms MOTOROLA CMOS LOGIC DATA g VOL (c) Data DCBA strobed into latches LD VDD 50% VSS tWH Figure 4. Dynamic Signal Waveforms MC14544B 5 TYPICAL APPLICATIONS FOR RIPPLE BLANKING LEADING EDGE ZERO SUPPRESSION DISPLAYS a–– –––g RBI RBO VDD (1) D C B A CONNECT TO INPUT CODE MC14544B 0 0 0 0 (0) a–– –––g RBI RBO 1 D C B A MC14544B 0 0 0 0 (0) a–– –––g RBI RBO 1 D C B A 0 MC14544B 0 1 0 1 (5) a–– –––g RBI RBO D C B A 0 a–– –––g RBI RBO D C B A MC14544B 0 0 0 0 (0) 0 MC14544B 0 0 0 1 (1) a–– –––g RBI RBO D C B A 0 MC14544B 0 0 1 1 (3) TRAILING EDGE ZERO SUPPRESSION DISPLAYS 0 INPUT CODE MC14544B 6 a–– –––g RBI RBO D C B A MC14544B 0 1 0 1 (5) a–– –––g RBI RBO 0 D C B A MC14544B 0 0 0 0 (0) a–– –––g RBI RBO 0 D C B A MC14544B 0 0 0 1 (1) 0 a–– –––g RBI RBO D C B A MC14544B 0 0 1 1 (3) 1 a–– –––g RBI RBO D C B A MC14544B 0 0 0 0 (0) 1 a – – – – – g CONNECT TO RBI RBO D C B A VDD (1) MC14544B 0 0 0 0 (0) INPUT CODE MOTOROLA CMOS LOGIC DATA OUTLINE DIMENSIONS L SUFFIX CERAMIC DIP PACKAGE CASE 726–04 ISSUE G NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F FOR FULL LEADS. HALF LEADS OPTIONAL AT LEAD POSITIONS 1, 9, 10, AND 18. –A– 18 10 1 9 –B– OPTIONAL LEAD CONFIGURATION (1, 9, 10, 18) DIM A B C D F G J K L M N L C N –T– K SEATING PLANE F M G D 18 PL 0.25 (0.010) J M T A 18 PL 0.25 (0.010) S M P SUFFIX PLASTIC DIP PACKAGE CASE 707–02 ISSUE C 18 10 B 1 9 T B C N F H D G K SEATING PLANE M J MILLIMETERS MIN MAX 22.35 23.11 6.10 7.49 ––– 5.08 0.38 0.53 1.40 1.78 2.54 BSC 0.20 0.30 3.18 4.32 7.62 BSC 0_ 15_ 0.51 1.02 S NOTES: 1. POSITIONAL TOLERANCE OF LEADS (D), SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM MATERIAL CONDITION, IN RELATION TO SEATING PLANE AND EACH OTHER. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. A L INCHES MIN MAX 0.880 0.910 0.240 0.295 ––– 0.200 0.015 0.021 0.055 0.070 0.100 BSC 0.008 0.012 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040 DIM A B C D F G H J K L M N MILLIMETERS MIN MAX 22.22 23.24 6.10 6.60 3.56 4.57 0.36 0.56 1.27 1.78 2.54 BSC 1.02 1.52 0.20 0.30 2.92 3.43 7.62 BSC 0_ 15_ 0.51 1.02 INCHES MIN MAX 0.875 0.915 0.240 0.260 0.140 0.180 0.014 0.022 0.050 0.070 0.100 BSC 0.040 0.060 0.008 0.012 0.115 0.135 0.300 BSC 0_ 15 _ 0.020 0.040 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 or 602–303–5454 JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–81–3521–8315 MFAX: [email protected] – TOUCHTONE 602–244–6609 INTERNET: http://Design–NET.com ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 MOTOROLA CMOS LOGIC DATA ◊ *MC14544B/D* MC14544B MC14544B/D 7