Cypress CY2DL818ZI 1:8 clock fanout buffer Datasheet

CY2DL818
1:8 Clock Fanout Buffer
Features
Low voltage operation
VDD = 3.3V
1:8 fanout
Single-input-configurable for LVDS, LVPECL, or LVTTL
8 pair of LVDS Outputs
Drives either a 50-ohm or 100-ohm load (selectable)
Low input capacitance
Low output skew
Low propagation delay
Typical (tpd < 4 ns)
Packages available include: TSSOP
Does not exceed Bellcore 802.3 standards
Operation at => 350 MHz – 700 Mbps
This Cypress series of network circuits is produced using
advanced 0.35-micron CMOS technology, achieving the
industry’s fastest logic.
The Cypress CY2DL818 fanout buffer features a single LVDS
or a single-ended LVTTL-compatible input and eight LVDS
output pairs.
Designed for data communications clock management applications, the large fanout from a single input reduces loading
on the input clock. The Cypress CY2DL818 is ideal for both
level translations from single-ended to LVDS and/or for the
distribution of LVDS-based clock signals.
The Cypress CY2DL818 has configurable input and output
functions. The input can be selectable for LVCMOS/LVTTL,
LVPECL, or LVDS signals, while the output drivers support
standard and high-drive LVDS. Drive either a 50-ohm or
100-ohm line with a single part number/device.
Pin Configuration
Block Diagram
37
36
Q1A
Q1B
35
34
INPUT
Q2A
Q2B
33
32
Q3A
Q3B
(LVPECL / LVDS / LVTTL)
10
INPUT A
INPUT B
31
30
Q4A
6
28
27
Q5A
VDD
GND
INPUT A
INPUT B
GND
VDD
VDD
VDD
VDD
VDD
GND
GND
Q4B
11
InConfig
GND
VDD
VDD
VDD
VDD
InConfig
CNTRL
Q5B
26
Q6A
Q6B
25
24
Q7A
Q7B
23
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CY2DL 818
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Description
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
GND
Q1A
Q1B
Q2A
Q2B
Q3A
Q3B
Q4A
Q4B
VDD
Q5A
Q5B
Q6A
Q6B
Q7A
Q7B
Q8A
Q8B
GND
38 pin TSSOP
22
Q8A
Q8B
21
CNTRL
7
OUTPUT
(LVDS)
Cypress Semiconductor Corporation
Document #: 38-07058 Rev. *B
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised December 15, 2002
CY2DL818
Pin Description
Pin Number
1, 9,12,
18,19,20,38
2,3,4,5,8, 13
14,15,16,17,29
10,11
Pin Name
GND
Pin Standard Interface
POWER
Ground
37, 36,35,34,
33,32,31, 30,
28,27,26,25,
24,23,22,21
6
Q1A, Q1B, Q2A, Q2B,
Q3A, Q3B, Q4A, Q4B,
Q5A, Q5B, Q6A, Q6B,
Q7A, Q7B, Q8A, Q8B
InConfig
7
CNTRL
Pin Description
VDD
POWER
Input A, Input B(#)
Default: LVPECL / LDVS Differential input pair or single line.
Optional: LVTTL/LVCMOS LVPECL/LVDS default. See InConfig below.
single pin.
LDVS
Differential Outputs
Power Supply
LVTTL / LVCMOS
LVTTL / LVCMOS
Converts inputs from the default
LVPECL/LVDS
(logic = 0)
To LVTTL/LVCMOS (logic = 1) “default pull-up”
See Figure 5 and Figure 6 for additional information
Converts into a high-speed driver.
Logic = 0 = 100 ohm
Logic = 1 = 50-ohm “default pull-up”
See Figure 7 for additional Information
Output Drive Control for Standard and Bus/B/Hi-Drive
CNTRL
Pin 7 Binary Value
0
Drive STD
Standard
1
Hi-drive/Bus/B
Impedance
100 Ohms
50 Ohms
100 Ohms
50 Ohms
Output Voltage Value
VO = Voutput
V = 1/2 * VO
V = 2 * VO
V = VO
Input Receiver Configuration for Differential or LVTTL/LVCMOS
InCONFIG
Pin 6 Binary Value
1
0
Input Receiver Family
LVTTL in LVCMOS
LVDS
LVPECL
Input Receiver Type
Single-ended non-inverting, inverting, void of bias resistors.
Low-voltage differential signaling
Low-voltage pseudo (positive) emitter coupled logic
Function Control of the TTL Input Logic Used to Accept or Invert the Input Signal
Ground
VCC
Ground
VCC
Input Condition
Input B (–) Pin 11
Input A (+) Pin 10
Input B (–) Pin 11
Input A (+) Pin 10
Input A (+) Pin 10
Input B (–) Pin 11
Input A (+) Pin 10
Input B (–) Pin 11
LVTTL/LVCMOS INPUT LOGIC
Input Logic
Input
Input – Bar
Input
Input – Bar
Input
Input – Bar
Input
Input – Bar
Output Logic Q Pins, Q1A or Q1
Input
Input – Bar
Input – Bar
Input
Input
Input – Bar
Input – Bar
Input
Power Supply Characteristics
Parameter
ICCD
IC
Description
Test Conditions
Dynamic Power Supply Current VDD = Max
Input toggling 50% Duty Cycle, Outputs Open
Total Power Supply Current
VDD = Max
Input toggling 50% Duty Cycle, Outputs Open
fL = 100 MHz
Document #: 38-07058 Rev. *B
Min.
Typ. Max.
Unit
0.40
0.5
mA/MHz
40
80
mA
Page 2 of 8
CY2DL818
Maximum Ratings[1][2]
Supply Voltage to Ground Potential
(Outputs only) ........................................ –0.3V to VDD + 0.3V
Storage Temperature: ................................–65°C to + 150°C
DC Input Voltage ................................... –0.3V to VDD + 0.3V
Ambient Temperature:................................... –40°C to +85°C
DC Output Voltage................................. –0.3V to VDD + 0.9V
Supply Voltage to Ground Potential
Power Dissipation........................................................ 0.75W
(Inputs and VCC only)....................................... –0.3V to 4.6V
DC Electrical Characteristics: 3.3V–LVDS Input
Parameter
VID
Description
Conditions
Min.
Magnitude of Differential Input Voltage
Typ.
Max. Unit
100
600
VIC
Common-mode of Differential Input VoltageIVIDI (min. and max.)
VIH
Input High Voltage
VIL
Input Low Voltage
Guaranteed Logic Low Level
IIH
Input High Current
VDD = Max
VIN = VDD
±10
IIL
Input Low Current
VDD = Max
VIN = VSS
±10
II
Input High Current
VDD = Max, VIN = VDD(max.)
Guaranteed Logic High Level
IVIDI/2 2.4 – (IVIDI/2)
InConfig/Cntrl Pins
2
mV
V
V
0.8
V
±20
µA
±20
µA
±20
µA
DC Electrical Characteristics: 3.3V–LVPECL Input
Parameter
Description
Conditions
Min.
Guaranteed Logic High Level
Typ.
Max.
Unit
400
2400
mV
1.65
2.25
V
I VID I
Differential input voltage p-p
VCM
Common-Mode Voltage
IIH
Input High Current
VDD = Max
VIN = VDD
±10
±20
µA
IIL
Input Low Current
VDD = Max
VIN = VSS
±10
±20
µA
Typ.
Max.
Unit
DC Electrical Characteristics: 3.3V–LVTTL/LVCMOS Input
Parameter
VIH
VIL
IIH
IIL
II
VIK
VH
Description
Input High Voltage
Conditions
Min.
Guaranteed Logic High Level
2
V
Input Low Voltage
Guaranteed Logic Low Level
0.8
V
Input High Current
VDD = Max
VIN = 2.7V
1
µA
Input Low Current
VDD = Max
VIN = 0.5V
–1
µA
Input High Current
VDD = Max., VIN = VDD(Max)
20
µA
Clamp Diode Voltage
VDD = Min., IIN = -18mA
–0.7
Input Hysteresis
–1.2
80
V
mV
DC Electrical Characteristics: 3.3V–LVDS OUTPUT
Parameter
Description
Conditions
I VOD I
Differential Output Voltage p-p
VDD = 3.3V, VIN = VIH or VIL
Risetime
Pin Control (pin 7) logic is “FALSE”
defaulting to 100-ohm output
DIfferential 20% to 80%
CL – 10 pF RL and CL to GND
CL = Cintrinsic and Cexternal
See Figure 3
Falltime
Pin Control (pin 7) logic is “TRUE”
setting 50-ohm output drivers
differential 20% to 80%
CL – 10 pF RL and CL to GND
CL = Cintrinsic and Cexternal
See Figure 3
IOS
Output Short Circuit
DOUT = 0V or DOUT- = 0V
VOH
Output Voltage high
VOL
Output Voltage low
Falltime
Risetime
Min.
RL = 100
ohm
Max.
Unit
0.55
V
800
1500
ps
800
1500
ps
350
600
ps
350
600
ps
–10
mA
1550
mV
0.25
RL = 50 ohm
RL = 100
ohm
Typ.
925
mV
Notes:
1. Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. This is intended to be a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
Document #: 38-07058 Rev. *B
Page 3 of 8
CY2DL818
AC Switching Characteristics @ 3.3 V VDD = 3.3V ±5%, Temperature = –40°C to +85°C
Parameter
Description
Conditions
Min.
Typ
Max
Unit
tPLH
Propagation Delay – Low to High
4.5
ns
tPHL
Propagation Delay – High to Low
4.5
ns
tSK(0)
Output Skew: Skew between outputs of the same
package (in phase)
tSK(p)
Pulse Skew: Skew between opposite transitions of the
same output (tPHL – tPLH)
tSK(t)
Package Skew: Skew between outputs of different
packages at the same power supply voltage, temperature
and package type.
200
200
ps
ps
1.6
ns
High Frequency Parametrics
Parameter
Description
Conditions
Fmax
Maximum frequency
VDD = 3.3V
50% duty cycle tW(50-50)
Standard Load Circuit.
LVDS VID = 100 mV
Dj
Deterministic Jitter
50% duty cycle tW(50-50)
Standard Load Circuit.
LVDS VID = 100 mV
Min.
Typ
50
Max
Unit
400
MHz
ps
Idd @ 25°C
Idd (mA) vs. Input Freq. (MHz)
200
180
160
Idd (mA)
140
High or B Drive Curves
120
100
80
60
Standard Drive Curves
40
20
0
40
140
240
LD 3.3
LD 3.465
340
440
540
Input Freq. (MHz)
LD 3.135
HD 3.135
HD 3.3
HD 3.465
Figure 1. IDD Current vs. Frequency in Low Drive and High Drive Full Load
Document #: 38-07058 Rev. *B
Page 4 of 8
CY2DL818
A
TPA
Pulse
50
10pF
Generator
TPC
B
50
TPB
Standard Termination
V1A
1.4 V
0V Differential
V1B
1.0 V
V0Y
1.4 V
0V Differential
1.0 V
V0Z
T PLH
TPHL
80%
0V Differential
V0Y - V0Z
20%
tR
tF
Figure 2. Differential Receiver to Driver Propagation Delay and Driver Transition Time[3,4,5,6]
A
TPA
50
P u ls e
G e n e r a to r
TP C
B
50
TP B
VOC
S t a n d a r d T e r m in a t io n
V I( A )
1 .4 0 V
V I( B )
1 .0 V
VOD
N e x t D e v ic e
V o c (p p )
VDD
V o c (s s )
Figure 3. Test Circuit and Voltage Definitions for the Driver Common-Mode Output Voltage[3,4,5,6,7]
Notes:
3. All input pulses are supplied by a frequency generator with the following characteristics: TR and tF ≤ 1 ns; pulse rate = 50 Mpps; pulse width = 10 ± 0.2 ns.
4. RL = 50 ohm/100 ohm ± 1%.
5. CL includes instrumentation and fixture capacitance within 6 mm of the DUT.
6. TPA and B are used for prop delay and Rise/Fall Measurements. TPC is used for VOC measurements only.
7. All outputs should be loaded, used or not, in order to minimize noise and currents.
Document #: 38-07058 Rev. *B
Page 5 of 8
CY2DL818
A
TPA
Pulse
Generator
50
10pF
TPC
B
50
TPB
Standard Termination
VI(A)
1.4V
VI(B)
1.0V
100%
80%
0.0V
20%
0%
tF
tR
Figure 4. Test Circuit and Voltage Definitions for the Differential Output Signal [3,4,5,6]
INPUT A
LVCMOS / LVTTL
INPUT B
GND
InConfig
1
LVTTL/LVCMOS
Figure 5. InConfig Control for LVCMOS Input[8]
LVPECL &
LVDS
In C o n fig
0
L V D S /L V P E C L
Figure 6. InConfig Control for Differential Input[9]
0
CNTRL
1
100
50
100
H i D r iv e B
50
S ta n d a rd
O hm s
Ohm s
O hm s
Ohm s
’V o = V o
’V o = 1 /2 V o
’V o = 2 V o
’V o = V o
Figure 7. CNTRL Control for Standard or High-drive Drivers[10]
Notes:
8. See Function Control of the TTL Input Logic Used to Accept or Invert the Input Signal on page 2.
9. LVPECL or LVDS differential input value.
10. Standard 100-ohm output impedance: high-drive 50-ohm output impedance.
Document #: 38-07058 Rev. *B
Page 6 of 8
CY2DL818
Ordering Information
Part Number
Package Type
Product Flow
CY2DL818ZI
38-pin TSSOP
Industrial, –40° to 85°C
CY2DL818ZIT
38-pin TSSOP–Tape and Reel
Industrial, –40° to 85°C
CY2DL818ZC
38-pin TSSOP
Commercial, 0° to 70°C
CY2DL818ZCT
38-pin TSSOP–Tape and Reel
Commercial, 0° to 70°C
Package Drawing and Dimensions
38-pin TSSOP (4.40 mm body) Z38
51-85151-**
All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-07058 Rev. *B
Page 7 of 8
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY2DL818
Document Title: CY2DL818 1:8 Clock Fanout Buffer
Document Number: 38-07058
Rev.
ECN No.
Issue Date
Orig. of
Change
Description of Change
**
115151
05/30/02
EHX
New Data Sheet
*A
117611
09/16/02
RGL
Changed the figure cross reference in page 2 and added a note 6 in page 5
*B
122745
12/15/02
RBI
Added power-up requirements to maximum ratings information.
Document #: 38-07058 Rev. *B
Page 8 of 8
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