MC74VHC32 Quad 2-Input OR Gate The MC74VHC32 is an advanced high speed CMOS 2−input OR gate fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V systems to 3.0 V systems. http://onsemi.com MARKING DIAGRAMS Features • • • • • • • • • • • • High Speed: tPD = 3.8 ns (Typ) at VCC = 5.0 V Low Power Dissipation: ICC = 2.0 mA (Max) at TA = 25°C High Noise Immunity: VNIH = VNIL = 28% VCC Power Down Protection Provided on Inputs Balanced Propagation Delays Designed for 2.0 V to 5.5 V Operating Range Low Noise: VOLP = 0.8 V (Max) Pin and Function Compatible with Other Standard Logic Families Latchup Performance Exceeds 300 mA ESD Performance: Human Body Model > 2000 V; Machine Model > 200 V Chip Complexity: 48 FETs or 12 Equivalent Gates These Devices are Pb−Free and are RoHS Compliant A1 B1 A2 B2 A3 B3 A4 B4 1 3 2 Y1 14 14 1 VHC32G AWLYWW SOIC−14 D SUFFIX CASE 751A 1 14 14 VHC 32 ALYW 1 TSSOP DT SUFFIX CASE 948G A WL, L Y WW, W G or 1 = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) 4 6 5 Y2 FUNCTION TABLE Y = A+B 9 8 10 Inputs Y3 A B Y Y4 L L H H L H L H L H H H 12 11 13 Output Figure 1. Logic Diagram VCC B4 A4 Y4 B3 A3 Y3 14 13 12 11 10 9 8 ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. 1 2 3 5 6 7 A1 B1 Y1 A2 B2 (Top View) 4 Y2 GND Figure 2. Pinout: 14−Lead Packages © Semiconductor Components Industries, LLC, 2014 September, 2014 − Rev. 7 1 Publication Order Number: MC74VHC32/D MC74VHC32 MAXIMUM RATINGS Symbol Value Unit VCC DC Supply Voltage Parameter –0.5 to +7.0 V Vin DC Input Voltage –0.5 to +7.0 V Vout DC Output Voltage –0.5 to VCC +0.5 V IIK Input Diode Current −20 mA IOK Output Diode Current ±20 mA Iout DC Output Current, per Pin ±25 mA ICC DC Supply Current, VCC and GND Pins ±50 mA PD Power Dissipation in Still Air, 500 450 mW Tstg Storage Temperature –65 to +150 °C SOIC Package† TSSOP Package† This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC ). Unused outputs must be left open. Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. †Derating − SOIC Package: – 7 mW/°C from 65° to 125°C TSSOP Package: − 6.1 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol Parameter VCC DC Supply Voltage Vin DC Input Voltage Vout DC Output Voltage TA Operating Temperature tr, tf Input Rise and Fall Time VCC = 3.3 V ±0.3 V VCC = 5.0 V ±0.5 V Min Max Unit 2.0 5.5 V 0 5.5 V 0 VCC V −40 +125 °C 0 0 100 20 ns/V Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. DC ELECTRICAL CHARACTERISTICS Min 1.50 VCC x 0.7 Symbol Parameter VIH Minimum High−Level Input Voltage 2.0 3.0 to 5.5 VIL Maximum Low−Level Input Voltage 2.0 3.0 to 5.5 VOH Minimum High−Level Output Voltage VOL Maximum Low−Level Output Voltage Test Conditions TA = 25°C VCC V Typ TA = −40°C to 125°C Max Min 1.50 VCC x 0.7 0.50 VCC x 0.3 Vin = VIH or VIL IOH = −50 mA 2.0 3.0 4.5 1.9 2.9 4.4 Vin = VIH or VIL IOH = −4.0 mA IOH = −8.0 mA 3.0 4.5 2.58 3.94 Vin = VIH or VIL IOL = 50 mA 2.0 3.0 4.5 Vin = VIH or VIL IOL = 4.0 mA IOL = 8.0 mA Max 2.0 3.0 4.5 Unit V 0.50 VCC x 0.3 V V 1.9 2.9 4.4 2.48 3.80 0.0 0.0 0.0 0.1 0.1 0.1 0.1 0.1 0.1 3.0 4.5 0.36 0.36 0.44 0.44 V Iin Maximum Input Leakage Current Vin = 5.5 V or GND 0 to 5.5 ±0.1 ±1.0 mA ICC Maximum Quiescent Supply Current Vin = VCC or GND 5.5 2.0 20.0 mA Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. http://onsemi.com 2 MC74VHC32 AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0 ns) TA = 25°C tPLH, tPHL Cin Maximum Propagation Delay, A or B to Y TA = −40°C to 125°C Typ Max Min Max Unit VCC = 3.3 ± 0.3 V CL = 15 pF CL = 50 pF 5.5 8.0 7.9 11.4 1.0 1.0 9.5 13.0 ns VCC = 5.0 ± 0.5 V CL = 15 pF CL = 50 pF 3.8 5.3 5.5 7.5 1.0 1.0 6.5 8.5 4 10 Parameter Symbol Min Test Conditions Maximum Input Capacitance 10 pF Typical @ 25°C, VCC = 5.0 V CPD 14 Power Dissipation Capacitance (Note 1) pF 1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 4 (per gate). CPD is used to determine the no−load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC. NOISE CHARACTERISTICS (Input tr = tf = 3.0 ns, CL = 50 pF, VCC = 5.0 V) TA = 25°C Typ Characteristic Symbol Max Unit VOLP Quiet Output Maximum Dynamic VOL 0.3 0.8 V VOLV Quiet Output Minimum Dynamic VOL −0.3 −0.8 V VIHD Minimum High Level Dynamic Input Voltage 3.5 V VILD Maximum Low Level Dynamic Input Voltage 1.5 V TEST POINT VCC A or B 50% OUTPUT DEVICE UNDER TEST GND tPLH Y tPHL CL* 50% VCC *Includes all probe and jig capacitance Figure 3. Switching Waveforms Figure 4. Test Circuit INPUT Figure 5. Input Equivalent Circuit http://onsemi.com 3 MC74VHC32 ORDERING INFORMATION Package Shipping† MC74VHC32DR2G SOIC−14 (Pb−Free) 2500 Units / Tape & Reel MC74VHC32DTG TSSOP−14 (Pb−Free) 96 Units / Rail MC74VHC32DTR2G TSSOP−14 (Pb−Free) 2500 Units / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 4 MC74VHC32 PACKAGE DIMENSIONS SOIC−14 CASE 751A−03 ISSUE K D A B 14 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF AT MAXIMUM MATERIAL CONDITION. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSIONS. 5. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 8 A3 E H L 1 0.25 M DETAIL A 7 B 13X M b 0.25 M C A S B S e DETAIL A h A X 45 M A1 C SEATING PLANE DIM A A1 A3 b D E e H h L M MILLIMETERS MIN MAX 1.35 1.75 0.10 0.25 0.19 0.25 0.35 0.49 8.55 8.75 3.80 4.00 1.27 BSC 5.80 6.20 0.25 0.50 0.40 1.25 0 7 SOLDERING FOOTPRINT* 6.50 14X 1.18 1 1.27 PITCH 14X 0.58 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 5 INCHES MIN MAX 0.054 0.068 0.004 0.010 0.008 0.010 0.014 0.019 0.337 0.344 0.150 0.157 0.050 BSC 0.228 0.244 0.010 0.019 0.016 0.049 0 7 MC74VHC32 PACKAGE DIMENSIONS TSSOP−14 CASE 948G ISSUE B 14X K REF 0.10 (0.004) 0.15 (0.006) T U T U M V S S S N 2X 14 L/2 0.25 (0.010) 8 M B −U− L PIN 1 IDENT. F 7 1 0.15 (0.006) T U N S DETAIL E K A −V− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. ÉÉÉ ÇÇÇ ÇÇÇ ÉÉÉ K1 J J1 SECTION N−N −W− C 0.10 (0.004) −T− SEATING PLANE D H G DIM A B C D F G H J J1 K K1 L M DETAIL E MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 −−− 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.50 0.60 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0 8 INCHES MIN MAX 0.193 0.200 0.169 0.177 −−− 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.020 0.024 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0 8 SOLDERING FOOTPRINT 7.06 1 0.65 PITCH 14X 0.36 14X 1.26 DIMENSIONS: MILLIMETERS ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. 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