HN58X24256AS Two-wire serial interface 256k EEPROM (32-kword × 8-bit) REJ03C0316-0001 Preliminary Rev.0.01 Mar.22.2007 Description HN58X24xxx series are two-wire serial interface EEPROM (Electrically Erasable and Programmable ROM). They realize high speed, low power consumption and a high level of reliability by employing advanced MNOS memory technology and CMOS process and low voltage circuitry technology. They also have a 64-byte page programming function to make their write operation faster. Note: Renesas Technology’s serial EEPROM are authorized for using consumer applications such as cellular phone, camcorders, audio equipment. Therefore, please contact Renesas Technology’s sales office before using industrial applications such as automotive systems, embedded controllers, and meters. Features • • • • • • • • Single supply: 1.8 V to 5.5 V Two-wire serial interface (I2C serial bus) Clock frequency: 400 kHz Power dissipation: Standby: 3 µA (max) Active (Read): 1 mA (max) Active (Write): 5 mA (max) Automatic page write: 64-byte/page Write cycle time: 5 ms Endurance: 106 Cycles Data retention: 10 Years Preliminary: The specifications of this device are subject to change without notice. Please contact your nearest Renesas Technology’s Sales Dept. regarding specifications. Rev.0.01, Mar.22.2007, page 1 of 20 HN58X24256AS • Small size packages: SOP-8pin, TSSOP-14pin • Shipping tape and reel TSSOP 14-pin: 2,000 IC/reel SOP 8-pin: 2,500 IC/reel • Temperature range: −40 to +85°C • Lead free products. Ordering Information Type No. Internal organization Operating voltage Frequency Package HN58X24256ASFPI 256k bit (32768 × 8-bit) 1.8 V to 5.5 V 400 kHz 150 mil 8-pin plastic SOP PRSP0008DF-B (FP-8DBV) Lead free HN58X24256ASTI 256k bit (32768 × 8-bit) 1.8 V to 5.5 V 400 kHz 14-pin plastic TSSOP PTSP0014JA-C (TTP-14DBV) Lead free Pin Arrangement 8-pin SOP 14-pin TSSOP A0 1 8 VCC A0 1 14 VCC A1 2 7 WP A1 2 13 WP A2 3 6 SCL NC 3 12 NC VSS 4 5 SDA NC 4 11 NC NC 5 10 NC A2 6 9 SCL VSS 7 8 SDA (Top view) (Top view) Rev.0.01, Mar.22.2007, page 2 of 20 HN58X24256AS Pin Description Pin name Function A0 to A2 Device address SCL Serial clock input SDA Serial data input/output WP Write protect VCC Power supply VSS Ground NC No connection Block Diagram High voltage generator Control logic A0, A1, A2 SCL X decoder WP Address generator VSS Memory array Y decoder VCC Y-select & Sense amp. SDA Serial-parallel converter Absolute Maximum Ratings Parameter Symbol Value Supply voltage relative to VSS VCC −0.6 to +7.0 Input voltage relative to VSS Vin −0.5* to +7.0* V Operating temperature range*1 Topr −40 to +85 °C Storage temperature range Tstg −65 to +125 °C 2 Notes: 1. Including electrical characteristics and data retention. 2. Vin (min): −3.0 V for pulse width ≤ 50 ns. 3. Should not exceed VCC + 1.0 V. Rev.0.01, Mar.22.2007, page 3 of 20 Unit V 3 HN58X24256AS DC Operating Conditions Parameter Symbol Min Typ Max Unit Supply voltage VCC 1.8 5.5 V VSS 0 0 0 V Input high voltage VIH VCC × 0.7 VCC + 0.5 V Input low voltage VIL −0.3*1 VCC × 0.3 V Operating temperature Topr −40 +85 °C Notes: 1. VIL (min): −1.0 V for pulse width ≤ 50 ns. DC Characteristics (Ta = −40 to +85°C, VCC = 1.8 V to 5.5 V) Parameter Symbol Min Typ Max Unit Test conditions Input leakage current ILI 2.0 µA VCC = 5.5 V, Vin = 0 to 5.5 V Output leakage current ILO 2.0 µA VCC = 5.5 V, Vout = 0 to 5.5 V Standby VCC current ISB 1.0 3.0 µA Vin = VSS or VCC Read VCC current ICC1 1.0 mA VCC = 5.5 V, Read at 400 kHz Write VCC current ICC2 5.0 mA VCC = 5.5 V, Write at 400 kHz Output low voltage VOL2 0.4 V VCC = 2.7 to 5.5 V, IOL = 3.0 mA VOL1 0.2 V VCC = 1.8 to 2.7 V, IOL = 1.5 mA Capacitance (Ta = +25°C, f = 1 MHz) Min Typ Max Unit Test conditions Input capacitance (A0 to A2, SCL, WP) Cin*1 6.0 pF Vin = 0 V 1 6.0 pF Vout = 0 V Parameter Output capacitance (SDA) Note: Symbol CI/O* 1. This parameter is sampled and not 100% tested. Rev.0.01, Mar.22.2007, page 4 of 20 HN58X24256AS AC Characteristics (Ta = −40 to +85°C, VCC = 1.8 to 5.5 V) Test Conditions • Input pules levels: VIL = 0.2 × VCC VIH = 0.8 × VCC • Input rise and fall time: ≤ 20 ns • Input and output timing reference levels: 0.5 × VCC • Output load: TTL Gate + 100 pF Parameter Symbol Min Typ Max Unit Clock frequency fSCL 400 kHz Clock pulse width low tLOW 1200 ns Clock pulse width high tHIGH 600 ns Noise suppression time tI 50 ns Access time tAA 100 900 ns Bus free time for next mode tBUF 1200 ns Notes 1 Start hold time tHD.STA 600 ns Start setup time tSU.STA 600 ns Data in hold time tHD.DAT 0 ns Data in setup time tSU.DAT 100 ns Input rise time tR 300 ns 1 Input fall time tF 300 ns 1 Stop setup time tSU.STO 600 ns Data out hold time tDH 50 ns Write protect hold time tHD.WP 1200 ns Write protect setup time tSU.WP 0 ns Write cycle time tWC 5 ms 2 Erase/Write Endurance cycles 3 6 10 Notes: 1. This parameter is sampled and not 100% tested. 2. tWC is the time from a stop condition to the end of internally controlled write cycle. 3. This parameter is sampled and not 100% tested (Ta = 25°C). Rev.0.01, Mar.22.2007, page 5 of 20 HN58X24256AS Timing Waveforms Bus Timing tF tHIGH 1/fSCL tLOW tR SCL tSU.STA tHD.DAT tSU.DAT tHD.STA tSU.STO SDA (in) tBUF tAA tDH SDA (out) tSU.WP tHD.WP WP Write Cycle Timing Stop condition Start condition SCL SDA D0 in Write data (Address (n)) ACK Rev.0.01, Mar.22.2007, page 6 of 20 tWC (Internally controlled) HN58X24256AS Pin Function Serial Clock (SCL) The SCL pin is used to control serial input/output data timing. The SCL input is used to positive edge clock data into EEPROM device and negative edge clock data out of each device. Maximum clock rate is 400 kHz. Serial Input/Output Data (SDA) The SDA pin is bidirectional for serial data transfer. The SDA pin needs to be pulled up by resistor as that pin is open-drain driven structure. Use proper resistor value for your system by considering VOL, IOL and the SDA pin capacitance. Except for a start condition and a stop condition which will be discussed later, the SDA transition needs to be completed during the SCL low period. Data Validity (SDA data change timing waveform) SCL SDA Data change Note: Data change High-to-low and low-to-high change of SDA should be done during the SCL low period. Rev.0.01, Mar.22.2007, page 7 of 20 HN58X24256AS Device Address (A0, A1, A2) Eight devices can be wired for one common data bus line as maximum. Device address pins are used to distinguish each device and device address pins should be connected to VCC or VSS. When device address code provided from SDA pin matches corresponding hard-wired device address pins A0 to A2, that one device can be activated. Pin Connections for A0 to A2 Pin connection Max connect Memory size number A2 A1 A0 256k bit VCC/VSS VCC/VSS VCC/VSS Note: 8 Note 1. “VCC/VSS” means that device address pin should be connected to VCC or VSS. Write Protect (WP) When the Write Protect pin (WP) is high, the write protection feature is enabled and operates as shown in the following table. When the WP is low, write operation for all memory arrays are allowed. The read operation is always activated irrespective of the WP pin status. Write Protect Area Write protect area WP pin status 256k bit VIH Full (256k bit) VIL Normal read/write operation Rev.0.01, Mar.22.2007, page 8 of 20 HN58X24256AS Functional Description Start Condition A high-to-low transition of the SDA with the SCL high is needed in order to start read, write operation (See start condition and stop condition). Stop Condition A low-to-high transition of the SDA with the SCL high is a stop condition. The stand-by operation starts after a read sequence by a stop condition. In the case of write operation, a stop condition terminates the write data inputs and place the device in a internally-timed write cycle to the memories. After the internally-timed write cycle which is specified as tWC, the device enters a standby mode (See write cycle timing). Start Condition and Stop Condition SCL SDA (in) Start condition Rev.0.01, Mar.22.2007, page 9 of 20 Stop condition HN58X24256AS Acknowledge All addresses and data words are serially transmitted to and from in 8-bit words. The receiver sends a zero to acknowledge that it has received each word. This happens during ninth clock cycle. The transmitter keeps bus open to receive acknowledgment from the receiver at the ninth clock. In the write operation, EEPROM sends a zero to acknowledge after receiving every 8-bit words. In the read operation, EEPROM sends a zero to acknowledge after receiving the device address word. After sending read data, the EEPROM waits acknowledgment by keeping bus open. If the EEPROM receives zero as an acknowledge, it sends read data of next address. If the EEPROM receives acknowledgment "1" (no acknowledgment) and a following stop condition, it stops the read operation and enters a stand-by mode. If the EEPROM receives neither acknowledgment "0" nor a stop condition, the EEPROM keeps bus open without sending read data. Acknowledge Timing Waveform SCL 1 SDA IN SDA OUT Rev.0.01, Mar.22.2007, page 10 of 20 2 8 9 Acknowledge out HN58X24256AS Device Addressing The EEPROM device requires an 8-bit device address word following a start condition to enable the chip for a read or a write operation. The device address word consists of 4-bit device code, 3-bit device address code and 1-bit read/write(R/W) code. The most significant 4-bit of the device address word are used to distinguish device type and this EEPROM uses “1010” fixed code. The device address word is followed by the 3-bit device address code in the order of A2, A1, A0. The device address code selects one device out of all devices which are connected to the bus. This means that the device is selected if the inputted 3bit device address code is equal to the corresponding hard-wired A2-A0 pin status. The eighth bit of the device address word is the read/write(R/W) bit. A write operation is initiated if this bit is low and a read operation is initiated if this bit is high. Upon a compare of the device address word, the EEPROM enters the read or write operation after outputting the zero as an acknowledge. The EEPROM turns to a stand-by state if the device code is not “1010” or device address code doesn’t coincide with status of the correspond hard-wired device address pins A0 to A2. Device Address Word Device address word (8-bit) Device code (fixed) 256k Note: 1 0 R/W code*1 Device address code 1 0 1. R/W=“1” is read and R/W = “0” is write. Rev.0.01, Mar.22.2007, page 11 of 20 A2 A1 A0 R/W HN58X24256AS Write Operations Byte Write: A write operation requires an 8-bit device address word with R/W = “0”. Then the EEPROM sends acknowledgment "0" at the ninth clock cycle. After these, the 128kbit and 256kbit EEPROMs receive 2 sequence 8-bit memory address words. Upon receipt of this memory address, the EEPROM outputs acknowledgment "0" and receives a following 8-bit write data. After receipt of write data, the EEPROM outputs acknowledgment "0". If the EEPROM receives a stop condition, the EEPROM enters an internally-timed write cycle and terminates receipt of SCL, SDA inputs until completion of the write cycle. The EEPROM returns to a standby mode after completion of the write cycle. 2nd Memory address (n) Write data (n) D7 D6 D5 D4 D3 D2 D1 D0 1st Memory address (n) 256k 1010 Start a14 a13 a12 a11 a10 a9 a8 *1 Device address a7 a6 a5 a4 a3 a2 a1 a0 Byte Write Operation W ACK R/W Note: 1. Don't care bit Rev.0.01, Mar.22.2007, page 12 of 20 ACK ACK Stop HN58X24256AS Page Write: The EEPROM is capable of the page write operation which allows any number of bytes up to 64 bytes to be written in a single write cycle. The page write is the same sequence as the byte write except for inputting the more write data. The page write is initiated by a start condition, device address word, memory address(n) and write data (Dn) with every ninth bit acknowledgment. The EEPROM enters the page write operation if the EEPROM receives more write data (Dn+1) instead of receiving a stop condition. The a0 to a5 address bits are automatically incremented upon receiving write data (Dn+1). The EEPROM can continue to receive write data up to 64 bytes. If the a0 to a5 address bits reaches the last address of the page, the a0 to a5 address bits will roll over to the first address of the same page and previous write data will be overwritten. Upon receiving a stop condition, the EEPROM stops receiving write data and enters internally-timed write cycle. Page Write Operation 1st Memory address (n) 2nd Memory address (n) Write data (n) Write data (n+m) Start ACK R/W Note: 1. Don't care bit Rev.0.01, Mar.22.2007, page 13 of 20 ACK ACK D5 D4 D3 D2 D1 D0 W D7 D6 D5 D4 D3 D2 D1 D0 1010 a7 a6 a5 a4 a3 a2 a1 a0 256k a14 a13 a12 a11 a10 a9 a8 *1 Device address ACK ACK Stop HN58X24256AS Acknowledge Polling: Acknowledge polling feature is used to show if the EEPROM is in a internally-timed write cycle or not. This feature is initiated by the stop condition after inputting write data. This requires the 8-bit device address word following the start condition during a internally-timed write cycle. Acknowledge polling will operate when the R/W code = “0”. Acknowledgment “1” (no acknowledgment) shows the EEPROM is in a internally-timed write cycle and acknowledgment “0” shows that the internally-timed write cycle has completed. See Write Cycle Polling using ACK. Write Cycle Polling Using ACK Send write command Send stop condition to initiate write cycle Send start condition Send device address word with R/W = 0 ACK returned No Yes Next operation is addressing the memory No Yes Proceed write operation Send memory address Send start condition Proceed random address read operation Send stop condition Rev.0.01, Mar.22.2007, page 14 of 20 Send stop condition HN58X24256AS Read Operation There are three read operations: current address read, random read, and sequential read. Read operations are initiated the same way as write operations with the exception of R/W = “1”. Current Address Read: The internal address counter maintains the last address accessed during the last read or write operation, with incremented by one. Current address read accesses the address kept by the internal address counter. After receiving a start condition and the device address word (R/W is “1”), the EEPROM outputs the 8-bit current address data from the most significant bit following acknowledgment “0”. If the EEPROM receives acknowledgment “1” (no acknowledgment) and a following stop condition, the EEPROM stops the read operation and is turned to a standby state. In case the EEPROM has accessed the last address of the last page at previous read operation, the current address will roll over and returns to zero address. In case the EEPROM has accessed the last address of the page at previous write operation, the current address will roll over within page addressing and returns to the first address in the same page. The current address is valid while power is on. The current address after power on will be indefinite. The random read operation described below is necessary to define the memory address. Current Address Read Operation Device address 1010 Start Rev.0.01, Mar.22.2007, page 15 of 20 R D7 D6 D5 D4 D3 D2 D1 D0 256k Read data (n+1) ACK R/W No ACK Stop HN58X24256AS Random Read: This is a read operation with defined read address. A random read requires a dummy write to set read address. The EEPROM receives a start condition, device address word (R/W=0) and memory address 2 × 8-bit sequentially. The EEPROM outputs acknowledgment “0” after receiving memory address then enters a current address read with receiving a start condition. The EEPROM outputs the read data of the address which was defined in the dummy write operation. After receiving acknowledgment “1”(no acknowledgment) and a following stop condition, the EEPROM stops the random read operation and returns to a standby state. Random Read Operation Start Device address W ACK R/W ACK 1010 Start ACK Dummy write Notes: 1. Don't care bit 2. 2nd device address code (#) should be same as 1st (@). Rev.0.01, Mar.22.2007, page 16 of 20 Read data (n) # # # R R/W ACK D7 D6 D5 D4 D3 D2 D1 D0 2nd Memory address (n) a7 a6 a5 a4 a3 a2 a1 a0 1010 @@@ a14 a13 a12 a11 a10 a9 a8 256k 1st Memory address (n) *1 Device address No ACK Stop Currect address read HN58X24256AS Sequential Read: Sequential reads are initiated by either a current address read or a random read. If the EEPROM receives acknowledgment “0” after 8-bit read data, the read address is incremented and the next 8-bit read data are coming out. This operation can be continued as long as the EEPROM receives acknowledgment “0”. The address will roll over and returns address zero if it reaches the last address of the last page. The sequential read can be continued after roll over. The sequential read is terminated if the EEPROM receives acknowledgment “1” (no acknowledgment) and a following stop condition. Sequential Read Operation ACK R/W Rev.0.01, Mar.22.2007, page 17 of 20 ACK ACK ACK D5 D4 D3 D2 D1 D0 R Read data (n+1) Read data (n+2) Read data (n+m) D7 D6 D5 D4 D3 D2 D1 D0 Start 1010 D7 D6 D5 D4 D3 D2 D1 D0 256k Read data (n) D7 D6 D5 D4 D3 D2 D1 D0 Device address No ACK Stop HN58X24256AS Notes Data Protection at VCC On/Off When VCC is turned on or off, noise on the SCL and SDA inputs generated by external circuits (CPU, etc) may act as a trigger and turn the EEPROM to unintentional program mode. To prevent this unintentional programming, this EEPROM has a power on reset function. Be careful of the notices described below in order for the power on reset function to operate correctly. • SCL and SDA should be fixed to VCC or VSS during VCC on/off. Low to high or high to low transition during VCC on/off may cause the trigger for the unintentional programming. • VCC should be turned off after the EEPROM is placed in a standby state. • VCC should be turned on from the ground level(VSS) in order for the EEPROM not to enter the unintentional programming mode. • VCC turn on speed should be longer than 10 µs. Noise Suppression Time This EEPROM have a noise suppression function at SCL and SDA inputs, that cut noise of width less than 50 ns. Be careful not to allow noise of width more than 50 ns. Rev.0.01, Mar.22.2007, page 18 of 20 HN58X24256AS Package Dimensions HN58X24256ASFPI (PRSP0008DF-B / Previous Code: FP-8DBV) JEITA Package Code P-SOP8-3.9x4.89-1.27 RENESAS Code PRSP0008DF-B *1 Previous Code FP-8DBV MASS[Typ.] 0.08g D 8 F NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. 5 *2 c E HE bp Index mark Terminal cross section ( Ni/Pd/Au plating ) Reference Dimension in Millimeters Symbol 4 1 Z e *3 bp x M A L1 A1 θ L y Detail F Rev.0.01, Mar.22.2007, page 19 of 20 D E A2 A1 A bp b1 c c1 θ HE e x y Z L L1 Min Nom Max 4.89 5.15 3.90 0.102 0.14 0.254 1.73 0.35 0.40 0.45 0.15 0.20 0.25 0° 8° 5.84 6.02 6.20 1.27 0.25 0.10 0.69 0.406 0.60 0.889 1.06 HN58X24256AS HN58X24256ASTI (PTSP0014JA-C / Previous Code: TTP-14DBV) JEITA Package Code P-TSSOP14-4.4x5-0.65 RENESAS Code PTSP0014JA-C *1 Previous Code TTP-14DBV MASS[Typ.] 0.05g D F 14 8 NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. *2 c E HE bp Terminal cross section ( Ni/Pd/Au plating ) Index mark 1 Reference Dimension in Millimeters Symbol 7 *3 Z bp x M L1 A e A1 θ y Rev.0.01, Mar.22.2007, page 20 of 20 L Detail F D E A2 A1 A bp b1 c c1 θ HE e x y Z L L1 Min Nom Max 5.00 5.30 4.40 0.03 0.07 0.10 1.10 0.15 0.20 0.25 0.10 0.15 0.20 0° 8° 6.20 6.40 6.60 0.65 0.13 0.10 0.83 0.40 0.50 0.60 1.00 Revision History Rev. Date Contents of Modification Page 0.01 Mar. 22, 2007 Description Initial issue HN58X24256AS Data Sheet Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. 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