LINER LT3023 Dual 100ma, low dropout, low noise, micropower regulator Datasheet

LT3023
Dual 100mA,
Low Dropout, Low Noise,
Micropower Regulator
FEATURES
DESCRIPTION
n
The LT®3023 is a dual, micropower, low noise, low dropout regulator. With an external 0.01μF bypass capacitor,
output noise drops to 20μVRMS over a 10Hz to 100kHz
bandwidth. Designed for use in battery-powered systems,
the low 20μA quiescent current per channel makes it an
ideal choice. In shutdown, quiescent current drops to less
than 0.1μA. Shutdown control is independent for each
channel, allowing for ﬂexibility in power management. The
device is capable of operating over an input voltage from
1.8V to 20V, and can supply 100mA of output current from
each channel with a dropout voltage of 300mV. Quiescent
current is well controlled in dropout.
n
n
n
n
n
n
n
n
n
n
n
n
n
Low Noise: 20μVRMS (10Hz to 100kHz)
Low Quiescent Current: 20μA/Channel
Wide Input Voltage Range: 1.8V to 20V
Output Current: 100mA/Channel
Very Low Shutdown Current: <0.1μA
Low Dropout Voltage: 300mV at 100mA
Adjustable Output from 1.22V to 20V
Stable with 1μF Output Capacitor
Stable with Aluminum, Tantalum or
Ceramic Capacitors
Reverse Battery Protected
No Reverse Current
No Protection Diodes Needed
Overcurrent and Overtemperature Protected
Thermally Enhanced 10-Lead MSOP and DFN
Packages
The LT3023 regulator is stable with output capacitors as
low as 1μF. Small ceramic capacitors can be used without
the series resistance required by other regulators.
Internal protection circuitry includes reverse battery
protection, current limiting, thermal limiting and reverse
current protection. The device is available as an adjustable device with a 1.22V reference voltage. The LT3023
regulator is available in the thermally enhanced 10-lead
MSOP and DFN packages.
APPLICATIONS
n
n
n
n
n
Cellular Phones
Pagers
Battery-Powered Systems
Frequency Synthesizers
Wireless Modems
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other
trademarks are the property of their respective owners.
TYPICAL APPLICATION
3.3V/2.5V Low Noise Regulators
10Hz to 100kHz Output Noise
VIN
3.7V TO
20V
IN
1μF
3.3V AT100mA
20μVRMS NOISE
OUT1
SHDN1
SHDN2
0.01μF
422k
10μF
BYP1
ADJ1
249k
LT3023
OUT2
0.01μF
261k
VOUT
100μV/DIV
20μVRMS
2.5V AT100mA
20μVRMS NOISE
10μF
BYP2
ADJ2
GND
3023 TA01b
249k
3023 TA01
3023fa
1
LT3023
ABSOLUTE MAXIMUM RATINGS
(Note 1)
IN Pin Voltage .........................................................±20V
OUT1, OUT2 Pin Voltage .........................................±20V
Input to Output Differential Voltage .........................±20V
ADJ1, ADJ2 Pin Voltage ............................................±7V
BYP1, BYP2 Pin Voltage ........................................±0.6V
SHDN1, SHDN2 Pin Voltage ...................................±20V
Output Short-Circut Duration ........................... Indeﬁnite
Operating Junction Temperature Range
(Note 2) ............................................. –40°C to 125°C
Storage Temperature Range................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec) .................. 300°C
(MSE package only)
PIN CONFIGURATION
TOP VIEW
TOP VIEW
BYP2
1
10 OUT2
ADJ2
2
9 SHDN2
11
GND
3
ADJ1
4
7 SHDN1
BYP1
5
6 OUT1
BYP2
ADJ2
GND
ADJ1
BYP1
8 IN
DD PACKAGE
10-LEAD (3mm s 3mm) PLASTIC DFN
TJMAX = 125°C, θJA = 40°C/W, θJC = 10°C/W
EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB
1
2
3
4
5
11
10
9
8
7
6
OUT2
SHDN2
IN
SHDN1
OUT1
MSE PACKAGE
10-LEAD PLASTIC MSOP
TJMAX = 150°C, θJA = 40°C/W, θJC = 10°C/W
EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT3023EDD#PBF
LT3023EDD#TRPBF
LAJA
10-Lead (3mm × 3mm) Plastic DFN
–40°C to 125°C
LT3023IDD#PBF
LT3023IDD#TRPBF
LAJA
10-Lead (3mm × 3mm) Plastic DFN
–40°C to 125°C
LT3023EMSE#PBF
LT3023EMSE#TRPBF
LTAHZ
10-Lead Plastic MSOP
–40°C to 125°C
LT3023IMSE#PBF
LT3023IMSE#TRPBF
LTAHZ
10-Lead Plastic MSOP
–40°C to 125°C
LEAD BASED FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT3023EDD
LT3023EDD#TR
LAJA
10-Lead (3mm × 3mm) Plastic DFN
–40°C to 125°C
LT3023IDD
LT3023IDD#TR
LAJA
10-Lead (3mm × 3mm) Plastic DFN
–40°C to 125°C
LT3023EMSE
LT3023EMSE#TR
LTAHZ
10-Lead Plastic MSOP
–40°C to 125°C
LT3023IMSE
LT3023IMSE#TR
LTAHZ
10-Lead Plastic MSOP
–40°C to 125°C
Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges. *The temperature grade is identiﬁed by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS
The l denotes the speciﬁcations which apply over the full operating
temperature range, otherwise speciﬁcations are at TA = 25°C. (Note 2)
PARAMETER
CONDITIONS
Minimum Input Voltage
(Notes 3, 11)
ILOAD = 100mA
l
MIN
ADJ1, ADJ2 Pin Voltage
(Note 3, 4)
VIN = 2V, ILOAD = 1mA
2.3V < VIN < 20V, 1mA < ILOAD < 100mA
l
1.205
1.190
TYP
MAX
1.8
2.3
UNITS
V
1.220
1.220
1.235
1.250
V
V
3023fa
2
LT3023
ELECTRICAL CHARACTERISTICS
The l denotes the speciﬁcations which apply over the full operating
temperature range, otherwise speciﬁcations are at TA = 25°C. (Note 2)
PARAMETER
CONDITIONS
Line Regulation (Note 3)
ΔVIN = 2V to 20V, ILOAD = 1mA
l
MIN
Load Regulation (Note 3)
VIN = 2.3V, ΔILOAD = 1mA to 100mA
VIN = 2.3V, ΔILOAD = 1mA to 100mA
l
Dropout Voltage
VIN = VOUT(NOMINAL) (Notes 5, 6, 11)
ILOAD = 1mA
ILOAD = 1mA
l
ILOAD = 10mA
ILOAD = 10mA
l
ILOAD = 50mA
ILOAD = 50mA
l
ILOAD = 100mA
ILOAD = 100mA
l
GND Pin Current (Per Channel)
VIN = VOUT(NOMINAL) (Notes 5, 7)
ILOAD = 0mA
ILOAD = 1mA
ILOAD = 10mA
ILOAD = 50mA
ILOAD = 100mA
l
l
l
l
l
Output Voltage Noise
COUT = 10μF, CBYP = 0.01μF, ILOAD = 100mA, BW = 10Hz to 100kHz
(Notes 3, 8)
Shutdown Threshold
VOUT = Off to On
VOUT = On to Off
l
l
SHDN1/SHDN2 Pin Current
(Note 9)
VSHDN = 0V
VSHDN = 20V
l
l
Quiescent Current in Shutdown
VIN = 6V, VSHDN = 0V (Both SHDN Pins)
Ripple Rejection (Note 3)
VIN = 2.72V (Avg), VRIPPLE = 0.5VP-P, fRIPPLE = 120Hz,
ILOAD = 50mA
Current Limit
VIN = 7V, VOUT = 0V
VIN = 2.3V, ΔVOUT = –5%
l
VIN = –20V, VOUT = 0V
l
Reverse Output Current (Notes 3,10) VOUT = 1.22V, VIN < 1.22V
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LT3023 is tested and speciﬁed under pulse load conditions
such that TJ ≅ TA. The LT3023E is 100% tested at TA = 25°C. Performance
at – 40°C and 125°C is assured by design, characterization and correlation
with statistical process controls. The LT3023I is guaranteed over the full
–40°C to 125°C operating junction temperature range.
Note 3: The LT3023 is tested and speciﬁed for these conditions with the
ADJ1/ADJ2 pin connected to the corresponding OUT1/OUT2 pin.
Note 4: Operating conditions are limited by maximum junction
temperature. The regulated output voltage speciﬁcation will not apply
for all possible combinations of input voltage and output current. When
operating at maximum input voltage, the output current range must be
limited. When operating at maximum output current, the input voltage
range must be limited.
Note 5: To satisfy requirements for minimum input voltage, the LT3023 is
tested and speciﬁed for these conditions with an external resistor divider
(two 250k resistors) for an output voltage of 2.44V. The external resistor
divider will add a 5μA DC load on the output.
MAX
1
10
mV
1
12
25
mV
mV
0.10
0.15
0.19
V
V
0.17
0.22
0.29
V
V
0.24
0.28
0.38
V
V
0.30
0.35
0.45
V
V
20
55
230
1
2.2
45
100
400
2
4
μA
μA
μA
mA
mA
20
ADJ1/ADJ2 Pin Bias Current
Input Reverse Leakage Current
TYP
0.25
55
UNITS
μVRMS
30
100
nA
0.8
0.65
1.4
V
V
0
1
0.5
3
μA
μA
0.01
0.1
μA
65
dB
200
mA
mA
110
5
1
mA
10
μA
Note 6: Dropout voltage is the minimum input to output voltage differential
needed to maintain regulation at a speciﬁed output current. In dropout, the
output voltage will be equal to: VIN – VDROPOUT.
Note 7: GND pin current is tested with VIN = 2.44V and a current source
load. This means the device is tested while operating in its dropout region
or at the minimum input voltage speciﬁcation. This is the worst-case GND
pin current. The GND pin current will decrease slightly at higher input
voltages.
Note 8: ADJ1 and ADJ2 pin bias current ﬂows into the pin.
Note 9: SHDN1 and SHDN2 pin current ﬂows into the pin.
Note 10: Reverse output current is tested with the IN pin grounded and the
OUT pin forced to the rated output voltage. This current ﬂows into the OUT
pin and out the GND pin.
Note 11: For the LT3023 dropout voltage will be limited by the minimum
input voltage speciﬁcation under some output voltage/load conditions.
See the curve of Minimum Input Voltage in the Typical Performance
Characteristics.
3023fa
3
LT3023
TYPICAL PERFORMANCE CHARACTERISTICS
Guaranteed Dropout Voltage
500
450
450
350
TJ = 125°C
300
250
TJ = 25°C
200
150
= TEST POINTS
450
400
TJ ≤ 125°C
350
300
TJ ≤ 25°C
250
200
150
400
350
250
150
100
50
50
50
0
10 20 30 40 50 60 70 80 90 100
OUTPUT CURRENT (mA)
3023 G01
Quiescent Current
ADJ1 or ADJ2 Pin Voltage
VIN = 6V
RL = 250k
IL = 5μA
ADJ PIN VOLTAGE (V)
VSHDN = VIN
15
10
5
0
–50
0
–25
25
50
75
100
125
1.225
1.220
1.215
1.210
1.200
–50
–25
0
25
50
75
100
0
125
RL = 24.4Ω
IL = 50mA*
0.75
0.25
0.9
2.00
SHDN PIN THRESHOLD (V)
GND PIN CURRENT (mA)
1.50
1.75
1.50
1.25
1.00
0.75
0.50
RL = 122Ω
IL = 10mA*
0
0
1
2
3 4 5 6 7
INPUT VOLTAGE (V)
8
9
10
3023 G07
IL = 1mA
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.25
0
6 8 10 12 14 16 18 20
INPUT VOLTAGE (V)
1.0
VIN = VOUT(NOMINAL) + 1V
2.25
RL = 12.2Ω
IL = 100mA*
0.50
4
SHDN1 or SHDN2 Pin Threshold
(On-to-Off)
2.50
RL = 1.22k
IL = 1mA*
2
3023 G06
GND Pin Current vs ILOAD
TJ = 25°C
*FOR VOUT = 1.22V
1.00
0
3023 G05
2.50
1.25
10
TEMPERATURE (°C)
GND Pin Current
1.75
15
VSHDN = 0V
3023 G03
2.00
VSHDN = VIN
20
5
TEMPERATURE (°C)
2.25
TJ = 25°C
RL = 250k
IL = 5μA
25
1.230
1.205
VSHDN = 0V
125
100
Quiescent Current
IL = 1mA
1.235
20
50
25
0
75
TEMPERATURE (°C)
30
QUIESCENT CURRENT (μA)
QUIESCENT CURRENT (μA)
25
–25
3023 G03
1.240
30
IL = 1mA
3023 G02
40
35
IL = 10mA
0
–50
0
10 20 30 40 50 60 70 80 90 100
OUTPUT CURRENT (mA)
IL = 50mA
200
100
0
IL = 100mA
300
100
0
GND PIN CURRENT (mA)
Dropout Voltage
500
DROPOUT VOLTAGE (mV)
400
DROPOUT VOLTAGE (mV)
DROPOUT VOLTAGE (mV)
Typical Dropout Voltage
500
0
10 20 30 40 50 60 70 80 90 100
OUTPUT CURRENT (mA)
3023 G08
0
–50
–25
50
25
0
75
TEMPERATURE (°C)
100
125
3023 G09
3023fa
4
LT3023
TYPICAL PERFORMANCE CHARACTERISTICS
SHDN1 or SHDN2 Pin Input
Current
1.0
0.9
0.9
IL = 100mA
0.8
0.7
0.6
IL = 1mA
0.5
0.4
0.3
0.2
0.1
SHDN1 or SHDN2 Pin Input
Current
1.4
VSHDN = 20V
SHDN PIN INPUT CURRENT (μA)
1.0
SHDN PIN INPUT CURRENT (μA)
SHDN PIN THRESHOLD (V)
SHDN1 or SHDN2 Pin Threshold
(Off-to-On)
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
–50
50
25
0
75
TEMPERATURE (°C)
–25
100
0
1
2
3 4 5 6 7 8
SHDN PIN VOLTAGE (V)
9
3023 G10
ADJ1 or ADJ2 Pin Bias Current
70
60
50
40
30
20
10
100
200
150
100
50
1
4
3
2
5
INPUT VOLTAGE (V)
30
20
150
100
0
9
10
3023 G16
–25
50
25
0
75
TEMPERATURE (°C)
3023 G15
Input Ripple Rejection
VIN = 0V
VOUT = VADJ = 1.22V
70
12
9
6
3
0
–50 –25
50
25
75
0
TEMPERATURE (°C)
125
100
80
10
3 4 5 6 7 8
OUTPUT VOLTAGE (V)
200
0
–50
7
6
RIPPLE REJECTION (dB)
REVERSE OUTPUT CURRENT (μA)
40
2
250
Reverse Output Current
50
VIN = 7V
VOUT = 0V
3023 G14
15
125
100
50
0
18
60
50
25
0
75
TEMPERATURE (°C)
300
250
Reverse Output Current
TA = 25°C
90 VIN = 0V
= VADJ
V
80 OUT
CURRENT FLOWS
70 INTO OUTPUT PIN
–25
Current Limit
VOUT = 0V
TJ = 25°C
300
0
125
100
1
0.2
350
3023 G13
0
0.4
3023 G12
CURRENT LIMIT (mA)
SHORT-CIRCUIT CURRENT (mA)
ADJ PIN BIAS CURRENT (nA)
80
50
25
0
75
TEMPERATURE (°C)
0.6
Current Limit
90
REVERSE OUTPUT CURRENT (μA)
10
350
–25
0.8
3023 G11
100
0
–50
1.0
0
–50
0
125
1.2
100
125
3023 G17
60
50
40
COUT = 10μF
30
20
I = 100mA
10 VL = 2.3V + 50mV
COUT = 1μF
IN
RMS RIPPLE
CBYP = 0
0
0.1
100
0.01
1
10
1000
FREQUENCY (kHz)
3023 G18
3023fa
5
LT3023
TYPICAL PERFORMANCE CHARACTERISTICS
Input Ripple Rejection
Input Ripple Rejection
70
60
CBYP = 1000pF
50
CBYP = 100pF
40
30
20
I = 100mA
10 VL = 2.3V + 50mV
IN
RMS RIPPLE
COUT = 10μF
0
0.1
0.01
1
10
FREQUENCY (kHz)
RIPPLE REJECTION (dB)
CBYP = 0.01μF
70
RIPPLE REJECTION (dB)
Channel-to-Channel Isolation
80
80
VOUT1
20mV/DIV
60
50
40
VOUT2
20mV/DIV
30
VIN = VOUT (NOMINAL) +
1V + 0.5VP-P RIPPLE
AT f = 120Hz
IL = 50mA
20
10
100
0
–50
1000
0
–25
25
50
75
100
3023 G20
Channel-to-Channel Isolation
Minimum Input Voltage
ILOAD = 100mA PER CHANNEL
–1
MINIMUM INPUT VOLTAGE (V)
90
80
70
60
50
40
30
20
2.0
IL = 100mA
1.5
IL = 50mA
1.0
1
10
FREQUENCY (kHz)
100
0
–50
1000
50
25
0
75
TEMPERATURE (°C)
–25
3023 G21b
OUTPUT NOISE SPECTRAL DENSITY (μV/√Hz)
VOUT SET FOR 5V
VOUT =VADJ
0.1
0.01
0.01
0.1
1
10
FREQUENCY (kHz)
–5
–6
–7
100
125
100
3023 G24
10
125
RMS Output Noise vs
Bypass Capacitor
160
COUT = 10μF
IL = 100mA
COUT = 10μF
IL = 100mA
f = 10Hz TO 100kHz
140
VOUT SET FOR 5V
100
3023 G23
Output Noise Spectral Density
COUT = 10μF
CBYP = 0
IL = 100mA
1
–4
3023 G22
Output Noise Spectral Density
10
–3
–9
ΔIL = 1mA TO 100mA
–10
0
50
75
–50 –25
25
TEMPERATURE (°C)
OUTPUT NOISE (μVRMS)
0.1
–2
–8
0.5
10
0
0.01
OUTPUT NOISE SPECTRAL DENSITY (μV/√Hz)
Load Regulation
0
2.5
LOAD REGULATION (mV)
CHANNEL-TO-CHANNEL ISOLATION (dB)
100
125
TEMPERATURE (°C)
3023 G19
3023 G21a
50μs/DIV
COUT1, COUT2 = 10μF
CBYP1, CBYP2 = 0.01μF
ΔIL1 = 10mA to 100mA
ΔIL2 = 10mA to 100mA
VIN = 6V, VOUT1 = VOUT2 = 5V
CBYP = 1000pF
1
CBYP = 100pF
VOUT =VADJ
0.1
CBYP = 0.01μF
120
VOUT SET FOR 5V
100
80
60
40
VOUT =VADJ
20
0.01
0.01
0
0.1
1
10
FREQUENCY (kHz)
100
10
100
1k
10k
CBYP (pF)
3023 G25
3023 G26
3023fa
6
LT3023
TYPICAL PERFORMANCE CHARACTERISTICS
RMS Output Noise vs
Load Current (10Hz to 100kHz)
160
10Hz to 100kHz Output Noise
CBYP = 100pF
COUT = 10μF
CBYP = 0μF
CBYP = 0.01μF
120
VOUT SET FOR 5V
VOUT
100μV/DIV
VOUT
100μV/DIV
100
80
VOUT =VADJ
60
40
VOUT SET FOR 5V
20
3023 G28
1ms/DIV
COUT = 10μF
IL = 100mA
VOUT SET FOR 5V OUT
VOUT =VADJ
0.1
1
10
LOAD CURRENT (mA)
100
1ms/DIV
COUT = 10μF
IL = 100mA
VOUT SET FOR 5V OUT
3023 G29
3023 G27
10Hz to 100kHz Output Noise
CBYP = 0.01μF
10Hz to 100kHz Output Noise
CBYP = 1000pF
VOUT
100μV/DIV
VOUT
100μV/DIV
3023 G30
1ms/DIV
1ms/DIV
COUT = 10μF
IL = 100mA
VOUT SET FOR 5V OUT
COUT = 10μF
IL = 100mA
VOUT SET FOR 5V OUT
Transient Response
CBYP = 0
Transient Response
CBYP = 0.01μF
OUTPUT VOLTAGE
DEVIATION (V)
0.2
0.1
0
–0.1
VIN = 6V
CIN = 10μF
COUT = 10μF
VOUT SET FOR 5V OUT
–0.2
100
LOAD CURRENT
(mA)
OUTPUT VOLTAGE
DEVIATION (V)
0
0.01
LOAD CURRENT
(mA)
OUTPUT NOISE (μVRMS)
140
10Hz to 100kHz Output Noise
CBYP = 0
50
0
0
400
800
1200
TIME (μs)
1600
2000
3023 G32
3023 G31
0.04
0.02
0
–0.02
VIN = 6V
CIN = 10μF
COUT = 10μF
VOUT SET FOR 5V OUT
–0.04
100
50
0
0
20 40 60 80 100 120 140 160 180 200
TIME (μs)
3023 G33
3023fa
7
LT3023
PIN FUNCTIONS
GND (Pin 3): Ground.
ADJ1/ADJ2 (Pins 4/2): Adjust Pin. These are the inputs to
the error ampliﬁers. These pins are internally clamped to
± 7V. They have a bias current of 30nA which ﬂows into the
pin (see curve of ADJ1/ADJ2 Pin Bias Current vs Temperature in the Typical Performance Characteristics section).
The ADJ1 and ADJ2 pin voltage is 1.22V referenced to
ground and the output voltage range is 1.22V to 20V.
BYP1/BYP2 (Pins 5/1): Bypass. The BYP1/BYP2 pins are
used to bypass the reference of the LT3023 regulator to
achieve low noise performance from the regulator. The
BYP1/BYP2 pins are clamped internally to ±0.6V (one VBE)
from ground. A small capacitor from the corresponding
output to this pin will bypass the reference to lower the
output voltage noise. A maximum value of 0.01μF can
be used for reducing output voltage noise to a typical
20μVRMS over a 10Hz to 100kHz bandwidth. If not used,
this pin must be left unconnected.
OUT1/OUT2 (Pins 6/10): Output. The outputs supply power
to the loads. A minimum output capacitor of 1μF is required
to prevent oscillations. Larger output capacitors will be
required for applications with large transient loads to limit
peak voltage transients. See the Applications Information
section for more information on output capacitance and
reverse output characteristics.
SHDN1/SHDN2 (Pins 7/9): Shutdown. The SHDN1/SHDN2
pins are used to put the corresponding channel of the
LT3023 regulator into a low power shutdown state. The
output will be off when the pin is pulled low. The SHDN1/
SHDN2 pins can be driven either by 5V logic or open-collector logic with pull-up resistors. The pull-up resistors
are required to supply the pull-up current of the opencollector gates, normally several microamperes, and the
SHDN1/SHDN2 pin current, typically 1μA. If unused, the
pin must be connected to VIN. The device will not function
if the SHDN1/SHDN2 pins are not connected.
IN (Pin 8): Input. Power is supplied to the device through
the IN pin. A bypass capacitor is required on this pin if
the device is more than six inches away from the main
input ﬁlter capacitor. In general, the output impedance of
a battery rises with frequency, so it is advisable to include
a bypass capacitor in battery-powered circuits. A bypass
capacitor in the range of 1μF to 10μF is sufﬁcient. The
LT3023 regulator is designed to withstand reverse voltages on the IN pin with respect to ground and the OUT
pin. In the case of a reverse input, which can happen if
a battery is plugged in backwards, the device will act as
if there is a diode in series with its input. There will be
no reverse current ﬂow into the regulator and no reverse
voltage will appear at the load. The device will protect both
itself and the load.
Exposed Pad (Pin 11): Ground. This pin must be soldered
to the PCB and electrically connected to ground.
3023fa
8
LT3023
APPLICATIONS INFORMATION
The LT3023 is a dual 100mA low dropout regulator with
micropower quiescent current and shutdown. The device
is capable of supplying 100mA per channel at a dropout
voltage of 300mV. Output voltage noise can be lowered
to 20μVRMS over a 10Hz to 100kHz bandwidth with the
addition of a 0.01μF reference bypass capacitor. Additionally, the reference bypass capacitor will improve transient
response of the regulator, lowering the settling time for
transient load conditions. The low operating quiescent
current (20μA per channel) drops to less than 1μA in
shutdown. In addition to the low quiescent current, the
LT3023 regulator incorporates several protection features
which make it ideal for use in battery-powered systems.
The device is protected against both reverse input and
reverse output voltages. In battery backup applications
where the output can be held up by a backup battery when
the input is pulled to ground, the LT3023 acts like it has a
diode in series with its output and prevents reverse current
ﬂow. Additionally, in dual supply applications where the
regulator load isreturned to a negative supply, the output
can be pulled below ground by as much as 20V and still
allow the device to start and operate.
Adjustable Operation
The LT3023 has an output voltage range of 1.22V to 20V.
The output voltage is set by the ratio of two external resistors as shown in Figure 1. The device servos the output
to maintain the corresponding ADJ1/ADJ2 pin voltage
at 1.22V referenced to ground. The current in R1 is then
equal to 1.22V/R1 and the current in R2 is the current in
R1 plus the ADJ1/ADJ2 pin bias current. The ADJ1/ADJ2
pin bias current, 30nA at 25°C, ﬂows through R2 into the
ADJ1/ADJ2 pin. The output voltage can be calculated using the formula in Figure 1. The value of R1 should be no
greater than 250k to minimize errors in the output voltage
caused by the ADJ1/ADJ2 pin bias current. Note that in
shutdown the output is turned off and the divider current will
be zero. Curves of ADJ1/ADJ2 Pin Voltage vs Temperature
and ADJ1/ADJ2 Pin Bias Current vs Temperature appear
in the Typical Performance Characteristics.
IN
VIN
OUT1/OUT2
VOUT
+
LT3023
R2
⎛ R2 ⎞
VOUT = 1.22V ⎜ 1 + ⎟ + IADJ R2
⎝ R1⎠
( )( )
VADJ = 1.22V
ADJ1/ADJ2
GND
IADJ = 30nA AT 25°C
R1
OUTPUT RANGE = 1.22V TO 20V
3023 F01
Figure 1. Adjustable Operation
The device is tested and speciﬁed with the ADJ1/ADJ2
pin tied to the corresponding OUT1/OUT2 pin for an output voltage of 1.22V. Speciﬁcations for output voltages
greater than 1.22V will be proportional to the ratio of the
desired output voltage to 1.22V: VOUT/1.22V. For example,
load regulation for an output current change of 1mA to
100mA is –1mV typical at VOUT = 1.22V. At VOUT = 12V,
load regulation is:
(12V/1.22V)(–1mV) = – 9.8mV
Bypass Capacitance and Low Noise Performance
The LT3023 regulator may be used with the addition of a
bypass capacitor from VOUT to the corresponding BYP1/
BYP2 pin to lower output voltage noise. A good quality
low leakage capacitor is recommended. This capacitor
will bypass the reference of the regulator, providing a
low frequency noise pole. The noise pole provided by this
bypass capacitor will lower the output voltage noise to
as low as 20μVRMS with the addition of a 0.01μF bypass
capacitor. Using a bypass capacitor has the added beneﬁt
of improving transient response. With no bypass capacitor
and a 10μF output capacitor, a 10mA to 100mA load step
will settle to within 1% of its ﬁnal value in less than 100μs.
With the addition of a 0.01μF bypass capacitor, the output
will stay within 1% for a 10mA to 100mA load step (see
Transient Reponse in Typical Performance Characteristics
section). However, regulator start-up time is proportional
to the size of the bypass capacitor, slowing to 15ms with
a 0.01μF bypass capacitor and 10μF output capacitor.
3023fa
9
LT3023
APPLICATIONS INFORMATION
The LT3023 regulator is designed to be stable with a
wide range of output capacitors. The ESR of the output capacitor affects stability, most notably with small
capacitors. A minimum output capacitor of 1μF with an
ESR of 3Ω or less is recommended to prevent oscillations. The LT3023 is a micropower device and output
transient response will be a function of output capacitance.
Larger values of output capacitance decrease the peak
deviations and provide improved transient response for
larger load current changes. Bypass capacitors, used to
decouple individual components powered by the LT3023,
will increase the effective output capacitor value. With
larger capacitors used to bypass the reference (for low
noise operation), larger values of output capacitors are
needed. For 100pF of bypass capacitance, 2.2μF of output
capacitor is recommended. With a 330pF bypass capacitor
or larger, a 3.3μF output capacitor is recommended. The
shaded region of Figure 2 deﬁnes the region over which
the LT3023 regulator is stable. The minimum ESR needed
is deﬁned by the amount of bypass capacitance used, while
the maximum ESR is 3Ω.
Extra consideration must be given to the use of ceramic
capacitors. Ceramic capacitors are manufactured with a
variety of dielectrics, each with different behavior across
temperature and applied voltage. The most common
dielectrics used are speciﬁed with EIA temperature characteristic codes of Z5U, Y5V, X5R and X7R. The Z5U and
Y5V dielectrics are good for providing high capacitances
in a small package, but they tend to have strong voltage
20
X5R
–20
–40
–60
Y5V
–80
–100
20
CHANGE IN VALUE (%)
2.0
CBYP = 0
CBYP = 100pF
CBYP = 330pF
CBYP > 3300pF
1.5
1.0
0.5
1
3
2
4 5 6 7 8 9 10
OUTPUT CAPACITANCE (μF)
3023 F02
Figure 2. Stability
4
14
8
6
10 12
DC BIAS VOLTAGE (V)
16
X5R
0
–20
–40
Y5V
–60
–80
0
2
Figure 3. Ceramic Capacitor DC Bias Characteristics
3.5
STABLE REGION
0
3023 F03
40
2.5
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10μF
0
4.0
3.0
ESR (Ω)
and temperature coefﬁcients as shown in Figures 3 and 4.
When used with a 5V regulator, a 16V 10μF Y5V capacitor
can exhibit an effective value as low as 1μF to 2μF for the
DC bias voltage applied and over the operating temperature range. The X5R and X7R dielectrics result in more
stable characteristics and are more suitable for use as the
output capacitor. The X7R type has better stability across
temperature, while the X5R is less expensive and is available in higher values. Care still must be exercised when
using X5R and X7R capacitors; the X5R and X7R codes
only specify operating temperature range and maximum
capacitance change over temperature. Capacitance change
due to DC bias with X5R and X7R capacitors is better than
Y5V and Z5U capacitors, but can still be signiﬁcant enough
to drop capacitor values below appropriate levels. Capacitor DC bias characteristics tend to improve as component
CHANGE IN VALUE (%)
Output Capacitance and Transient Response
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10μF
–100
–50 –25
50
25
75
0
TEMPERATURE (°C)
100
125
3023 F04
Figure 4. Ceramic Capacitor Temperature Characteristics
3023fa
10
LT3023
APPLICATIONS INFORMATION
case size increases, but expected capacitance at operating
voltage should be veriﬁed.
Voltage and temperature coefﬁcients are not the only
sources of problems. Some ceramic capacitors have a
piezoelectric response. A piezoelectric device generates
voltage across its terminals due to mechanical stress,
similar to the way a piezoelectric accelerometer or microphone works. For a ceramic capacitor the stress can be
induced by vibrations in the system or thermal transients.
The resulting voltages produced can cause appreciable
amounts of noise, especially when a ceramic capacitor is
used for noise bypassing. A ceramic capacitor produced
Figure 5’s trace in response to light tapping from a pencil.
Similar vibration induced behavior can masquerade as
COUT = 10μF
CBYP = 0.01μF
ILOAD = 100mA
Characteristics section. Power dissipation will be equal
to the sum of the two components listed above. Power
dissipation from both channels must be considered during
thermal analysis.
The LT3023 regulator has internal thermal limiting designed to protect the device during overload conditions.
For continuous normal conditions, the maximum junction
temperature rating of 125°C must not be exceeded. It is
important to give careful consideration to all sources of
thermal resistance from junction to ambient. Additional
heat sources mounted nearby must also be considered.
For surface mount devices, heat sinking is accomplished
by using the heat spreading capabilities of the PC board
and its copper traces. Copper board stiffeners and plated
through-holes can also be used to spread the heat generated by power devices.
The following tables list thermal resistance for several
different board sizes and copper areas. All measurements
were taken in still air on 3/32" FR-4 board with one ounce
copper.
VOUT
500μV/DIV
Table 1. MSE Package, 10-Lead MSOP
COPPER AREA
100ms/DIV
3023 F05
Figure 5. Noise Resulting from Tapping on a Ceramic Capacitor
increased output voltage noise.
Thermal Considerations
The power handling capability of the device will be limited
by the maximum rated junction temperature (125°C). The
power dissipated by the device will be made up of two
components (for each channel):
THERMAL RESISTANCE
BOARD AREA (JUNCTION-TO-AMBIENT)
TOPSIDE*
BACKSIDE
2500mm2
2500mm2
2500mm2
40°C/W
1000mm2
2500mm2
2500mm2
45°C/W
225mm2
2500mm2
2500mm2
50°C/W
100mm2
2500mm2
2500mm2
62°C/W
*Device is mounted on topside.
Table 2. DD Package, 10-Lead DFN
COPPER AREA
TOPSIDE*
BACKSIDE
THERMAL RESISTANCE
BOARD AREA (JUNCTION-TO-AMBIENT)
2500mm2
2500mm2
2500mm2
40°C/W
1. Output current multiplied by the input/output voltage
differential: (IOUT)(VIN – VOUT), and
1000mm2
2500mm2
2500mm2
45°C/W
225mm2
2500mm2
2500mm2
50°C/W
2. GND pin current multiplied by the input voltage:
(IGND)(VIN).
100mm2
2500mm2
2500mm2
62°C/W
*Device is mounted on topside.
The ground pin current can be found by examining the
GND Pin Current curves in the Typical Performance
The thermal resistance juncton-to-case (θJC), measured
at the Exposed Pad on the back of the die is 10°C/W.
3023fa
11
LT3023
APPLICATIONS INFORMATION
Calculating Junction Temperature
Example: Given an output voltage on the ﬁrst channel of
3.3V, an output voltage of 2.5V on the second channel, an
input voltage range of 4V to 6V, output current ranges of
0mA to 100mA for the ﬁrst channel and 0mA to 50mA for the
second channel, with a maximum ambient temperature of
50°C, what will the maximum junction temperature be?
The power dissipated by each channel of the device will
be equal to:
IOUT(MAX)(VIN(MAX) – VOUT) + IGND(VIN(MAX))
where (for the ﬁrst channel):
IOUT(MAX) = 100mA
VIN(MAX) = 6V
IGND at (IOUT = 100mA, VIN = 6V) = 2mA
so:
P1 = 100mA(6V – 3.3V) + 2mA(6V) = 0.28W
and (for the second channel):
IOUT(MAX) = 50mA
VIN(MAX) = 6V
IGND at (IOUT = 50mA, VIN = 6V) = 1mA
so:
P2 = 50mA(6V – 2.5V) + 1mA(6V) = 0.18W
The thermal resistance will be in the range of 40°C/W to
60°C/W depending on the copper area. So the junction
temperature rise above ambient will be approximately
equal to:
(0.28W + 018W)(60°C/W) = 27.8°C
The maximum junction temperature will then be equal to
the maximum junction temperature rise above ambient
plus the maximum ambient temperature or:
TJMAX = 50°C + 27.8°C = 77.8°C
Protection Features
The LT3023 regulator incorporates several protection
features which makes it ideal for use in battery-powered
circuits. In addition to the normal protection features
associated with monolithic regulators, such as current
limiting and thermal limiting, the devices are protected
against reverse input voltages, reverse output voltages
and reverse voltages from output to input.
Current limit protection and thermal overload protection
are intended to protect the device against current overload
conditions at the output of the device. For normal operation,
the junction temperature should not exceed 125°C.
The input of the device will withstand reverse voltages
of 20V. Current ﬂow into the device will be limited to less
than 1mA (typically less than 100μA) and no negative
voltage will appear at the output. The device will protect
both itself and the load. This provides protection against
batteries which can be plugged in backward.
The output of the LT3023 can be pulled below ground
without damaging the device. If the input is left open circuit
or grounded, the output can be pulled below ground by
20V. The output will act like an open circuit; no current will
ﬂow out of the pin. If the input is powered by a voltage
source, the output will source the short-circuit current of
the device and will protect itself by thermal limiting. In
this case, grounding the SHDN1/SHDN2 pins will turn off
the device and stop the output from sourcing the shortcircuit current.
The ADJ1 and ADJ2 pins can be pulled above or below
ground by as much as 7V without damaging the device.
If the input is left open circuit or grounded, the ADJ1 and
ADJ2 pins will act like an open circuit when pulled below
ground and like a large resistor (typically 100k) in series
with a diode when pulled above ground.
In situations where the ADJ1 and ADJ2 pins are connected
to a resistor divider that would pull the pins above their 7V
clamp voltage if the output is pulled high, the ADJ1/ADJ2
pin input current must be limited to less than 5mA. For
example, a resistor divider is used to provide a regulated
1.5V output from the 1.22V reference when the output
is forced to 20V. The top resistor of the resistor divider
must be chosen to limit the current into the ADJ pin to
less than 5mA when the ADJ1/ADJ2 pin is at 7V. The 13V
difference between output and ADJ1/ADJ2 pin divided by
the 5mA maximum current into the ADJ1/ADJ2 pin yields
a minimum top resistor value of 2.6k.
3023fa
12
LT3023
APPLICATIONS INFORMATION
In circuits where a backup battery is required, several
different input/output conditions can occur. The output
voltage may be held up while the input is either pulled
to ground, pulled to some intermediate voltage or is left
open circuit. Current ﬂow back into the output will follow
the curve shown in Figure 6.
REVERSE OUTPUT CURRENT (μA)
100
When the IN pin of the LT3023 is forced below the OUT1
or OUT2 pins or the OUT1/OUT2 pins are pulled above the
IN pin, input current will typically drop to less than 2μA.
This can happen if the input of the device is connected
to a discharged (low voltage) battery and the output is
held up by either a backup battery or a second regulator
circuit. The state of the SHDN1/SHDN2 pins will have no
effect on the reverse output current when the output is
pulled above the input.
TA = 25°C
90 VIN = 0V
= VADJ
V
80 OUT
CURRENT FLOWS
760 INTO OUTPUT PIN
60
50
40
30
20
10
0
0
1
2
3 4 5 6 7 8
OUTPUT VOLTAGE (V)
9
10
3023 F06
Figure 6. Reverse Output Current
TYPICAL APPLICATIONS
Noise Bypassing Slows Startup, Allows Outputs to Track
VSHDN1/SHDN2
1V/DIV
VIN
3.7V TO 20V
VOUT1
1V/DIV
VOUT2
1V/DIV
OUT1
IN
0.01μF
1μF
10μF
3.3V
AT 100mA
422k
BYP1
3023 TA02b
2ms/DIV
ADJ1
249k
LT3023
SHDN1
OUT2
0.01μF
SHDN2
BYP2
GND
10μF
2.5V
AT 100mA
100
261k
ADJ2
249k
3023 TA02a
STARTUP TIME (ms)
OFF ON
Startup Time
10
1
0.1
10
100
1000
10000
CBYP (pF)
3023 TA02c
3023fa
13
LT3023
PACKAGE DESCRIPTION
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1699)
R = 0.115
TYP
6
0.38 ± 0.10
10
0.675 ±0.05
3.50 ±0.05
1.65 ±0.05
2.15 ±0.05 (2 SIDES)
3.00 ±0.10
(4 SIDES)
PACKAGE
OUTLINE
1.65 ± 0.10
(2 SIDES)
PIN 1
TOP MARK
(SEE NOTE 6)
(DD) DFN 1103
5
0.25 ± 0.05
0.200 REF
0.50
BSC
2.38 ±0.05
(2 SIDES)
1
0.75 ±0.05
0.00 – 0.05
0.25 ± 0.05
0.50 BSC
2.38 ±0.10
(2 SIDES)
BOTTOM VIEW—EXPOSED PAD
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
3023fa
14
LT3023
PACKAGE DESCRIPTION
MSE Package
10-Lead Plastic MSOP, Exposed Die Pad
(Reference LTC DWG # 05-08-1664 Rev B)
BOTTOM VIEW OF
EXPOSED PAD OPTION
2.794 ± 0.102
(.110 ± .004)
5.23
(.206)
MIN
0.889 ± 0.127
(.035 ± .005)
1
2.06 ± 0.102
(.081 ± .004)
1.83 ± 0.102
(.072 ± .004)
2.083 ± 0.102 3.20 – 3.45
(.082 ± .004) (.126 – .136)
10
0.50
0.305 ± 0.038
(.0197)
(.0120 ± .0015)
BSC
TYP
RECOMMENDED SOLDER PAD LAYOUT
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
10 9 8 7 6
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
4.90 ± 0.152
(.193 ± .006)
0.254
(.010)
DETAIL “A”
0° – 6° TYP
1 2 3 4 5
GAUGE PLANE
0.53 ± 0.152
(.021 ± .006)
DETAIL “A”
0.18
(.007)
0.497 ± 0.076
(.0196 ± .003)
REF
SEATING
PLANE
0.86
(.034)
REF
1.10
(.043)
MAX
0.17 – 0.27
(.007 – .011)
TYP
0.50
(.0197)
BSC
0.1016 ± 0.0508
(.004 ± .002)
MSOP (MSE) 0307 REV B
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
3023fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
15
LT3023
TYPICAL APPLICATION
Startup Sequencing
Turn-On Waveforms
VIN
3.7V TO 20V
VSHDN1
1V/DIV
10μF
0.01μF
LT3023
1μF
3.3V
AT
100mA
OUT1
IN
BYP1
422k
35.7k
249k
28k
VOUT1
1V/DIV
VOUT2
1V/DIV
ADJ1
OFF ON
SHDN1
OUT2
SHDN2
BYP2
10μF
0.01μF
GND
0.47μF
2.5V
AT
100mA
2ms/DIV
3023 TA03b
Turn-Off Waveforms
261k
ADJ2
249k
VSHDN1
1V/DIV
3023 TA03a
VOUT1
1V/DIV
VOUT2
1V/DIV
2ms/DIV
3023 TA03c
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1129
700mA, Micropower, LDO
VIN: 4.2V to 30V, VOUT(MIN) = 3.75V, IQ = 50μA, ISD = 16μA, DD, SOT-223, S8,TO220,
TSSOP20 Packages
LT1175
500mA, Micropower Negative LDO
Guaranteed Voltage Tolerance and Line/Load Regulation, VIN: –20V to –4.3V,
VOUT(MIN) = –3.8V, IQ = 45μA, ISD = 10μA, DD,SOT-223, S8 Packages
LT1185
3A, Negative LDO
Accurate Programmable Current Limit, Remote Sense, VIN: –35V to –4.2V, VOUT(MIN)
= –2.40V, IQ = 2.5mA, ISD <1μA, TO220-5 Package
LT1761
100mA, Low Noise Micropower, LDO
Low Noise < 20μVRMS, Stable with 1μF Ceramic Capacitors, VIN: 1.8V to 20V,
VOUT(MIN) = 1.22V, IQ = 20μA, ISD <1μA, ThinSOT Package
LT1762
150mA, Low Noise Micropower, LDO
Low Noise < 20μVRMS, VIN: 1.8V to 20V, VOUT(MIN) = 1.22V, IQ = 25μA, ISD <1μA,
MS8 Package
LT1763
500mA, Low Noise Micropower, LDO
Low Noise < 20μVRMS, VIN: 1.8V to 20V, VOUT(MIN) = 1.22V, IQ = 30μA, ISD <1μA,
S8 Package
LT1764/LT1764A
3A, Low Noise, Fast Transient Response, LDO
Low Noise < 40μVRMS, "A" Version Stable with Ceramic Capacitors, VIN: 2.7V to 20V,
VOUT(MIN) = 1.21V, IQ = 1mA, ISD <1μA, DD, TO220 Packages
LTC1844
150mA, Very Low Drop-Out LDO
Low Noise < 30μVRMS, Stable with 1μF Ceramic Capacitors, VIN: 1.6V to 6.5V,
VOUT(MIN) = 1.25V, IQ = 40μA, ISD <1μA, ThinSOT Package
LT1962
300mA, Low Noise Micropower, LDO
Low Noise < 20μVRMS, VIN: 1.8V to 20V, VOUT(MIN) = 1.22V, IQ = 30μA, ISD <1μA,
MS8 Package
LT1963/LT1963A
1.5A, Low Noise, Fast Transient Response, LDO Low Noise < 40μVRMS, "A" Version Stable with Ceramic Capacitors, VIN: 2.1V to 20V,
VOUT(MIN) = 1.21V, IQ = 1mA, ISD <1μA, DD, TO220, SOT-223, S8 Packages
LT1964
200mA, Low Noise Micropower, Negative LDO
Low Noise < 30μVRMS, Stable with Ceramic Capacitors, VIN: –0.9V to –20V,
VOUT(MIN) = –1.21V, IQ = 30μA, ISD = 3μA, ThinSOT Package
LTC3407
Dual 600mA. 1.5MHz Synchronous Step Down
DC/DC Converter
VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6 V, IQ = 40μA, ISD <1μA, MSE Package
3023fa
16 Linear Technology Corporation
LT 0208 REV A • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2003

Open as PDF

Similar pages