LINER LTC3407EDD-3 Dual synchronous, 1.8v/0.8a and 3.3v/0.8a 2.25mhz step-down dc/dc regulator Datasheet

LTC3407-3
Dual Synchronous,
1.8V/0.8A and 3.3V/0.8A
2.25MHz Step-Down DC/DC Regulator
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FEATURES
DESCRIPTIO
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The LTC®3407-3 is a dual, constant frequency, synchronous step down DC/DC converter. Intended for low power
applications, it operates from 3.3V to 5.5V input voltage
range and has a constant 2.25MHz switching frequency,
allowing the use of tiny, low cost capacitors and inductors
with a profile ≤1.0mm. Internal synchronous 0.35Ω, 1.2A
power switches provide high efficiency without the need
for external Schottky diodes.
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Very Low Quiescent Current: Only 40µA
1.8V at 800mA/3.3V at 800mA
High Efficiency: Up to 95%
2.25MHz Constant Frequency Operation
High Switch Current: 1.2A on Each Channel
No Schottky Diodes Required
Low RDS(ON) Internal Switches: 0.35Ω
VIN: 3.3V to 5.5V
Current Mode Operation for Excellent Line
and Load Transient Response
Short-Circuit Protected
Low Dropout Operation: 100% Duty Cycle
Ultralow Shutdown Current: IQ < 1µA
Power-On Reset Output
Externally Synchronizable Oscillator
Small Thermally Enhanced 3mm × 3mm DFN Package
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APPLICATIO S
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A user selectable mode input is provided to allow the user
to trade-off noise ripple for low power efficiency. Burst
Mode® operation provides high efficiency at light loads,
while Pulse Skip Mode provides low noise ripple at light
loads.
To further maximize battery life, the P-channel MOSFETs
are turned on continuously in dropout (100% duty cycle),
and both channels draw a total quiescent current of only
40µA. In shutdown, the device draws <1µA.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
Burst Mode is a registered trademark of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Protected by U.S. Patents, including 5481178, 6580258, 6304066, 6127815, 6498466,
6611131.
PDAs/Palmtop PCs
Digital Cameras
Cellular Phones
Portable Media Players
PC Cards
Wireless and DSL Modems
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TYPICAL APPLICATIO
LTC3407-3 Efficiency/Power Loss
100
VIN
3.3V TO 5.5V
RUN2
VIN
LTC3407-3
2.2µH
80
RESET
2.2µH
VOUT1
1.8V
SW1
SW2
10µF
POR
100k
VOUT1
VOUT2
GND
10µF
34073 TA01
NOTE: IN DROPOUT, THE OUTPUT TRACKS THE INPUT VOLTAGE
Figure 1. 1.8V/3.3V at 800mA Step-Down Regulators
VOUT = 1.8V
0.1
70
60
VOUT = 3.3V
50
0.01
VOUT = 1.8V
40
POWER LOSS (W)
MODE/SYNC
RUN1
EFFICIENCY (%)
10µF
VOUT2
3.3V
1
VOUT = 3.3V
90
0.001
30
VIN = 5V
Burst Mode OPERATION
NO LOAD ON OTHER CHANNEL
20
10
1
10
100
LOAD CURRENT (mA)
0.000
1000
34073 TA01b
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LTC3407-3
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ABSOLUTE
AXI U RATI GS
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PACKAGE/ORDER I FOR ATIO
(Note 1)
VIN Voltages.................................................– 0.3V to 6V
VOUT1, VOUT2 Voltages .................... – 0.3V to VIN + 0.3V
RUN1, RUN2 Voltages ................................ –0.3V to VIN
MODE/SYNC Voltage .................................. – 0.3V to VIN
SW1, SW2 Voltage ......................... – 0.3V to VIN + 0.3V
POR Voltage ................................................– 0.3V to 6V
Ambient Operating Temperature
Range (Note 2) ....................................... – 40°C to 85°C
Junction Temperature (Note 5) ............................. 125°C
Storage Temperature Range ................. – 65°C to 125°C
TOP VIEW
10 VOUT2
VOUT1
1
RUN1
2
VIN
3
SW1
4
7 SW2
GND
5
6 MODE/
SYNC
9 RUN2
11
8 POR
DD PACKAGE
10-LEAD (3mm × 3mm) PLASTIC DFN
TJMAX = 125°C, θJA = 40°C/W, θJC = 10°C/W
EXPOSED PAD (PIN 11) IS PGND, MUST BE SOLDERED TO PCB GND
ORDER PART NUMBER
DD PART MARKING
LTC3407EDD-3
LCJB
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 3.6V, unless otherwise specified. (Note 2)
SYMBOL
VIN
VOUT1
VOUT2
∆VLINE REG
∆VLOAD REG
IS
fOSC
fSYNC
ILIM
RDS(ON)
ISW(LKG)
POR
VRUN
IRUN
VMODE
PARAMETER
Operating Voltage Range
Output Voltage (Note 3)
CONDITIONS
0°C ≤ TA ≤ 85°C
–40°C ≤ TA ≤ 85°C
Output Voltage (Note 3)
0°C ≤ TA ≤ 85°C
–40°C ≤ TA ≤ 85°C
Reference Voltage Line Regulation (Note 3) VIN = 3.3V to 5.5V (Channel 1)
VIN = 3.6V to 5.5V (Channel 2)
Output Voltage Load Regulation (Note 3)
Input DC Supply Current (Note 4)
Active Mode
VOUT1 = 1.5V, VOUT2 = 2.8V
Sleep Mode
VOUT1 = 1.9V, VOUT2 = 3.5V, MODE/SYNC = 3.6V
Shutdown
RUN = 0V, VIN = 5.5V, MODE/SYNC = 0V
Oscillator Frequency
VOUT1 = 1.8V, VOUT2 = 3.3V
Synchronization Frequency
Peak Switch Current Limit, Channel 1 +
VIN = 3V, VOUT1 = 1.5V, VOUT2 = 2.8V,
Channel 2
Duty Cycle <35%
Top Switch On-Resistance
(Note 6)
Bottom Switch On-Resistance
(Note 6)
Switch Leakage Current
VIN = 5V, VRUN = 0V, VOUT1 = VOUT2 = 0V
Power-On Reset Threshold
VOUT Ramping Down, MODE/SYNC = 0V
Power-On Reset On-Resistance
Power-On Reset Delay
RUN Threshold
RUN Leakage Current
MODE Threshold Low
MODE Threshold High
●
●
●
MIN
3.3
1.764
1.755
3.234
3.218
TYP
1.8
1.8
3.3
3.3
0.3
MAX
5.5
1.836
1.836
3.366
3.366
0.5
0.5
●
1.8
0.95
●
0.3
●
0
VIN – 0.5
UNITS
V
V
V
V
V
%/V
%
700
40
0.1
2.25
2.25
1.2
950
60
1
2.7
0.35
0.30
0.01
–8.5
100
262,144
1
0.01
0.45
0.45
1
1.6
200
1.5
1
0.5
VIN
µA
µA
µA
MHz
MHz
A
Ω
Ω
µA
%
Ω
Cycles
V
µA
V
V
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LTC3407-3
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime. No pin shall exceed 6V.
Note 2: The LTC3407E-3 is guaranteed to meet specified performance
from 0°C to 85°C. Specifications over the – 40°C and 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
Note 3: The LTC3407-3 is tested in a proprietary test mode that connects
the output of the error amplifier to an outside servo loop.
Note 4: Dynamic supply current is higher due to the internal gate charge
being delivered at the switching frequency.
Note 5: TJ is calculated from the ambient TA and power dissipation PD
according to the following formula: TJ = TA + (PD • θJA).
Note 6: The DFN switch on-resistance is guaranteed by correlation to
wafer level measurements.
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TYPICAL PERFOR A CE CHARACTERISTICS
Burst Mode Operation
SW
5V/DIV
VOUT
20mV/DIV
VOUT
20mV/DIV
IL
200mA/DIV
IL
200mA/DIV
2µs/DIV
Load Step
Pulse Skipping Mode
SW
5V/DIV
VIN = 3.6V
VOUT = 1.8V
ILOAD = 100mA
TA = 25°C unless other wise specified.
34073 G01
VOUT
200mV/DIV
IL
500mA/DIV
ILOAD
500mA/DIV
VIN = 3.6V
VOUT = 1.8V
ILOAD = 20mA
1µs/DIV
34073 G02
Oscillator Frequency Deviation
vs Supply Voltage
Oscillator Frequency vs
Temperature
Load Step
2.5
VOUT
200mV/DIV
10
VIN = 3.6V
8
ILOAD
500mA/DIV
VIN = 5V
20µs/DIV
VOUT = 3.3V
ILOAD = 80mA TO 800mA
CIRCUIT OF FIGURE 1
34073 G04
FREQUENCY DEVIATION (%)
FREQUENCY (MHz)
2.4
IL
500mA/DIV
34073 G03
VIN = 3.6V
20µs/DIV
VOUT = 1.8V
ILOAD = 80mA TO 800mA
CIRCUIT OF FIGURE 1
2.3
2.2
2.1
6
4
2
0
–2
–4
–6
–8
2.0
–50 –25
–10
50
25
75
0
TEMPERATURE (°C)
100
125
2
3
4
5
6
SUPPLY VOLTAGE (V)
34073 G05
34073 G06
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LTC3407-3
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TYPICAL PERFOR A CE CHARACTERISTICS
Reference Voltage vs
Temperature
RDS(ON) vs Input Voltage
0.615
RDS(ON) vs Temperature
500
VIN = 3.6V
550
500
0.610
450
VIN = 3.6V
450
0.600
0.595
400
RDS(ON) (mΩ)
0.605
RDS(ON) (mΩ)
REFERENCE VOLTAGE (V)
TA = 25°C unless other wise specified.
MAIN
SWITCH
350
300
0.590
250
0.585
–50 –25
200
SYNCHRONOUS
SWITCH
VIN = 4.2V
400
350
300
250
200
150
50
25
75
0
TEMPERATURE (°C)
100
1
125
2
3
4
VIN (V)
5
Efficiency vs VIN
Efficiency vs Load Current
95
25 50 75 100 125 150
TEMPERATURE (°C)
Efficiency vs Load Current
100
95
Burst Mode OPERATION
100mA
90
85
800mA
80
1mA
75
70
65
85
80
PULSE SKIP MODE
75
70
60
VOUT = 1.8V
Burst Mode OPERATION
CH2 OFF
55
50
2
4
3
60
1
6
INPUT VOLTAGE (V)
10
100
LOAD CURRENT (mA)
Load Regulation
4
3
3
2
1000
0
PULSE SKIP MODE
–2
Line Regulation
0.80
VOUT = 1.8V
0.60 IOUT = 200mA
0.40
1
Burst Mode OPERATION
0
PULSE SKIP MODE
–1
–2
VIN = 3.6V, VOUT = 1.8V
NO LOAD ON OTHER CHANNEL
–4
1
10
100
LOAD CURRENT (mA)
1000
34073 G12
1000
34073 G11
VOUT ERROR (%)
VOUT ERROR (%)
1
10
100
LOAD CURRENT (mA)
1
2
Burst Mode OPERATION
VIN = 3.6V, VOUT = 1.8V
NO LOAD ON OTHER CHANNEL
60
Load Regulation
4
–3
PULSE SKIP MODE
34073 G14
34073 G10
–1
80
70
VIN = 5V,
VOUT = 3.3V
NO LOAD ON
OTHER CHANNEL
65
5
Burst Mode OPERATION
90
EFFICIENCY (%)
10mA
EFFICIENCY (%)
EFFICIENCY (%)
0
34073 G09
100
100
VOUT ERROR (%)
7
6
MAIN SWITCH
SYNCHRONOUS SWITCH
34073 G08
34073 G07
90
100
–50 –25
0.20
0
–0.20
–0.40
–0.60
–3
VIN = 5V, VOUT = 3.3V
NO LOAD ON OTHER CHANNEL
–4
1
10
100
LOAD CURRENT (mA)
1000
–0.80
–1.00
2
3
4
5
6
VIN (V)
34073 G13
34073 G15
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LTC3407-3
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PI FU CTIO S
VOUT1 (Pin 1): Output Voltage Feedback Pin for Channel 1.
An internal resistive divider divides the output voltage
down for comparison to the internal reference voltage.
RUN1 (Pin 2): Regulator 1 Enable. Forcing this pin to VIN
enables regulator 1, while forcing it to GND causes regulator 1 to shut down. Do not float this pin.
VIN (Pin 3): Main Power Supply. Must be closely decoupled
to GND.
SW1 (Pin 4): Regulator 1 Switch Node Connection to the
Inductor. This pin swings from VIN to GND.
GND (Pin 5): Main Ground. Connect to the (–) terminal of
COUT, and (–) terminal of CIN.
MODE/SYNC (Pin 6): Combination Mode Selection and
Oscillator Synchronization. This pin controls the operation
of the device. When tied to VIN or GND, Burst Mode
operation or pulse skipping mode is selected, respectively. The oscillation frequency can be syncronized to an
external oscillator applied to this pin and pulse skipping
mode is automatically selected. Do not float this pin.
SW2 (Pin 7): Regulator 2 Switch Node Connection to the
Inductor. This pin swings from VIN to GND.
POR (Pin 8): Power-On Reset . This common-drain logic
output is pulled to GND when the output voltage falls
below –8.5% of regulation and goes high after 262,144
clock cycles when both channels are within regulation.
RUN2 (Pin 9): Regulator 2 Enable. Forcing this pin to VIN
enables regulator 2, while forcing it to GND causes regulator 2 to shut down. Do not float this pin.
VOUT2 (Pin 10): Output Voltage Feedback Pin for Channel 2. An internal resistive divider divides the output
voltage down for comparison to the internal reference
voltage.
Exposed Pad (GND) (Pin 11): Power Ground. Connect to
the (–) terminal of COUT, and (–) terminal of CIN. Must be
connected to electrical ground on PCB.
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LTC3407-3
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BLOCK DIAGRA
REGULATOR 1
MODE/SYNC
6
BURST
CLAMP
VIN
SLOPE
COMP
VOUT1
1
R1
VFB
EN
–
+
0.6V
EA
SLEEP
ITH
–
+
5Ω
ICOMP
+
0.65V
–
BURST
R3
S
Q
RS
LATCH
R
Q
0.55V
–
UVDET
UV
+
SWITCHING
LOGIC
AND
BLANKING
CIRCUIT
ANTI
SHOOTTHRU
4 SW1
+
OVDET
–
+
0.65V
OV
IRCMP
SHUTDOWN
–
11 GND
VIN
PGOOD1
RUN1
2
RUN2
9
3 VIN
8 POR
0.6V REF
POR
COUNTER
OSC
OSC
5 GND
PGOOD2
VOUT2 10
REGULATOR 2 (IDENTICAL TO REGULATOR 1)
R1 = 240k, R3 = 120k FOR CHANNEL 1
R1 = 270k, R2 = 60k FOR CHANNEL 2
7 SW2
34073 BD
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LTC3407-3
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OPERATIO
The LTC3407-3 uses a constant frequency, current mode
architecture. The operating frequency is set at 2.25MHz
and can be synchronized to an external oscillator. Both
channels share the same clock and run in-phase. To suit
a variety of applications, the selectable Mode pin allows
the user to choose between low noise and light load
efficiency.
The output voltage is set by an internal divider. An error
amplfier compares the divided output voltage with a
reference voltage of 0.6V and adjusts the peak inductor
current accordingly. An undervoltage comparator pulls
the POR output low if the output voltage is not above
–8.5% of the reference voltage. The POR output will go
high after 262,144 clock cycles of achieving regulation.
Main Control Loop
During normal operation, the top power switch (P-channel
MOSFET) is turned on at the beginning of a clock cycle
when the VOUT voltage is below the the regulated voltage.
The current flows into the inductor and the load increases
until the current limit is reached. The switch turns off and
energy stored in the inductor flows through the bottom
switch (N-channel MOSFET) into the load until the next
clock cycle.
The peak inductor current is controlled by the internally
compensated ITH voltage, which is the output of the error
amplifier.This amplifier compares the VFB (see Block Diagram) to the 0.6V reference. When the load current increases, the VFB voltage decreases slightly below the
reference. This decrease causes the error amplifier to
increase the ITH voltage until the average inductor current
matches the new load current.
The main control loop is shut down by pulling the RUN pin
to ground.
Low Current Operation
Two modes are available to control the operation of the
LTC3407-3 at low currents. Both modes automatically
switch from continuous operation to the selected mode
when the load current is low.
To optimize efficiency, the Burst Mode operation can be
selected. When the load is relatively light, the LTC3407-3
automatically switches into Burst Mode operation, in
which the PMOS switch operates intermittently based on
load demand with a fixed peak inductor current. By running cycles periodically, the switching losses which are
dominated by the gate charge losses of the power MOSFETs
are minimized. The main control loop is interrupted when
the output voltage reaches the desired regulated value. A
voltage comparator trips when ITH is below 0.65V, shutting off the switch and reducing the power. The output
capacitor and the inductor supply the power to the load
until ITH exceeds 0.65V, turning on the switch and the main
control loop which starts another cycle.
For lower ripple noise at low currents, the pulse skipping
mode can be used. In this mode, the LTC3407-3 continues
to switch at a constant frequency down to very low
currents, where it will begin skipping pulses. The efficiency in pulse skip mode can be improved slightly by
connecting the SW node to the MODE/SYNC input which
reduces the clock frequency by approximately 30%.
Dropout Operation
When the input supply voltage decreases toward the
output voltage, the duty cycle increases to 100% which is
the dropout condition. In dropout, the PMOS switch is
turned on continuously with the output voltage being
equal to the input voltage minus the voltage drops across
the internal p-channel MOSFET and the inductor.
An important design consideration is that the RDS(ON) of
the P-channel switch increases with decreasing input
supply voltage (See Typical Performance Characteristics).
Therefore, the user should calculate the power dissipation
when the LTC3407-3 is used at 100% duty cycle with low
input voltage (See Thermal Considerations in the Applications Information Section).
Low Supply Operation
To prevent unstable operation, the LTC3407-3 incorporates an Undervoltage Lockout circuit which shuts down
the part when the input voltage drops below about 1.65V.
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LTC3407-3
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APPLICATIO S I FOR ATIO
A general LTC3407-3 application circuit is shown in
Figure 2. External component selection is driven by the
load requirement, and begins with the selection of the
inductor L. Once the inductor is chosen, CIN and COUT can
be selected.
Table 1 shows some typical surface mount inductors that
work well in LTC3407-3 applications.
Inductor Selection
Although the inductor does not influence the operating
frequency, the inductor value has a direct effect on ripple
current. The inductor ripple current ∆IL decreases with
higher inductance and increases with higher VIN or VOUT:
∆IL =
VOUT ⎛ VOUT ⎞
• ⎜ 1–
⎟
fO • L ⎝
VIN ⎠
Accepting larger values of ∆IL allows the use of low
inductances, but results in higher output voltage ripple,
greater core losses, and lower output current capability.
A reasonable starting point for setting ripple current is
∆IL = 0.3 • ILIM, where ILIM is the peak switch current limit.
The largest ripple current ∆IL occurs at the maximum
input voltage. To guarantee that the ripple current stays
below a specified maximum, the inductor value should be
chosen according to the following equation:
⎛
⎞
V
• ⎜ 1 – OUT ⎟
⎝ VIN(MAX) ⎠
The inductor value will also have an effect on Burst Mode
operation. The transition from low current operation
begins when the peak inductor current falls below a level
set by the burst clamp. Lower inductor values result in
higher ripple current which causes this to occur at lower
load currents. This causes a dip in efficiency in the upper
range of low current operation. In Burst Mode operation,
lower inductance values will cause the burst frequency to
increase.
L=
VOUT
fO • ∆IL
Inductor Core Selection
Different core materials and shapes will change the size/
current and price/current relationship of an inductor.
Toroid or shielded pot cores in ferrite or permalloy materials are small and don’t radiate much energy, but generally cost more than powdered iron core inductors with
similar electrical characterisitics. The choice of which
style inductor to use often depends more on the price vs
size requirements and any radiated field/EMI requirements than on what the LTC3407-3 requires to operate.
Table 1. Representative Surface Mount Inductors
PART
NUMBER
VALUE
(µH)
DCR
(Ω MAX)
MAX DC
SIZE
CURRENT (A) W × L × H (mm3)
Sumida
CDRH3D16
2.2
3.3
4.7
0.075
0.110
0.162
1.20
1.10
0.90
3.8 × 3.8 × 1.8
Sumida
CDRH2D11
1.5
2.2
0.068
0.170
0.900
0.780
3.2 × 3.2 × 1.2
Sumida
CMD4D11
2.2
3.3
0.116
0.174
0.950
0.770
4.4 × 5.8 × 1.2
Murata
LQH32CN
1.0
2.2
0.060
0.097
1.00
0.79
2.5 × 3.2 × 2.0
Toko
D312F
2.2
3.3
0.060
0.260
1.08
0.92
2.5 × 3.2 × 2.0
Panasonic
ELT5KT
3.3
4.7
0.17
0.20
1.00
0.95
4.5 × 5.4 × 1.2
Input Capacitor (CIN) Selection
In continuous mode, the input current of the converter is
a square wave with a duty cycle of approximately VOUT/
VIN. To prevent large voltage transients, a low equivalent
series resistance (ESR) input capacitor sized for the maximum RMS current must be used. The maximum RMS
capacitor current is given by:
IRMS ≈ IMAX
VOUT ( VIN – VOUT )
VIN
where the maximum average output current IMAX equals
the peak current minus half the peak-to-peak ripple current, IMAX = ILIM – ∆IL/2.
This formula has a maximum at VIN = 2VOUT, where IRMS
= IOUT/2. This simple worst-case is commonly used to
design because even significant deviations do not offer
much relief. Note that capacitor manufacturer’s ripple
current ratings are often based on only 2000 hours lifetime. This makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature
than required. Several capacitors may also be paralleled to
meet the size or height requirements of the design. An
additional 0.1µF to 1µF ceramic capacitor is also recommended on VIN for high frequency decoupling, when not
using an all ceramic capacitor solution.
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LTC3407-3
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APPLICATIO S I FOR ATIO
Output Capacitor (COUT) Selection
The selection of COUT is driven by the required ESR to
minimize voltage ripple and load step transients. Typically,
once the ESR requirement is satisfied, the capacitance is
adequate for filtering. The output ripple (∆VOUT) is determined by:
∆VOUT
⎛
1 ⎞
≈ ∆IL ⎜ ESR +
8 fO COUT ⎟⎠
⎝
where f = operating frequency, COUT = output capacitance
and ∆IL = ripple current in the inductor. The output ripple
is highest at maximum input voltage since ∆IL increases
with input voltage. With ∆IL = 0.3 • ILIM the output ripple
will be less than 100mV at maximum VIN and fO = 2.25MHz
with:
In addition, the high Q of ceramic capacitors along with
trace inductance can lead to significant ringing.
In most cases, 0.1µF to 1µF of ceramic capacitors should
also be placed close to the LTC3407-3 in parallel with the
main capacitors for high frequency decoupling.
VIN
10µF
RUN2
VIN
MODE/SYNC
L2 µH
VOUT2
COUT2
RUN1
POR
100k
RESET
L1 µH
LTC3407-3
SW2
SW1
VOUT2
VOUT1
GND
VOUT1
COUT1
34073 F02
Figure 2. LTC3407-3 General Schematic
ESRCOUT < 150mΩ
Once the ESR requirements for COUT have been met, the
RMS current rating generally far exceeds the IRIPPLE(P-P)
requirement, except for an all ceramic solution.
In surface mount applications, multiple capacitors may
have to be paralleled to meet the capacitance, ESR or RMS
current handling requirement of the application. Aluminum electrolytic, special polymer, ceramic and dry tantulum
capacitors are all available in surface mount packages. The
OS-CON semiconductor dielectric capacitor available from
Sanyo has the lowest ESR(size) product of any aluminum
electrolytic at a somewhat higher price. Special polymer
capacitors, such as Sanyo POSCAP, Panasonic Special
Polymer (SP), and Kemet A700, offer very low ESR, but
have a lower capacitance density than other types. Tantalum capacitors have the highest capacitance density, but
they have a larger ESR and it is critical that the capacitors
are surge tested for use in switching power supplies. An
excellent choice is the AVX TPS series of surface mount
tantalums, available in case heights ranging from 2mm to
4mm. Aluminum electrolytic capacitors have a significantly larger ESR, and are often used in extremely costsensitive applications provided that consideration is given
to ripple current ratings and long term reliability. Ceramic
capacitors have the lowest ESR and cost, but also have the
lowest capacitance density, a high voltage and temperature coefficient, and exhibit audible piezoelectric effects.
Ceramic Input and Output Capacitors
Higher value, lower cost ceramic capacitors are now
becoming available in smaller case sizes. These are tempting for switching regulator use because of their very low
ESR. Unfortunately, the ESR is so low that it can cause
loop stability problems. Solid tantalum capacitor ESR
generates a loop “zero” at 5kHz to 50kHz that is instrumental in giving acceptable loop phase margin. Ceramic capacitors remain capacitive to beyond 300kHz and usually
resonate with their ESL before ESR becomes effective.
Also, ceramic caps are prone to temperature effects which
requires the designer to check loop stability over the
operating temperature range. To minimize their large
temperature and voltage coefficients, only X5R or X7R
ceramic capacitors should be used. A good selection of
ceramic capacitors is available from Taiyo Yuden, AVX,
Kemet, TDK, and Murata.
Great care must be taken when using only ceramic input
and output capacitors. When a ceramic capacitor is used
at the input and the power is being supplied through long
wires, such as from a wall adapter, a load step at the output
can induce ringing at the VIN pin. At best, this ringing can
couple to the output and be mistaken as loop instability. At
worst, the ringing at the input can be large enough to
damage the part.
34073fa
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LTC3407-3
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APPLICATIO S I FOR ATIO
Since the ESR of a ceramic capacitor is so low, the input
and output capacitor must instead fulfill a charge storage
requirement. During a load step, the output capacitor must
instantaneously supply the current to support the load
until the feedback loop raises the switch current enough to
support the load. The time required for the feedback loop
to respond is dependent on the compensation and the
output capacitor size. Typically, 3-4 cycles are required to
respond to a load step, but only in the first cycle does the
output drop linearly. The output droop, VDROOP, is usually
about 2-3 times the linear drop of the first cycle. Thus, a
good place to start is with the output capacitor size of
approximately:
COUT ≈ 2.5
∆IOUT
fO • VDROOP
More capacitance may be required depending on the duty
cycle and load step requirements.
In most applications, the input capacitor is merely required to supply high frequency bypassing, since the
impedance to the supply is very low. A 10µF ceramic
capacitor is usually enough for these conditions.
Power-On Reset
The POR pin is an open-drain output which pulls low when
either regulator is out of regulation. When both output
voltages are above –8.5% of regulation, a timer is started
which releases POR after 218 clock cycles (about 117ms).
This delay can be significantly longer in Burst Mode
operation with low load currents, since the clock cycles
only occur during a burst and there could be milliseconds
of time between bursts. This can be bypassed by tying the
POR output to the MODE/SYNC input, to force pulse
skipping mode during a reset. In addition, if the output
voltage faults during Burst Mode sleep, POR could have a
slight delay for an undervoltage output condition and may
not respond to an overvoltage output. This can be avoided
by using pulse skipping mode instead. When either channel is shut down, the POR output is pulled low, since one
or both of the channels are not in regulation.
Mode Selection & Frequency Synchronization
The MODE/SYNC pin is a multipurpose pin which provides mode selection and frequency synchronization.
Connecting this pin to VIN enables Burst Mode operation,
which provides the best low current efficiency at the cost
of a higher output voltage ripple. Connecting this pin to
ground selects pulse skipping mode, which provides the
lowest output ripple, at the cost of low current efficiency.
The LTC3407-3 can also be synchronized to an external
2.25MHz clock signal (such as the SW pin on another
LTC3407-3)by the MODE/SYNC pin. During synchronization, the mode is set to pulse skipping and the top switch
turn-on is synchronized to the rising edge of the external
clock.
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, VOUT immediately shifts by an amount
equal to ∆ILOAD • ESR, where ESR is the effective series
resistance of COUT. ∆ILOAD also begins to charge or
discharge COUT, generating a feedback error signal used
by the regulator to return VOUT to its steady-state value.
During this recovery time, VOUT can be monitored for
overshoot or ringing that would indicate a stability
problem. The initial output voltage step may not be within
the bandwidth of the feedback loop, so the standard
second-order overshoot/DC ratio cannot be used to determine phase margin.
The output voltage settling behavior is related to the
stability of the closed-loop system and will demonstrate
the actual overall supply performance. For a detailed
explanation of optimizing the compensation components,
including a review of control loop theory, refer to Application Note 76.
In some applications, a more severe transient can be caused
by switching in loads with large (>1µF) input capacitors.
The discharged input capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator
can deliver enough current to prevent this problem, if the
switch connecting the load has low resistance and is driven
quickly. The solution is to limit the turn-on speed of the
load switch driver. A Hot SwapTM controller is designed
specifically for this purpose and usually incorporates current limiting, short-circuit protection, and soft-starting.
Hot Swap is registered trademark of Linear Technology Corporation.
34073fa
10
LTC3407-3
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APPLICATIO S I FOR ATIO
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can be
expressed as:
%Efficiency = 100% - (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage
of input power.
Although all dissipative elements in the circuit produce
losses, 4 main sources usually account for most of the
losses in LTC3407-3 circuits: 1)VIN quiescent current, 2)
switching losses, 3) I2R losses, 4) other losses.
1) The VIN current is the DC supply current given in the
Electrical Characteristics which excludes MOSFET driver
and control currents. VIN current results in a small (<0.1%)
loss that increases with VIN, even at no load.
2) The switching current is the sum of the MOSFET driver
and control currents. The MOSFET driver current results
from switching the gate capacitance of the power MOSFETs.
Each time a MOSFET gate is switched from low to high to
low again, a packet of charge dQ moves from VIN to
ground. The resulting dQ/dt is a current out of VIN that is
typically much larger than the DC bias current. In continuous mode, IGATECHG = fO(QT + QB), where QT and QB are the
gate charges of the internal top and bottom MOSFET
switches. The gate charge losses are proportional to VIN
and thus their effects will be more pronounced at higher
supply voltages.
3) I2R losses are calculated from the DC resistances of the
internal switches, RSW, and external inductor, RL. In
continuous mode, the average output current flows through
inductor L, but is “chopped” between the internal top and
bottom switches. Thus, the series resistance looking into
the SW pin is a function of both top and bottom MOSFET
RDS(ON) and the duty cycle (DC) as follows:
RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 – DC)
The RDS(ON) for both the top and bottom MOSFETs can be
obtained from the Typical Performance Characteristics
curves. Thus, to obtain I2R losses:
I2R losses = IOUT2(RSW + RL)
4) Other ‘hidden’ losses such as copper trace and internal
battery resistances can account for additional efficiency
degradations in portable systems. It is very important to
include these “system” level losses in the design of a
system. The internal battery and fuse resistance losses
can be minimized by making sure that CIN has adequate
charge storage and very low ESR at the switching frequency. Other losses including diode conduction losses
during dead-time and inductor core losses generally account for less than 2% total additional loss.
Thermal Considerations
In a majority of applications, the LTC3407-3 does not
dissipate much heat due to its high efficiency. However, in
applications where the LTC3407-3 is running at high
ambient temperature with low supply voltage and high
duty cycles, such as in dropout, the heat dissipated may
exceed the maximum junction temperature of the part. If
the junction temperature reaches approximately 150°C,
both power switches will turn off and the SW node will
become high impedance.
To prevent the LTC3407-3 from exceeding the maximum
junction temperature, the user will need to do some
thermal analysis. The goal of the thermal analysis is to
determine whether the power dissipated exceeds the
maximum junction temperature of the part. The temperature rise is given by:
TRISE = PD • θJA
where PD is the power dissipated by the regulator and θJA
is the thermal resistance from the junction of the die to the
ambient temperature.
The junction temperature, TJ, is given by:
TJ = TRISE + TAMBIENT
As an example, consider the case when the LTC3407-3 is
in dropout on both channels at an input voltage of 2.7V
34073fa
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LTC3407-3
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APPLICATIO S I FOR ATIO
with a load current of 800mA and an ambient temperature
of 70°C. From the Typical Performance Characteristics
graph of Switch Resistance, the RDS(ON) resistance of the
main switch is 0.425Ω. Therefore, power dissipated by
each channel is:
Choosing a vendor’s closest inductor value of 2.2µH,
results in a maximum ripple current of:
∆IL =
PD = I2 • RDS(ON) = 272mW
1.8 V
⎛ 1.8 V ⎞
• ⎜ 1−
= 208mA
2.25MHz • 2.2µH ⎝ 4.2V ⎟⎠
For cost reasons, a ceramic capacitor will be used. COUT
selection is then based on load step droop instead of ESR
requirements. For a 5% output droop:
The DFN package junction-to-ambient thermal resistance,
θJA, is 40°C/W. Therefore, the junction temperature of the
regulator operating in a 70°C ambient temperature is
approximately:
COUT ≈ 1.8
TJ = 2 • 0.272 • 40 + 70 = 91.8°C
800mA
= 7.1µF
2.25MHz •(5% • 1.8 V)
A good standard value is 10µF. Since the output impedance of a Li-Ion battery is very low, CIN is typically 10µF.
The PGOOD pin is a common drain output and requires a
pull-up resistor. A 100k resistor is used for adequate speed.
which is below the absolute maximum junction temperature of 125°C.
Design Example
Figure 1 shows the complete schematic for this design
example.
As a design example, consider using the LTC3407-3 in an
portable application with a Li-Ion battery. The battery
provides a VIN = 2.8V to 4.2V. The load requires a maximum of 800mA in active mode and 2mA in standby mode.
The output voltage is VOUT = 1.8V. Since the load still
needs power in standby, Burst Mode operation is selected
for good low load efficiency.
Board Layout Considerations
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3407-3. These items are also illustrated graphically in
the layout diagram of Figure 3. Check the following in your
layout:
First, calculate the inductor value for about 30% ripple
current at maximum VIN:
1. Does the capacitor CIN connect to the power VIN (Pin 3)
and GND (exposed pad) as close as possible? This capacitor provides the AC current to the internal power MOSFETs
and their drivers.
1.8 V
⎛ 1.8 V ⎞
L=
• ⎜ 1–
= 1.5µH
2.25MHz • 300mA ⎝ 4.2V ⎟⎠
VIN
CIN
RUN2
VIN
RUN1
MODE/SYNC
VOUT2
POR
LTC3407-3
L2
VOUT1
VFB1
VFB2
COUT2
L1
SW1
SW2
COUT1
GND
34073 F03
BOLD LINES INDICATE
HIGH CURRENT PATH
Figure 3. LTC3407-3 Layout Diagram (See Board Layout Checklist)
34073fa
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LTC3407-3
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APPLICATIO S I FOR ATIO
2. Are the COUT and L1 closely connected? The (–) plate of
COUT returns current to GND and the (–) plate of CIN.
5. A ground plane is preferred, but if not available, keep the
signal and power grounds segregated with small signal
components returning to the GND pin at one point and
should not share the high current path of CIN or COUT.
3. The output feedback line should be routed away from
noisy components and traces, such as the SW line
(Pins 4 and 7), and its trace should be minimized.
6. Flood all unused areas on all layers with copper.
Flooding with copper will reduce the temperature rise of
power components. These copper areas should be connected to VIN or GND.
4. Keep sensitive components away from the SW pins. The
input capacitor CIN should be routed away from the SW
traces and the inductors.
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TYPICAL APPLICATIO S
Low Ripple Buck Regulators Using Ceramic Capacitors
VIN
5V
C1*
10µF
RUN2
VIN
MODE/SYNC
L2
4.7µH
VOUT2
3.3V
800mA
C3
10µF
R5
100k
RUN1
POR
L1
4.7µH
LTC3407-3
SW2
SW1
VOUT2
VOUT1
POWER-ON
RESET
VOUT1
1.8V
800mA
C2
10µF
GND
34073 TA03a
C1, C2, C3: TAIYO YUDEN JMK316BJ106ML
L1, L2: SUMIDA CDRH2D18/HP-4R7NC
*IF C1 IS GREATER THAN 3" FROM POWER SOURCE,
ADDITIONAL CAPACITANCE MAY BE REQUIRED.
Efficiency vs Load Current
100
95
EFFICIENCY (%)
90
VOUT = 3.3V
85
80
VOUT = 1.8V
75
70
65
60
VIN = 5V
PULSE SKIP MODE
NO LOAD ON OTHER CHANNEL
55
50
10
100
LOAD CURRENT (mA)
1000
34073 TA02b
34073fa
13
LTC3407-3
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TYPICAL APPLICATIO S
1mm Height Core Supply
VIN
5V
C1*
10µF
RUN2
VIN
MODE/SYNC
L2
2.2µH
VOUT2
3.3V
800mA
POR
L1
2.2µH
LTC3407-3
POWER-ON
RESET
SW1
SW2
VOUT1
VOUT2
C3
10µF
R5
100k
RUN1
VOUT1
1.8V
800mA
C2
10µF
GND
34073 TA03a
C1, C2, C3: TAIYO YUDEN JMK212BJ106MD-B
L1, L2: COILCRAFT LDO3310-222MX
*IF C1 IS GREATER THAN 3" FROM POWER SOURCE,
ADDITIONAL CAPACITANCE MAY BE REQUIRED.
Efficiency vs Load Current
100
95
EFFICIENCY (%)
90
VOUT = 3.3V
85
80
VOUT = 1.8V
75
70
65
60
VIN = 5V
55 Burst Mode OPERATION
NO LOAD ON OTHER CHANNEL
50
10
100
1
LOAD CURRENT (mA)
1000
34073 TA03b
34073fa
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LTC3407-3
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PACKAGE DESCRIPTIO
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1699)
0.675 ±0.05
3.50 ±0.05
1.65 ±0.05
2.15 ±0.05 (2 SIDES)
PACKAGE
OUTLINE
0.25 ± 0.05
0.50
BSC
2.38 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
R = 0.115
TYP
6
3.00 ±0.10
(4 SIDES)
0.38 ± 0.10
10
1.65 ± 0.10
(2 SIDES)
PIN 1
TOP MARK
(SEE NOTE 6)
(DD10) DFN 1103
5
0.200 REF
1
0.75 ±0.05
0.00 – 0.05
0.25 ± 0.05
0.50 BSC
2.38 ±0.10
(2 SIDES)
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
34073fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
15
LTC3407-3
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TYPICAL APPLICATIO
2mm Height Lithium-Ion Single Inductor Buck-Boost Regulator and a Buck Regulator
VIN
2.8V TO 4.2V
C1
10µF
RUN2
VIN
MODE/SYNC
VOUT2
3.3V
200mA
L2
10µH
D1
C6
47µF
POWER-ON
RESET
POR
L1
2.2µH
LTC3407-3
SW2
+
R5
100k
RUN1
SW1
M1
C3
10µF
VOUT1
VOUT2
VOUT1
1.8V
800mA
C2
10µF
GND
34073 TA04a
C1, C2, C3: TAIYO YUDEN JMK316BJ106ML
C6: SANYO 6TPB47M
D1: PHILIPS PMEG2010
L1: MURATA LQH32CN2R2M33
L2: TOKO A914BYW-100M (D52LC SERIES)
M1: SILICONIX Si2302
Efficiency vs Load Current
Efficiency vs Load Current
100
90
95
2.8V
90
4.2V
70
60
3.6V
50
EFFICIENCY (%)
EFFICIENCY (%)
80
2.8V
40 VOUT = 3.3V
Burst Mode OPERATION
NO LOD ON OTHER CHANNEL
30
1
10
100
LOAD CURRENT (mA)
4.2V
85
3.6V
80
75
70
VOUT = 1.8V
Burst Mode OPERATION
NO LOAD ON OTHER CHANNEL
65
60
1000
1
10
100
LOAD CURRENT (mA)
1000
34073 TA04c
34073 TA04b
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2.25MHz/400mA/800mA (IOUT) Dual
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34073fa
16
Linear Technology Corporation
LT 1006 REV A • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
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