Catalyst CAT25C16VA-1.8-GT3 8k/16k spi serial cmos eeprom Datasheet

Not Recommended for New Design,
Replace with CAT25080/CAT25160
CAT25C08, CAT25C16
8K/16K SPI Serial CMOS EEPROM
FEATURES
DESCRIPTION
■ 10 MHz SPI compatible
The CAT25C08/16 is a 8K/16K Bit SPI Serial CMOS
EEPROM internally organized as 1024x8/2048x8 bits.
Catalyst’s advanced CMOS Technology substantially
reduces device power requirements. The CAT25C08/
16 features a 32-byte page write buffer. The device
operates via the SPI bus serial interface and is enabled
though a Chip Select (CS). In addition to the Chip Select,
the clock input (SCK), data in (SI) and data out (SO) are
required to access the device. The HOLD pin may be
used to suspend any serial communication without
resetting the serial sequence. The CAT25C08/16 is
designed with software and hardware write protection
features including Block Write protection. The device is
available in 8-pin DIP, 8-pin SOIC and 8-pin TSSOP
packages.
■ 1.8 to 5.5 volt operation
■ SPI modes (0,0 & 1,1)
■ 32-byte page write buffer
■ Self-timed write cycle
■ Hardware and software protection
■ Block write protection
– Protect 1/4, 1/2 or all of EEPROM array
■ Low power CMOS technology
■ 1,000,000 program/erase cycles
■ 100 year data retention
■ Industrial temperature range
■ RoHS-compliant packages
For Ordering Information details, see page 15.
PIN CONFIGURATION
FUNCTIONAL SYMBOL
PDIP (L)
SOIC (V)
TSSOP (Y)
VCC
CS
1
8
VCC
SO
2
7
HOLD
WP
3
6
SCK
VSS
4
5
SI
SI
CS
WP
CAT25C08
CAT25C16
SO
HOLD
SCK
PIN FUNCTIONS
Pin Name
Function
SO
Serial Data Output
SCK
Serial Clock
WP
Write Protect
VCC
Power Supply
VSS
Ground
CS
Chip Select
SI
Serial Data Input
HOLD
Suspends Serial Input
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
VSS
1
Doc. No. 1016, Rev. C
CAT25C08/16
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature Under Bias ................. –55°C to +125°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum
rating for extended periods may affect device performance and reliability.
Storage Temperature ....................... –65°C to +150°C
Voltage on any Pin with
Respect to VSS(1) .................. –1.5V to +VCC +1.5V
VCC with Respect to VSS ................................ –0.5V to +6.0V
Package Power Dissipation
Capability (Ta = 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100 mA
RELIABILITY CHARACTERISTICS
Symbol
Parameter
NEND(3)
Endurance
TDR(3)
VZAP
(3)
ILTH(3)(4)
Min.
Typ.
Max.
Units
1,000,000
Cycles/Byte
Data Retention
100
Years
ESD Susceptibility
2000
Volts
Latch-up
100
mA
D.C. OPERATING CHARACTERISTICS
VCC = +1.8V to +5.5V, unless otherwise specified.
Limits
Symbol
Parameter
Min.
Typ.
Max.
Units
Test Conditions
ICC1
Power Supply Current
(Operating Write)
5
mA
VCC = 5V @ 5MHz
SO=open; CS=Vss
ICC2
Power Supply Current
(Operating Read)
3
mA
VCC = 5.5V
FCLK = 5MHz
ISB(6)
Power Supply Current
(Standby)
1
µA
CS = VCC
VIN = VSS or VCC
ILI
Input Leakage Current
2
µA
ILO
Output Leakage Current
3
µA
VIL(5)
Input Low Voltage
-1
VCC x 0.3
V
(5)
Input High Voltage
VCC x 0.7
VCC + 0.5
V
0.4
V
VIH
VOL1
Output Low Voltage
VOH1
Output High Voltage
VOL2
Output Low Voltage
VOH2
Output High Voltage
VCC - 0.8
V
0.2
VCC-0.2
VOUT = 0V to VCC,
CS = 0V
2.5V≤VCC<5.5V
IOL = 3.0mA
IOH = -1.6mA
V
1.8V≤VCC<2.5V
V
IOL = 150µA
IOH = -100µA
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –1.5V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC +1.5V for periods of less than 20 ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) These parameter are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.
(5) VILMIN and VIHMAX are reference values only and are not tested.
(6) Maximum standby current (ISB ) = 10µA for the Automotive and Extended Automotive temperature range.
Doc. No. 1016, Rev. C
2
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT25C08/16
PIN CAPACITANCE (1)
Applicable over recommended operating range from TA=25˚C, f=1.0 MHz, VCC=+5.0V (unless otherwise noted).
Symbol
Test Conditions
Max.
Units
Conditions
COUT
Output Capacitance (SO)
8
pF
VOUT=0V
CIN
Input Capacitance (CS, SCK, SI, WP, HOLD)
6
pF
VIN=0V
A.C. CHARACTERISTICS
CAT25Cxx-1.8
1.8V-5.5V
SYMBOL PARAMETER
Min.
CAT25Cxx
2.5V-5.5V
Max. Min.
Max.
4.5V-5.5V
Min.
Max.
Test
UNITS Conditions
tSU
Data Setup Time
50
20
20
ns
tH
Data Hold Time
50
20
20
ns
tWH
SCK High Time
250
75
40
ns
tWL
SCK Low Time
250
75
40
ns
fSCK
Clock Frequency
DC
tLZ
HOLD to Output Low Z
50
tRI(1)
Input Rise Time
tFI(1)
Input Fall Time
tHD
HOLD Setup Time
100
40
20
ns
tCD
HOLD Hold Time
100
40
20
ns
tWC(3)
Write Cycle Time
10
5
5
ms
CL = 50pF
tV
Output Valid from Clock Low
250
75
40
ns
(2)
tHO
Output Hold Time
tDIS
Output Disable Time
250
75
75
ns
tHZ
HOLD to Output High Z
150
50
50
ns
tCS
CS High Time
500
100
100
ns
tCSS
CS Setup Time
500
100
100
ns
tCSH
CS Hold Time
500
100
100
ns
tWPS
WP Setup Time
150
50
50
ns
tWPH
WP Hold Time
150
50
50
ns
1
DC
10
MHz
50
20
ns
2
2
2
µs
2
2
2
µs
0
5
0
DC
0
ns
Power-Up Timing(4)(5)
Symbol
Parameter
Max.
Units
tPUR
Power-up to Read Operation
1
ms
tPUW
Power-up to Write Operation
1
ms
NOTE:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) AC Test Conditions:
Input Pulse Voltages: 0.3VCC to 0.7VCC
Input rise and fall times: ≤10ns
Input and output reference voltages: 0.5VCC
Output load: current source IOL max/IOH max; CL = 50pF
(3) tWC is the time from the rising edge of CS after a valid write sequence to the end of the internal write cycle.
(4) This parameter is tested initially and after a design or process change that affects the parameter.
(5) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
3
Doc. No. 1016, Rev. C
CAT25C08/16
FUNCTIONAL DESCRIPTION
PIN DESCRIPTION
The CAT25C08/16 supports the SPI bus data transmission protocol. The synchronous Serial Peripheral Interface (SPI) helps the CAT25C08/16 to interface directly
with many of today’s popular microcontrollers. The
CAT25C08/16 contains an 8-bit instruction register.
(The instruction set and the operation codes are detailed in the instruction set table)
SI: Serial Input
SI is the serial data input pin. This pin is used to input all
opcodes, byte addresses, and data to be written to the
25C08/16. Input data is latched on the rising edge of the
serial clock for SPI modes (0, 0 & 1, 1).
SO: Serial Output
SO is the serial data output pin. This pin is used to
transfer data out of the 25C08/16. During a read cycle,
data is shifted out on the falling edge of the serial clock
for SPI modes (0,0 & 1,1).
After the device is selected with CS going low, the first
byte will be received. The part is accessed via the SI pin,
with data being clocked in on the rising edge of SCK.
The first byte contains one of the six op-codes that define
the operation to be performed.
SCK: Serial Clock
SCK is the serial clock pin. This pin is used to synchronize the communication between the microcontroller
Figure 1. Sychronous Data Timing
tCS
VIH
CS
VIL
tCSH
tCSS
VIH
tWL
tWH
SCK
VIL
tH
tSU
VIH
VALID IN
SI
VIL
tRI
tFI
tV
VOH
SO
tHO
tDIS
HI-Z
HI-Z
VOL
Note: Dashed Line= mode (1, 1) – – – – –
INSTRUCTION SET
Instruction
Opcode
Operation
WREN
0000 0110
Enable Write Operations
WRDI
0000 0100
Disable Write Operations
RDSR
0000 0101
Read Status Register
WRSR
0000 0001
Write Status Register
READ
0000 0011
Read Data from Memory
WRITE
0000 0010
Write Data to Memory
Doc. No. 1016, Rev. C
4
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT25C08/16
and the 25C08/16. Opcodes, byte addresses, or data
present on the SI pin are latched on the rising edge of the
SCK. Data on the SO pin is updated on the falling edge
of the SCK for SPI modes (0,0 & 1,1) .
takes the SO output pin to high impedance and forces
the devices into a Standby Mode (unless an internal
write operation is underway) The CAT25C08/16 draws
ZERO current in the Standby mode. A high to low
transition on CS is required prior to any sequence being
initiated. A low to high transition on CS after a valid write
sequence is what initiates an internal write cycle.
CS
CS: Chip Select
CS is the Chip select pin. CS low enables the CAT25C08/
16 and CS high disables the CAT25C08/16. CS high
BYTE ADDRESS
Device
Address Significant Bits
Address Don't Care Bits
# Address Clock Pulse
CAT25C08
A9 - A0
A15 - A10
16
CAT25C16
A10 - A0
A15 - A11
16
STATUS REGISTER
7
6
5
4
3
2
1
0
WPEN
0
1
0
BP1
BP0
WEL
RDY
BLOCK PROTECTION BITS
Status Register Bits
BP1
BP0
Array Address
Protected
Protection
0
0
None
No Protection
0
1
25C08: 0300-03FF
25C16: 0600-07FF
Quarter Array Protection
1
0
25C08: 0200-03FF
25C16: 0400-07FF
Half Array Protection
1
1
25C08: 0000-03FF
25C16: 0000-07FF
Full Array Protection
WRITE PROTECT ENABLE OPERATION
WPEN
0
WP
X
WEL
0
Protected
Blocks
Protected
Unprotected
Blocks
Protected
Status
Register
Protected
0
X
1
Protected
Writable
Writable
1
Low
0
Protected
Protected
Protected
1
Low
1
Protected
Writable
Protected
X
High
0
Protected
Protected
Protected
X
High
1
Protected
Writable
Writable
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
5
Doc. No. 1016, Rev. C
CAT25C08/16
WP
WP: Write Protect
WP is the Write Protect pin. The Write Protect pin will
allow normal read/write operations when held high.
When WP is tied low and the WPEN bit in the status
register is set to “1”, all write operations to the status
register are inhibited. WP going low while CS is still low
will interrupt a write to the status register. If the internal
write cycle has already been initiated, WP going low will
have no effect on any write operation to the status
register. The WP pin function is blocked when the WPEN
bit is set to 0. Figure 10 illustrates the WP timing
sequence during a write operation.
STATUS REGISTER
The Status Register indicates the status of the device.
The RDY (Ready) bit indicates whether the CAT25C08/
16 is busy with a write operation. When set to 1 a write
cycle is in progress and when set to 0 the device
indicates it is ready. This bit is read only. The WEL
(Write Enable) bit indicates the status of the write
enable latch. When set to 1, the device is in a Write
Enable state and when set to 0 the device is in a Write
Disable state. The WEL bit can only be set by the
WREN instruction and can be reset by the WRDI
instruction.
HOLD
HOLD: Hold
The BP0 and BP1 (Block Protect) bits indicate which
blocks are currently protected. These bits are set by the
user issuing the WRSR instruction. The user is allowed
to protect quarter of the memory, half of the memory or
the entire memory by setting these bits. Once protected
the user may only read from the protected portion of the
array. These bits are non-volatile.
HOLD is the HOLD pin. The HOLD pin is used to pause
transmission to the CAT25C08/16 while in the middle of
a serial sequence without having to re-transmit entire
sequence at a later time. To pause, HOLD must be
brought low while SCK is low. The SO pin is in a high
impedance state during the time the part is paused, and
transitions on the SI pins will be ignored. To resume
communication, HOLD is brought high, while SCK is low.
HOLD should be held high any time this function is not
being used. HOLD may be tied high directly to VCC or
tied to VCC through a resistor. Figure 9 illustrates hold
timing sequence.
The WPEN (Write Protect Enable) is an enable bit for
the WP pin. The WP pin and WPEN bit in the status
register control the programmable hardware write protect feature. Hardware write protection is enabled when
WP is low and WPEN bit is set to high. The user cannot
write to the status register, (including the block protect
Figure 2. WREN Instruction Timing
CS
SCK
0
SI
0
0
0
1
0
1
0
HIGH IMPEDANCE
SO
Note: Dashed Line= mode (1, 1) – – – – –
Figure 3. WRDI Instruction Timing
CS
SCK
SI
SO
0
0
0
0
0
1
0
0
HIGH IMPEDANCE
Note: Dashed Line= mode (1, 1) – – – – –
Doc. No. 1016, Rev. C
6
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT25C08/16
bits and the WPEN bit) and the block protected sections
in the memory array when the chip is hardware write
protected. Only the sections of the memory array that
are not block protected can be written. Hardware write
protection is disabled when either WP pin is high or the
WPEN bit is zero.
is automatically incremented to the next higher address
after each byte of data is shifted out. When the highest
address is reached, the address counter rolls over to
0000h allowing the read cycle to be continued indefinitely. The read operation is terminated by pulling the CS
high. To read the status register, RDSR instruction
should be sent. The contents of the status register are
shifted out on the SO line. The status register may be
read at any time even during a write cycle. Read
sequece is illustrated in Figure 4. Reading status register
is illustrated in Figure 5.
DEVICE OPERATION
Write Enable and Disable
The CAT25C08/16 contains a write enable latch. This
latch must be set before any write operation. The device
powers up in a write disable state when Vcc is applied.
WREN instruction will enable writes (set the latch) to the
device. WRDI instruction will disable writes(reset the
latch) to the device. Disabling writes will protect the
device against inadvertent writes.
WRITE Sequence
The CAT25C08/16 powers up in a Write Disable state.
Prior to any write instructions, the WREN instruction
must be sent to CAT25C08/16. The device goes into
Write enable state by pulling the CS low and then
clocking the WREN instruction into CAT25C08/16. The
CS must be brought high after the WREN instruction to
enable writes to the device. If the write operation is
initiated immediately after the WREN instruction without
CS being brought high, the data will not be written to the
array because the write enable latch will not have been
properly set. Also, for a successful write operation the
address of the memory location(s) to be programmed
must be outside the protected address field location
selected by the block protection level.
READ Sequence
The part is selected by pulling CS low. The 8-bit read
instruction is transmitted to the CAT25C08/16, followed
by the 16-bit address for 25C08/16. (only 10-bit addresses are used for 25C08, 11-bit addresses are used
for 25C16. The rest of the bits are don't care bits).
After the correct read instruction and address are sent,
the data stored in the memory at the selected address is
shifted out on the SO pin. The data stored in the memory
at the next address can be read sequentially by continuing to provide clock pulses. The internal address pointer
Figure 4. Read Instruction Timing
CS
0
1
2
3
4
5
6
7
8
9
10
20
21
22
*
23
24
25
26
27
28
29
*
30
2
1
SCK
BYTE ADDRESS*
OPCODE
SI
0
0
0
0
0
0
1
1
AN
A0
DATA OUT
HIGH IMPEDANCE
SO
7
6
5
4
3
0
MSB
*Please check the Byte Address Table.
Note: Dashed Line= mode (1, 1) – – – –
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
7
Doc. No. 1016, Rev. C
CAT25C08/16
Byte Write
Once the device is in a Write Enable state, the user may
proceed with a write sequence by setting the CS low,
issuing a write instruction via the SI line, followed by the
16-bit address for 25C08/16. (only 10-bit addresses are
used for 25C08, 11-bit addresses are used for 25C16.
The rest of the bits are don't care bits). Programming will
start after the CS is brought high. Figure 6 illustrates
byte write sequence. During an internal write cycle, all
commands will be ignored except the RDSR (Read
Status Register) instruction.
bytes. After each byte of data received, lower order
address bits are internally incremented by one; the high
order bits of address will remain constant.The only
restriction is that the 32 bytes must reside on the same
page. If the address counter reaches the end of the
page and clock continues, the counter will “roll over” to
the first address of the page and overwrite any data that
may have been written. The CAT25C08/16 is automatically returned to the write disable state at the completion
of the write cycle. Figure 8 illustrates the page write
sequence.
The Status Register can be read to determine if the write
cycle is still in progress. If Bit 0 of the Status Register is
set at 1, write cycle is in progress. If Bit 0 is set at 0, the
device is ready for the next instruction
To write to the status register, the WRSR instruction
should be sent. Only Bit 2, Bit 3 and Bit 7 of the status
register can be written using the WRSR instruction.
Figure 7 illustrates the sequence of writing to status
register.
Page Write
The CAT25C08/16 features page write capability. After
the initial byte, the host may continue to write up to 32
Figure 5. RDSR Instruction Timing
CS
0
1
2
3
4
5
6
7
1
0
1
8
9
10
11
7
6
5
4
12
13
14
2
1
SCK
OPCODE
0
SI
0
0
0
0
DATA OUT
HIGH IMPEDANCE
SO
3
0
MSB
Note: Dashed Line= mode (1, 1) – – – – –
Figure 6. Write Instruction Timing
CS
0
1
2
3
4
5
6
7
8
21
22
23
24
25
26
27
28
29
30
*
31
SCK
BYTE ADDRESS*
OPCODE
SI
0
0
0
0
0
0
1
0
AN
DATA IN
A0 D7 D6 D5 D4 D3 D2 D1 D0
HIGH IMPEDANCE
SO
*Please check the Byte Address Table
Note: Dashed Line= mode (1, 1) – – – – –
Doc. No. 1016, Rev. C
8
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT25C08/16
DESIGN CONSIDERATIONS
The CAT25C08/16 powers up in a write disable state
and in a low power standby mode. A WREN instruction
must be issued to perform any writes to the device after
power up. Also,on power up CS should be brought low
to enter a ready state and receive an instruction. After
a successful byte/page write or status register write, the
CAT25C08/16 goes into a write disable mode. CS must
be set high after the proper number of clock cycles to
start an internal write cycle. Access to the array during
an internal write cycle is ignored and programming is
continued. On power up, SO is in a high impedance. If
an invalid op code is received, no data will be shifted
into the CAT25C08/16, and the serial output pin (SO)
will remain in a high impedance state until the falling
edge of CS is detected again.
When powering down, the supply should be taken down
to 0V, so that the CAT25C08/16 will be reset when
power is ramped back up. If this is not possible, then,
following a brown-out episode, the CAT25C08/16 can
be reset by refreshing the contents of the Status Register (See Application Note AN10).
Figure 7. WRSR Timing
CS
0
1
2
3
4
5
6
7
8
9
10
11
1
7
6
5
4
12
13
14
15
2
1
0
SCK
OPCODE
SI
0
0
0
0
DATA IN
0
0
0
3
MSB
HIGH IMPEDANCE
SO
Note: Dashed Line= mode (1, 1) – – – – –
Figure 8. Page Write Instruction Timing
CS
0
1
2
3
4
5
6
7
8
21
22
23 24-31
32-39
24+(N-1)x8-1..24+(N-1)x8 24+Nx8-1
SCK
SI
0
0
0
0
0
DATA IN
BYTE ADDRESS*
OPCODE
0
1
0
AN
A0
Data
Byte 1
Data
Byte 2
Data
Byte 3
Data Byte N
0
7..1
HIGH IMPEDANCE
SO
*Please check the Byte Address Table.
Note: Dashed Line= mode (1, 1) – – – – –
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
9
Doc. No. 1016, Rev. C
CAT25C08/16
Figure 9. HOLD Timing
CS
tCD
tCD
SCK
tHD
tHD
HOLD
tHZ
HIGH IMPEDANCE
SO
tLZ
Note: Dashed Line= mode (1, 1) – – – – –
Figure 10. WP Timing
t WPS
t WPH
CS
SCK
WP
WP
Note: Dashed Line= mode (1, 1) – – – – –
Doc. No. 1016, Rev. C
10
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT25C08/16
PACKAGE INFORMATION
8-LEAD 300 MIL WIDE PLASTIC DIP (L)
E1
E
D
A2
A
A1
L
e
eB
b2
b
SYMBOL
A
A1
A2
b
b2
D
E
E1
e
eB
L
MIN
NOM
MAX
4.57
0.38
3.05
0.36
1.14
9.02
7.62
6.09
7.87
0.115
0.46
7.87
6.35
2.54 BSC
0.130
3.81
0.56
1.77
10.16
8.25
7.11
9.65
0.150
24C16_8-LEAD_DIP_(300P).eps
Notes:
1. All dimensions are in millimeters.
2. Complies with JEDEC Standard MS001.
3. Dimensioning and tolerancing per ANSI Y14.5M-1982
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
11
Doc. No. 1016, Rev. C
CAT25C08/16
8-LEAD 150 MIL WIDE SOIC (V)
E1
E
h x 45
D
C
A
θ1
e
A1
L
b
SYMBOL
MIN
A1
A
b
C
D
E
E1
e
h
L
θ1
0.10
1.35
0.33
0.19
4.80
5.80
3.80
NOM
MAX
0.25
1.75
0.51
0.25
5.00
6.20
4.00
1.27 BSC
0.25
0.40
0°
0.50
1.27
8°
24C16_8-LEAD_SOIC.eps
Notes:
1. All dimensions are in millimeters.
2. Complies with JEDEC specification MS-012.
Doc. No. 1016, Rev. C
12
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT25C08/16
8-LEAD TSSOP (Y)
D
5
8
SEE DETAIL A
c
E
E1
E/2
GAGE PLANE
4
1
PIN #1 IDENT.
0.25
θ1
L
A2
SEATING PLANE
SEE DETAIL A
A
e
A1
b
SYMBOL
A
A1
A2
b
c
D
E
E1
e
L
θ1
MIN
0.05
0.80
0.19
0.09
2.90
6.30
4.30
0.50
0.00
NOM
0.90
3.00
6.4
4.40
0.65 BSC
0.60
MAX
1.20
0.15
1.05
0.30
0.20
3.10
6.50
4.50
0.75
8.00
Notes:
1. All dimensions are in millimeters.
2. Complies with JEDEC Standard MO-153
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
13
Doc. No. 1016, Rev. C
CAT25C08/16
PACKAGE MARKING
8-Lead PDIP
8-Lead SOIC
VV
25C16LI
FYYWWA
VV
25C16VI
FYYWWA
CSI = Catalyst Semiconductor, Inc.
25C16L = Device Code
25C08L
25C16L
I = Temperature Range
F = Lead Finish
4 = NiPdAu
3 = Matte-Tin
YY = Production Year
WW = Production Week
A = Product Revision
VV = Voltage Range
1.8V - 5.5V = 18
2.5V - 5.5V = Blank
CSI = Catalyst Semiconductor, Inc.
25C16V = Device Code
25C08V
25C16V
I = Temperature Range
F = Lead Finish
4 = NiPdAu
3 = Matte-Tin
YY = Production Year
WW = Production Week
A = Product Revision
VV = Voltage Range
1.8V - 5.5V = 18
2.5V - 5.5V = Blank
8-Lead TSSOP
YMBF
25Y16
Y
M
A
25Y16
= Production Year
= Production Month
= Die Revision
= Device Code
25Y08
25Y16
I = Industrial Temperature Range
F = Voltage Range + Lead Finish
Matte-Tin
1.8V - 5.5V = S
2.5V - 5.5V = T
NiPdAu
1.8V - 5.5V = A
2.5V - 5.5V = G
Doc. No. 1016, Rev. C
14
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT25C08/16
EXAMPLE OF ORDERING INFORMATION
Prefix
CAT
Company ID
Device #
Suffix
25C16
Product
Number
25C16: 16K
25C08: 8K
V
I
-1.8
T3
–G
Tape & Reel
T: Tape & Reel
3: 3000/Reel
Temperature Range
I = Industrial (-40°C to +85°C)
A = Automotive (-40°C to +105°C)
E = Extended (-40°C to +125°C)
Operating Voltage
Blank: (VCC = 2.5V to 5.5V)
1.8: (VCC = 1.8V to 5.5V)
Package
L: PDIP
V: SOIC, JEDEC
Y: TSSOP
Lead Finish
Blank: Matte-Tin
G: NiPdAu
Notes:
(1) All packages are RoHS-compliant (Lead-free, Halogen-free).
(2) The standard lead finish is NiPdAu.
(3) The device used in the above example is a CAT25C16VI-1.8GT3 (SOIC, Industrial Temperature, 1.8V to 5.5V Operating Voltage,
NiPdAu, Tape & Reel).
(4) For additional package and temperature options, please contact your nearest Catalyst Semiconductor Sales office.
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
15
Doc. No. 1016, Rev. C
REVISION HISTORY
Date
Rev.
Reason
03/21/2006
A
Initial Issue
05/25/2006
B
Update Features
Update Absolute Maximum Ratings
Update A.C. Characteristics
Update Status Register
Update Figure 8
Update Package Information
Remove Tape & Reel
Update Package Marking
Update Example of Ordering Information
10/13/06
C
Update Features
Update Pin Configuration
Update Pin Functions
Update D.C. Operating Characteristics
Update Package Information
Update Example of Ordering Information
Copyrights, Trademarks and Patents
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
AE2 ™
Beyond Memory™,
DPP™,
EZDim™,
MiniPot™
Quad-Mode™
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING
THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT
INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE
OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING OUT OF ANY SUCH USE OR APPLICATION,
INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant
into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst
Semiconductor product could create a situation where personal injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products
with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for
sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit
diagrams illustrate typical semiconductor applications and may not be complete.
Catalyst Semiconductor, Inc.
Corporate Headquarters
2975 Stender Way
Santa Clara, CA 95054
Phone: 408.542.1000
Fax: 408.542.1200
www.catsemi.com
Publication #:
Revison:
Issue date:
1016
C
10/13/06