PD - 95156
IRLZ44NS/LPbF
Logic-Level Gate Drive
l Advanced Process Technology
l Surface Mount (IRLZ44NS)
l Low-profile through-hole (IRLZ44NL)
l 175°C Operating Temperature
l Fast Switching
l Fully Avalanche Rated
l Lead-Free
Description
HEXFET® Power MOSFET
l
D
RDS(on) = 0.022Ω
G
Fifth Generation HEXFETs from International Rectifier
utilize advanced processing techniques to achieve
extremely low on-resistance per silicon area. This
benefit, combined with the fast switching speed and
ruggedized device design that HEXFET Power MOSFETs
are well known for, provides the designer with an extremely
efficient and reliable device for use in a wide variety of
applications.
The D2Pak is a surface mount power package capable of
accommodating die sizes up to HEX-4. It provides the
highest power capability and the lowest possible onresistance in any existing surface mount package. The
D2Pak is suitable for high current applications because of
its low internal connection resistance and can dissipate
up to 2.0W in a typical surface mount application.
The through-hole version (IRLZ44NL) is available for lowprofile applications.
ID = 47A
S
D 2 Pak
Absolute Maximum Ratings
ID @ TC = 25°C
ID @ TC = 100°C
IDM
PD @TA = 25°C
PD @TC = 25°C
V GS
EAS
IAR
EAR
dv/dt
TJ
TSTG
VDSS = 55V
TO-262
Parameter
Max.
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
Power Dissipation
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Single Pulse Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
47
33
160
3.8
110
0.71
±16
210
25
11
5.0
-55 to + 175
Units
A
W
W
W/°C
V
mJ
A
mJ
V/ns
300 (1.6mm from case )
°C
Thermal Resistance
Parameter
RθJC
RθJA
Junction-to-Case
Junction-to-Ambient ( PCB Mounted,steady-state)**
Typ.
Max.
Units
1.4
40
°C/W
4/21/04
IRLZ44NS/LPbF
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter
Drain-to-Source Breakdown Voltage
∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Min.
55
1.0
21
LS
Internal Source Inductance
Ciss
Coss
Crss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
V (BR)DSS
RDS(on)
Static Drain-to-Source On-Resistance
VGS(th)
gfs
Gate Threshold Voltage
Forward Transconductance
IDSS
Drain-to-Source Leakage Current
IGSS
Typ.
0.070
11
84
26
15
Max. Units
Conditions
V
V GS = 0V, ID = 250µA
V/°C Reference to 25°C, ID = 1mA
0.022
V GS = 10V, ID = 25A
0.025
Ω
V GS = 5.0V, ID = 25A
0.035
V GS = 4.0V, ID = 21A
2.0
V
V DS = V GS, ID = 250µA
S
V DS = 25V, I D = 25A
25
V DS = 55V, V GS = 0V
µA
250
V DS = 44V, VGS = 0V, TJ = 150°C
100
V GS = 16V
nA
-100
V GS = -16V
48
I D = 25A
8.6
nC
V DS = 44V
25
V GS = 5.0V, See Fig. 6 and 13
V DD = 28V
I D = 25A
ns
R G = 3.4Ω, V GS = 5.0V
R D = 1.1Ω, See Fig. 10
Between lead,
7.5
nH
and center of die contact
1700
V GS = 0V
400
pF
V DS = 25V
150
= 1.0MHz, See Fig. 5
Source-Drain Ratings and Characteristics
IS
I SM
V SD
trr
Q rr
ton
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
Forward Turn-On Time
Min. Typ. Max. Units
Conditions
D
MOSFET symbol
47
showing the
A
G
integral reverse
160
S
p-n junction diode.
1.3
V
TJ = 25°C, IS = 25A, VGS = 0V
80 120
ns
TJ = 25°C, IF = 25A
210 320
nC
di/dt = 100A/µs
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Repetitive rating; pulse width limited by
ISD ≤ 25A, di/dt ≤ 270A/µs, VDD ≤ V(BR)DSS,
VDD = 25V, starting TJ = 25°C, L =470µH
Pulse width ≤ 300µs; duty cycle ≤ 2%.
max. junction temperature. ( See fig. 11 )
R G = 25Ω, IAS = 25A. (See Figure 12)
TJ ≤ 175°C
Uses IRLZ44N data and test conditions
** When mounted on 1" square PCB ( FR-4 or G-10 Material ).
For recommended footprint and soldering techniques refer to application note #AN-994.
IRLZ44NS/LPbF
1000
1000
VGS
15V
12V
10V
8.0V
6.0V
4.0V
3.0V
BOTTOM 2.5V
100
10
2.5V
20µs PULSE WIDTH
T J = 25°C
1
0.1
1
10
100
10
A
100
3.0
R DS(on) , Drain-to-Source On Resistance
(Normalized)
I D , Drain-to-Source Current (A)
TJ = 25°C
100
TJ = 175°C
10
V DS= 25V
20µs PULSE WIDTH
4.0
5.0
6.0
7.0
8.0
VGS , Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
1
10
A
100
Fig 2. Typical Output Characteristics
1000
3.0
20µs PULSE WIDTH
T J = 175°C
VDS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
1
2.5V
1
0.1
VDS , Drain-to-Source Voltage (V)
2.0
VGS
15V
12V
10V
8.0V
6.0V
4.0V
3.0V
BOTTOM 2.5V
TOP
ID , Drain-to-Source Current (A)
ID , Drain-to-Source Current (A)
TOP
9.0
A
I D = 41A
2.5
2.0
1.5
1.0
0.5
VGS = 10V
0.0
-60 -40 -20
0
20
40
60
A
80 100 120 140 160 180
TJ , Junction Temperature (°C)
Fig 4. Normalized On-Resistance
Vs. Temperature
IRLZ44NS/LPbF
2800
15
2400
VGS , Gate-to-Source Voltage (V)
V GS = 0V,
f = 1MHz
C iss = Cgs + C gd , Cds SHORTED
C rss = C gd
Ciss C oss = Cds + C gd
C, Capacitance (pF)
2000
1600
Coss
1200
800
Crss
400
0
1
10
100
I D = 25A
V DS = 44V
V DS = 28V
12
9
6
3
FOR TEST CIRCUIT
SEE FIGURE 13
0
A
0
VDS , Drain-to-Source Voltage (V)
20
30
40
50
60
70
A
Q G , Total Gate Charge (nC)
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
1000
1000
OPERATION IN THIS AREA LIMITED
BY R DS(on)
I D , Drain Current (A)
ISD , Reverse Drain Current (A)
10
100
TJ = 175°C
TJ = 25°C
VGS = 0V
10
0.4
0.8
1.2
1.6
2.0
VSD , Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
A
2.4
100
10µs
100µs
10
1ms
TC = 25°C
TJ = 175°C
Single Pulse
1
1
10ms
10
A
100
VDS , Drain-to-Source Voltage (V)
Fig 8. Maximum Safe Operating Area
IRLZ44NS/LPbF
50
RD
V DS
VGS
ID , Drain Current (A)
40
D.U.T.
RG
30
+
V- DD
5.0V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
20
Fig 10a. Switching Time Test Circuit
10
VDS
90%
0
25
50
75
100
125
150
TC , Case Temperature ( °C)
175
10%
VGS
Fig 9. Maximum Drain Current Vs.
Case Temperature
td(on)
tr
t d(off)
tf
Fig 10b. Switching Time Waveforms
Thermal Response (Z thJC )
10
1
D = 0.50
0.20
0.10
0.1
0.01
0.00001
PDM
0.05
0.02
0.01
t1
SINGLE PULSE
(THERMAL RESPONSE)
t2
Notes:
1. Duty factor D = t 1 / t 2
2. Peak TJ = P DM x Z thJC + TC
0.0001
0.001
0.01
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
0.1
L
VDS
D.U.T.
RG
+
V
- DD
IAS
5.0 V
tp
0.01Ω
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS
E AS , Single Pulse Avalanche Energy (mJ)
IRLZ44NS/LPbF
500
TOP
BOTTOM
400
300
200
100
0
VDD = 25V
25
tp
ID
10A
17A
25A
50
A
75
100
125
150
175
Starting TJ , Junction Temperature (°C)
VDD
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
VDS
IAS
Fig 12b. Unclamped Inductive Waveforms
Current Regulator
Same Type as D.U.T.
50KΩ
QG
12V
.2µF
.3µF
5.0 V
QGS
D.U.T.
QGD
+
V
- DS
VGS
VG
3mA
Charge
Fig 13a. Basic Gate Charge Waveform
IG
ID
Current Sampling Resistors
Fig 13b. Gate Charge Test Circuit
IRLZ44NS/LPbF
Peak Diode Recovery dv/dt Test Circuit
+
D.U.T
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
-
-
+
RG
•
•
•
•
Driver Gate Drive
P.W.
+
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
Period
D=
-
V DD
P.W.
Period
VGS=10V
D.U.T. ISD Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor Curent
Ripple ≤ 5%
* VGS
= 5V for Logic Level Devices
Fig 14. For N-Channel HEXFETS
ISD
*
IRLZ44NS/LPbF
D2Pak Package Outline
Dimensions are shown in millimeters (inches)
D2Pak Part Marking Information (Lead-Free)
T H IS IS AN IR F 5 3 0 S W IT H
L O T CO D E 8 0 2 4
AS S E M B L E D O N W W 0 2 , 2 0 0 0
IN T H E AS S E M B L Y L IN E "L "
IN T E R N AT IO N AL
R E CT IF IE R
L O GO
N ote: "P " in as s em bly lin e
po s i tion in dicates "L ead-F r ee"
P AR T N U M B E R
F 53 0 S
AS S E M B L Y
L O T CO D E
OR
IN T E R N AT IO N AL
R E C T IF IE R
L OGO
AS S E M B L Y
L OT COD E
P AR T N U M B E R
F 530S
D AT E CO D E
P = D E S IG N AT E S L E AD -F R E E
P R O D U C T (O P T IO N AL )
Y E AR 0 = 2 0 0 0
W E E K 02
A = AS S E M B L Y S IT E CO D E
D AT E CO D E
Y E AR 0 = 2 0 0 0
W E E K 02
L IN E L
IRLZ44NS/LPbF
TO-262 Package Outline
IGBT
1- GATE
2- COLLECTOR
3- EMITTER
TO-262 Part Marking Information
EXAMPLE: T HIS IS AN IRL3103L
LOT CODE 1789
AS SEMBLED ON WW 19, 1997
IN T HE ASS EMBLY LINE "C"
Note: "P" in as s embly line
pos ition indicates "Lead-Free"
INT ERNAT IONAL
RECT IFIER
LOGO
ASS EMBLY
LOT CODE
PART NUMBER
DAT E CODE
YEAR 7 = 1997
WEEK 19
LINE C
OR
INT ERNAT IONAL
RECT IFIER
LOGO
AS S EMBLY
LOT CODE
PART NUMBER
DAT E CODE
P = DES IGNAT ES LEAD-FREE
PRODUCT (OPTIONAL)
YEAR 7 = 1997
WEEK 19
A = AS S EMBLY S ITE CODE
IRLZ44NS/LPbF
D2Pak Tape & Reel Infomation
Dimensions are shown in millimeters (inches)
TRR
1.60 (.063)
1.50 (.059)
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
FEED DIRECTION 1.85 (.073)
11.60 (.457)
11.40 (.449)
1.65 (.065)
0.368 (.0145)
0.342 (.0135)
15.42 (.609)
15.22 (.601)
24.30 (.957)
23.90 (.941)
TRL
1.75 (.069)
1.25 (.049)
10.90 (.429)
10.70 (.421)
4.72 (.136)
4.52 (.178)
16.10 (.634)
15.90 (.626)
FEED DIRECTION
13.50 (.532)
12.80 (.504)
27.40 (1.079)
23.90 (.941)
4
330.00
(14.173)
MAX.
60.00 (2.362)
MIN.
NOTES :
1. COMFORMS TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
26.40 (1.039)
24.40 (.961)
3
30.40 (1.197)
MAX.
4
Data and specifications subject to change without notice.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.04/04
Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/