Siemens HYB5117400BT-70 4m x 4-bit dynamic ram Datasheet

4M x 4-Bit Dynamic RAM
HYB5117400BJ -50/-60/-70
HYB5117400BT -50/-60/-70
Advanced Information
•
4 194 304 words by 4-bit organization
•
0 to 70 °C operating temperature
•
Performance:
-50
-60
-70
tRAC
RAS access time
50
60
70
ns
tCAC
CAS access time
13
15
20
ns
tAA
Access time from address
25
30
35
ns
tRC
Read/Write cycle time
90
110
130
ns
tPC
Fast page mode cycle time
35
40
45
ns
•
Single + 5 V (± 10 %) supply
•
Low power dissipation
max. 660 active mW (-50 version)
max. 605 active mW (-60 version)
max. 550 active mW (-70 version)
11 mW standby (TTL)
5.5. mW standby (MOS)
•
Output unlatched at cycle end allows two-dimensional chip selection
•
Read, write, read-modify-write, CAS-before-RAS refresh, RAS-only refresh, hidden refresh,
self refresh and test mode
•
Fast page mode capability
•
All inputs, outputs and clocks fully TTL-compatible
•
2048 refresh cycles / 32 ms
•
Plastic Package:
Semiconductor Group
P-SOJ-26/24 300 mil
P TSOPII-26/24 300 mil
1
1.96
HYB 5117400BJ/BT-50/-60/-70
4M x 4-DRAM
The HYB 5117400BJ/BT is a 16MBit dynamic RAM organized as 4194304 words by 4-bits. The
HYB 5117400BJ/BT utilizes a submicron CMOS silicon gate process technology, as well as
advanced circuit techniques to provide wide operating margins, both internally and for the system
user. Multiplexed address inputs permit the HYB 5117400BJ/BT to be packaged in a standard SOJ
26/24 or TSOPII-26/24 plastic package, both with 300 mil width. These packages provide high
system bit densities and are compatible with commonly used automatic testing and insertion
equipment. System-oriented features include single + 5 V (± 10 %) power supply, direct interfacing
with high-performance logic device families such as Schottky TTL.
Ordering Information
Type
Ordering Code
Package
Descriptions
HYB 5117400BJ-50
Q67100-Q1086
P-SOJ-26/24 300 mil
DRAM (access time 50 ns)
HYB 5117400BJ-60
Q67100-Q1087
P-SOJ-26/24 300 mil
DRAM (access time 60 ns)
HYB 5117400BJ-70
Q67100-Q1088
P-SOJ-26/24 300 mil
DRAM (access time 70 ns)
HYB 5117400BT-50
on request
P-TSOPII-26/24 300mil
DRAM (access time 50 ns)
HYB 5117400BT-60
on request
P-TSOPII-26/24 300mil
DRAM (access time 60 ns)
HYB 5117400BT-70
on request
P-TSOPII-26/24 300mil
DRAM (access time 70 ns)
Pin Names
A0 to A10
Row Address Inputs
A0 to A10
Column Address Inputs
RAS
Row Address Strobe
OE
Output Enable
I/O1-I/O4
Data Input/Output
CAS
Column Address Strobe
WE
Read/Write Input
VCC
Power Supply (+ 5 V)
VSS
Ground (0 V)
N.C.
not connected
Semiconductor Group
2
HYB 5117400BJ/BT-50/-60/-70
4M x 4-DRAM
Vcc
I/O1
I/O2
WE
RAS
N.C.
1
2
3
4
5
6
26
25
24
23
22
21
Vss
I/O4
I/O3
CAS
OE
A9
A10
A0
A1
A2
A3
VCC
8
9
10
11
12
13
19
18
17
16
15
14
A8
A7
A6
A5
A4
Vss
P-SOJ-26/24
300 mil
P-TSOPII-26/24 300 mil
Pin Configuration
Semiconductor Group
3
HYB 5117400BJ/BT-50/-60/-70
4M x 4-DRAM
I/O1 I/O2 I/O3 I/O4
WE
CAS
&
.
Data in
Buffer
No. 2 Clock
Generator
11
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
Data out
Buffer
4
4
Column
Address
Buffer(11)
OE
11
Column
Decoder
Refresh
Controller
Sense Amplifier
I/O Gating
Refresh
Counter (11)
4
2048
x4
11
Row
11
RAS
Address
Buffers(11)
Row
Decoder 2048
11
No. 1 Clock
Generator
Voltage Down
Generator
Block Diagram
Semiconductor Group
Memory Array
2048x2048x4
4
VCC
VCC (internal)
HYB 5117400BJ/BT-50/-60/-70
4M x 4-DRAM
Absolute Maximum Ratings
Operating temperature range ............................................................................................0 to 70 °C
Storage temperature range.........................................................................................– 55 to 150 °C
Input/output voltage ................................................................................-0.5 to min (Vcc+0.5,7.0) V
Power supply voltage...................................................................................................-1.0V to 7.0 V
Power dissipation..................................................................................................................... 1.0 W
Data out current (short circuit) ................................................................................................ 50 mA
Note:
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage of
the device. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
DC Characteristics
TA = 0 to 70 °C, VSS = 0 V, VCC = 5 V ± 10 %; tT = 5 ns
Parameter
Symbol
Limit Values
min.
max.
Unit Test
Condition
Input high voltage
VIH
2.4
Vcc+0.5
V
1)
Input low voltage
VIL
– 0.5
0.8
V
1)
Output high voltage (IOUT = – 5 mA)
VOH
2.4
–
V
1)
Output low voltage (IOUT = 4.2 mA)
VOL
–
0.4
V
1)
Input leakage current
(0 V ≤ VIH ≤ Vcc + 0.3V, all other pins = 0 V)
II(L)
– 10
10
µA
1)
Output leakage current
(DO is disabled, 0 V ≤ VOUT ≤ Vcc + 0.3V)
IO(L)
– 10
10
µA
1)
Average VCC supply current:
ICC1
-50 ns version
-60 ns version
-70 ns version
(RAS, CAS, address cycling: tRC = tRC min.)
–
–
–
120
110
100
mA
mA
mA
2) 3) 4)
Standby VCC supply current (RAS = CAS = VIH) ICC2
–
2
mA
–
Average VCC supply current, during RAS-only
refresh cycles:
-50 ns version
-60 ns version
-70 ns version
(RAS cycling, CAS = VI,H, tRC = tRC min.)
ICC3
–
–
–
120
110
100
mA
mA
mA
2) 4)
Semiconductor Group
5
2) 3) 4)
2) 3) 4)
2) 4)
2) 4)
HYB 5117400BJ/BT-50/-60/-70
4M x 4-DRAM
DC Characteristics (cont’d)
TA = 0 to 70 °C, VSS = 0 V, VCC = 5 V ± 10 %; tT = 5 ns
Parameter
Symbol
Average VCC supply current,
ICC4
during fast page mode:
-50 ns version
-60 ns version
-70 ns version
(RAS = VIL, CAS, address cycling:tPC = tPC min.)
Standby VCC supply current
(RAS = CAS = VCC – 0.2 V)
ICC5
Average VCC supply current, during CASbefore-RAS refresh mode: -50 ns version
-60 ns version
-70 ns version
(RAS, CAS cycling: tRC = tRC min.)
ICC6
Average Self Refresh Current
ICC7
Limit Values
min.
max.
Unit Test
Condition
–
–
–
40
35
30
mA
mA
mA
–
1
mA
–
–
–
120
110
100
mA
mA
mA
_
1
mA
2) 3) 4)
2) 3) 4)
2) 3) 4)
1)
2) 4)
2) 4)
2) 4)
(CBR cycle with tRAS>TRASSmin., CAS held low,
WE=Vcc-0.2V, Address and Din=Vcc-0.2V or 0.2V)
Capacitance
TA = 0 to 70 °C,VCC = 5 V ± 10 %, f = 1 MHz
Parameter
Symbol
Limit Values
min.
max.
Unit
Input capacitance (A0 to A10)
CI1
–
5
pF
Input capacitance (RAS, CAS, WE, OE)
CI2
–
7
pF
I/O capacitance (I/O1-I/O4)
CIO
–
7
pF
Semiconductor Group
6
HYB 5117400BJ/BT-50/-60/-70
4M x 4-DRAM
AC Characteristics 5)6)
TA = 0 to 70 °C,VCC = 5 V ± 10 %, tT = 5 ns
Parameter
16F
Limit Values
Symbol
-50
Unit Note
-60
-70
min.
max. min.
max. min.
max.
common parameters
Random read or write cycle time
tRC
90
–
110
–
130
–
ns
RAS precharge time
tRP
30
–
40
–
50
–
ns
RAS pulse width
tRAS
50
10k
60
10k
70
10k
ns
CAS pulse width
tCAS
13
10k
15
10k
20
10k
ns
Row address setup time
tASR
0
–
0
–
0
–
ns
Row address hold time
tRAH
8
–
10
–
10
–
ns
Column address setup time
tASC
0
–
0
–
0
–
ns
Column address hold time
tCAH
10
–
15
–
15
–
ns
RAS to CAS delay time
tRCD
18
37
20
45
20
50
RAS to column address delay
time
tRAD
13
25
15
30
15
35
ns
RAS hold time
tRSH
13
15
–
20
–
ns
CAS hold time
tCSH
50
60
–
70
–
ns
CAS to RAS precharge time
tCRP
5
–
5
–
5
–
ns
Transition time (rise and fall)
tT
3
50
3
50
3
50
ns
Refresh period
tREF
–
32
–
32
–
32
ms
Access time from RAS
tRAC
–
50
–
60
–
70
ns
8, 9
Access time from CAS
tCAC
–
13
–
15
–
20
ns
8, 9
Access time from column address tAA
–
25
–
30
–
35
ns
8,10
OE access time
–
13
–
15
–
20
ns
Column address to RAS lead time tRAL
25
–
30
–
35
–
ns
Read command setup time
tRCS
0
–
0
–
0
–
ns
Read command hold time
tRCH
0
–
0
–
0
–
ns
11
Read command hold time
referenced to RAS
tRRH
0
–
0
–
0
–
ns
11
CAS to output in low-Z
tCLZ
0
–
0
–
0
–
ns
8
Output buffer turn-off delay
tOFF
0
13
0
15
0
20
ns
12
7
Read Cycle
Semiconductor Group
tOEA
7
HYB 5117400BJ/BT-50/-60/-70
4M x 4-DRAM
AC Characteristics (cont’d) 5)6)
TA = 0 to 70 °C,VCC = 5 V ± 10 %, tT = 5 ns
Parameter
16F
Limit Values
Symbol
-50
Unit Note
-60
-70
min.
max. min.
max. min.
max.
Output buffer turn-off delay from
OE
tOEZ
0
13
0
15
0
20
ns
12
Data to OE low delay
tDZO
0
–
0
–
0
–
ns
13
CAS high to data delay
tCDD
13
–
15
–
20
–
ns
14
OE high to data delay
tODD
13
–
15
–
20
–
ns
14
Write command hold time
tWCH
8
–
10
–
10
–
ns
Write command pulse width
tWP
8
–
10
–
10
–
ns
Write command setup time
tWCS
0
–
0
–
0
–
ns
Write command to RAS lead time tRWL
13
–
15
–
20
–
ns
Write command to CAS lead time tCWL
13
–
15
–
20
–
ns
Data setup time
tDS
0
–
0
–
0
–
ns
16
Data hold time
tDH
10
–
10
–
15
–
ns
16
Data to CAS low delay
tDZC
0
–
0
–
0
–
ns
13
Read-write cycle time
tRWC
126
–
150
–
180
–
ns
RAS to WE delay time
tRWD
68
–
80
–
95
–
ns
15
CAS to WE delay time
tCWD
31
–
35
–
45
–
ns
15
Column address to WE delay time tAWD
43
–
50
–
60
–
ns
15
OE command hold time
tOEH
13
–
15
–
20
–
ns
Fast page mode cycle time
tPC
35
–
40
–
45
–
ns
CAS precharge time
tCP
10
–
10
–
10
–
ns
Access time from CAS precharge
tCPA
–
30
–
35
–
40
ns
RAS pulse width
tRAS
50
200k 60
200k 70
200k ns
CAS precharge to RAS Delay
tRHPC
30
–
–
–
Write Cycle
15
Read-Modify-Write Cycle
Fast Page Mode Cycle
Semiconductor Group
8
35
40
ns
7
HYB 5117400BJ/BT-50/-60/-70
4M x 4-DRAM
AC Characteristics (cont’d) 5)6)
TA = 0 to 70 °C,VCC = 5 V ± 10 %, tT = 5 ns
Parameter
16F
Limit Values
Symbol
-50
min.
Unit Note
-60
-70
max. min.
max. min.
max.
Fast Page Mode Read-Modify-Write Cycle
Fast page mode read-write cycle
time
tPRWC
71
–
80
–
95
–
ns
CAS precharge to WE
tCPWD
48
–
55
–
65
–
ns
CAS setup time
tCSR
10
–
10
–
10
–
ns
CAS hold time
tCHR
10
–
10
–
10
–
ns
RAS to CAS precharge time
tRPC
5
–
5
–
5
–
ns
Write to RAS precharge time
tWRP
10
–
10
–
10
–
ns
Write hold time referenced to RAS tWRH
10
–
10
–
10
–
ns
tCPT
35
–
40
–
40
–
ns
CAS hold time
tCHRT
30
–
30
–
30
–
ns
Write command setup time
tWTS
10
–
10
–
10
–
ns
Write command hold time
tWTH
10
–
10
–
10
–
ns
RAS pulse width
tRASS
100k –
100k –
100k –
ns
17
RAS precharge time
tRPS
95
–
110
–
130
–
ns
17
CAS hold time
tCHS
-50
–
-50
–
-50
–
ns
17
CAS-before-RAS Refresh Cycle
CAS-before-RAS Counter Test Cycle
CAS precharge time
Test Mode
Self Refresh Cycle
Semiconductor Group
9
HYB 5117400BJ/BT-50/-60/-70
4M x 4-DRAM
Notes:
1) All voltages are referenced to VSS.
2) ICC1, ICC3, ICC4 and ICC6 depend on cycle rate.
3) ICC1 and ICC4 depend on output loading. Specified values are measured with the output open.
4) Address can be changed once or less while RAS = VIL. In the case of ICC4 it can be changed once or less
during a fast page mode cycle (tPC).
5) An initial pause of 200 µs is required after power-up followed by 8 RAS cycles of which at least one cycle has
to be a refresh cycle, before proper device operation is achieved. In case of using internal refresh counter, a
minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required.
6) AC measurements assume tT = 5 ns.
7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are also
measured between VIH and VIL.
8) Measured with a load equivalent to 2 TTL loads and 100 pF.
9) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a
reference point only: If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by
tCAC.
10)Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a
reference point only: If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by
tAA.
11)Either tRCH or tRRH must be satisfied for a read cycle.
12)tOFF (max.) and tOEZ (max.) define the time at which the outputs achieve the open-circuit condition and are
not referenced to output voltage levels.
13)Either tDZC or tDZO must be satisfied.
14)Either tCDD or tODD must be satisfied.
15)tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data
sheet as electrical characteristics only. If tWCS > tWCS (min.), the cycle is an early write cycle and the I/O pin
will remain open-circuit (high impedance) through the entire cycle; if tRWD > tRWD (min.), tCWD > tCWD
(min.), tAWD > tAWD (min.) and tCPWD > tCPWD (min.) , the cycle is a read-write cycle and I/O pins will
contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the condition of
the I/O pins (at access time) is indeterminate.
16)These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge
in read-write cycles.
17)When using Self Refresh mode, the following refresh operations must be performed to ensure proper DRAM
operation:
If row addresses are being refreshed on an evenly distributed manner over the refresh interval using CBR
refresh cycles, then only one CBR cycle must be performed immediately after exit from Self Refresh.
If row addresses are being refreshed in any other manner (ROR - Distributed/Burst; or CBR-Burst) over the
refresh interval, then a full set of row refreshes must be performed immediately before entry to and immediately
after exit from Self Refresh.
Semiconductor Group
10
HYB 5117400BJ/BT-50/-60/-70
4M x 4-DRAM
tRC
tRAS
RAS
V
IH
VIL
tCSH
V
IH
VIL
tRAD
tASR
Address
V
IH
VIL
tCRP
tRSH
tCAS
tRCD
CAS
tRP
tRAL
tCAH
tASC
tASR
Column
Row
Row
tRCH
tRAH
tRCS
tRRH
V
WE
OE
I/O
(Inputs)
IH
VIL
tAA
tOEA
V
IH
VIL
tCDD
tDZC
tODD
tDZO
V
IH
tCAC
VIL
tCLZ
V
OH
I/O
(Outputs) V
Hi Z
tOFF
tOEZ
Valid Data Out
Hi Z
OL
tRAC
WL1
“H” or “L”
Read Cycle
Semiconductor Group
11
HYB 5117400BJ/BT-50/-60/-70
4M x 4-DRAM
tRC
tRAS
tRP
V
IH
RAS
VIL
tCSH
tRCD
tRSH
tCAS
V
IH
CAS
VIL
tRAD
tASR
Address
V
IH
tRAL
Row
OE
.
Row
tCWL
tWCS
t WP
IH
VIL
tWCH
tRWL
V
IH
VIL
tDS
I/O
(Inputs)
tASR
Column
VIL
V
WE
tCAH
tASC
tRAH
tCRP
tDH
V
IH
Valid Data In
VIL
V
OH
I/O
(Outputs) V
Hi Z
OL
WL2
“H” or “L”
Write Cycle (Early Write)
Semiconductor Group
12
HYB 5117400BJ/BT-50/-60/-70
4M x 4-DRAM
tRC
tRAS
tRP
V
IH
RAS
VIL
tCSH
tRCD
V
IH
CAS
VIL
tRAD
tASR
tCRP
tRSH
tCAS
tCAH
tASC
tRAL
tASR
.
V
IH
Address V
IL
Row
tCWL
tRWL
tWP
tRAH
V
WE
Row
Column
IH
VIL
tOEH
V
OE
IH
tODD
tDS
tOEZ
VIL
tDZO
tDZC
I/O
(Inputs)
tDH
V
IH
Valid Data
VIL
tCLZ
tOEA
V
OH
I/O
(Outputs) V
Hi-Z
Hi-Z
OL
“H” or “L”
WL3
Write Cycle (OE Controlled Write)
Semiconductor Group
13
HYB 5117400BJ/BT-50/-60/-70
4M x 4-DRAM
tRWC
tRAS
RAS
V
IH
tRP
tCSH
VIL
tRSH
tCAS
tRCD
V
tCRP
IH
CAS
VIL
tRAH
tCAH
tASR
tASC
tASR
V
IH
Address
VIL
Row
Column
Row
tCWL
tRWL
tAWD
tRAD
tCWD
tRWD
tWP
V
IH
WE
VIL
tAA
tRCS
tOEH
tOEA
V
IH
OE
VIL
tDS
tDZO
tDZC
I/O
(Inputs)
tDH
V
IH
Valid
Data in
VIL
tCLZ
tODD
tCAC
tOEZ
V
OH
I/O
(Outputs) VOL
Data
Out
tRAC
“H” or “L”
WL4
Read-Write (Read-Modify-Write) Cycle
Semiconductor Group
14
HYB 5117400BJ/BT-50/-60/-70
4M x 4-DRAM
tRP
tRASP
V
IH
RAS
VIL
tRHCP
tRSH
tCAS
tPC
tCAS
tRCD
tCAS
tCP
V
tCRP
IH
CAS
VIL
tCSH
tRAH
tASR
V
Address
tCAH
tASC
tASC
IH
VIL
Row
tCAH
tCAH
Column
Column
tASR
tASC
Column
Row
tRAD
tRCH
tRCH
tRCS
tRCS
tRCS
tCPA
tAA
tCPA
tAA
tOEA
V
IH
WE
VIL
tAA
OE
VIL
tDZC
tDZC
tDZC
tDZO
tDZO
I/O
(Inputs)
tOEA
tOEA
V
IH
tODD
V
tODD
tRRH
tCDD
tDZO
tODD
IH
VIL
tCAC
tRAC
tCLZ
tOFF
tOEZ
tCAC
tCLZ
tOFF
tOEZ
V
OH
I/O
(Outputs) V
Valid
Data Out
OL
Valid
Data Out
tCAC
tCLZ
tOFF
tOEZ
Valid
Data Out
“H” or “L”
FPM1
Fast Page Mode Read Cycle
Semiconductor Group
15
HYB 5117400BJ/BT-50/-60/-70
4M x 4-DRAM
tRP
tRAS
V
IH
RAS
VIL
tRSH
tPC
tRCD
tCAS
tCP
tCAS
tCAS
tCRP
V
IH
CAS
VIL
tRAL
tRAH
tCAH
tASR
tASC
V
Address
IH
VIL
tCWL
tWCS
tCWL
tWCS
tASR
Column
tCWL
tRWL
tWCH
tWP
tWP
VIL
V
IH
VIL
tDH
tDS
I/O
(Inputs)
tCAH
Column
tWCH
tWP
IH
tASC
Column
tWCH
V
OE
tASC
Column
Row
tRAD
tWCS
WE
tCAH
tDH
tDH
tDS
tDS
V
IH
VIL
Valid
Data In
Valid
Data In
Valid
Data In
V
OH
I/O
(Outputs) V
HI-Z
OL
“H” or “L”
FPM2
Fast Page Mode Early Write Cycle
Semiconductor Group
16
Semiconductor Group
Fast Page Mode Read-Modify-Write Cycle
17
IH
IH
IH
IH
V
IH
V IL
V
V IL
V
V IL
V
V IL
V
V IL
IH
OL
OH
I/O
(Outputs) V
V
I/O
(Inputs) V IL
OE
WE
Address
CAS
RAS
V
tASR
tRAC
tCAS
tAA
tOEA
tAWD
tCAC
Data
Out
tOEH
Data In
tDS
tCAH
tAA
tCLZ
tCPA
tDZC
tOEZ
tDS
tDH
tOEH
tCAH
tDZC
tAA
tCAC
tCLZ
tCPA
tDS
tOEZ
tRWL
tCWL
tWP
tDH
tOEH
Data In
tODD
tRAL
tCAS
tRSH
Data
Out
tOEA
tAWD
tCPWD
tCWD
Column
tASC
tCWL
tWP
Data In
tODD
Data
Out
tOEA
tAWD
tPRWC
tCAS
tCPWD
tCWD
Column
Address
tASC
tCP
tCWL
tWP
tOEZ tDH
tODD
tRWD
tCWD
Column
tASC
tCAH
tDZC
tCLZ
tDZO
tRCS
“H” or “L”
Row
tRAH
tRAD
tRCD
tCSH
tRAS
tCRP
Row
tASR
tRP
HYB 5117400BJ/BT-50/-60/-70
4M x 4-DRAM
HYB 5117400BJ/BT-50/-60/-70
4M x 4-DRAM
tRC
tRAS
RAS
tRP
V
IH
VIL
tCRP
tRPC
CAS
V
IH
VIL
tRAH
tASR
tASR
V
Address
IH
Row
VIL
Row
V
OH
I/O
(Outputs) V
HI-Z
OL
“H” or “L”
WL9
RAS-Only Refresh Cycle
Semiconductor Group
18
HYB 5117400BJ/BT-50/-60/-70
4M x 4-DRAM
tRC
tRP
tRAS
tRP
V
RAS
IH
VIL
tRPC
tCSR
tCRP
tCP
CAS
tRPC
tCHR
V
IH
VIL
tWRP
tWRH
V
WE
IH
VIL
tOEZ
V
IH
OE
VIL
tCDD
I/O
(Inputs)
V
IH
VIL
tODD
V
OH
I/O
(Outputs)VOL
HI-Z
tOFF
“H” or “L”
WL10
CAS-Before-RAS Refresh Cycle
Semiconductor Group
19
HYB 5117400BJ/BT-50/-60/-70
4M x 4-DRAM
tRC
tRC
RAS
tRP
tRAS
V
tRP
tRAS
IH
VIL
tRSH
tRCD
tCRP
tCHR
V
CAS
IH
tRAD
VIL
tWRP
tASC
tASR
tRAH
tASR
tWRH
tCAH
V
Address
IH
VIL
Column
Row
Row
tRRH
tRCS
V
WE
IH
VIL
tAA
tOEA
V
OE
IH
VIL
tDZC
tCDD
tDZO
tODD
V
I/O
(Inputs)
IH
VIL
tCAC
tOFF
tCLZ
tOEZ
tRAC
V
OH
I/O
(Outputs) V
Valid Data Out
HI-Z
OL
“H” or “L”
WL11
Hidden Refresh Cycle (Read)
Semiconductor Group
20
HYB 5117400BJ/BT-50/-60/-70
4M x 4-DRAM
tRC
tRC
tRP
RAS
tRAS
V
IH
WE
tRSH
VIL
tCRP
tRAD
tRAH
tASC
tCAH
V
IH
VIL
Row
tASR
Row
Column
tWCS
tWRP
tWCH
tWRH
tWP
V
IH
VIL
tDS
I/O
(Input)
tCHR
V
IH
tASR
Address
tRP
VIL
tRCD
CAS
tRAS
V
IH
tDH
Valid Data
V
IL
V
OH
I/O
(Output) V
OL
HI-Z
“H” or “L”
WL12
Hidden Refresh Cycle (Early Write)
Semiconductor Group
21
HYB 5117400BJ/BT-50/-60/-70
4M x 4-DRAM
tRASS
tRP
RAS
tRPS
V
IH
VIL
tRPC
tCP
V
CAS
tCRP
tCHS
tCSR
IH
VIL
tWRP
tWRH
V
WE
OE
IH
VIL
V
IH
VIL
tCDD
I/O
(Inputs)
V
IH
VIL
tODD
tOEZ
V
OH
I/O
(Outputs) V
OL
HI-Z
tOFF
“H” or “L”
WL13
CAS before RAS Self Refresh Cycle
Semiconductor Group
22
HYB 5117400BJ/BT-50/-60/-70
4M x 4-DRAM
tRP
tRAS
Read Cycle:
RAS
V
IH
V IL
tRSH
tCAS
tCP
tCHR
tCSR
CAS
V IH
V IL
tRAL
tASC
Address
V IH
Column
V IL
tWRP
WE
OE
I/O
(Inputs)
I/O
(Outputs)
V IL
Row
tWRH
tOEA
tRCS
V IH
V IL
tDZC
V IH
V IL
tODD
tDZO
VOH
VOL
V IH
V IL
OE
V IH
V IL
I/O
(Inputs)
V IH
tOEZ
Data Out
tWCS
tRWL
tCWL
tWCH
tWRH
tDS
V
IH
V
IL
HI-Z
CAS-Before-RAS Refresh Counter Test Cycle
Semiconductor Group
tDH
Data In
V IL
23
tCDD
tOFF
tCLZ
Write Cycle:
I/O
(Outputs)
tRRH
tAA
tCAC
V IH
tWRP
WE
tASR
tCAH
tRCH
HYB 5117400BJ/BT-50/-60/-70
4M x 4-DRAM
tRC
tRP
tRAS
V
RAS
tRP
IH
VIL
tRPC
tCP
tCSR
tCHR
tRPC
tCRP
V
CAS
IH
VIL
tASR tRAH
V
Address IH
Row
VIL
tWTS
tWTH
V
WE
IH
VIL
V
OE
IH
VIL
V
I/O
IH
(Inputs) V
IL
tODD
HI-Z
tCDD
tOEZ
V
OH
I/O
(Outputs) V
HI-Z
OL
tOFF
“H” or “L”
WL15
Test Mode Entry
Semiconductor Group
24
HYB 5117400BJ/BT-50/-60/-70
4M x 4-DRAM
Test Mode
As the HYB 5117400BJ/BT is organized internally as 1M x 16-bits, a test mode cycle using 4:1
compression can be used to improve test time. Note that in the 4M x 4 version the test time is
reduced by 1/4 for a N test pattern.
In a test mode “write” the data from each I/O pin is written into four 1M blocks simultaneously (all
“1” s or all “0” s). In test mode “read” each I/O output is used for indicating the test mode result. If
the internal four bits are equal, the I/O would indicate a “1”. If they were not equal, the I/O would
indicate a “0”. The WCBR cycle (WE, CAS before RAS) puts the device into test mode. To exit
from test mode, a “CAS before RAS refresh”, “RAS only refresh” or “Hidden refresh” can be
used.Refresh during test mode operation can be performed by normal read cycles or by WCBR
refresh cycles.
Row addresses A0 through A9 have to kept high to perform a testmode entry cycle. All other
addresses are don’t care.
A0C,A1C
A0C,A1C
Normal
I/O 1
Test
1 M Block
Vcc
1 M Block
Normal
I/O 1
1 M Block
Test
1 M Block
A0C,A1C
A0C,A1C
Normal
I/O 2
Test
Vss
Vcc
1 M Block
Normal
1 M Block
I/O 2
1 M Block
Test
1 M Block
A0C,A1C
A0C,A1C
Normal
I/O 3
1 M Block
Vss
Vcc
1 M Block
Normal
Test
1 M Block
I/O 3
Test
1 M Block
A0C,A1C
A0C,A1C
Normal
I/O 4
Test
1 M Block
Vss
Vcc
1 M Block
Normal
I/O 4
1 M Block
Test
1 M Block
Vss
Block Diagram in Test Mode
Semiconductor Group
25
HYB 5117400BJ/BT-50/-60/-70
4M x 4-DRAM
Package Outlines
Plastic Package P-SOJ-26/24 (300 mil)
(Small Outline J-leads, SMD)
GPJ05628
Index Marking
1) Does not include plastic or metal protrusion of 0.15 max per side
7.62
1.27
0.4
+- 0.13
0.6
+0.12
-0.1
0.2
M
0.1
24x
26
9.22
-0.2
+- 0.2
14
GPX05857
1
13
17.27
-0.25
1)
Index Marking
Semiconductor Group
26