PRELIMINARY ICS8440258-46 FEMTOCLOCK™ CRYSTAL/LVCMOS-TOLVDS/LVCMOS FREQUENCY SYNTHESIZER GENERAL DESCRIPTION FEATURES The ICS8440258-46 is an 8 output synthesizer ICS optimized to generate Ethernet clocks and a HiPerClockS™ member of the HiPerClock S ™ family of high performance clock solutions from IDT. Using a 25MHz, 18pF parallel resonant crystal, the device will generate both 125MHz and 25MHz clocks with mixed LVDS and LVCMOS/LVTTL output logic. The ICS8440258-46 uses IDT’s 3rd generations low phase noise VCO technology and can achieve <1ps typical rms phase jitter, easily meeting Ethernet jitter requirements. The ICS8440258-46 is packaged in a small, 5mm x 5mm VFQFN package. • Four differential LVDS outputs at 125MHz Two LVCMOS/LVTTL single-ended outputs at 125MHz Two LVCMOS/LVTTL single-ended outputs at 25MHz • Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended input • VCO range: 490MHz - 680MHz • RMS phase jitter @ 125MHz, using a 25MHz crystal (1.875MHz - 20MHz): 0.34ps (typical) • Full 2.5V operating supply • 0°C to 70°C ambient operating temperature VDDA nPLL_SEL MR VDD REF_CLK nXTAL_SEL XTAL_IN PIN ASSIGNMENT XTAL_OUT • Available in both standard (RoHS 5) and lead-free (RoHS6) packages 32 31 30 29 28 27 26 25 Q0 1 24 nc nQ0 2 23 nc GND 3 22 nc Q1 4 21 GND nQ1 5 20 Q7 VDD 6 19 VDDO2 Q2 7 18 Q6 nQ2 8 17 GND BLOCK DIAGRAM ICS8440258-46 32-Lead VFQFN 5mm x 5mm x 0.925mm package body K Package Top View Q5 GND Q4 VDDO1 VDD GND nQ0 Q3 Q0 nPLL_SEL Pulldown nQ3 9 10 11 12 13 14 15 16 MR Pulldown Q1 nQ1 25MHz XTAL_IN OSC Q2 nQ2 ÷5 XTAL_OUT REF_CLK Pulldown 1 0 VCO Phase Detector 490-680MHz 0 Q3 nQ3 1 Q4 nXTAL_SEL Pulldown ÷25 Q5 Q6 Q7 The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice. IDT ™ / ICS™ LVDS/LVCMOS FREQUENCY SYNTHESIZER 1 ICS8440258AK-46 REV B JANUARY 15, 2008 ICS8440258-46 FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-LVDS/ LVCMOS FREQUENCY SYNTHESIZER PRELIMINARY TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1, 2 3, 12, 16, 17, 21 4, 5 Q0, nQ0 Output Differential clock outputs. LVDS interface levels. GND Power Power supply ground. Q1, nQ1 Output Differential clock outputs. LVDS interface levels. 6, 11, 27 VDD Power Core supply pin. 7, 8 Q2, nQ2 Output Differential clock outputs. LVDS interface levels. 9, 10 13, 15, 18, 20 14 Q3, nQ3 Q4, Q5, Q6, Q7 VDDO1 Output Differential clock outputs. LVDS interface levels. Output Single-ended clock outputs. LVCMOS/LVTTL interface levels. Power Power output supply pin for Q4 and Q5 LVCMOS outputs. 19 VDDO2 Power Power output supply pin for Q6 and Q7 LVCMOS outputs. 22, 23, 24 nc Unused 25 VDDA Power No connect. Analog supply pin. PLL Bypass. When LOW, the output is driven from the VCO output. When HIGH, the PLL is bypassed and the output frequency = 26 nPLL_SEL Input Pulldown reference clock frequency/N output divider. LVCMOS/LVTTL interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are 28 MR Input Pulldown reset causing the outputs to go low. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. 29 REF_CLK Input Pulldown Single-ended LVCMOS/LVTTL reference clock input. Selects between the crystal or REF_CLK inputs as the PLL reference 30 nXTAL_SEL Input Pulldown source. When HIGH, selects REF_CLK. When LOW, selects XTAL inputs. LVCMOS/LVTTL interface levels. 31, XTAL_OUT, Crystal oscillator interface. XTAL_OUT is the output. Input 32 XTAL_IN XTAL_IN is the input. NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units CIN Input Capacitance 4 pF CPD Power Dissipation Capacitance 8 pF RPULLDOWN Input Pulldown Resistor 51 kΩ ROUT Output Impedance 22 Ω IDT ™ / ICS™ LVDS/LVCMOS FREQUENCY SYNTHESIZER 2 ICS8440258AK-46 REV B JANUARY 15, 2008 ICS8440258-46 FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-LVDS/ LVCMOS FREQUENCY SYNTHESIZER PRELIMINARY ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO (LVCMOS) -0.5V to VDD + 0.5V ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed Outputs, IO (LVDS) Continuous Current Surge Current in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended 10mA 15mA periods may affect product reliability. Operating Temperature Range, TA -40°C to +85°C Storage Temperature, TSTG -65°C to 150°C Package Thermal Impedance, θJA 37°C/W (0 mps) TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO1 = VDDO2 = 2.5V ± 5%,TA = 0°C TO 70°C Symbol VDD Parameter Core Supply Voltage Test Conditions Minimum 2.375 Typical 2.5 Maximum 2.625 Units V VDDA Analog Supply Voltage VDD – 0.13 2.5 VDD V VDDO Output Supply Voltage 2.375 2.5 2.625 V IDD, IDDO1, IDDO2 Power Supply Current 170 mA IDDA Analog Supply Current 13 mA TABLE 3B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO1 = VDDO2 = 2.5V ± 5%,TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage 1.7 VDD + 0.3 V VIL Input Low Voltage -0.3 0.7 V IIH Input High Current MR, REF_CLK, nPLL_SEL, nXTAL_SEL VDD = VIN = 2.625V 150 µA IIL Input Low Current MR, REF_CLK, nPLL_SEL, nXTAL_SEL VDD = 2.625V, VIN = 0V -5 µA Output High Voltage; Q4:Q7 1.8 VDDO1, VDDO1 = 2.625V±5% NOTE 1 Output Low Voltage; Q4:Q7 VOL VDDO1, VDDO1 = 2.625V±5% NOTE 1 NOTE 1: Outputs terminated with 50Ω to VDDOX/2. See Parameter Measurement Information, Output Load Test Circuit diagram. VOH IDT ™ / ICS™ LVDS/LVCMOS FREQUENCY SYNTHESIZER 3 V 0.5 V ICS8440258AK-46 REV B JANUARY 15, 2008 ICS8440258-46 FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-LVDS/ LVCMOS FREQUENCY SYNTHESIZER PRELIMINARY TABLE 3C. LVDS DC CHARACTERISTICS, VDD = VDDA = VDDO1 = VDDO2 = 2.5V ± 5%,TA = 0°C TO 70°C Symbol Parameter Test Conditions VOD Differential Output Voltage Δ VOD VOD Magnitude Change VOS Offset Voltage Δ VOS VOS Magnitude Change Minimum Typical Maximum Units 390 mV 50 mV 1.25 V 50 mV TABLE 4. CRYSTAL CHARACTERISTICS Parameter Test Conditions Minimum Mode of Oscillation Typical Maximum Units Fundamental Frequency 25 MHz Ω Equivalent Series Resistance (ESR) 50 Shunt Capacitance 7 pF Drive Level 1 mW Maximum Units NOTE: Characterized using an 18pF parallel resonant cr ystal. TABLE 5. AC CHARACTERISTICS, VDD = VDDA = VDDO1 = VDDO2 = 2.5V ± 5%,TA = 0°C TO 70°C Symbol Parameter fOUT Output Frequency Test Conditions Minimum Typical Q0:3/nQ0:3 125 MHz Q4, Q5 125 MHz Q6, Q7 25 MHz tsk(o) Output Skew; NOTE 1, 2 Q0:3/nQ0:3 50 ps Q4:Q7 50 ps tjit(Ø) RMS Phase Jitter (Random); NOTE 3 Q0:3/nQ0:3 125MHz, (1.875MHz - 20MHz) 0.34 ps Q4, Q5 125MHz, (1.875MHz - 20MHz) 0.37 ps tR / tF Output Rise/Fall Time Q0:3/nQ0:3 20% to 80% 480 ps Q4:Q7 20% to 80% 1.4 ns 50 % odc Output Duty Cycle Q0:3/nQ0:3 Q4:Q7 46 NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDOX/2. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Please refer to the Phase Noise Plot. IDT ™ / ICS™ LVDS/LVCMOS FREQUENCY SYNTHESIZER 4 54 % ICS8440258AK-46 REV B JANUARY 15, 2008 ICS8440258-46 FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-LVDS/ LVCMOS FREQUENCY SYNTHESIZER PRELIMINARY TYPICAL PHASE NOISE AT 125MHZ (LVCMOS) ➤ 0 -10 -20 Ethernet Filter -30 -40 125MHz -60 RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.37ps (typical) -70 -80 -90 Raw Phase Noise Data -100 ➤ NOISE POWER dBc Hz -50 -110 -120 -130 -140 -150 -160 ➤ -170 -180 Phase Noise Result by adding Ethernet Filter to raw data -190 -200 10 100 1k 10k 100k 1M 10M 100M OFFSET FREQUENCY (HZ) TYPICAL PHASE NOISE AT 125MHZ (LVDS) ➤ 0 -10 -20 Ethernet Filter -50 125MHz -60 RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.34ps (typical) -70 -80 -90 -100 Raw Phase Noise Data -110 ➤ NOISE POWER dBc Hz -30 -40 -120 -130 -140 -150 -160 -170 ➤ -180 -190 Phase Noise Result by adding Ethernet Filter to raw data -200 10 100 1k 10k 100k 1M 10M 100M OFFSET FREQUENCY (HZ) IDT ™ / ICS™ LVDS/LVCMOS FREQUENCY SYNTHESIZER 5 ICS8440258AK-46 REV B JANUARY 15, 2008 ICS8440258-46 FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-LVDS/ LVCMOS FREQUENCY SYNTHESIZER PRELIMINARY PARAMETER MEASUREMENT INFORMATION 1.25V±5% 1.25V±5% VDD, VDDO1, VDDO2 SCOPE VDD, VDDO1, VDDA VDDO2 2.5V±5% POWER SUPPLY + Float GND – Qx SCOPE VDDA Qx LVCMOS LVDS GND nQx -1.25V±5% 2.5V LVDS OUTPUT LOAD AC TEST CIRCUIT 2.5V LVCMOS OUTPUT LOAD AC TEST CIRCUIT nQx V DDO Qx Qx 2 nQy V DDO Qy Qy 2 t sk(o) t sk(o) LVDS OUTPUT SKEW LVCMOS OUTPUT SKEW 80% 80% 80% 80% VOD Clock Outputs 20% 20% tR Clock Outputs tF LVDS OUTPUT RISE/FALL TIME IDT ™ / ICS™ LVDS/LVCMOS FREQUENCY SYNTHESIZER 20% 20% tR tF LVCMOS OUTPUT RISE/FALL TIME 6 ICS8440258AK-46 REV B JANUARY 15, 2008 ICS8440258-46 FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-LVDS/ LVCMOS FREQUENCY SYNTHESIZER PRELIMINARY Phase Noise Plot Noise Power nQ0:nQ3 Q0:Q3 t PW Phase Noise Mask t f1 Offset Frequency odc = f2 PERIOD t PW x 100% t PERIOD RMS Jitter = Area Under the Masked Phase Noise Plot LVDS OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD RMS PHASE JITTER V DDO 2 Q4:Q7 t PW t odc = PERIOD t PW x 100% t PERIOD LVCMOS OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD IDT ™ / ICS™ LVDS/LVCMOS FREQUENCY SYNTHESIZER 7 ICS8440258AK-46 REV B JANUARY 15, 2008 ICS8440258-46 FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-LVDS/ LVCMOS FREQUENCY SYNTHESIZER PRELIMINARY APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS8440258-46 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA, VDDO1 and VDDO2 should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10Ω resistor along with a 10µF and a 0.01μF bypass capacitor should be connected to each VDDA. 2.5V VDD .01μF 10Ω VDDA .01μF 10μF FIGURE 1. POWER SUPPLY FILTERING CRYSTAL INPUT INTERFACE were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. The ICS8440258-46 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 below XTAL_IN C1 22p X1 18pF Parallel Cry stal XTAL_OUT C2 22p ICS84332 FIGURE 2. CRYSTAL INPUt INTERFACE IDT ™ / ICS™ LVDS/LVCMOS FREQUENCY SYNTHESIZER 8 ICS8440258AK-46 REV B JANUARY 15, 2008 ICS8440258-46 FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-LVDS/ LVCMOS FREQUENCY SYNTHESIZER PRELIMINARY LVCMOS TO XTAL INTERFACE (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50Ω applications, R1 and R2 can be 100Ω. This can also be accomplished by removing R1 and making R2 50Ω. The XTAL_IN input can accept a single-ended LVCMOS signal through an AC couple capacitor. A general interface diagram is shown in Figure 3. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output impedance of the driver VDD VDD R1 Ro .1uf Rs Zo = 50 XTAL_IN R2 Zo = Ro + Rs XTAL_OUT Figure 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: CRYSTAL INPUTS For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1kW resistor can be tied from XTAL_IN to ground. LVCMOS OUTPUTS All unused LVCMOS output can be left floating. There should be no trace attached. LVDS OUTPUTS All unused LVDS output pairs can be either left floating or terminated with 100Ω across. If they are left floating, there should be no trace attached. REF_CLK INPUT For applications not requiring the use of the reference clock, it can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from the REF_CLK to ground. LVCMOS CONTROL PINS All control pins have internal pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. IDT ™ / ICS™ LVDS/LVCMOS FREQUENCY SYNTHESIZER 9 ICS8440258AK-46 REV B JANUARY 15, 2008 ICS8440258-46 FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-LVDS/ LVCMOS FREQUENCY SYNTHESIZER PRELIMINARY 2.5V LVDS DRIVER TERMINATION Figure 4 shows a typical ter mination for LVDS driver in characteristic impedance of 100Ω differential (50Ω single) transmission line environment. For buffer with multiple LDVS driver, it is recommended to terminate the unused outputs. 2.5V 2.5V LVDS_Driv er + R1 100 - 100 Ohm Differential Transmission Line Ω 100Ω Differential Transmission Line FIGURE 4. TYPICAL LVDS DRIVER TERMINATION VFQFN EPAD THERMAL RELEASE PATH are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/ slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, refer to the Application Note on the Surface Mount Assembly of Amkor’s Thermally/ Electrically Enhance Leadfame Base Package, Amkor Technology. In order to maximize both the removal of heat from the package and the electrical perfor mance, a land patter n must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 5. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) PIN PIN PAD SOLDER EXPOSED HEAT SLUG GROUND PLANE SOLDER LAND PATTERN THERMAL VIA PIN PIN PAD (GROUND PAD) FIGURE 5. P.C.ASSEMBLY FOR EXPOSED PAD THERMAL RELEASE PATH –SIDE VIEW (DRAWING NOT TO SCALE) IDT ™ / ICS™ LVDS/LVCMOS FREQUENCY SYNTHESIZER 10 ICS8440258AK-46 REV B JANUARY 15, 2008 ICS8440258-46 FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-LVDS/ LVCMOS FREQUENCY SYNTHESIZER PRELIMINARY POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS8440258-46. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS840258-46 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 2.5V + 5% = 2.625V, which gives worst case results. Core and LVDS Output Power Dissipation • Power (core, LVDS) = VDD_MAX * (IDD + IDDO1 + IDDO2 + IDDA ) = 2.625V * (170mA + 13mA) = 480.4mW LVCMOS Output Power Dissipation • Output Impedance ROUT Power Dissipation due to Loading 50Ω to VDDO/2 Output Current IOUT = VDDO_MAX / [2 * (50Ω + ROUT)] = 2.625V / [2 * (50Ω + 12Ω)] = 21.2mA • Power Dissipation on the ROUT per LVCMOS output Power (ROUT) = ROUT * (IOUT)2 = 12Ω * (21.2mA)2 = 5.4mW per output • Total Power Dissipation on the ROUT Total Power (ROUT) = 5.4mW * 4 = 21.6mW • Dynamic Power Dissipation at 125MHz Power (125MHz) = CPD * Frequency * (VDDO)2 = 8pF * 125MHz * (2.625V)2 = 6.9mW per output Total Power (125MHz) = 6.9mW * 2 = 13.8mW • Dynamic Power Dissipation at 25MHz Power (25MHz) = CPD * frequency * (VDDO)2 = 8pF * 25MHz * (2.625V)2 = 1.4 mW per output Total Power (25MHz) = 1.4mW * 2 = 2.8mW Total Power Dissipation • Total Power = Power (core, LVDS) + Total Power (ROUT) + Total Power (125MHz) + Total Power (25MHz) = 480.4mW + 21.6mW + 13.8mW + 2.8mW = 518.6mW IDT ™ / ICS™ LVDS/LVCMOS FREQUENCY SYNTHESIZER 11 ICS8440258AK-46 REV B JANUARY 15, 2008 ICS8440258-46 FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-LVDS/ LVCMOS FREQUENCY SYNTHESIZER PRELIMINARY 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 37°C/W per Table 6. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.519W * 37°C/W = 89.2°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 6. THERMAL RESISTANCE θJA FOR 32-LEAD VFQFN, FORCED CONVECTION θJA vs. Air Flow (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards IDT ™ / ICS™ LVDS/LVCMOS FREQUENCY SYNTHESIZER 0 1 2.5 37.0°C/W 32.4°C/W 29.0°C/W 12 ICS8440258AK-46 REV B JANUARY 15, 2008 ICS8440258-46 FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-LVDS/ LVCMOS FREQUENCY SYNTHESIZER PRELIMINARY RELIABILITY INFORMATION TABLE 7. θJAVS. AIR FLOW TABLE FOR 32 LEAD VFQFN θJA vs. Air Flow (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 37.0°C/W 32.4°C/W 29.0°C/W TRANSISTOR COUNT The transistor count for ICS8440258-46 is: 2589 IDT ™ / ICS™ LVDS/LVCMOS FREQUENCY SYNTHESIZER 13 ICS8440258AK-46 REV B JANUARY 15, 2008 ICS8440258-46 FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-LVDS/ LVCMOS FREQUENCY SYNTHESIZER PRELIMINARY PACKAGE OUTLINE - K SUFFIX FOR 32 LEAD VFQFN NOTE: The following package mechanical drawing is a generic drawing that applies to any pin count VFQFN package. This drawing is not intended to convey the actual pin count or pin layout of this device. The pin count and pinout are shown on the front page. The package dimensions are in Table 8 below. TABLE 8. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS VHHD-2 SYMBOL MINIMUM NOMINAL A 0.80 A1 0 -- 1.00 -- 0.05 0.25 Ref. A3 b 0.18 0.25 8 NE 5.00 BASIC D 1.25 2.25 1.25 2.25 3.25 0.50 BASIC e L 3.25 5.00 BASIC E E2 0.30 8 ND D2 MAXIMUM 32 N 0.30 0.40 0.50 Reference Document: JEDEC Publication 95, MO-220 IDT ™ / ICS™ LVDS/LVCMOS FREQUENCY SYNTHESIZER 14 ICS8440258AK-46 REV B JANUARY 15, 2008 ICS8440258-46 FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-LVDS/ LVCMOS FREQUENCY SYNTHESIZER PRELIMINARY TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS8440258AK-46 ICS40258A46 32 Lead VFQFN Tray 0°C to 70°C ICS8440258AK-46T ICS40258A46 32 Lead VFQFN 1000 Tape & Reel 0°C to 70°C ICS8440258AK-46LF ICS0258A46L 32 Lead "Lead-Free" VFQFN Tray 0°C to 70°C ICS8440258AK-46LFT ICS0258A46L 32 Lead "Lead-Free" VFQFN 1000 Tape & Reel 0°C to 70°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT ™ / ICS™ LVDS/LVCMOS FREQUENCY SYNTHESIZER 15 ICS8440258AK-46 REV B JANUARY 15, 2008 ICS8440258-46 FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-LVDS/ LVCMOS FREQUENCY SYNTHESIZER PRELIMINARY Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 [email protected] 480-763-2056 Corporate Headquarters Asia Pacific and Japan Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 IDT Europe, Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England +44 (0) 1372 363 339 Fax: +44 (0) 1372 378851 © 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA