HP HCPL-261A Hcmos compatible, high cmr, 10 mbd optocoupler Datasheet

H
HCMOS Compatible, High CMR,
10 MBd Optocouplers
Technical Data
HCPL-261A
HCPL-263A
HCPL-261N
HCPL-263N
Features
• HCMOS/LSTTL/TTL
Performance Compatible
• 1000 V/µs Minimum
Common Mode Rejection
(CMR) at VCM = 50 V (HCPL261A Family) and 15 kV/µs
Minimum CMR at VCM =
1000 V (HCPL-261N Family)
• High Speed: 10 MBd Typical
• AC and DC Performance
Specified over Industrial
Temperature Range -40°C to
+85°C
• Available in 8 Pin DIP,
SOIC-8 Packages
• Safety Approval
UL Recognized per UL1577
2500 V rms for 1 minute and
5000 V rms for 1 minute
(Option 020)
CSA Approved
VDE 0884 Approved with
VIORM = 630 V peak for
HCPL-261A/261N
Option 060
• Computer-Peripheral
Interface
• Digital Isolation for A/D,
D/A Conversion
• Switching Power Supplies
• Instrumentation
Input/Output Isolation
• Ground Loop Elimination
• Pulse Transformer
Replacement
Description
The HCPL-261A family of optically
coupled gates shown on this data
sheet provide all the benefits of the
industry standard 6N137 family
with the added benefit of HCMOS
compatible input current. This
allows direct interface to all
common circuit topologies without
additional LED buffer or drive
components. The AlGaAs LED
used allows lower drive currents
and reduces degradation by using
the latest LED technology. On the
single channel parts, an enable
output allows the detector to be
strobed. The output of the detector
IC is an open collector schottkyclamped transistor. The internal
shield provides a minimum
common mode transient immunity
of 1000 V/µs for the HCPL-261A
family and 15000 V/µs for the
HCPL-261N family.
Functional Diagram
HCPL-261A/261N
HCPL-061A/061N
HCPL-263A/263N
HCPL-063A/063N
ANODE 1
1
8
VCC
VE
CATHODE 1
2
7
VO1
6
VO
CATHODE 2
3
6
VO2
5
GND
ANODE 2
4
5
GND
NC
1
8
VCC
ANODE
2
7
CATHODE
3
NC
4
Applications
• Low Input Current (3.0 mA)
HCMOS Compatible Version
of 6N137 Optocoupler
• Isolated Line Receiver
• Simplex/Multiplex Data
Transmission
HCPL-061A
HCPL-063A
HCPL-061N
HCPL-063N
SHIELD
TRUTH TABLE
(POSITIVE LOGIC)
LED
ON
OFF
ON
OFF
ON
OFF
ENABLE
H
H
L
L
NC
NC
OUTPUT
L
H
H
H
L
H
SHIELD
TRUTH TABLE
(POSITIVE LOGIC)
LED
ON
OFF
OUTPUT
L
H
The connection of a 0.1 µF bypass capacitor between pins 5 and 8 is required.
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to
prevent damage and/or degradation which may be induced by ESD.
1-166
5965-3593E
Minimum CMR
dV/dt
(V/µs)
VCM
(V)
Input
OnCurrent
(mA)
NA
NA
5
8-Pin DIP (300 Mil)
Output
Enable
Single
Channel
Package
YES
6N137[1]
Dual
Channel
Package
50
YES
10,000
1,000
YES
HCPL-2601[1]
HCPL-2631[1]
NO
YES
HCPL-2602[1]
3,500
300
YES
HCPL-2612[1]
1,000
50
YES
HCPL-261A
1,000
50
HCPL-261N
HCNW2611[1]
HCPL-0661[1]
HCPL-063A
HCPL-061N
NO
12.5
HCNW2601[1]
HCPL-0631[1]
HCPL-263A
YES
Single and
Dual Channel
Packages
HCPL-061A
NO
1,000
Hermetic
Single
Channel
Package
HCNW137[1]
HCPL-0611[1]
HCPL-4661[1]
50
Widebody
(400 Mil)
HCPL-0630[1]
HCPL-0601[1]
HCPL-2611[1]
1,000
1,000[2]
Dual
Channel
Package
HCPL-0600[1]
NO
3
Single
Channel
Package
HCPL-2630[1]
NO
5,000
Small-Outline SO-8
HCPL-263N
HCPL-063N
[3]
HCPL-193X[1]
HCPL-56XX[1]
HCPL-66XX[1]
Notes:
1. Technical data are on separate HP publications.
2. 15 kV/µs with VCM = 1 kV can be achieved using HP application circuit.
3. Enable is available for single channel products only, except for HCPL-193X devices.
Ordering Information
Specify Part Number followed by Option Number (if desired).
Example:
HCPL-261A#XXX
020 = 5000 V rms/1 minute UL Rating Option*
060 = VDE 0884 VIORM = 630 Vpeak Option**
300 = Gull Wing Surface Mount Option***
500 = Tape and Reel Packaging Option
Option data sheets available. Contact your Hewlett-Packard sales representative or authorized distributor for
information.
*For HCPL-261A/261N/263A/263N (8-pin DIP products) only.
**For HCPL-261A/261N only. Combination of Option 020 and Option 060 is not available.
***Gull wing surface mount option applies to through hole parts only.
HCPL-263A/263N
HCPL-063A/063N
ICC
Schematic
1
HCPL-261A/261N
HCPL-061A/061N
IF
8
IF1
IO1
+
ICC
8
2+
IO
6
VCC
VO
7
VCC
VO1
VF1
–
2
SHIELD
3
VF
IO2
–
–
3
IF2
SHIELD
IE
5
7
VE
USE OF A 0.1 µF BYPASS CAPACITOR CONNECTED
BETWEEN PINS 5 AND 8 IS RECOMMENDED (SEE NOTE 16).
6
GND
VO2
VF2
+
4
SHIELD
5
GND
1-167
OPTOCOUPLERS
Selection Guide
HCPL-261A/261N/263A/263N Outline Drawing
Pin Location (for reference only)
9.40 (0.370)
9.90 (0.390)
8
7
6
5
OPTION CODE*
TYPE NUMBER
HP
PIN ONE
2
3
0.20 (0.008)
0.33 (0.013)
7.36 (0.290)
7.88 (0.310)
YYWW
1
6.10 (0.240)
6.60 (0.260)
DATE CODE
XXXXZ
5° TYP.
4
1.78 (0.070) MAX.
1.19 (0.047) MAX.
DIMENSIONS IN MILLIMETERS AND (INCHES).
4.70 (0.185) MAX.
0.51 (0.020) MIN.
* MARKING CODE LETTER FOR OPTION NUMBERS.
"L" = OPTION 020
"V" = OPTION 060
OPTION NUMBERS 300 AND 500 NOT MARKED.
2.92 (0.115) MIN.
0.76 (0.030)
1.40 (0.056)
0.65 (0.025) MAX.
2.28 (0.090)
2.80 (0.110)
Figure 1. 8-Pin Dual In-Line Package Device Outline Drawing.
PIN LOCATION (FOR REFERENCE ONLY)
9.65 ± 0.25
(0.380 ± 0.010)
8
7
6
1.02 (0.040)
1.19 (0.047)
5
4.83 TYP.
(0.190)
6.350 ± 0.25
(0.250 ± 0.010)
1
2
3
9.65 ± 0.25
(0.380 ± 0.010)
4
1.19 (0.05)
1.78 (0.07)
9.65 ± 0.25
(0.380 ± 0.010)
1.780
(0.070)
MAX.
1.19
(0.047)
MAX.
7.62 ± 0.25
(0.300 ± 0.010)
0.20 (0.008)
0.33 (0.013)
4.19 MAX.
(0.165)
1.080 ± 0.320
(0.043 ± 0.013)
2.540
(0.100)
BSC
0.635 ± 0.130
(0.025 ± 0.005)
0.635 ± 0.25
(0.025 ± 0.010)
DIMENSIONS IN MILLIMETERS (INCHES).
TOLERANCES (UNLESS OTHERWISE SPECIFIED): xx.xx = 0.01
xx.xxx = 0.005
LEAD COPLANARITY
MAXIMUM: 0.102 (0.004)
Figure 2. Gull Wing Surface Mount Option #300.
1-168
0.38 (0.015)
0.64 (0.025)
12° NOM.
OPTOCOUPLERS
HCPL-061A/061N/063A/063N Outline Drawing
8
7
6
5
5.842 ± 0.203
(0.236 ± 0.008)
XXX
YWW
3.937 ± 0.127
(0.155 ± 0.005)
TYPE NUMBER (LAST 3 DIGITS)
2
PIN 1
ONE
3
DATE CODE
4
0.381 ± 0.076
(0.016 ± 0.003)
1.270 BSG
(0.050)
45° X 0.432
(0.017)
7°
5.080 ± 0.005
(0.200 ± 0.005)
3.175 ± 0.127
(0.125 ± 0.005)
0.228 ± 0.025
(0.009 ± 0.001)
1.524
(0.060)
0.152 ± 0.051
(0.006 ± 0.002)
0.305
MIN.
(0.012)
DIMENSIONS IN MILLIMETERS AND (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
Figure 3. 8-Pin Small Outline Package Device Drawing.
TEMPERATURE – °C
Solder Reflow Temperature Profile (HCPL-06XX and Gull Wing Surface Mount
Option 300 Parts)
260
240
220
200
180
160
140
120
100
80
60
40
20
0
∆T = 145°C, 1°C/SEC
∆T = 115°C, 0.3°C/SEC
∆T = 100°C, 1.5°C/SEC
0
1
2
3
4
5
6
7
8
9
10
11
12
TIME – MINUTES
Note: Use of Nonchlorine Activated Fluxes is Recommended.
Regulatory Information
The HCPL-261A and HCPL-261N
families have been approved by
the following organizations:
CSA
Approved under CSA Component
Acceptance Notice #5, File CA
88324.
UL
Recognized under UL 1577,
Component Recognition
Program, File E55361.
VDE
Approved according to VDE
0884/06.92. (HCPL-261A/261N
Option 060 only)
1-169
Insulation and Safety Related Specifications
Parameter
Minimum External Air
Gap (External
Clearance)
Minimum External
Tracking (External
Creepage)
Minimum Internal Plastic
Gap (Internal Clearance)
Tracking Resistance
(Comparative Tracking
Index)
Isolation Group
8-Pin DIP
(300 Mil) SO-8
Symbol
Value
Value Units
L(101)
7.1
4.9
mm
L(102)
CTI
7.4
4.8
mm
0.08
0.08
mm
200
200
Volts
IIIa
IIIa
Conditions
Measured from input terminals to
output terminals, shortest distance
through air.
Measured from input terminals to
output terminals, shortest distance
path along body.
Through insulation distance, conductor
to conductor, usually the direct
distance between the photoemitter and
photodetector inside the optocoupler
cavity.
DIN IEC 112/ VDE 0303 Part 1
Material Group (DIN VDE 0110, 1/89,
Table 1)
Option 300 – surface mount classification is Class A in accordance with CECC 00802.
VDE 0884 Insulation Related Characteristics
(HCPL-261A/261N Option 060 ONLY)
Description
Installation classification per DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤ 300 V rms
for rated mains voltage ≤ 450 V rms
Climatic Classification
Pollution Degree (DIN VDE 0110/1.89)
Maximum Working Insulation Voltage
Input to Output Test Voltage, Method b*
VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec,
Partial Discharge < 5 pC
Input to Output Test Voltage, Method a*
VIORM x 1.5 = VPR, Type and sample test, tm = 60 sec,
Partial Discharge < 5 pC
Highest Allowable Overvoltage*
(Transient Overvoltage, tini = 10 sec)
Safety Limiting Values
(Maximum values allowed in the event of a failure,
also see Figure 18, Thermal Derating curve.)
Case Temperature
Input Current
Output Power
Insulation Resistance at TS, VIO = 500 V
Symbol
Characteristic
Units
VIORM
I-IV
I-III
55/85/21
2
630
V peak
VPR
1181
V peak
VPR
945
V peak
VIOTM
6000
V peak
TS
IS,INPUT
PS,OUTPUT
RS
175
230
600
≥ 109
°C
mA
mW
Ω
*Refer to the front of the optocoupler section of the current catalog, under Product Safety Regulations section (VDE 0884), for a
detailed description.
Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in
application.
1-170
Parameter
Storage Temperature
Operating Temperature
Average Input Current
Reverse Input Voltage
Supply Voltage
Enable Input Voltage
Output Collector Current (Each Channel)
Output Power Dissipation (Each Channel)
Output Voltage (Each channel)
Lead Solder Temperature
(Through Hole Parts Only)
Solder Reflow Temperature Profile
(Surface Mount Parts Only)
Symbol
Min.
Max.
Units
TS
-55
125
°C
TA
-40
+85
°C
IF(AVG)
10
mA
VR
3
Volts
VCC
-0.5
7
Volts
VE
-0.5
5.5
Volts
IO
50
mA
PO
60
mW
VO
-0.5
7
Volts
260°C for 10 s, 1.6 mm Below Seating Plane
Note
1
2
3
See Package Outline Drawings section
Recommended Operating Conditions
Parameter
Input Voltage, Low Level
Input Current, High Level
Power Supply Voltage
High Level Enable Voltage
Low Level Enable Voltage
Fan Out (at RL = 1 kΩ)
Output Pull-up Resistor
Operating Temperature
Symbol
VFL
IFH
VCC
VEH
VEL
N
RL
TA
Min.
-3
3.0
4.5
2.0
0
330
-40
Max.
0.8
10
5.5
VCC
0.8
5
4k
85
Units
V
mA
Volts
Volts
Volts
TTL Loads
Ω
°C
1-171
OPTOCOUPLERS
Absolute Maximum Ratings
Electrical Specifications
Over recommended operating temperature (TA = -40°C to +85°C) unless otherwise specified.
Parameter
High Level Output
Current
Low Level Output
Voltage
Symbol
IOH
VOL
0.4
0.6
High Level Supply
Current
ICCH
7
9
10
15
Low Level Supply
Current
ICCL
8
12
13
21
High Level Enable
Current**
Low Level Enable
Current**
Input Forward
Voltage
Temperature Coefficient of Forward
Voltage
Input Reverse
Breakdown Voltage
Input Capacitance
IEH
-0.6
-1.6
IEL
-0.9
-1.6
mA
1.3
1.6
V
VF
Min. Typ.*
3.1
1.0
∆VF /∆TA
BVR
CIN
Max.
100
-1.25
3
Fig. Note
4
18
5, 8
4, 18
4
VCC = 5.5 V, VE = 0.5 V
IF = 4 mA
mV/°C IF = 4 mA
5
V
IR = 100 µA
60
pF
f = 1 MHz, VF = 0 V
*All typical values at TA = 25°C, VCC = 5 V
**Single Channel Products only (HCPL-261A/261N/061A/061N)
***Dual Channel Products only (HCPL-263A/263N/063A/063N)
1-172
Units
Test Conditions
µA
VCC = 5.5 V, VO = 5.5 V,
VF = 0.8 V, VE = 2.0 V
V
VCC = 5.5 V, IOL = 13 mA
(sinking), IF = 3.0 mA,
VE = 2.0 V
mA VE = 0.5 V**
VCC = 5.5 V
IF = 0 mA
Dual Channel
Products***
mA
VE = 0.5 V**
VCC = 5.5 V
IF = 3.0 mA
Dual Channel
Products***
mA VCC = 5.5 V, VE = 2.0 V
6
4
4
4
Over recommended operating temperature (TA = -40°C to +85°C) unless otherwise specified
Parameter
Input Current Threshold
High to Low
Propagation Delay
Time to High Output
Level
Propagation Delay
Time to Low Output
Level
Pulse Width Distortion
Symbol
ITHL
tPLH
tPHL
Min. Typ.* Max. Units
Test Conditions
Fig. Note
1.5
3.0
mA VCC = 5.5 V, VO = 0.6 V, 7, 10 18
IO >13 mA (Sinking)
52
100
ns
IF = 3.5 mA
9, 11, 4, 9,
VCC = 5.0 V,
12
18
VE = Open,
CL = 15 pF,
53
100
ns
9, 11, 4, 10,
RL = 350 Ω
12
18
PWD
|tPHL - tPLH|
Propagation Delay Skew
tPSK
Output Rise Time
tR
Output Fall Time
tF
Propagation Delay
tEHL
Time of Enable
from VEH to VEL
Propagation Delay
tELH
Time of Enable
from VEL to VEH
11
45
ns
9, 13 17, 18
60
42
12
19
ns
ns
ns
ns
24 11, 18
9, 14 4, 18
9, 14 4, 18
15,
12
16
30
ns
IF = 3.5 mA
VCC = 5.0 V,
VEL = 0 V, VEH = 3 V,
CL = 15 pF,
RL = 350 Ω
15,
16
12
*All typical values at TA = 25°C, VCC = 5 V.
Common Mode Transient Immunity Specifications, All values at TA = 25°C
Parameter
Output High
Level Common
Mode Transient
Immunity
Device
Symbol Min.
HCPL-261A |CMH|
1
HCPL-061A
HCPL-263A
HCPL-063A
HCPL-261N
1
HCPL-061N
HCPL-263N
15
HCPL-063N
Output Low
HCPL-261A |CML|
1
Level Common HCPL-061A
Mode Transient HCPL-263A
Immunity
HCPL-063A
HCPL-261N
1
HCPL-061N
HCPL-263N
15
HCPL-063N
Typ. Max. Units
Test Conditions
5
kV/µs VCM = 50 V
VCC = 5.0 V,
RL = 350 Ω,
IF = 0 mA,
TA = 25°C
5
kV/µs VCM = 1000 V VO(MIN) = 2 V
25
4, 13,
15
17 4, 14,
15, 18
5
Using HP App
Circuit
kV/µs VCM = 50 V
VCC = 5.0 V,
RL = 350 Ω,
IF = 3.5 mA,
VO(MAX) = 0.8 V
kV/µs VCM = 1000 V TA = 25°C
25
kV/µs
20
5
kV/µs
Fig. Note
17 4, 13,
15, 18
Using HP App
Circuit
20
4, 14,
15
1-173
OPTOCOUPLERS
Switching Specifications
Package Characteristics
All Typicals at TA = 25°C
Parameter
Input-Output
Momentary Withstand Voltage**
Input-Output
Resistance
Input-Output
Capacitance
Input-Input
Insulation
Leakage Current
Resistance
(Input-Input)
Capacitance
(Input-Input)
Sym.
VISO
Package*
Min.
2500
OPT 020†
5000
Typ.
Max.
Units
V rms
RI-O
1012
Ω
CI-O
0.6
pF
II-I
Dual Channel
0.005
µA
RI-I
Dual Channel
1011
Ω
CI-I
Dual 8-pin DIP
Dual SO-8
0.03
0.25
pF
Test Conditions
RH ≤ 50%,
t = 1 min.,
TA = 25°C
VI-O = 500 Vdc
f = 1 MHz,
TA = 25°C
RH ≤ 45%,
t = 5 s,
VI-I = 500 V
Fig.
Note
5, 6
5, 7
4, 8
4, 8
19
19
f = 1 MHz
19
*Ratings apply to all devices except otherwise noted in the Package column.
**The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output
continuous voltage rating. For the continuous voltage rating refer to the VDE 0884 Insulation Characteristics Table (if applicable),
your equipment level safety specification or HP Application Note 1074 entitled “Optocoupler Input-Output Endurance Voltage.”
†For 8-pin DIP package devices (HCPL-261A/261N/263A/263N) only.
Notes:
1. Peaking circuits may be used which
produce transient input currents up
to 30 mA, 50 ns maximum pulse
width, provided the average current
does not exceed 10 mA.
2. 1 minute maximum.
3. Derate linearly above 80°C free-air
temperature at a rate of 2.7 mW/°C
for the SOIC-8 package.
4. Each channel.
5. Device considered a two-terminal
device: Pins 1, 2, 3, and 4 shorted
together and Pins 5, 6, 7, and 8
shorted together.
6. In accordance with UL1577, each
optocoupler is proof tested by
applying an insulation test voltage
≥ 3000 VRMS for 1 second (leakage
detection current limit, II-O ≤ 5 µA).
This test is performed before the
100% production test for partial
discharge (method b) shown in the
VDE 0884 Insulation Characteristics
Table, if applicable.
7. In accordance with UL1577, each
optocoupler is proof tested by
applying an insulation test voltage
≥ 6000 VRMS for 1 second (leakage
detection current limit, II-O ≤ 5 µA).
1-174
8. Measured between the LED anode and
cathode shorted together and pins 5
through 8 shorted together.
9. The tPLH propagation delay is
measured from the 1.75 mA point on
the falling edge of the input pulse to
the 1.5 V point on the rising edge of
the output pulse.
10. The tPHL propagation delay is
measured from the 1.75 mA point on
the rising edge of the input pulse to
the 1.5 V point on the falling edge of
the output pulse.
11. Propagation delay skew (tPSK) is
equal to the worst case difference in
tPLH and/or tPHL that will be seen
between any two units under the
same test conditions and operating
temperature.
12. Single channel products only (HCPL261A/261N/061A/061N).
13. Common mode transient immunity in
a Logic High level is the maximum
tolerable |dVCM/dt| of the common
mode pulse, VCM, to assure that the
output will remain in a Logic High
state (i.e., Vo > 2.0 V).
14. Common mode transient immunity in
a Logic Low level is the maximum
tolerable |dVCM/dt| of the common
mode pulse, VCM, to assure that the
output will remain in a Logic Low
state (i.e., VO < 0.8 V).
15. For sinusoidal voltages
(|dVCM /dt|)max = πfCM VCM(P-P).
16. Bypassing of the power supply line is
required with a 0.1 µF ceramic disc
capacitor adjacent to each optocoupler as shown in Figure 19. Total lead
length between both ends of the
capacitor and the isolator pins should
not exceed 10 mm.
17. Pulse Width Distortion (PWD) is
defined as the difference between
tPLH and tPHL for any given device.
18. No external pull up is required for a
high logic state on the enable input of
a single channel product. If the VE pin
is not used, tying VE to VCC will result
in improved CMR performance.
19. Measured between pins 1 and 2
shorted together, and pins 3 and 4
shorted together. For dual channel
parts only.
10
5
0
-60 -40 -20
20
0
40
60
80 100
80
100.0
VCC = 5 V
VE = 2 V
VOL = 0.6 V
IF = 3.5 mA
60
40
20
0
-60 -40 -20
TA – TEMPERATURE – °C
20
0
40
60
80 100
TA – TEMPERATURE – °C
Figure 4. Typical High Level Output
Current vs. Temperature.
OPTOCOUPLERS
VCC = 5.5 V
VO = 5.5 V
VE = 2 V
VF = 0.8 V
IF – INPUT FORWARD CURRENT – mA
IOL – LOW LEVEL OUTPUT CURRENT – mA
IOH – HIGH LEVEL OUTPUT CURRENT – µA
15
10.0
TA = 85 °C
TA = 40 °C
1.0
TA = 25 °C
0.1
0.01
1.0
IF
+
VF
–
1.1
1.3
1.2
1.4
1.5
VF – FORWARD VOLTAGE – V
Figure 5. Low Level Output Current
vs. Temperature.
Figure 6. Typical Diode Input
Forward Current Characteristic.
VOL – LOW LEVEL OUTPUT VOLTAGE – V
HCPL-261A fig 5
VO – OUTPUT VOLTAGE – V
5.0
4.0
RL = 350 Ω
3.0
RL = 1 kΩ
2.0
RL = 4 kΩ
1.0
0
0
0.5
1.0
1.5
2.0
0.6
VCC = 5.5 V
VE = 2 V
IF = 3.0 mA
0.5
IO = 16 mA
IO = 12.8 mA
0.4
0.3
IO = 9.6 mA
IO = 6.4 mA
0.2
-60 -40 -20 0 20 40
Figure 7. Typical Output Voltage vs.
Forward Input Current.
IF
INPUT
MONITORING
NODE
+5 V
1
VCC 8
2
7
3
6
4
5
0.1 µF
BYPASS
RL
*CL
RM
80 100
Figure 8. Typical Low Level Output
Voltage vs. Temperature.
HCPL-261A/261N
PULSE GEN.
Z O = 50 Ω
t f = t r = 5 ns
60
TA – TEMPERATURE – °C
IF – FORWARD INPUT CURRENT – mA
GND
OUTPUT VO
MONITORING
NODE
*CL IS APPROXIMATELY 15 pF WHICH INCLUDES
PROBE AND STRAY WIRING CAPACITANCE.
I F = 3.5 mA
INPUT
IF
90%
90%
VOH
I F = 1.75 mA
t PHL
OUTPUT
VO
10%
10%
t PLH
VOL
1.5 V
trise
tfall
Figure 9. Test Circuit for tPHL and tPLH.
1-175
RL = 350 Ω
RL = 1 kΩ
1.0
RL = 4 kΩ
0.5
VCC = 5 V
VO = 0.6 V
0
-60 -40 -20
0
20
40
60
100
80
60
20
PWD – ns
30
20
RL = 1 kΩ
RL = 350 Ω
20
40
60
TA – TEMPERATURE – °C
Figure 13. Typical Pulse Width
Distortion vs. Temperature.
1-176
80 100
tr, tf – RISE, FALL TIME – ns
VCC = 5 V
IF = 3.5 mA
0
0
VCC = 5 V
IF = 3.5 mA
20
40
60
80 100
Figure 11. Typical Propagation Delay
vs. Temperature.
160
RL = 4 kΩ
0
-60 -40 -20
TPLH
RL = 350 k
TA – TEMPERATURE – °C
60
10
TPHL
RL = 350 Ω, 1 kΩ, 4 kΩ
0
-60 -40 -20
80 100
Figure 10. Typical Input Threshold
Current vs. Temperature.
40
TPLH
RL = 1 k
40
TA – TEMPERATURE – °C
50
120
TPLH
RL = 4 k
140
VCC = 5 V
IF = 3.5 mA
trise
tfall
RL = 4 kΩ
120
60
RL = 1 kΩ
40
RL = 350 Ω
20
0
-60 -40 -20
RL = 350 Ω, 1 kΩ, 4 kΩ
0 20 40 60 80 100
TA – TEMPERATURE – °C
Figure 14. Typical Rise and Fall Time
vs. Temperature.
tp – PROPAGATION DELAY – ns
1.5
tp – PROPAGATION DELAY – ns
ITH – INPUT THRESHOLD CURRENT – mA
120
2.0
100
TPLH
RL = 4 kΩ
80
TPLH
RL = 1 kΩ
60
TPLH
RL = 350 Ω
TPHL
RL = 350 Ω, 1 kΩ, 4 kΩ
40
20
0
VCC = 5 V
TA = 25 °C
0
2
4
6
8
10
12
IF – PULSE INPUT CURRENT – mA
Figure 12. Typical Propagation Delay
vs. Pulse Input Current.
HCPL-261A/261N
1
3.5 mA
IF
+5 V
VCC 8
2
7
3
6
0.1 µF
BYPASS
RL
OUTPUT VO
MONITORING
NODE
*C L
4
GND
5
120
90
OPTOCOUPLERS
INPUT VE
MONITORING NODE
tE – ENABLE PROPAGATION DELAY – ns
PULSE GEN.
Z O = 50 Ω
t f = t r = 5 ns
VCC = 5 V
VEH = 3 V
VEL = 0 V
IF = 3.5 mA
tELH, RL = 4 kΩ
60
tELH, RL = 1 kΩ
tELH, RL = 350 Ω
30
tEHL, RL = 350 Ω, 1k Ω, 4 kΩ
0
-60 -40 -20 0 20 40 60 80 100
TA – TEMPERATURE – °C
Figure 16. Typical Enable Propagation Delay vs. Temperature. HCPL261A/-261N/-061A/-061N Only.
*CL IS APPROXIMATELY 15 pF WHICH INCLUDES
PROBE AND STRAY WIRING CAPACITANCE.
3.0 V
INPUT
VE
1.5 V
t EHL
t ELH
OUTPUT
VO
1.5 V
HCPL-261A/261N
VCC 8
1
V CM
2
7
IF
A
B
VFF
3
6
4
GND 5
+5 V
0.1 µF
BYPASS
350 Ω
OUTPUT VO
MONITORING
NODE
OUTPUT POWER – PS, INPUT CURRENT – IS
Figure 15. Test Circuit for tEHL and tELH.
800
HCPL-261A/261N OPTION 060 ONLY
PS (mW)
700
IS (mA)
600
500
400
300
200
100
0
0
25
50
75 100 125 150 175 200
TS – CASE TEMPERATURE – °C
PULSE GEN.
Z O = 50 Ω
+
_
Figure 18. Thermal Derating Curve,
Dependence of Safety Limiting Value
with Case Temperature per
VDE 0884.
VCM (PEAK)
VCM
VO
0V
5V
SWITCH AT A: IF = 0 mA
CM H
VO (min.)
SWITCH AT B: IF = 3.5 mA
VO
VO (max.)
0.5 V
CM L
Figure 17. Test Circuit for Common Mode Transient Immunity and
Typical Waveforms.
1-177
Application Information
SINGLE CHANNEL PRODUCTS
Common-Mode Rejection for
HCPL-261A/HCPL-261N
Families:
Figure 20 shows the recommended drive circuit for the
HCPL-261N/-261A for optimal
common-mode rejection
performance. Two main points to
note are:
1. The enable pin is tied to VCC
rather than floating (this
applies to single-channel parts
only).
2. Two LED-current setting
resistors are used instead of
one. This is to balance ILED
variation during commonmode transients.
GND BUS (BACK)
VCC BUS (FRONT)
N.C.
ENABLE
(IF USED)
0.1µF
OUTPUT 1
N.C.
N.C.
ENABLE
(IF USED)
0.1µF
N.C.
OUTPUT 2
10 mm MAX. (SEE NOTE 16)
DUAL CHANNEL PRODUCTS
GND BUS (BACK)
VCC BUS (FRONT)
OUTPUT 1
0.1µF
OUTPUT 2
10 mm MAX. (SEE NOTE 16)
Figure 19. Recommended Printed Circuit Board Layout.
*
HCPL-261A/261N
1
VCC
357 Ω
(MAX.)
357 Ω
(MAX.)
74LS04
OR ANY TOTEM-POLE
OUTPUT LOGIC GATE
8
VCC+
0.01 µF
350 Ω
2
7
3
6
VO
5
GND
4
SHIELD
*
GND1
GND2
* HIGHER CMR MAY BE OBTAINABLE BY CONNECTING PINS 1, 4 TO INPUT GROUND (GND1).
Figure 20. Recommended Drive Circuit for HCPL-261A/-261N Families for HighCMR (Similar for HCPL-263A/-263N).
*Higher CMR May Be Obtainable by Connecting Pins 1, 4 to Input Ground (Gnd1).
1-178
If the enable pin is left floating, it
is possible for common-mode
transients to couple to the enable
pin, resulting in common-mode
failure. This failure mechanism
only occurs when the LED is on
and the output is in the Low
State. It is identified as occurring
when the transient output voltage
rises above 0.8 V. Therefore, the
enable pin should be connected
to either VCC or logic-level high
for best common-mode
performance with the output low
(CMRL ). This failure mechanism
is only present in single-channel
parts (HCPL-261N, -261A,
-061N, -061A) which have the
enable function.
Also, common-mode transients
can capacitively couple from the
LED anode (or cathode) to the
output-side ground causing
current to be shunted away from
the LED (which can be bad if the
LED is on) or conversely cause
current to be injected into the
LED (bad if the LED is meant to
be off). Figure 21 shows the
parasitic capacitances which
exists between LED
For transients occurring when the
LED is on, common-mode rejection (CMRL, since the output is in
the “low” state) depends upon the
amount of LED current drive (IF).
For conditions where IF is close
to the switching threshold (ITH),
CMRL also depends on the extent
which ILP and ILN balance each
other. In other words, any
condition where common-mode
transients cause a momentary
decrease in IF (i.e. when
dVCM /dt>0 and |IFP| > |IFN|,
referring to Table 1) will cause
common-mode failure for
transients which are fast enough.
CMR with Other Drive
Circuits
CMR performance with drive
circuits other than that shown in
Figure 20 may be enhanced by
following these guidelines:
1. Use of drive circuits where
current is shunted from the
LED in the LED “off” state (as
shown in Figures 22 and 23).
This is beneficial for good
CMRH.
2. Use of IFH > 3.5 mA. This is
good for high CMRL.
Using any one of the drive
circuits in Figures 22-24 with
IF = 10 mA will result in a typical
CMR of 8 kV/µs for the HCPL261N family, as long as the PC
board layout practices are
followed. Figure 22 shows a
1
8
2
7
1/2 RLED
Likewise for common-mode
transients which occur when the
LED is off (i.e. CMRH, since the
output is “high”), if an imbalance
between ILP and ILN results in a
transient IF equal to or greater
than the switching threshold of
the optocoupler, the transient
“signal” may cause the output to
spike below 2 V (which constitutes a CMRH failure).
circuit which can be used with
any totem-pole-output TTL/
LSTTL/HCMOS logic gate. The
buffer PNP transistor allows the
circuit to be used with logic
devices which have low currentsinking capability. It also helps
maintain the driving-gate powersupply current at a constant level
to minimize ground shifting for
other devices connected to the
input-supply ground.
When using an open-collector
TTL or open-drain CMOS logic
gate, the circuit in Figure 23 may
be used. When using a CMOS
gate to drive the optocoupler, the
circuit shown in Figure 24 may
be used. The diode in parallel
with the RLED speeds the turn-off
of the optocoupler LED.
VCC+
0.01 µF
350 Ω
ILP
1/2 RLED
3
CLA
ILN
6
VO
15 pF
CLC
4
5
GND
SHIELD
+
–
VCM
Figure 21. AC Equivalent Circuit for HCPL-261X.
VCC
By using the recommended
circuit in Figure 20, good CMR
can be achieved. (In the case of
the -261N families, a minimum
CMR of 15 kV/µs is guaranteed
using this circuit.) The balanced
ILED-setting resistors help equalize
ILP and ILN to reduce the amount
by which ILED is modulated from
transient coupling through CLA
and CLC.
HCPL-261X
420 Ω
(MAX)
74L504
(ANY
TTL/CMOS
GATE)
2N3906
(ANY PNP)
1
2
LED
3
4
Figure 22. TTL Interface Circuit for the HCPL-261A/261N Families.
1-179
OPTOCOUPLERS
anode/cathode and output ground
(CLA and CLC). Also shown in
Figure 21 on the input side is an
AC-equivalent circuit. Table 1
indicates the directions of ILP and
ILN flow depending on the
direction of the common-mode
transient.
VCC
VCC
HCPL-261X
820 Ω
1
2
74HC00
(OR ANY
OPEN-COLLECTOR/
OPEN-DRAIN
LOGIC GATE)
HCPL-261A/261N
1
1N4148
LED
3
2
750 Ω
74HC04
(OR ANY
TOTEM-POLE
OUTPUT LOGIC
GATE)
LED
3
4
4
Figure 23. TTL Open-Collector/Open Drain Gate Drive Circuit
for HCPL-261A/-261N Families.
Figure 24. CMOS Gate Drive Circuit for HCPL-261A/261N Families.
Table 1. Effects of Common Mode Pulse Direction on Transient ILED
If dVCM/dt Is:
positive (>0)
negative (<0)
then ILP Flows:
away from LED
anode through CLA
toward LED
anode through CLA
Propagation Delay, PulseWidth Distortion and
Propagation Delay Skew
Propagation delay is a figure of
merit which describes how
quickly a logic signal propagates
through a system. The propagation delay from low to high (tPLH)
is the amount of time required for
an input signal to propagate to
the output, causing the output to
change from low to high.
Similarly, the propagation delay
from high to low (tPHL) is the
amount of time required for the
input signal to propagate to the
output, causing the output to
change from high to low (see
Figure 9).
Pulse-width distortion (PWD)
results when tPLH and tPHL differ
in value. PWD is defined as the
difference between tPLH and tPHL
and often determines the
1-180
and ILN Flows:
away from LED
cathode through CLC
toward LED
cathode through CLC
If |ILP| < |ILN|,
LED IF Current
Is Momentarily:
increased
If |ILP| > |ILN|,
LED IF Current
Is Momentarily:
decreased
decreased
increased
maximum data rate capability of
a transmission system. PWD can
be expressed in percent by
dividing the PWD (in ns) by the
minimum pulse width (in ns)
being transmitted. Typically,
PWD on the order of 20-30% of
the minimum pulse width is
tolerable; the exact figure
depends on the particular application (RS232, RS422, T-1, etc.).
Propagation delay skew, tPSK, is
an important parameter to consider in parallel data applications
where synchronization of signals
on parallel data lines is a concern. If the parallel data is being
sent through a group of optocouplers, differences in propagation delays will cause the data to
arrive at the outputs of the optocouplers at different times. If this
difference in propagation delay is
large enough it will determine the
maximum rate at which parallel
data can be sent through the
optocouplers.
Propagation delay skew is defined
as the difference between the
minimum and maximum propagation delays, either tPLH or tPHL, for
any given group of optocouplers
which are operating under the
same conditions (i.e., the same
drive current, supply voltage,
output load, and operating
temperature). As illustrated in
Figure 25, if the inputs of a group
of optocouplers are switched
either ON or OFF at the same
time, tPSK is the difference
between the shortest propagation
delay, either tPLH or tPHL, and the
longest propagation delay, either
tPLH or tPHL.
As mentioned earlier, tPSK can
determine the maximum parallel
Propagation delay skew represents the uncertainty of where an
edge might be after being sent
through an optocoupler. Figure
26 shows that there will be
uncertainty in both the data and
the clock lines. It is important
that these two areas of uncertainty not overlap, otherwise the
clock signal might arrive before
all of the data outputs have
settled, or some of the data
outputs may start to change
before the clock signal has
arrived. From these considerations, the absolute minimum
pulse width that can be sent
through optocouplers in a parallel
application is twice tPSK. A
cautious design should use a
slightly longer pulse width to
ensure that any additional
uncertainty in the rest of the
circuit does not cause a problem.
IF
OPTOCOUPLERS
data transmission rate. Figure 26
is the timing diagram of a typical
parallel data application with both
the clock and the data lines being
sent through optocouplers. The
figure shows data and clock
signals at the inputs and outputs
of the optocouplers. To obtain the
maximum data transmission rate,
both edges of the clock signal are
being used to clock the data; if
only one edge were used, the
clock signal would need to be
twice as fast.
50%
1.5 V
VO
TPHL
IF
50%
TPLH
VO
1.5 V
t PSK
Figure 25. Illustration of Propagation Delay Skew – tPSK.
DATA
INPUTS
CLOCK
DATA
OUTPUTS
t PSK
CLOCK
t PSK
Figure 26. Parallel Data Transmission Example.
The tPSK specified optocouplers
offer the advantages of guaranteed specifications for propagation delays, pulse-width
distortion, and propagation delay
skew over the recommended
temperature, input current, and
power supply ranges.
1-181