CSD19533Q5A www.ti.com SLPS486 – DECEMBER 2013 100 V N-Channel NexFET™ Power MOSFETs Check for Samples: CSD19533Q5A FEATURES 1 • • • • • • • 2 PRODUCT SUMMARY Ultra-Low Qg and Qgd Low Thermal Resistance Avalanche Rated Pb-Free Terminal Plating RoHS Compliant Halogen Free SON 5-mm × 6-mm Plastic Package TA = 25°C UNIT Drain-to-Source Voltage 100 V Qg Gate Charge Total (10 V) 27 nC Qgd Gate Charge Gate to Drain RDS(on) Drain-to-Source On Resistance VGS(th) Threshold Voltage 4.9 nC VGS = 6 V 8.7 mΩ VGS = 10 V 7.8 mΩ 2.8 V ORDERING INFORMATION APPLICATIONS • • • TYPICAL VALUE VDS Primary Side Telecom Secondary Side Synchronous Rectifier Motor Control Device Package Media Qty Ship CSD19533Q5A SON 5-mm × 6-mm Plastic Package 13-Inch Reel 2500 Tape and Reel ABSOLUTE MAXIMUM RATINGS DESCRIPTION TA = 25°C VALUE UNIT This 100 V, 7.8 mΩ, SON 5 mm x 6 mm NexFET™ power MOSFET is designed to minimize losses in power conversion applications. VDS Drain-to-Source Voltage 100 V VGS Gate-to-Source Voltage ±20 V Continuous Drain Current (Package limited) 100 Continuous Drain Current (Silicon limited), TC = 25°C 75 Continuous Drain Current, TA = 25 °C(1) 13 ID Top View S S S 8 1 7 2 6 3 D D IDM Pulsed Drain Current, TA = 25 °C(2) 80 A PD Power Dissipation(1) 3.2 W TJ, TSTG Operating Junction and Storage Temperature Range –55 to 150 °C EAS Avalanche Energy, single pulse ID = 46 A, L = 0.1 mH, RG = 25 Ω 106 mJ D D G 5 4 D (1) Typical RθJA = 40 °C/W on a 1-inch2, 2-oz. Cu pad on a 0.06inch thick FR4 PCB. (2) Pulse duration ≤ 300 μs, duty cycle ≤ 1% P0093-01 RDS(on) vs VGS GATE CHARGE 10 TC = 25°C, I D = 13A TC = 125°C, I D = 13A 27 VGS - Gate-to-Source Voltage (V) RDS(on) - On-State Resistance (mΩ) 30 24 21 18 15 12 9 6 3 0 0 2 4 A 6 8 10 12 14 16 VGS - Gate-to- Source Voltage (V) 18 20 G001 ID = 13A VDS = 50V 9 8 7 6 5 4 3 2 1 0 0 3 6 9 12 15 18 21 Qg - Gate Charge (nC) 24 27 30 G001 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NexFET is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2013, Texas Instruments Incorporated CSD19533Q5A SLPS486 – DECEMBER 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise stated) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Static Characteristics BVDSS Drain-to-Source Voltage VGS = 0 V, ID = 250 μA IDSS Drain-to-Source Leakage Current VGS = 0 V, VDS = 80 V IGSS Gate-to-Source Leakage Current VDS = 0 V, VGS = 20 V VGS(th) Gate-to-Source Threshold Voltage VDS = VGS, ID = 250 μA RDS(on) Drain-to-Source On Resistance gfs Transconductance 100 2.2 V 1 μA 100 nA 2.8 3.4 V VGS = 6 V, ID = 13 A 8.7 11.1 mΩ VGS = 10 V, ID = 13 A 7.8 9.4 mΩ VDS = 10 V, ID = 13 A 63 S Dynamic Characteristics Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance RG Series Gate Resistance Qg Qgd Qgs Gate Charge Gate to Source Qg(th) Gate Charge at Vth Qoss Output Charge td(on) 2050 2670 pF 395 514 pF 9.6 12.5 pF 1.2 2.4 Ω Gate Charge Total (10 V) 27 35 nC Gate Charge Gate to Drain 4.9 nC 7.9 nC 5.7 nC 75 nC Turn On Delay Time 6 ns tr Rise Time 6 ns td(off) Turn Off Delay Time 16 ns tf Fall Time 5 ns VGS = 0 V, VDS = 50 V, f = 1 MHz VDS = 50 V, ID = 13 A VDS = 50 V, VGS = 0 V VDS = 50 V, VGS = 10 V, IDS = 13 A, RG = 0 Ω Diode Characteristics VSD Diode Forward Voltage ISD = 13 A, VGS = 0 V 0.8 Qrr Reverse Recovery Charge 163 nC trr Reverse Recovery Time VDS= 50 V, IF = 13 A, di/dt = 300 A/μs 1.0 V 62 ns THERMAL CHARACTERISTICS (TA = 25°C unless otherwise stated) MAX UNIT RθJC Thermal Resistance Junction to Case (1) PARAMETER 1.3 °C/W RθJA Thermal Resistance Junction to Ambient (1) (2) 50 °C/W (1) (2) 2 MIN TYP RθJC is determined with the device mounted on a 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu pad on a 1.5-inch × 1.5-inch (3.81-cm × 3.81-cm), 0.06-inch (1.52-mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the user’s board design. Device mounted on FR4 material with 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: CSD19533Q5A CSD19533Q5A www.ti.com GATE SLPS486 – DECEMBER 2013 GATE Source N-Chan 5x6 QFN TTA MIN Rev3 N-Chan 5x6 QFN TTA MAX Rev3 Max RθJA = 50°C/W when mounted on 1 inch2 (6.45 cm2) of 2-oz. (0.071-mm thick) Cu. Source Max RθJA = 115°C/W when mounted on a minimum pad area of 2-oz. (0.071-mm thick) Cu. DRAIN DRAIN M0137-02 M0137-01 TYPICAL MOSFET CHARACTERISTICS (TA = 25°C unless otherwise stated) Figure 1. Transient Thermal Impedance Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: CSD19533Q5A 3 CSD19533Q5A SLPS486 – DECEMBER 2013 www.ti.com TYPICAL MOSFET CHARACTERISTICS (continued) (TA = 25°C unless otherwise stated) TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 120 180 IDS - Drain-to-Source Current (A) IDS - Drain-to-Source Current (A) 200 160 140 120 100 80 60 VGS =10V VGS =8V VGS =6V 40 20 0 0 0.5 1 1.5 2 2.5 3 3.5 4 VDS - Drain-to-Source Voltage (V) 4.5 VDS = 5V 100 80 60 40 0 5 TC = 125°C TC = 25°C TC = −55°C 20 0 1 Figure 2. Saturation Characteristics TEXT ADDED FOR SPACING G001 TEXT ADDED FOR SPACING Ciss = Cgd + Cgs Coss = Cds + Cgd Crss = Cgd ID = 13A VDS = 50V C − Capacitance (pF) 8 7 6 5 4 3 10000 1000 100 2 10 1 0 3 6 9 12 15 18 21 Qg - Gate Charge (nC) 24 27 1 30 0 10 20 G001 Figure 4. Gate Charge 30 40 50 60 70 80 VDS - Drain-to-Source Voltage (V) 90 100 G001 Figure 5. Capacitance TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 3.4 30 ID = 250uA 3.2 RDS(on) - On-State Resistance (mΩ) VGS(th) - Threshold Voltage (V) 6 100000 9 0 3 2.8 2.6 2.4 2.2 2 1.8 1.6 −75 −25 25 75 125 TC - Case Temperature (ºC) Figure 6. Threshold Voltage vs. Temperature 4 5 Figure 3. Transfer Characteristics 10 VGS - Gate-to-Source Voltage (V) 2 3 4 VGS - Gate-to-Source Voltage (V) G001 175 TC = 25°C, I D = 13A TC = 125°C, I D = 13A 27 24 21 18 15 12 9 6 3 0 0 2 G001 4 6 8 10 12 14 16 VGS - Gate-to- Source Voltage (V) 18 20 G001 Figure 7. On-State Resistance vs. Gate-to-Source Voltage Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: CSD19533Q5A CSD19533Q5A www.ti.com SLPS486 – DECEMBER 2013 TYPICAL MOSFET CHARACTERISTICS (continued) (TA = 25°C unless otherwise stated) TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 2 100 VGS = 6V VGS = 10V ISD − Source-to-Drain Current (A) Normalized On-State Resistance 2.2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 −75 TC = 25°C TC = 125°C 10 1 0.1 0.01 0.001 ID = 13A −25 25 75 125 TC - Case Temperature (ºC) 175 0.0001 0 0.2 0.4 0.6 0.8 VSD − Source-to-Drain Voltage (V) G001 Figure 8. Normalized On-State Resistance vs. Temperature TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 10us 100us 1ms 10ms DC TC = 25ºC TC = 125ºC IAV - Peak Avalanche Current (A) IDS - Drain-to-Source Current (A) 100 100 10 1 Single Pulse Max RthetaJC = 0.8ºC/W 0.1 0.1 G001 Figure 9. Typical Diode Forward Voltage 5000 1000 1 1 10 100 VDS - Drain-to-Source Voltage (V) 1000 10 0.01 0.1 TAV - Time in Avalanche (mS) G001 Figure 10. Maximum Safe Operating Area 1 G001 Figure 11. Single Pulse Unclamped Inductive Switching TEXT ADDED FOR SPACING IDS - Drain- to- Source Current (A) 100 90 80 70 60 50 40 30 20 10 0 −50 −25 0 25 50 75 100 125 TC - Case Temperature (ºC) 150 175 G001 Figure 12. Maximum Drain Current vs. Temperature Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: CSD19533Q5A 5 CSD19533Q5A SLPS486 – DECEMBER 2013 www.ti.com MECHANICAL DATA 2 3 4 5 4 5 6 3 6 7 2 7 1 8 1 DIM 6 8 Q5A Package Dimensions MILLIMETERS MIN NOM MAX A 0.90 1.00 1.10 b 0.33 0.41 0.51 c 0.20 0.25 0.34 D1 4.80 4.90 5.00 D2 3.61 3.81 4.02 E 5.90 6.00 6.10 E1 5.70 5.75 5.80 E2 3.38 3.58 3.78 E3 3.03 3.13 3.23 e 1.17 1.27 1.37 e1 0.27 0.37 0.47 e2 0.15 0.25 0.35 H 0.41 0.56 0.71 K 1.10 L 0.51 0.61 0.71 L1 0.06 0.13 0.20 θ 0° Submit Documentation Feedback 12° Copyright © 2013, Texas Instruments Incorporated Product Folder Links: CSD19533Q5A CSD19533Q5A www.ti.com SLPS486 – DECEMBER 2013 Recommended PCB Pattern MILLIMETERS DIM MAX MIN MAX F1 6.205 6.305 0.244 0.248 F2 4.46 4.56 0.176 0.18 F3 4.46 4.56 0.176 0.18 F4 0.65 0.7 0.026 0.028 F5 0.62 0.67 0.024 0.026 F6 0.63 0.68 0.025 0.027 F7 0.7 0.8 0.028 0.031 F8 0.65 0.7 0.026 0.028 F9 0.62 0.67 0.024 0.026 F10 4.9 5 0.193 0.197 F11 4.46 4.56 0.176 0.18 F1 F7 8 F3 1 F2 F11 F5 F9 5 4 F6 INCHES MIN F8 F4 F10 M0139-01 For recommended circuit layout for PCB designs, see application note SLPA005 – Reducing Ringing Through PCB Layout Techniques. Recommended Stencil Opening (0.020) 8x 0.500 (0.020) 0.500 5 4 0.500 (0.020) 8x 1.585 (0.062) 1.235 (0.049) (0.024) 0.620 (0.170) 4.310 0.385 (0.015) 1.270 (0.050) 1 8 1.570 (0.062) 4x 0.615 (0.024) 1.105 (0.044) 3.020 (0.119) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: CSD19533Q5A 7 CSD19533Q5A SLPS486 – DECEMBER 2013 www.ti.com K0 4.00 ±0.10 (See Note 1) 0.30 ±0.05 2.00 ±0.05 +0.10 –0.00 12.00 ±0.30 Ø 1.50 1.75 ±0.10 Q5A Tape and Reel Information 5.50 ±0.05 B0 R 0.30 MAX A0 8.00 ±0.10 Ø 1.50 MIN A0 = 6.50 ±0.10 B0 = 5.30 ±0.10 K0 = 1.40 ±0.10 R 0.30 TYP M0138-01 Notes: 1. 10-sprocket hole-pitch cumulative tolerance ±0.2 2. Camber not to exceed 1 mm in 100 mm, noncumulative over 250 mm 3. Material: black static-dissipative polystyrene 4. All dimensions are in mm (unless otherwise specified) 5. A0 and B0 measured on a plane 0.3 mm above the bottom of the pocket 8 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: CSD19533Q5A PACKAGE OPTION ADDENDUM www.ti.com 5-Feb-2014 PACKAGING INFORMATION Orderable Device Status (1) CSD19533Q5A ACTIVE Package Type Package Pins Package Drawing Qty SON DQJ 8 2500 Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Pb-Free (RoHS Exempt) CU SN Level-1-260C-UNLIM Op Temp (°C) Device Marking (4/5) -55 to 150 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. 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Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 5-Feb-2014 Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 18-Dec-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device CSD19533Q5A Package Package Pins Type Drawing SON DQJ 8 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 6.3 B0 (mm) K0 (mm) P1 (mm) 5.3 1.2 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 18-Dec-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CSD19533Q5A SON DQJ 8 2500 340.0 340.0 38.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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