Renesas HA16116FPJ Switching regulator for chopper type dc/dc converter Datasheet

HA16116FP/FPJ, HA16121FP/FPJ
Switching Regulator for Chopper Type DC/DC Converter
REJ03F0056-0200Z
(Previous: ADE-204-019A)
Rev.2.0
Sep.18.2003
Description
HA16116FP/FPJ and HA16121FP/FPJ are dual-channel PWM switching regulator controller ICs for use in
chopper-type DC/DC converters.
This IC series incorporates totem pole gate drive circuits to allow direct driving of a power MOS FET. The
output logic is preset for booster, step-down, or inverting control in a DC/DC converter. This logic
assumes use of an N-channel power MOS FET for booster control, and a P-channel power MOS FET for
step-down or inverting control.
HA16116 includes a built-in logic circuit for step-down control only, and one for use in both step-down and
inverting control. HA16121 has a logic circuit for booster control only and one for both step-down and
inverting control.
Both ICs have a pulse-by-pulse current limiter, which limits PWM pulse width per pulse as a means of
protecting against overcurrent, and which uses an on/off timer for intermittent operation. Unlike
conventional methods that use a latch timer for shutdown, when the pulse-by-pulse current limiter
continues operation beyond the time set in the timer, the IC is made to operate intermittently (flickering
operation), resulting in sharp vertical setting characteristics. When the overcurrent condition subsides, the
output is automatically restored to normal.
The dual control circuits in the IC output identical triangle waveforms, for completely synchronous
configuring a compact, high efficiency dual-channel DC/DC converter, with fewer external components
than were necessary previously.
Functions
• 2.5 V reference voltage (Vref) regulator
• Triangle wave form oscillator
• Dual overcurrent detector
• Dual totem pole output driver
• UVL (under voltage lock out) system
• Dual error amplifier
• Vref overvoltage detector
• Dual PWM comparator
Rev.2.0, Sep.18.2003, page 1 of 33
HA16116FP/FPJ, HA16121FP/FPJ
Features
• Wide operating supply voltage range* (3.9 V to 40.0 V)
• Wide operating frequency range (600 kHz maximum operation)
• Direct power MOS FET driving (output current ±1 A peak in maximum rating)
• Pulse-by-pulse overcurrent protection circuit with intermittent operation function (When overcurrent
state continues beyond time set in timer, the IC operates intermittently to prevent excessive output
current.)
• Grounding the ON/OFF pin turns the IC off, saving power dissipation. (HA16116: IOFF = 10 µA max.;
HA16121: IOFF = 150 µA max.)
• Built-in UVL circuit (UVL voltage can be varied with external resistance.)
• Built-in soft start and quick shutoff functions
Note: The reference voltage 2.5 V is under the condition of VIN ≥ 4.5 V.
Ordering Information
Hitachi Control ICs for Chopper-Type DC/DC Converters
Product
Channel
Channels
Number
No.
Step-Up
Step-Down
Dual
HA17451
Ch 1
❍
Ch 2
HA16114
HA16120
HA16116
Single
Dual
HA16121
Control Functions
Overcurrent
Inverting
Output Circuits
Protection
❍
❍
Open collector
SCP with timer (latch)
❍
❍
❍
—
—
❍
❍
—
❍
—
—
Ch 1
—
❍
❍
Totem pole
power MOS FET
driver
Pulse-by-pulse
current limiter and
intermittent operation
by on/off timer
Ch 2
—
❍
—
Ch 1
—
❍
❍
Ch 2
❍
—
—
Rev.2.0, Sep.18.2003, page 2 of 33
HA16116FP/FPJ, HA16121FP/FPJ
Pin Arrangement
S.GND*1
1
20
S.VIN*2
CT
2
19
Vref
RT
3
18
TIM
IN(+)1
4
17
ON/OFF
IN(−)1
5
16
IN(−)2
E/O1
6
15
E/O2
DB1
7
14
DB2
CL1
8
13
CL2
OUT1
9
12
OUT2
10
11
P.VIN*2
Channel 1
P.GND
*1
Channel 2
(Top view)
Notes: 1. Pins S.GND (pin 1) and P.GND (pin 10) have no direct internal interconnection.
Both pins must be connected to ground.
2. Pins S.VIN (pin 20) and P.V IN (pin 11) have no direct internal interconnection.
Both pins must be connected to VIN.
Rev.2.0, Sep.18.2003, page 3 of 33
HA16116FP/FPJ, HA16121FP/FPJ
Pin Functions
Pin No.
Symbol
Function
1
S.GND
Signal circuitry* ground
2
CT
Timing capacitance (triangle wave oscillator output)
3
RT
Timing resistance (for bias current synchronization)
4
IN(+)1
Error amp. noninverting input (1)
5
IN(–)1
Error amp. inverting input (1)
6
E/O1
Error amp. output (1)
7
DB1
Dead band timer off period adjustment input (1)
8
CL1
Overcurrent detection input (1)
9
OUT1
PWM pulse output (1)
10
P.GND
Output stage* ground
11
P.VIN
Output stage* power supply input
12
OUT2
PWM pulse output (2)
13
CL2
Overcurrent detection input (2)
14
DB2
Dead band timer off period adjustment input (2)
15
E/O2
Error amp. output (2)
16
IN(–)2
Error amp. inverting input (2)*
17
ON/OFF
IC on/off switch input (off when grounded)
18
TIM
Setting of intermittent operation timing when overcurrent is detected
(collector input of timer transistor)
19
Vref
2.5 V reference voltage output
20
S.VIN
Signal circuitry* power supply input
1
Channel 1
1
1
Channel 2
2
1
Notes: 1. Here “output stage” refers to the power MOS FET driver circuits, and “signal circuitry” refers to all
other circuits on the IC. Note that this IC is not protected against reverse insertion, which can
cause breakdown of the IC between VIN and GND. Be careful to insert the IC correctly.
2. Noninverting input of the channel 2 error amp is connected internally to Vref.
Rev.2.0, Sep.18.2003, page 4 of 33
Rev.2.0, Sep.18.2003, page 5 of 33
OVP
CT
S.GND
) in the case of
IN(+)1
RT
Q
4
R
S
Latch
OR
UVL
output
17
ON/OFF
3
Bias current
latch reset pulse
1.1 V
RT
V L VH
UVL
triangle wave
1.0 V
1.6 V
2
5k
L
H
18
TIM
Triangle wave
oscillator circuit
1
0.8V
VIN
Note: * This block is AND (
HA16121.
from
UVL
ON/OFF
19
20
2.5 V output
band gap
reference
voltage
generator
circuit
Vref
S.VIN
VIN
+
EA1
−
6
14
DB2
5k
DB1
7
8
9
11
P.VIN
OUT1
P.GND
10
NAND
NAND
(HA16116)
OUT2*
OUT1
0.2 V
Vref
Vref
12
OUT2
0.2 V
to S.VIN
CL1
− +
CL1
from UVL
− +
CL2
to S.VIN
13
CL2
from UVL
PWM COMP 1
−
+
+
+
+
−
PWM COMP 2
5k
from
UVL
E/O1
0.8V
VIN
0.8V
−
EA2
+
from
UVL
15
E/O2
[Channel 1] (HA16116/HA16121)
Step-down or inverting control
IN(−)1
5
16
IN(−)2
[Channel 2]
Step-down control only (HA16116)
Booster control only (HA16121)
HA16116FP/FPJ, HA16121FP/FPJ
Block Diagram
HA16116FP/FPJ, HA16121FP/FPJ
Function and Timing Chart
Relation between triangle wave and PWM output (in steady-state operation)
CT triangle wave
1.6 V typ
Dead band
voltage
1.0 V typ
E/O Error amp output
Booster
channel
output
(HA16121Ch 2) only
PWM
pulse
output
VIN (on)
tON
tOFF
GND (off)
This pulse
is for
N-channel
power MOS
FET gate
driving.
T
Step-down
or inverting
output
(HA16116Ch 1, Ch 2/
HA16121-Ch 1)
Note: On duty = tON/T, where T = 1/fOSC.
Rev.2.0, Sep.18.2003, page 6 of 33
VIN (off)
GND (on)
This pulse
is for
P-channel
power MOS
FET gate
driving.
HA16116FP/FPJ, HA16121FP/FPJ
Determining External Component Constants (pin usage)
Constant settings are explained for the following items.
S.GND 1
1.
2.
Oscillator
frequency
(fOSC) setting
DC/DC converter
output voltage
setting and
error amp usage
CT 2
19 Vref
RT 3
18 TIM
IN(+)1 4
17 ON/OFF
IN(−)1 5
16 IN(−)2
E/O1 6
3.
Dead band duty
and soft start
setting
20 S.VIN
DB1 7
15 E/O2
Channel 1
Channel 2
CL1 8
4.
Output stage
circuit and
power MOS FET
driving method
5.
Vref UVL and
OVP
6.
Setting of intermittent operation
timing when
overcurrent is
detected
7.
ON/OFF pin
usage
8.
Overcurrent
detection value
setting
14 DB2
13 CL2
OUT1 9
12 OUT2
P.GND 10
11 P.VIN
1. Oscillator Frequency (fOSC) Setting
Figure 1.1 shows an equivalent circuit for the triangle wave oscillator.
VH
1.6 V typ
t1
t2
(3.3 V
IC internal circuits)
Vref (2.5 V)
VL
1.0 V typ
CT charging
IO
RA
Comparator
RC
IO
Discharging
1.1 V
1:2
RT
RB
CT
(external)
CT
RT
(external)
Inside the IC
Figure 1.1 Equivalent Circuit for the Triangle Wave Oscillator
Rev.2.0, Sep.18.2003, page 7 of 33
HA16116FP/FPJ, HA16121FP/FPJ
The triangle wave is a voltage waveform used as a reference in creating a PWM pulse. This block operates
according to the following principles. A constant current IO, determined by an external timing resistor RT, is
made to flow continuously to external timing capacitor CT. When the CT pin voltage exceeds the
comparator threshold voltage VH, the comparator output causes a switch to operate, discharging a current IO
from CT. Next, when the CT pin voltage drops below threshold voltage VL, the comparator output again
causes the switch to operate, stopping the IO discharge. The triangle wave is generated by this repeated
operation.
Note that IO = 1.1 V/RT. Since the IO current mirror circuit has a very limited current producing ability, RT
should be set to ≥ 5 kΩ (IO ≥ 220 µA).
With this IC series, VH and VL of the triangle wave are fixed internally at about 1.6 V and 1.0 V by the
internal resistors RA, RB, and RC. The oscillator frequency can be calculated as follows.
fOSC =
1
t1 + t2 + t3
Here,
t1 =
C R ⋅ (VH − VL)
CT ⋅ (VH − VL)
= T T
1.1 V/RT
1.1 V
t2 =
C R ⋅ (VH − VL)
CT ⋅ (VH − VL)
= T T
= t1
(2 − 1) × 1.1 V/RT
1.1 V
VH − VL = 0.6 V
t1 = t2 =
0.6
C R
1.1 T T
t3 ≈ 0.8 µs (comparator delay time in the oscillator)
Accordingly,
fOSC ≈
1
1
[Hz]
≈
2t1 + t3
1.1 CT RT + 0.8 µs
Note that the value of fOSC may differ slightly from the above calculation depending on the amount of delay
in the comparator circuit. Also, at high frequencies this comparator delay can cause triangle wave
overshoot or undershoot, skewing the dead band threshold. Confirm the actual value in implementation
and adjust the constants accordingly.
Rev.2.0, Sep.18.2003, page 8 of 33
HA16116FP/FPJ, HA16121FP/FPJ
2. DC/DC Converter Output Voltage Setting and Error Amp Usage
2.1 Positive Voltage Booster (VO > VIN) or Step-Down (VIN > VO > Vref)
Use VO =
R1 + R2
⋅ Vref (V)
R2
Booster output is possible only at channel 2 of HA16121.
HA16116 or channel 1 of HA16121 are used.
VO
For step-down output, both channels of
Error amp.
IN(−)1 −
CH1
R1
R2
IN(+)1 +
VO
R1
IN(−)2 −
R2
CH2
+
Vref pin
Vref
2.5 V
(internal connection)
Figure 2.1
2.2 Negative Voltage (VO < Vref) for Inverting Output
Use VO = −Vref ⋅
R3 + R 4
R1
⋅
−1
R3
R1 + R 2
(V)
Channel 1 is used for inverting output on both ICs.
Vref pin
Vref 2.5 V
R1
IN(−)1
R2
R3
IN(+)2
R4
−
+
Error amp
VO
Figure 2.2 Inverting Output
Rev.2.0, Sep.18.2003, page 9 of 33
CH1
HA16116FP/FPJ, HA16121FP/FPJ
2.3 Error Amplifier
Figure 2.3 shows an equivalent circuit of the error amplifier. The error amplifier on these ICs is configured
of a simple NPN transistor differential input amplifier and the output circuit of a constant-current driver.
This amplifier features wide bandwidth (fT = 4 MHz) with open loop gain kept to 50 dB, allowing stable
feedback to be applied when the power supply is designed. Phase compensation is also easy.
Both HA16116 and HA16121 have a noninverting input (IN(+)) pin, in order to allow use of the channel 1
error amplifier for inverting control. The channel 2 error amplifier, on the other hand, is used for stepdown control in HA16116 and booster control in HA16121; so the channel 2 noninverting input is
connected internally to Vref.
IC internal VIN
IN(−)
E/O
IN(+)
To internal PWM
comparator
80 µA
40 µA
Figure 2.3 Error Amplifier Equivalent Circuit
3. Dead Band (DB) Duty and Soft Start Setting (common to both channels)
3.1 Dead Band Duty Setting
Dead band duty is set by adjusting the DB pin input voltage (VDB). A convenient means of doing this is to
connect two external resistors to the Vref of this IC so as to divide VDB (see figure 3.1).
VDB = Vref ×
Duty (DB) =
Here, T =
R2
(V)
R1 + R2
VTH − VDB
× 100 (%) ⋅ ⋅ ⋅ ⋅ This applies when VDB > VTL.
VTH − VTL
If VDB < VTL, there is no PWM output.
1
fOSC
Note: VTH: 1.6 V (Typ)
VTL: 1.0 V (Typ)
Vref is typically 2.5 V. Select R1 and R2 so that 1.0 V ≤ VDB ≤ 1.6 V.
Rev.2.0, Sep.18.2003, page 10 of 33
HA16116FP/FPJ, HA16121FP/FPJ
To Vref
CT
VDB
R1
DB
E/O
−
+
+
PWM
comparator VIN
1.6 V typ
VTL
1.0 V typ
Booster
channel
5k
CST R
2
VTH
VE/O
VDB
From UVL
On
tON
tOFF
PWM
pulse
output Step-down/
0.8V
VIN
Off
Off
inverting
channel
On
GND
VIN
GND
T
Figure 3.1 Dead Band Duty Setting
3.2 Soft Start (SST) Setting (each channel)
When the power is turned on, the soft start function gradually raises VDB (refer to section 3.1), and the
PWM output pulse width gradually widens. This function is realized by adding a capacitor CST to the DB
pin. The function is realized as follows.
In the figure 3.2, the DB pin is clamped internally at approximately 0.8 V, which is 0.2 V lower than the
triangle wave VTL = 1.0 V typ.
tA: Standby time until PWM pulse starts widening.
tB: Time during which SST is in effect.
During soft start, the DB pin voltage in the figure below is as expressed in the following equation.
VSST = VDB ⋅ 1 − e
−t − t0.8
T
,
tSST = tA + tB
Here,
t0.8 = −T ln
1−
0.8
VDB
,
T = CST ⋅ (R1 // R2)
How to select values: If the soft start time tSST is too short, the DC/DC converter output voltage will tend to
overshoot. To prevent this, set tSST to a few tens of ms or above.
Rev.2.0, Sep.18.2003, page 11 of 33
HA16116FP/FPJ, HA16121FP/FPJ
V
(voltage)
VSST
Triangle wave
VTH
1.6 V
VTL
1.0 V
Starts from clamp
voltage of 0.8 V
PWM output
pulse starts to
widen
t0.8
tA
Steady-state
operation
VIN
Booster
channel
PWM pulse
output
0V
tB
0V
Step-down/
inverting
channel
VIN
0V
VO
DC/DC converter output
(positive in this example)
0V
t = 0 (here IC is on)
t = tSST
Figure 3.2 Soft Start (SST) Setting
Rev.2.0, Sep.18.2003, page 12 of 33
HA16116FP/FPJ, HA16121FP/FPJ
4. Totem Pole Output Stage Circuit and Power MOS FET Driving Method
The output stage of this IC series is configured of totem pole circuits, allowing direct connection to a power
MOS FET as an external switching device, so long as VIN is below the gate breakdown voltage.
If there is a possibility that VIN will exceed the gate breakdown voltage of the power MOS FET, a Zener
diode circuit like that shown figure 4.1 or other protective measures should be used. The figure 4.1 shows
an example using a P-channel power MOS FET.
P.VIN
Bias
circuit
E.g.: VIN = 18 V
Zener diode for
gate protection
OUT Gate
protection
resistor
Drive circuit
VO
+
−
Schottky
barrier diode
Figure 4.1 P-channel Power MOS FET (example)
5. Vref Undervoltage Error Prevention (UVL) and Overvoltage Protection (OVP) Functions
5.1 Operation Principles
The reference voltage circuit is equipped with UVL and OVP functions.
• UVL
In normal operation the Vref output voltage is fixed at 2.5 V. If VIN is lower than normal, the UVL
circuit detects the Vref output voltage with a hysteresis of 1.7 V and 2.0 V, and shuts off the PWM
output if Vref falls below this level, in order to prevent malfunction.
• OVP
The OVP circuit protects the IC from inadvertent application of a high voltage from outside, such as if
VIN is shorted. A Zener diode (5.6 V) and resistor are used between Vref and GND for overvoltage
detection. PWM output is shut off if Vref exceeds approximately 7.0 V.
Note that the PWM output pulse logic and the precision of the switching regulator output voltage are not
guaranteed at an applied voltage of 2.5 V to 7 V.
Rev.2.0, Sep.18.2003, page 13 of 33
HA16116FP/FPJ, HA16121FP/FPJ
5.2 Quick Shutoff
When the UVL circuit goes into operation, a sink transistor is switched on as in the figure below, drawing
off the excess current. This transistor also functions when the IC is turned off, drawing off current from the
CT, E/O, and DB pins and enabling quick shutoff.
PWM
output
On
PWM
output
off
PWM output on
PWM
output off
Off
1.7 2.0
2.5
When VIN is
low
5.0
7.0
Vref (V)
Abnormal voltage
applied to Vref
Relation of Vref to UVL and OVP
VIN
Vref
generation
circuit
Vref
Vref
2.0 V and
1.7 V
detection
ZD
5.6 V
UVL
Internal
pulse
signal
line
OUT
R
OVP
10 kΩ
Sink
transistor
To other circuitry
Figure 5.1 Quick Shutoff
Rev.2.0, Sep.18.2003, page 14 of 33
OUT
HA16116FP/FPJ, HA16121FP/FPJ
6. Setting of Intermittent Operation Timing when Overcurrent is Detected
6.1 Operation Principles
The current limiter on this IC detects overcurrent in each output pulse, providing pulse-by-pulse
overcurrent protection by limiting pulse output whenever an overcurrent is detected. If the overcurrent
state continues, the TIM pin and ON/OFF pin can be used to operate the IC intermittently. As a result, a
power supply with sharp vertical characteristics can be configured.
The ON/OFF timing for intermittent operation makes use of the hysteresis in the ON/OFF pin threshold
voltage VON and VOFF, such that VON – VOFF = VBE. Setting method is performed as described on the
following pages. VBE is based-emitter voltage of internal transistor.
Note: When an overcurrent is detected in one channel of this IC but not the other, the pulse-by-pulse
current limiter still goes into operation on both channels. Also, when the intermittent operation
feature is not used, the TIM pin should be set to open state and the ON/OFF pin pulled up to high
level (above VON).
VIN
390 kΩ
RA
4.7 kΩ
2.2 µF
RB
+
−
Latch
S
Q
R
TM
ON/OFF
Current
limiter
CL
Vref
generation
circuit
CON/OFF
Figure 6.1 Connection Diagram (example)
6.2 Intermittent Operation Timing Chart (VON/OFF only)
*1
4VBE
c
c
VON/OFF
3VBE
2VBE
VBE
0V
On
IC is on
a
IC is off
On
Off
b
TON
t
TOFF
2TON
a. Continuous overcurrent detected
b. Intermittent operation starts (IC is off)
c. Overcurrent cleared (dotted line)
Note: 1.V BE is the base-emitter voltage in transistors on the IC, and is approximately 0.7 V
(see the figure 7.1).
For details, see the overall waveform timing diagram.
Figure 6.2 Intermittent Operation Timing Chart
Rev.2.0, Sep.18.2003, page 15 of 33
HA16116FP/FPJ, HA16121FP/FPJ
6.3 Calculating Intermittent Operation Timing
Intermittent operation timing is calculated as follows.
(1) TON time (the time until the IC is shut off when continuous overcurrent occurs)
TON = CON/OFF × RB × ln
3VBE
2VBE
= CON/OFF × RB × ln1.5 ×
1
×
1 − On duty*
1
1 − On duty*
≈ 0.4 × CON/OFF × RB ×
1
1 − On duty*
(2) TOFF time (when the IC is off, the time until it next goes on)
TOFF = CON/OFF × (RA + RB) × ln
VIN − 2VBE
VIN − 3VBE
Where, VBE ≈ 0.7 V
Note: 1. On duty is the percent of time the IC is on during one PWM cycle when the pulse-by-pulse
current limiter is operating.
From the first equation (1) above, it is seen that the shorter the time TON when the pulse-by-pulse current
limiter goes into effect (resulting in a larger overload), the smaller the value TON becomes.
As seen in the second equation (2), TOFF is a function of VIN. Further, according to this setting, when VIN is
switched on, the IC goes on only after TOFF has elapsed.
Dead band voltage
Triangle wave
Point at which current
limiter operate
PWM output
(step-down channel)
tON
On duty =
T
tON
T
Where T = 1/fOSC
Note: On duty is the percent of time the IC is on during one PWM cycle when
the pulse-by-pulse current limiter is operating.
Figure 6.3
Rev.2.0, Sep.18.2003, page 16 of 33
HA16116FP/FPJ, HA16121FP/FPJ
6.4 Examples of Intermittent Operation Timing (calculated values)
4
(1) TON
TON = T1 × CON/OFF × RB
3
Here, coefficient
T1 = 0.4 ×
1
1 − On duty
2
from section 6.3 (1) previously.
T1
1
Example: If CON/OFF = 2.2 µF,
RB = 4.7 kΩ, and the on duty
of the current limiter is 75%,
then TON = 16 ms.
0
0
20
40
60
80
100
(PWM) ON Duty (%)
Figure 6.4 Examples of Intermittent Operation Timing (1)
(2) TOFF
TOFF = T2 × CON/OFF × (RA + RB)
0.1
Here, coefficient
T2 = ln
VIN − 2VBE
VIN − 3VBE
from section 6.3 (2) previously.
T2
0.05
Example: If CON/OFF = 2.2 µF, RB = 4.7 kΩ,
RA = 390 kΩ, VIN = 12 V,
0
then TOFF = 60 ms.
0
10
20
VIN (V)
Figure 6.5 Examples of Intermittent Operation Timing (2)
Rev.2.0, Sep.18.2003, page 17 of 33
30
40
HA16116FP/FPJ, HA16121FP/FPJ
Example of step-up circuit
VIN
Triangle wave VCT
Dead band VDB
CF
RF
Error output VE/O
PWM pulse output
(In case of HA16120)
IC
RCS
CL
Inductor
L
OUT
Power MOS FET
drain current (ID)
(dotted line shows
inductor current)
VIN
Current limiter
pin (CL)
VIN − 0.2 V
VOUT
ID
F.B.
Determined by L and VIN
VTH (CL)
Determined by RCS and RF
Figure 6.6
7. ON/OFF
OFF Pin Usage
7.1 IC Shutoff by the ON/OFF
OFF Pin
As shown in the figure 7.1, these ICs can be turned off safely by lowering the voltage at the ON/OFF pin to
below 2VBE. This feature is used to conserve the power in the power supply system. In off state the IC
current consumption (IOFF) is 10 µA (Max) for HA16116 and 150 µA (Max) for HA16121.
The ON/OFF pin can also be used to drive logic ICs such as TTL or CMOS with a sink current of 50 µA
(Typ) at an applied voltage of 5 V. When it is desired to employ this feature along with intermittent
operation, an open collector or open drain logic IC should be used.
VIN
IIN
RA
External logic IC
Off
On
RB
P.VIN
TIM
S.VIN
To output
stage
To latch
50 kΩ
ON/OFF
Switch
+
−
CON/OFF
4 VBE
To other circuitry
Q1
Q2
Q3
Vref
output
Q4
GND
HA16116,
HA16121
Figure 7.1 IC Shutoff by the ON/OFF
OFF Pin
Rev.2.0, Sep.18.2003, page 18 of 33
Vref
generation
circuit
On/off hysteresis circuit
HA16116FP/FPJ, HA16121FP/FPJ
7.2 Adjusting UVL Voltage (when intermittent operation is not used)
The UVL voltage setting in this IC series can be adjusted externally as shown below.
Using the relationships shown in the figure, the UVL voltage in relation to VIN can be adjusted by changing
the relative values of VTH and VTL.
When the IC is operating, transistor Q4 is off, so VON = 3VBE ≈ 2.1 V. Accordingly, by connecting resistors
RC and RD, the voltage at which UVL is cancelled is as follows.
VIN = 2.1 V ×
RC + RD
RD
This VIN is simply the supply voltage at which the UVL stops functioning, so in this state Vref is still below
2.5 V. In order to restore Vref to 2.5 V, a VIN of approximately 4.3 V should be applied.
With this IC series, VON/OFF makes use of the VBE of internal transistors, so when designing a power supply
system it should be noted that VON has a temperature dependency of around –6 mV/°C.
VIN
P.VIN
To output
stage
To latch
TIM
(open)
RC
S.VIN
ON/OFF
Q1
50 kΩ
RD
Q2
Q3
GND
3
Vref
generation
circuit
On/off hysteresis circuit
VIN ≥ 4.5 V
2
VOFF
1.4 V
1
0
1
VON
2.1 V
2
3
4
5
VON/OFF
Figure 7.2 Adjusting UVL Voltage
Rev.2.0, Sep.18.2003, page 19 of 33
Vref output
Q4
2.5 V
Vref
0
To other circuitry
HA16116FP/FPJ, HA16121FP/FPJ
Overcurrent Detection Value Setting
The overcurrent detection value VTH for this IC series is 0.2 V (Typ) and the bias current is 200 µA (Typ)
The power MOS FET peak current value before the current limiter goes into operation is derived from the
following equation.
ID =
VTCL − (RF + RCS) ⋅ IBCL
RCS
Here VTH = VIN – VCL = 0.2 V, VCL is a voltage referd on GND.
Note that CF and RCS form a low-pass filter, determined by their time constants, that prevents malfunctions
from current spikes when the power MOS FET is turned on or off.
CF 1800 PF
S.VIN
To other
circuitry
CL
1k
VIN
RF
240 Ω
This circuit is an example
for step-down output use.
G
OUT
200 µA
RCS
0.05 Ω
IBCL
VCL
S
D
Detection
output
(internal)
VO
+
− +
−
IN(−)
Figure 8.1 Example for Step-Down Use
The sample values given in this figure are calculated from the following equation.
ID =
0.2 V − (240 Ω + 0.05 Ω) × 200 µA
0.05 Ω
= 3.04 [A]
The filter cutoff frequency is calculated as follows.
fC =
1
2π CF RF
=
1
6.28 × 1800 pF × 240 Ω
Rev.2.0, Sep.18.2003, page 20 of 33
= 370 [kHz]
HA16116FP/FPJ, HA16121FP/FPJ
Absolute Maximum Ratings
(Ta = 25°C)
Rating
Item
Symbol
HA16116FP,
HA16121FP
HA16116FPJ,
HA16121FPJ
Unit
Supply voltage
VIN
40
40
V
Output current (DC)
IO
±0.1
±0.1
A
Output current (peak)
IO peak
±1.0
±1.0
A
Current limiter pin voltage
VCL
VIN
VIN
V
Error amp input voltage
VIEA
VIN
VIN
V
E/O input voltage
VIE/O
Vref
Vref
V
RT pin source current
IRT
500
500
µA
TIM pin sink current
ITM
20
1
20
1
mA
1
Power dissipation*
PT
680*
680*
mW
Operation temperature range
Topr
–40 to +85
–40 to +85
°C
Junction temperature
TjMax
125
125
°C
Storage temperature range
Tstg
–55 to +125
–55 to +125
°C
Permissible dissipation PT (mW)
Note:
1. This value is based on actual measurements on a 40 × 40 × 1.6 mm glass epoxy circuit board.
At a wiring density of 10%, it is the permissible value up to Ta = 45°C, but at higher temperatures
this value should be derated by 8.3 mW/°C. At a wiring density of 30% it is the permissible value
up to Ta = 64°C, but at higher temperatures it should be derated by 11.1 mW/°C.
800
10% wiring density
680 mW
30% wiring density
600
447 mW
400
348 mW
200
0
−40
−20
0
20
40
45°C
64°C
85°C
60
80
100
Operating ambient temperature Ta (°C)
Rev.2.0, Sep.18.2003, page 21 of 33
125°C
120
140
HA16116FP/FPJ, HA16121FP/FPJ
Electrical Characteristics
(Ta = 25°C, VIN = 12 V, fOSC = 300 kHz)
Item
Reference
voltage
block
Triangle
wave
oscillator
block
Dead band
adjust block
PWM
comparator
block
Symbol
Min
Typ
Max
Unit
Test Conditions
Output voltage
Vref
2.45
2.50
2.55
V
IO = 1 mA
Line regulation
Line
—
30
60
mV
4.5 V ≤ VIN ≤ 40 V
Load regulation
Load
—
30
60
mV
0 ≤ IO ≤ 10 mA
Output shorting
current
IOS
10
25
—
mA
Vref = 0 V
Vref OVP voltage
Vrovp
6.2
6.8
7.0
V
Output voltage
temperature
dependence
∆Vref/∆Ta
—
100
—
ppm/°C
Maximum oscillator
frequency
fOSCmax
600
—
—
kHz
Minimum oscillator
frequency
fOSCmin
—
—
1
Hz
Oscillator frequency
input voltage stability
∆fOSC/∆VIN
—
±1
±3
%
4.5 V ≤ VIN ≤ 40 V
Oscillator frequency
temperature stability
∆fOSC/∆Ta
—
±5
—
%
–20°C ≤ Ta ≤ 85°C
Oscillator frequency
fOSC
270
300
330
kHz
CT = 220 pF, RT = 10 kΩ)
Low-level threshold
voltage
VTLDB
0.87
0.97
1.07
V
Output on duty 0%
High-level threshold
voltage
VTHDB
1.48
1.65
1.82
V
Output on duty 100%
Threshold differential
voltage
∆VTDB
0.55
0.65
0.75
V
∆VTH = VTH – VTL
Output source current
IOsource (DB)
100
150
200
µA
DB pin = 0 V
Low-level threshold
voltage
VTLCMP
0.87
0.97
1.07
V
Output on duty = 0%
High-level threshold
oltage
VTHCMP
1.48
1.65
1.82
V
Output on duty = 100%
Threshold differential
voltage
∆VTCMP
0.55
0.65
0.75
V
∆VTH = VTH – VTL
Dead band precision
DBdev
–5
0
+5
%
Deviation when
VEO = (VTL + VTH)/2,
duty = 50 %
Rev.2.0, Sep.18.2003, page 22 of 33
HA16116FP/FPJ, HA16121FP/FPJ
Electrical Characteristics (cont.)
(Ta = 25°C, VIN = 12 V, fOSC = 300 kHz)
Item
Error amp
block
Overcurrent
detection
block
Output
stage
Symbol
Min
Typ
Max
Unit
Input offset voltage
VIOEA
—
2
10
mV
Input bias current
IBEA
—
0.8
2
µA
Output sink current
IOsink (EA)
28
40
52
µA
In open loop,
VI = 3 V, VO = 2 V
Output source current
IOsource (EA)
28
40
52
µA
In open loop,
VI = 2 V, VO = 1 V
Voltage gain
AV
40
50
—
dB
f = 10 kHz
Unity gain band-width
BW
3
4
—
MHz
High-level output voltage
VOHEA
2.2
3.0
—
V
IO = 10 µA
Low-level output voltage
VOLEA
—
0.2
0.5
V
IO = 10 µA
Threshold voltage
VTCL
VIN–0.22
VIN–0.2
VIN–0.18
V
CL bias current
IBCL
150
200
250
µA
CL = VIN
Operating time
tOFFCL
—
200
300
ns
CL = VIN –0.3 V
—
500
600
ns
Applies only to ch 2
of HA16121
—
0.7
2.2
V
IOsink = 10 mA
Applies only to HA16116
—
1.6
1.9
V
IOsink = 10 mA
Applies only to HA16121
—
1.0
1.3
V
IOsink = 0 mA
Applies only to HA16121
—
1.6
1.9
V
IOsink = 1 mA
ON/OFF pin = 0 V
Applies only to ch 2
of HA16121
—
1.0
1.3
V
IOsink = 0 mA
ON/OFF = 0 V
Applies only to ch 2
of HA16121
VIN–1.9
VIN–1.6
—
V
IOsource = 10 mA
VIN–1.3
VIN–1.0
—
V
IOsource = 0 A
VIN–1.9
VIN–1.6
—
V
IOsource = 1 mA
ON/OFF pin = 0 V
VIN–1.3
VIN–1.0
—
V
IOsource = 0 A
ON/OFF pin = 0 V
Output low voltage
Off state low voltage
Output high voltage
Off state high voltage
VOL1
VOL2
VOH1
VOH2
Test Conditions
Rise time
tr
—
70
130
ns
CL = 1000 pF (to VIN) *1, *2
Fall time
tf
—
70
130
ns
CL = 1000 pF (to VIN) *1, *2
Rev.2.0, Sep.18.2003, page 23 of 33
HA16116FP/FPJ, HA16121FP/FPJ
Electrical Characteristics (cont.)
(Ta = 25°C, VIN = 12 V, fOSC = 300 kHz)
Item
UVL block
ON/OFF
block
TIM block
Common
block
Symbol
Min
Typ
Max
Unit
VIN high-level threshold
voltage
VTUH1
3.3
3.6
3.9
V
VIN low-level threshold
voltage
VTUL1
3.0
3.3
3.6
V
VIN threshold differential
voltage
∆VTU1
0.1
0.3
0.5
V
Vref high-level threshold
voltage
VTUH2
1.7
2.0
2.3
V
Vref low-level threshold
voltage
VTUL2
1.4
1.7
2.0
V
Vref threshold differential
voltage
∆VTU2
0.1
0.3
0.5
V
∆VTU2 = VTUH2 – VTUL2
ON/OFF pin sink current
ION/OFF
—
35
50
µA
ON/OFF pin = 5 V
IC on-state voltage
VON
1.8
2.1
2.4
V
IC off-state voltage
VOFF
1.1
1.4
1.7
V
ON/OFF threshold
differential voltage
∆VON/OFF
0.5
0.7
0.9
V
TIM pin sink current in
steady state
ITIM1
0
—
10
µA
CL pin = VIN, VTIM = 0.3 V
TIM pin sink current at
overcurrent detection
ITIM2
10
15
20
mA
CL pin = VIN – 0.3 V
VTIM = 0.3 V
Operating current
IIN
6.0
8.5
11.1
mA
CL = 0 pF (to VIN) *1, *2
8.5
12.1
15.7
mA
CL = 500 pF (to VIN) *1, *2
11.0
15.7
20.5
mA
CL = 1000 pF (to VIN) *1, *2
0
—
10
µA
HA16116FP
0
120
150
µA
HA16121FP
Off current
IOFF
Test Conditions
∆VTU1 = VTUH1 – VTUL1
Notes: 1. CL is load capacitor for Power MOS FET’s gate, and CL = 1000 pF to GND in the case of
HA16121 – ch 2.
2. CL in channel 2 of HA16121 is connected to GND.
Rev.2.0, Sep.18.2003, page 24 of 33
ON/OFF
pin = 0 V
HA16116FP/FPJ, HA16121FP/FPJ
Characteristic Curves
• Reference Voltage Block (Vref)
2
Ta = 25°C
RA = 390 kΩ
(Between the VIN
and ON/OFF pins)
2.5 V
UVL release: 3.6 V
UVL operate: 3.3 V
1
3.3 3.6
0
Vref Temperature Characteristics
2.54
Reference voltage Vref (V)
Reference voltage Vref (V)
Reference Voltage vs. Power Supply Input Voltage
3
VIN = 12 V
IO (Vref) = 1 mA
2.52
2.50
2.48
4.3
1
2
3
4
5
Power supply input voltage VIN (V)
40
2.46
−20
85
0
20
Vref Load Regulation
Reference voltage Vref (V)
3.0
2.5
2.0
1.50
Short
circuit
current
0
10
20
Output current IO sink (mA)
30
• UVL (Low Input Voltage Malfunction Prevention) Block
Hysteresis Voltage Temperature Characteristics
VIN UL voltage (V)
4.5
High threshold voltage
4.0
Hysteresis
3.5
3.0
2.5
Low threshold voltage
−20
Rev.2.0, Sep.18.2003, page 25 of 33
0
40
60
Ambient temperature Ta (°C)
20
40
60
80
Ambient temperature Ta (°C)
100
80
100
HA16116FP/FPJ, HA16121FP/FPJ
• Triangle Wave Oscillator Block
2.0
Sawtooth wave level (V)
RT pin voltage (V)
Sawtooth Wave Amplitude vs. Oscillator Frequency
RT pin Output Current Characteristics
1.1
1.0
0.9
Reccomended
usage range
10 (RT ≈ 100 kΩ)
0.8
0
100
VTH
1.5
VTL
1.0
Sawtooth wave
amplitude
Note: Due to these characteristics, the dead
band and PWM comparator threshold
voltages change at high frequencies.
0.5
330 (RT ≈ 3 kΩ)
200
300
400
500
0
(DC)
IRT (µA)
100
200
300
400
fOSC (kHz) (linear scale)
CT, RT Values (VIN = 12V) vs. Oscillator Frequency
100
70
C
RT (kΩ)
50
T
30
20
0
10
00
22
10
7
00
47
00
00
.1
5
3
47
10
µF
20
30
22
0
pF
=
10
47
0p
pF
600 kHz
F
pF
pF
pF
pF
50
70 100
200 300
Oscillator frequency fOSC (kHz)
500 700 1 M
Oscillator Frequency Temperature Stability
Frequency variation
(∆f/fo) (%)
+10
VIN = 12 V
+5
A: fOSC = 300 kHz
B: fOSC = 600 kHz
B
0
A
A
−5
B
85
−10
−20
Rev.2.0, Sep.18.2003, page 26 of 33
0
20
40
60
Ambient temperature Ta (°C)
80
100
500
600
HA16116FP/FPJ, HA16121FP/FPJ
• Error Amplifier Block
Open Loop Gain Characteristics
60
Phase delay φ (deg.)
Open loop gain AVO (dB)
AVO
0
40
φ
45
90
20
135
BW
0
1k
3k
10 k
30 k
100 k
300 k
1M
180
10 M
3M
Error amplifier input frequency fIN (Hz)
Common Mode Input Characteristics
+100
Output offset VO (mV)
0
−
EA
+
−100
VO
− +
VI
Vref
−200
−300
0
1
2
3
Input voltage VI (V)
4
• On Duty Characteristics
On Duty Characteristics
On Duty Characteristics
100
kH
z
Hz
z
0k
40
fO
SC
=5
20
20
30
0
40
60
0
k
60
0
On duty*2 (%)
60
Hz
Boost PWM output
(HA16121-2 ch)
kH
kH
z
80
0
0k
30
=5
SC
60
fO
On duty*1 (%)
80
Step-down
PWM output
(HA16116-1, 2ch
HA16121-1ch)
Hz
100
0
0.8
1.0
1.2
1.4
VDB or VE/O (V)
1.6
1.8
Notes: 1. The percentage of a single timing cycle
during which the output is low.
Rev.2.0, Sep.18.2003, page 27 of 33
0
0.8
1.0
1.2
1.4
VDB or VE/O (V)
1.6
1.8
2. The percentage of a single timing cycle
during which the output is high.
HA16116FP/FPJ, HA16121FP/FPJ
• Other Characteristics
IC On Voltage and Off Voltage Temperature Characteristics
4
210
3
VON or VOFF (V)
Detection voltage VTH (mV)
Current Limiter Level Temperature Characteristics
220
85°C
200
190
180
−20
0
20
40
60
Ambient temperature Ta (°C)
80
IIN vs. VIN Characteristics
0
20
40
60
80
Ambient temperature Ta (°C)
12
100
Output high voltage
when off (channels 1
and 2 in the HA16116
and channel 1 in the
HA16121)
10
Load capacitance:
1000 pF/ch
20
500 pF/ch
VGS
(P-channel
Power
MOS FET)
Output high voltage when on
11
Output voltage VO (VDC)
Current dissipation IIN (mA)
VOFF off voltage
(about −4mV/°C)
Output pin (Output Resistor) Characteristics
Maximum
rating at
Ta = 25°C:
680 mW
30
85°C
1
0
−20
100
40
fOSC = 300 kHz
On duty: 50%
Ta = 25°C
VON on voltage (about −6mV/°C)
2
9
3
No load
Output low voltage when on
10
2
Output low voltage
when off (channels 1
and 2 in the HA16121)
1
10
20
30
Power supply voltage VIN (V)
0
40
0
Output Drive Circuit Power MOS FET
Direct Drive ability Data
2
4
6
8
IO sink or IO source (mA)
10
VGS
(N-channel
Power
MOS FET)
Gate Drive Waveforms for the 2SJ214
800
VIN = 12 V
fOSC = 130 kHz
IO peak (mA)
600
2SJ214
2SJ176
2SJ216
Drive voltage:
5 V/div
400
200
0
Drive current: *
200 mA/div
1000
2000
3000
4000
Ciss (pF)
Note: The solid line is data measured with discrete
capacitances (for each channel of HA16116).
Rev.2.0, Sep.18.2003, page 28 of 33
650 nsec/div
Note: * Measured using a current probe.
(The boost channel (channel 2 in the HA16121)
load is with respect to ground, and has
almost identical characteristics.)
12V
VIN
Rev.2.0, Sep.18.2003, page 29 of 33
from
UVL
5k
S.GND
1
0.8V
VIN
2.5 V
output
band gap
reference
voltage
ON/OFF
generation
circuit
20
S.VIN
L
H
OVP
V L VH
UVL
18
TIM
CT
220p
CT
2
Bias current
RT
10k
RT
3
1.1 V
RT
Latch reset pulse
Triangle wave
1.0 V
1.6 V
Triangle wave
oscillator circuit
19
Vref
Units: R : Ω
C : µF (unless otherwise specified)
pF (p)
The IC is the HA16116.
Cref
0.1
Q
IN(+)1
4
R
S
Latch
OR
UVL
output
+
EA1
−
0.8V
VIN
12k
14
DB2
+
2.2
−
24k
33k
E/O1
5k
from UVL
R3
2k
2.2
R4
12k
24k
+
−
DB1
7
CL2
IN
CL1
8
0.2 V
Vref
Vref
0.2 V
to S.VIN
CL1
− +
− +
CL2
1800p
240
240
330µH
HRP24
4.7
4.7
1800p
P.GND
10
NAND
OUT1
OUT1
9
11
P.VIN
NAND
(HA16116)
OUT2*
OUT2
13 to S.V 12
from UVL
PWM COMP 1
−
+
+
+
+
−
PWM COMP 2
5k
from
UVL
from
UVL
6
12k
4700p 10k
100k
33k
E/O2
15
0.8V
−
EA2
+
IN(−)1
5
16
VIN
100k
10k
4700p
ON/OFF IN(−)2
17
RB
4.7k
CTM
2.2
RA
390k
HA16116FP is used in a ±5 V output power supply, with a +12 V input.
20k
20k
0.05
2SJ214
HRP24
+
− 470
Inverting output
Step-down output
+
470 −
330µH
2SJ214
0.05
+
−5 V
1A
output
−
−
+5 V
1A
output
+
HA16116FP/FPJ, HA16121FP/FPJ
Application Examples (1)
HA16116FP/FPJ, HA16121FP/FPJ
Overall Waveform Timing Diagram (for Application Examples (1))
12 V
VIN
0V
VTIM,
2.8 V
2.1 V
VTIM,
VON/OFF
VON/OFF
2.1 V
1.4 V
0V
On
On
(V)
3.0
On
VE/O
Off
2.0
VE/O,
VCT,
VDB
On
On
Off
Off
Off
Off
VCT
triangle wave
1.0
VDB
0.0
VCL
12 V
11.8 V
0V
Pulse-by-pulse
current limiter
operates
VOUT*1 12 V
PWM
pulse 0 V
DC/DC output
(example for
positive
voltage)
Soft start
IC operation
states
Power
IC on
supply on
Steady-state
operation
Overcurrent
detected;
intermittent
operation
Overcurrent Quick
cleared;
shut-off
steady-state
operation
Power supply off,
IC off
Note: 1.This PWM pulse is on the step-down/inverting control channel.
The booster control channel output consists of alternating L and H of the IC ÒonÓ cycle.
Rev.2.0, Sep.18.2003, page 30 of 33
HA16116FP/FPJ, HA16121FP/FPJ
Application Examples (2) (Some Pointers on Use)
1. Inductor, Power MOS FET, and Diode Connections
1. Booster specification
2. Step-down specification
VIN
VIN
CF
RF
VIN
RCS
CL
CF
Applicable only
to channel 2
of HA16121FP
RF
VIN
RCS
CL
OUT
Applicable to
HA16116FP and
to channel 1
of HA16121FP
VO
VO
OUT
GND
GND
FB
FB
3. Inverting specification
CF
RF
VIN
4. Negative booster specification (Flyback transformer)
RCS
CF
Applicable only
to channel 1
RF
VIN
CL
RCS
Applicable only
to channel 1
CL
OUT
OUT
VO
GND
GND
FB
FB
Vref
2. Turning Output On and Off while the IC is On
1. To turn only one channel off, ground the DB pin
or the E/O pin. In the case of E/O, however,
there will be no soft start when the output is
turned back on.
2. When only one channel is to be used,
the channel not used should be connected
as follows.
VIN
DB
Connect CL to VIN.
Ground IN(+) and IN(−).
Leave other pins open.
E/O
OFF
Rev.2.0, Sep.18.2003, page 31 of 33
CL
IN +
IN −
GND
5V
VIN
Rev.2.0, Sep.18.2003, page 32 of 33
20
1
5k
Triangle wave
1.0 V
1.6 V
S.GND
2
CT
220p
CT
Bias current
3
RT
10k
RT
1.1 V
RT
R
S
4
Q
Latch
UVL
output
17
Triangle wave
generation circuit
TIM
OR
VL VH
UVL
18
CTM
2.2
RB
4.7k
RA
390k
OVP
L
H
Vref
Units: R : Ω
C : µF (unless otherwise specified)
pF (p)
The IC is the HA16121.
from
UVL
0.8V
VIN
19
Latch reset pulses
S.VIN
2.5 V
band
gap
reference
voltage
ON/OFF
generation
circuit
Cref
0.1
IN(+)1
ON/OFF
VIN
IN(−)1
100k
+
EA1
−
0.8V
VIN
0.8V
−
EA2
+
100k
IN(−)2
12k
12k
4700p 10k
5
16
6
from UVL
33k
E/O1
from
UVL
5k
R3
1.2k
24k
+
−
7
R4
22k
2.2
DB1
8
0.2 V
CL1
to S.VIN
CL1
− +
9
Vref
Vref
0.2 V
11
OUT1
10
NAND
OUT1
1800p
P.VIN
1800p
P.GND
NAND
(HA16116)
OUT2*
CL2
OUT2
12
to S.VIN
− +
CL2
13
from UVL
PWM COMP 1
−
+
+
+
+
−
PWM COMP 2
5k
from
UVL
DB2
2.2
14
−
+
24k
E/O2
33k
15
4700p 10k
Power supply using the HA16121FP: +5 V input, +12 and −22 V outputs
240
4.7
330µH
2SK1094
4.7
240
+
+
−
470
Inverting output
2SJ214
0.05
1.3 k
5.1 k
Boost output
470 −
HRP24
330µH
0.05
−
−12 V
output
+
−
+12 V
output
+
HA16116FP/FPJ, HA16121FP/FPJ
Application Examples (3)
HA16116FP/FPJ, HA16121FP/FPJ
Package Dimensions
As of January, 2003
Unit: mm
12.6
13 Max
11
1
10
1.27
*0.42 ± 0.08
0.40 ± 0.06
0.10 ± 0.10
0.80 Max
*0.22 ± 0.05
0.20 ± 0.04
2.20 Max
5.5
20
0.20
7.80 +– 0.30
1.15
0˚ – 8 ˚
0.70 ± 0.20
0.15
0.12 M
*Dimension including the plating thickness
Base material dimension
Rev.2.0, Sep.18.2003, page 33 of 33
Package Code
JEDEC
JEITA
Mass (reference value)
FP-20DA
—
Conforms
0.31 g
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