Freescale MCIMX286DVM4B Processors data sheet for consumer product Datasheet

Freescale Semiconductor
Data Sheet: Technical Data
i.MX28 Applications
Processors Data Sheet for
Consumer Products
Document Number: IMX28CEC
Rev. 1, 04/2011
i.MX28
Silicon Version 1.2
Package Information
Plastic package
Case 5284 14 x 14 mm, 0.8 mm Pitch
1
Introduction
The i.MX28 is a low-power, high-performance
applications processor optimized for the general
embedded industrial and consumer markets.The
core of the i.MX28 is Freescale's fast,
power-efficient implementation of the
ARM926EJ-S™ core, with speeds of up to
454 MHz.
The device is suitable for a wide range of
applications, including the following:
• Human-machine interface (HMI) panels:
industrial, home
• Industrial drive, PLC, I/O control display,
factory robotics display, graphical remote
controls
• Handheld scanners and printers
• Patient-monitoring, portable medical
devices
• Smart energy meters, energy gateways
• Media phones, media gateways
The integrated power management unit (PMU) on
the i.MX28 is composed of a triple output DC-DC
switching converter and multiple linear regulators.
These provide power sequencing for the device and
its I/O peripherals such as memories and SD cards,
as well as provide battery charging capability for
Li-Ion batteries.
© Freescale Semiconductor, Inc., 2011. All rights reserved.
Ordering Information
See Table 1 on page 3 for ordering information.
Contents
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1. Device Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2. Ordering Information & Functional Part Differences 3
1.3. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1. Special Signal Considerations . . . . . . . . . . . . . . . 10
3. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1. i.MX28 Device-Level Conditions . . . . . . . . . . . . . . 11
3.2. Thermal Characteristics . . . . . . . . . . . . . . . . . . . . 19
3.3. I/O DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 19
3.4. I/O AC Timing and Parameters . . . . . . . . . . . . . . . 24
3.5. Module Timing and Electrical Parameters . . . . . . 28
4. Package Information and Contact Assignments . . . . . . . 60
4.1. 289-Ball MAPBGA—Case 14 x 14 mm,
0.8 mm Pitch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4.2. Ground, Power, Sense, and Reference Contact
Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4.3. Signal Contact Assignments . . . . . . . . . . . . . . . . . 62
4.4. i.MX287 Ball Map . . . . . . . . . . . . . . . . . . . . . . . . . 65
4.5. i.MX286 Ball Map . . . . . . . . . . . . . . . . . . . . . . . . . 66
4.6. i.MX283 Ball Map . . . . . . . . . . . . . . . . . . . . . . . . . 67
4.7. i.MX280 Ball Map . . . . . . . . . . . . . . . . . . . . . . . . . 68
5. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
The i.MX28 processor includes an additional 128-Kbyte on-chip SRAM to make the device ideal for
eliminating external RAM in applications with small footprint RTOS.
The i.MX28 supports connections to various types of external memories, such as mobile DDR, DDR2 and
LV-DDR2, SLC and MLC NAND Flash.
The i.MX28 can be connected to a variety of external devices such as high-speed USB2.0 OTG, CAN,
10/100 Ethernet, and SD/SDIO/MMC.
1.1
Device Features
The following lists the features of the i.MX28:
• ARM926EJ-S CPU running at 454 MHz:
— 16-Kbyte instruction cache and 32-Kbyte data cache
— ARM embedded trace macrocell (CoreSight™ ETM9™)
— Parallel JTAG interface
• 128 KBytes of integrated low-power on-chip SRAM
• 128 KBytes of integrated mask-programmable on-chip ROM
• 1280 bits of on-chip one-time-programmable (OCOTP) ROM
• 16-bit mobile DDR (mDDR) (1.8 V), DDR2 (1.8 V) and LV-DDR2 (1.5 V), up to 205 MHz DDR
clock frequency with voltage overdrive
• Support for up to eight NAND flash memory devices with up to 20-bit BCH ECC
• Four synchronous serial ports (SSP) for SDIO/MMC/MS/SPI. Two can be used for
SDIO/MMC/MS interfaces (supports SD2.0, eMMC4.4 and MSPro), and all can be used for the
SPI interface.
• 10/100-Mbps Ethernet MAC compatible with IEEE Std 802.3™, supporting
IEEE Std 1588™-compatible hardware timestamp. Also supports 50-MHz/25-MHz clock output
for external Ethernet PHY.
• Two 2.0B protocol-compatible Controller Area Network (CAN) interfaces
• One USB2.0 OTG device/host controller and PHY
• One USB2.0 host controller and PHY
• LCD controller, up to 24-bit RGB (DOTCK) modes and 24-bit system-mode
• Pixel-processing pipeline (PXP) supports full path from color-space conversion, scaling,
alpha-blending to rotation without intermediate memory access.
• SPDIF transmitter
• Dual serial audio interface (SAIF) to support full-duplex transmit and receive operations; each
SAIF supports three stereo pairs
• Five application Universal Asynchronous Receiver-Transmitters (UARTs), up to 3.25 Mbps with
hardware flow control
• One debug UART operating at up to 115 Kb/s using programmed I/O
• Two I2C master/slave interfaces, up to 400 kbps
• Four 32-bit timers and a rotary decoder
i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1
2
Freescale Semiconductor
•
•
•
•
•
•
•
•
•
•
Eight Pulse Width Modulators (PWMs)
Real-time clock (RTC)
GPIO with interrupt capability
Power Management Unit (PMU) supports a triple output DC-DC switching converter, multiple
linear regulators, battery charger, and detector.
16-channel Low-Resolution A/D Converter (LRADC)
4/5-wire touchscreen controller
Up to 8X8 keypad matrix with button-detect circuit
Single channel High Speed A/D Converter (HSADC), up to 2 Msps data rate
Security features:
— Read-only unique ID for Digital Rights Management (DRM) algorithms
— Secure boot using 128-bit AES hardware decryption
— SHA-1 and SHA256 hashing hardware
— High assurance boot (HAB4)
Offered in 289-pin Ball Grid Array (BGA)
1.2
Ordering Information & Functional Part Differences
Table 1 provides the ordering information for the i.MX28.
Table 1. Ordering Information
Part Number
Projected Temperature Range (°C)
Package
MCIMX280DVM4B
–20 to +70
14 x 14 mm, 0.8mm pitch, MAPBGA-289
MCIMX280CVM4B
–40 to +85
14 x 14 mm, 0.8mm pitch, MAPBGA-289
MCIMX283DVM4B
–20 to +70
14 x 14 mm, 0.8 mm pitch, MAPBGA-289
MCIMX283CVM4B
–40 to +85
14 x 14 mm, 0.8 mm pitch, MAPBGA-289
MCIMX286DVM4B
–20 to +70
14 x 14 mm, 0.8 mm pitch, MAPBGA-289
MCIMX286CVM4B
–40 to +85
14 x 14 mm, 0.8 mm pitch, MAPBGA-289
MCIMX287CVM4B
–40 to +85
14 x 14 mm, 0.8 mm pitch, MAPBGA-289
Table 2 provides the functional differences between the i.MX280, i.MX283, i.MX286, and the i.MX287.
Table 2. i.MX28 Functional Differences
Function
i.MX280
i.MX283
i.MX286
i.MX287
LCD Interface
—
Yes
Yes
Yes
Touch Screen
—
Yes
Yes
Yes
Ethernet
x1
x1
x1
x2
L2 Switch
—
—
—
Yes
CAN
—
—
x2
x2
12-bit ADC
x8
x8
x8
x8
i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1
Freescale Semiconductor
3
Table 2. i.MX28 Functional Differences (continued)
Function
i.MX280
i.MX283
i.MX286
i.MX287
x1
x1
x1
x1
OTG HS with
HS PHY x1
OTG HS with HS PHY x1
OTG HS with HS PHY x1
OTG HS with HS PHY x1
HS Host with
HS PHY x1
HS Host with HS PHY x1
HS Host with HS PHY x1
HS Host with HS PHY x1
SDIO
x4
x4
x4
x4
SPI
x4
x4
x4
x4
Application UART
x6
x5
x5
x5
Debug UART
x1
x1
x1
x1
PWM
—
x8
x8
x8
S/PDIF Tx
—
—
Yes
Yes
Securtiy
Yes
Yes
Yes
Yes
High-speed ADC
USB 2.0
i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1
4
Freescale Semiconductor
1.3
Block Diagram
Figure 1 shows the simplified interface block diagram.
Figure 1. i.MX28 Simplified Interface Block Diagram
2
Features
Table 3 shows the device functions.
Table 3. i.MX28 Functions
Function
External Memory Interface (EMI)
(1.5 V LV-DDR2, 1.8 V DDR2, 1.8 V LP-DDR1)
BGA289
Yes
General-Purpose Media Interface (GPMI):
• NAND data width
• Number of external NANDs supported
8-bit
4 dedicated / 8 with muxing
Pulse Width Modulator (PWM)
5 dedicated / 8 with muxing
i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1
Freescale Semiconductor
5
Table 3. i.MX28 Functions (continued)
Function
BGA289
Application UART (AUART): Interfaces supported
4 dedicated / 5 with muxing
Synchronous Serial Port (SSP): Supported through dedicated pins
3 dedicated / 4 with muxing
2
I C
1 dedicated / 2 with muxing
SPDIF
1
SAIF
2
FlexCAN
2
LCD interface
24 bits
High-speed ADC
Yes
LRADC (touchscreen, keypad...)
Yes
Ethernet MAC and switch
2 MACs with switch
Universal Serial Bus (USB)
2
Table 4 describes the digital and analog modules of the device.
Table 4. i.MX28 Digital and Analog Modules
Block
Mnemonic
Block Name
Subsystem
Brief Description
APBHDMA
AHB to APBH System control
Bridge with
DMA
The AHB to APBH bridge with DMA includes the AHB-to-APB PIO bridge for
memory-mapped I/O to the APB devices, as well a central DMA facility for
devices on this bus. The bridge provides a peripheral attachment bus running
on the AHB’s HCLK. (The ‘H’ in APBH denotes that the APBH is synchronous
to HCLK, as compared to APBX, which runs on the crystal-derived XCLK.)
The DMA controller transfers read and write data to and from each peripheral
on APBH bridge.
APBXDMA
AHB to APBX System control
Bridge with
DMA
The AHB-to-APBX bridge includes the AHB-to-APB PIO bridge for
memory-mapped I/O to the APB devices, as well a central DMA facility for
devices on this bus. The AHB-to-APBX bridge provides a peripheral
attachment bus running on the AHB’s XCLK. (The ‘X’ in APBX denotes that
the APBX runs on a crystal-derived clock, as compared to APBH, which is
synchronous to HCLK.) The DMA controller transfers read and write data to
and from each peripheral on APBX bridge.
ARM9 or
ARM926
ARM926EJ-S ARM®
CPU
The ARM926 Platform consists of the ARM926EJ-S™ core and the ETM
real-time debug modules. It contains the 16-Kbyte L1 instruction cache,
32-Kbyte L1 data cache, 128-Kbyte ROM and 128-Kbyte RAM.
AUART(5)
Application
UART
interface
Each of the UART modules supports the following serial data
transmit/receive protocols and configurations:
• 7- or 8-bit data words, one or two stop bits, programmable parity (even,
odd, or none)
• Programmable baud rates up to 3.25 MHz. This is a higher maximum
baud rate than the 1.875 MHz specified by the TIA/EIA-232-F standard
and previous Freescale UART modules. 16-byte FIFO on Tx and 16-byte
FIFO on Rx supporting auto-baud detection
Connectivity
peripherals
i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1
6
Freescale Semiconductor
Table 4. i.MX28 Digital and Analog Modules (continued)
Block
Mnemonic
Block Name
Subsystem
Brief Description
BCH
Bit-correcting Connectivity
ECC
peripherals
accelerator
The Bose, Ray-Chaudhuri, Hocquenghem (BCH) Encoder and Decoder
module is capable of correcting from 2 to 20 single bit errors within a block of
data no larger than about 900 bytes (512 bytes is typical) in applications such
as protecting data and resources stored on modern NAND flash devices.
BSI
Boundary
Connectivity
Scan Interface peripherals
The boundary scan interface is provided to enable board level testing.
There are five pins on the device which is used to implement the IEEE Std
1149.1™ boundary scan protocol.
CLKCTRL
Clock control
module
Clocks
The clock control module, or CLKCTRL, generates the clock domains for all
components in the i.MX28 system. The crystal clock or PLL clock are the two
fundamental sources used to produce most of the clock domains. For lower
performance and reduced power consumption, the crystal clock is selected.
The PLL is selected for higher performance requirements but requires
increased power consumption. In most cases, when the PLL is used as the
source, a Phase Fractional Divider (PFD) can be programmed to reduce the
PLL clock frequency by up to a factor of 2.
DCP
Data
co-processor
Security
This module provides support for general encryption and hashing functions
typically used for security functions. Because its basic job is moving data
from memory to memory, it also incorporates a memory-copy (memcopy)
function for both debugging and as a more efficient method of copying data
between memory blocks than the DMA-based approach.
DFLPT
System control
Default
first-level page
table
The DFLPT provides a unique method of implementing the ARM MMU
first-level page table (L1PT) using a hardware-based approach.
DIGCTL
Digital control System control
and on-chip
RAM
The digital control module includes sections for controlling the SRAM, the
performance monitors, high-entropy pseudo-random number seed,
free-running microseconds counter, and other chip control functions.
DUART
Debug UART Connectivity
peripherals
The Debug UART performs the following data conversions:
• Serial-to-parallel conversion on data received from a peripheral device
• Parallel-to-serial conversion on data transmitted to the peripheral device
External
memory
interface
Connectivity
peripherals
The i.MX28 supports off-chip DRAM storage through the EMI controller,
which is connected to the four internal AHB/AXI busses. The EMI supports
multiple external memory types, including:
• 1.8-V Mobile DDR1 (LP-DDR1)
• Standard 1.8-V DDR2
• Low Voltage 1.5-V DDR2 (LV-DDR2)
Ethernet MAC Connectivity
Controller
peripherals
Ethernet MAC controller connected to the uDMA (unified DMA). Supports
10/100 Mbps with TCP/UDP/IP Acceleration and IEEE 1588 Functions; also
supports RMII or MII connectivity.
FlexCAN(2)
Controller
area network
module
Connectivity
peripherals
The Controller Area Network (CAN) protocol is a message based protocol
used for serial data. It was designed specifically for automotive but is also
used in industrial control and medical applications. The serial data bus runs
at 1 Mbps.
GPMI
General-purpose media
interface
Connectivity
peripherals
The General-Purpose Media Interface (GPMI) controller is a flexible NAND
flash controller with 8-bit data width, up to 50-MBps I/O speed and individual
chip select and DMA channels for up to 8 NAND devices. It also provides a
interface to 20-bit BCH for ECC.
EMI
ENET
i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1
Freescale Semiconductor
7
Table 4. i.MX28 Digital and Analog Modules (continued)
Block
Mnemonic
Block Name
Subsystem
Brief Description
HSADC
High-speed
ADC
Connectivity
peripherals
The high-speed ADC block is designed to sample an analog input with 12-bit
resolution and a sample rate of up to 2 Msps. The output of the HSADC block
can be moved to the external memory through APBH-DMA. A typical user
case of the HSADC is to work with the PWM block to drive an external linear
image scanner sensor.
I2C(2)
I2C module
Connectivity
peripherals
The I2C is a standard two-wire serial interface used to connect the chip with
peripherals or host controllers. The I2C operates up to 400 kbps in either I2C
master or I2C slave mode. Each I2C has a dedicated DMA channel and can
also controlled by CPU in PIO or PIO queue modes. It supports both 7-bit and
10-bit device address in master mode, and has programmable 7-bit address
in slave mode.
ICOLL
Interrupt
Collector
System control
The ARM9 CPU core has two interrupt input lines, IRQ and FIQ. The interrupt
collector (ICOLL) can steer any of 128 interrupt sources to either the FIQ or
IRQ line of the ARM9 CPU.
L2 Switch
3-Port L2
Switch
Network Control Programmable 3-Port Ethernet Switch with QOS
LCDIF
LCD Interface Multimedia
peripherals
The LCDIF provides display data for external LCD panels from simple
text-only displays to WVGA, 16/18/24 bpp color TFT panels. The LCDIF
supports all of these different interfaces by providing fully programmable
functionality and sharing register space, FIFOs, and ALU resources at the
same time. The LCDIF supports RGB (DOTCLK) modes as well as system
mode including both VSYNC and WSYNC modes.
LRADC
Low resolution Connectivity
ADC module peripherals
The sixteen-channel 12-bit low-resolution ADC (LRADC) block is used for
voltage measurement. Channels 0 – 6 measure the voltage on the seven
application-dependent LRADC pins. The auxiliary channels can be used for
a variety of uses, including a resistor-divider-based wired remote control,
external temperature sensing, touch-screen, and other measurement
functions.
OCOTP
Controller
On-chip OTP
controller
Security
The on-chip one-time-programmable (OCOTP) ROM serves the functions of
hardware and software capability bits, Freescale operations and unique-ID,
the customer-programmable cryptography key, and storage of various ROM
configuration bits.
PINCTRL
Pin control
and GPIO
System control
peripherals
Used for general purpose input/output to external ICs. Each GPIO bank
supports 32 bits of I/O.
i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1
8
Freescale Semiconductor
Table 4. i.MX28 Digital and Analog Modules (continued)
Block
Mnemonic
PMU
PWM(8)
Block Name
Subsystem
Brief Description
Power
Power
management management
Unit (DC-DC) system
The i.MX28 integrates a comprehensive power supply subsystem, including
the following features:
• One integrated DC-DC converter that supports Li-Ion battery.
• Four linear regulators directly power the supply rails from 5-V.
• Linear battery charger for Li-Ion cells.
• Battery voltage and brownout detection monitoring for VDDD, VDDA,
VDDIO, VDD4P2 and 5-V supplies.
• Integrated current limiter from 5-V power source.
• Reset controller.
• System monitors for temperature and speed.
• Generates USB-Host 5-V from Li-Ion battery (using PWM).
• Support for on-the-fly transitioning between 5-V and battery power.
• VDD4P2, a nominal 4.2-V supply, is available when the i.MX28 is
connected to a 5-V source and allows the DCDC to run from a 5-V source
with a depleted battery.
• The 4.2-V regulated output also allows for programmable current limits:
– Battery Charge current + DCDC input current < the 5-V current limit
– DCDC input current (which ultimately provides current to the on-chip
and off-chip loads) as the priority and battery charge current is
automatically reduced if the 5-V current limit is reached
Pulse width
modulation
There are eight PWM output controllers that can be used in place of GPIO
pins. Applications include HSADC driving signals and LED & backlight
brightness control. Independent output control of each phase allows 0, 1, or
high-impedance to be independently selected for the active and inactive
phases. Individual outputs can be run in lock step with guaranteed
non-overlapping portions for differential drive applications.
Connectivity
peripherals
PXP
Pixel Pipeline Multimedia
The pixel pipeline (PXP) is used to perform alpha blending of graphic or video
buffers with graphics data before sending to an LCD display. The PXP also
supports image rotation for hand-held devices that require both portrait and
landscape image support.
RTC
Real-time
clock, alarm,
watchdog
Clocks
The real-time clock (RTC) and alarm share a one-second pulse time domain.
The watchdog reset and millisecond counter run on a one-millisecond time
domain. The RTC, alarm, and persistent bits reside in a special power
domain (crystal domain) that remains powered up even when the rest of the
chip is in its powered-down state.
SAIF(2)
Serial audio
interface
Connectivity
peripherals
SAIF provides a half-duplex serial port for communication with a variety of
serial devices, including industry-standard codecs and DSPs. It supports a
continuous range of sample rates from 8 kHz–192 kHz using a
high-resolution fractional divider driven by the PLL. Samples are transferred
to/from the FIFO through the APBX DMA interface, a FIFO service interrupt,
or software polling.
SPDIF
SPDIF
Connectivity
peripherals
The Sony-Philips Digital Interface Format (SPDIF) transmitter module
transmits data according to the SPDIF digital audio interface standard
(IEC-60958).
i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1
Freescale Semiconductor
9
Table 4. i.MX28 Digital and Analog Modules (continued)
Block
Mnemonic
Block Name
Subsystem
Brief Description
SSP(4)
Synchronous
serial port
Connectivity
peripherals
The synchronous serial port is a flexible interface for inter-IC and removable
media control and communication. The SSP supports master operation of
SPI, Texas Instruments SSI; 1-bit, 4-bit, and 8-bit SD/SDIO/MMC and 1-bit
and 4-bit MS modes.
The SPI mode has enhancements to support 1-bit legacy MMC cards. SPI
master dual (2-bit) and quad (4-bit) mode reads are also supported. The SSP
also supports slave operation for the SPI and SSI modes. The SSP has a
dedicated DMA channel in the bridge and can also be controlled directly by
the CPU through PIO registers. Each of the four SSP modules is
independent of the other and can have separate SSPCLK frequencies.
TIMROT
Timers and
Rotary
Decoder
Timer
peripherals
This module implements four timers and a rotary decoder. The timers and
decoder can take their inputs from any of the pins defined for PWM, rotary
encoders, or certain divisions from the 32-kHz clock input. Thus, the PWM
pins can be inputs or outputs, depending on the application.
USBOTG
USBHOST
High-speed
USB
on-the-go
Connectivity
peripherals
The USB module provides high-performance USB On-The-Go (OTG) and
host functionality (up to 480 Mbps), compliant with the USB 2.0 specification
and the OTG supplement. The module has DMA capabilities for handling
data transfer between internal buffers and system memory.
When the OTG controller works in device mode, it can only work in FS or HS
mode. Two USB2.0 PHYs are also integrated (one for the OTG port, another
for the host port.)
Integrated
USB PHY
Connectivity
peripherals
The integrated USB 2.0 PHY macrocells are capable of connecting to USB
host/device systems at the USB low-speed (LS) rate of 1.5 Mbps, full-speed
(FS) rate of 12 Mbps or at the USB 2.0 high-speed (HS) rate of 480 Mbps.
The integrated PHYs provide a standard UTM interface. The USB_DP and
USB_DN pins connect directly to a USB connector.
USBPHY
2.1
Special Signal Considerations
Special signal considerations are listed in Table 5. The package contact assignment is found in Section 4,
“Package Information and Contact Assignments.” Signal descriptions are provided in the reference
manual.
Table 5. Signal Considerations
Signal
Descriptions
PSWITCH
The pin is used for chip power on or recovery. VDDIO can be applied to PSWITCH through a
10 kΩ resistor. This is necessary in order to enter the chip’s firmware recovery. The on-chip
circuitry prevents the actual voltage on the pin from exceeding acceptable levels.
VDDXTAL
This pin is an output of i.MX28. Should be coupled to ground with a 0.1 uF capacitor. User
should not supply external power to this pin.
BATTERY
This pin should be connected to the battery with minimal resistance. It provides charging current
to the battery.
See the “Power Supply” section of the reference manual for details.
i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1
10
Freescale Semiconductor
Table 5. Signal Considerations (continued)
Signal
Descriptions
DCDC_BATTERY
XTALI
XTALO
These analog pins are connected to an external 24 MHz crystal circuit. This crystal provides the
clock source for on-chip PLLs.
RTC_XTALO
RTC_XTALI
These analog pins are connected to an external 32.768/32.0 kHz crystal circuit. This crystal
provides clock source to the on-chip real-time counter circuits.
RESETN
This pin resets the chip if it is low. This pin is pulled up to VDDIO33 with an internal 10 kohm
resistor. No external pull up resistors are needed.
DEBUG
This pin is used for JTAG interface.
DEBUG=0: JTAG interface works for boundary scan.
DEBUG=1: JTAG interface works for ARM debugging.
TESTMODE
3
This pin is an input of i.MX28 that provides supply to the DCDC converter. It should be
connected to the battery with minimal resistance. See the “Power Supply” section of the
reference manual for details.
For Freescale factory use only. Must be externally connected to GND for normal operation.
Electrical Characteristics
This section provides the device-level and module-level electrical characteristics for the i.MX28.
3.1
i.MX28 Device-Level Conditions
This section provides the device-level electrical characteristics for the IC.
3.1.1
DC Absolute Maximum Ratings
Table 7 provides the DC absolute maximum operating conditions.
•
•
•
CAUTION
Stresses beyond those listed under Table 7 may cause permanent
damage to the device.
Exposure to absolute-maximum-rated conditions for extended periods
may affect device reliability.
Table 6 gives stress ratings only—functional operation of the device is
not implied beyond the conditions indicated in Table 8.
Table 6. DC Absolute Maximum Ratings
Parameter
Symbol
Min.
Max.
Units
BATT, VDD4P2V
–0.3
4.242
V
5-Volt Source Pin - transient, t<30ms, duty cycle <0.05%
VDD5V
–0.3
7.00
V
5 Volt Source Pin - static
VDD5V
–0.3
6.00
V
—
–0.3
BATT/2
V
Battery Pin
PSWITCH1
i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1
Freescale Semiconductor
11
Table 6. DC Absolute Maximum Ratings (continued)
Parameter
Symbol
Min.
Max.
Units
Analog Supply Voltage
VDDA
–0.3
2.10
V
Digital Core Supply Voltage
VDDD
–0.3
1.575
V
Non-EMI Digital I/O Supply
VDDIO
–0.3
3.63
V
VDDIO.EMI
–0.3
3.63
V
DCDC_BATT
–0.3
BATT
V
Input Voltage on Any Digital I/O Pin Relative to Ground
—
–0.3
VDDIO+0.3
V
Input Voltage on USB_DP and USB_DN Pins Relative to Ground3
—
–0.3
3.63
V
Analog I/O absolute maximum ratings (exceptions: XTALI, XTALO,
RTC_XTALI, RTC_XTALO)
—
–0.3
VDDIO+0.3
V
Storage Temperature
—
–40
125
°C
EMI Digital I/O Supply
DC-DC Converter2
1
VDDIO can be applied to PSWITCH through a 10 kΩ resistor. This is necessary in order to enter the chip’s firmware recovery
mode. (The on-chip circuitry prevents the actual voltage on the pin from exceeding acceptable levels.)
2 Application should include a Schottky diode between BATT and VDD4P2.
3 USB_DN and USB_DP can tolerate 5V for up to 24 hours. Note that while 5V is applied to USB_DN or USB_DP, LRADC
readings can be corrupted.
Table 7 shows the electrostatic discharge immunity.
Table 7. Electrostatic Discharge Immunity
289-Pin BGA Package
Tested Level
Human Body Model (HBM)
2 kV
Charge Device Model (CDM)
500 V
Note that HBM and CDM pass ESD testing per AEC-Q100.
i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1
12
Freescale Semiconductor
3.1.2
DC Operating Conditions
Table 8 provides the DC recommended operating conditions.
Table 8. Recommended Power Supply Operating Conditions
Parameter
Symbol
Min
Typ
Max
Units
Analog Core Supply Voltage
VDDA
1.62
—
2.10
V
Digital Core Supply Voltage
Specification dependent on frequency.1, 2
VDDD
1.35
—
1.55
V
3.0
1.7
—
—
3.6
1.9
1.7
1.425
1.8
1.5
1.9
1.625
BATT
DCDC_BATT
3.103
—
4.242
V
VDD5V Supply Voltage (5 V current < 100 mA)
—
TBD
5.00
5.25
V
VDD5V Supply Voltage (5V current ≥ 100 mA)
—
4.75
5.00
5.25
V
• 32-kHz RTC off, BATT = 4.2 V
—
—
11
30
µA
• 32-kHz RTC on, BATT = 4.2 V
—
—
13.5
30
µA
VDDIO33/VDDIO33_EMI/VDDI
Digital Supply Voltages:
• VDDIO33/VDDIO33_EMI
• VDDIO18
O18
V
VDDIO.EMI/VDDIO_EMIQ
EMI Digital I/O Supply Voltage:
• DDR2/mDDR
• LVDDR2
Battery / DCDC Input Voltage - BATT, DCDC_BATT
V
4
Offstate Current:
1
For optimum USB jitter performance, VDDD = 1.35 V or greater.
VDDD supply minimum voltage includes 75 mV guardband.
3 Tested with only the i.MX28 processor loading the MX28 PMU output rails during start up.
4 When the real-time clock is enabled, the chip consumes additional current in the OFF state to keep the crystal oscillator and
the real-time clock running.
2
Table 9 provides the DC operating temperature conditions.
Table 9. Operating Temperature Conditions
Parameter
Symbol
Min
Typ
Max
Units
Commercial Ambient Operating Temperature Range1, 2
TA
–20
—
70
°C
Commercial Junction Temperature Range1, 2
TJ
–20
—
85
°C
TA
–40
—
85
°C
TJ
–40
—
105
°C
Industrial Ambient Operating Temperature
Industrial Junction Temperature Range1, 2
1
Range1, 2
In most portable systems designs, battery and display specifications limits the operating range to well within these
specifications. Most battery manufacturers recommend enabling battery charge only when the ambient temperature is
between 0°C and 40°C. To ensure that battery charging does not occur outside the recommended temperature range, the
system ambient temperature may be monitored by connecting a thermistor to the LRADC0 or LRADC6 pin on the i.MX28.
i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1
Freescale Semiconductor
13
2
Maximum Ambient Operating Temperature may be limited due to on-chip power dissipation. TA (MAX) ≤ TJ - (ΘJA x PD) where:
TJ = Maximum Junction Temperature
ΘJA = Package Thermal Resistance. See Section 3.2, “Thermal Characteristics.”
PD = Total On-chip Power Dissipation =PVDD4P2 + PBatteryCharger + PDCDC + PLinearRegulators + PInternal. Depending
on the application, some of these power dissipation terms may not apply.
PVDD4P2 = VDD4P2 On-Chip Power Dissipation = (VDD5V - VDD4P2) x IDD4P2
PBatteryCharger = Battery Charger On-Chip Power Dissipation = (VDD5V - BATT) x ICHARGE
PDCDC = DC-DC Converter On-Chip Power Dissipation = (BATT x DCDC Input Current) x (1 - efficiency)
PLinearRegulators = Linear Regulator On-Chip Power Dissipation = (VDD5V - VDDIO) x (IDDIO + IDDA + IDDD + IDD1P5) +
(VDDIO - VDDA) x (IDDA + IDDD) + (VDDA - VDDD) x IDDD + (VDDA - VDD1P5) x IDD1P5
PInternal = Internal Digital On-Chip Power Dissipation = ~VDDD x IDDD
Table 10 provides the recommended analog operating conditions.
Table 10. Recommended Analog Operating Conditions
Parameter
Low Resolution ADC Input Impedance (CH0 - CH5)
Min
Typ
Max
Units
>1
—
—
MΩ
Table 11 shows the PSWITCH input characteristics. See the reference schematics for the recommended
PSWITCH button circuitry.
Table 11. PSWITCH Input Characteristics
Parameter
HW_PWR_STS_PSWITCH
Min
Max
Units
PSWITCH LOW LEVEL
0x00
0.00
0.30
V
PSWITCH MID LEVEL & STARTUP1
0x01
0.65
1.50
V
0x11
(1.1 * VDDXTAL) +
0.58
2.45
V
PSWITCH HIGH
LEVEL2
1
A MID LEVEL PSWITCH state can be generated by connecting the VDDXTAL output of the SOC to PSWITCH through a
switch.
2 PSWITCH acts like a high impedance input (>300 kΩ) when the voltage applied to it is less than 1.5V. However, above 1.5V
it becomes lower impedance. To simplify design, it is recommended that a 10 kΩ resistor to VDDIO be applied to PSWITCH
to set the HIGH LEVEL state (the PSWITCH input can tolerate voltages greater than 2.45 V as long as there is a 10 kΩ resistor
in series to limit the current).
Table 12 shows the power consumption.
Table 12. Power Consumption
Parameter
Min
Typ
Max
Units
Power Consumption: Conditions - TBD
—
TBD
—
mW
i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1
14
Freescale Semiconductor
Table 13 illustrates the power supply characteristics.
Table 13. Power Supply Characteristics
Parameter
Min
Typ
Max
Units
Output Voltage Accuracy (VDDIO, VDDA, VDDM, VDDD)1
–3
—
+3
%
VDDIO Maximum Output Current (VDDIO = 3.30 V, VDD5V = 4.75 V)2, 3
270
—
—
mA
VDDIO Maximum Output Current (VDDIO = 3.30 V, VDD5V = 4.40 V)2, 3
200
—
—
mA
VDDM Maximum Output Current (VDDM = 1.5 V)2
160
—
—
mA
VDDA Maximum Output Current (VDDA = 1.8 V)2, 3
225
—
—
mA
VDDD Maximum Output Current (VDDD = 1.2 V)2, 3
200
—
—
mA
Output Voltage Accuracy (DCDC_VDDIO, DCDC_VDDA,
DCDC_VDDD)1
–3
—
+3
%
DCDC_VDDD Maximum Output Current (VDDD = 1.55 V)4, 5
250
—
—
mA
200
—
—
mA
250
—
—
mA
–3
—
+3
%
VDD4P2 Output Current Limit Accuracy (VDD5V = 4.75 V,
ILIMIT=480 mA)7
TBD
480
TBD
mA
VDD4P2 Output Current Limit Accuracy (VDD5V=4.75 V,
ILIMIT=100 mA)7
TBD
100
TBD
mA
-2
—
+1
%
Linear Regulators
DCDC Converters
DCDC_VDDA Maximum Output Current (VDDA = 1.8
V)4, 5
DCDC_VDDIO Maximum Output Current (VDDIO = 3.15 V, 3.3 V < BATT
< 4.242 V)4, 5, 6
VDD4P2 Regulated Output
VDD4P2 Output Voltage Accuracy (TARGET=4.2V)1
Battery Charger
Final Charge Voltage Accuracy (TARGET=4.2 V)
1
2
3
4
5
6
No load.
Maximum output current measured when output voltage droops 100 mV from the programmed target voltage with no load
present.
Because the internal linear regulators are cascaded, it is not possible to simultaneously operate the VDDIO, VDDA, VDDM, and
VDDD linear regulators at the maximum specified load current. For example, the VDDIO linear regulator provides current to both
the VDDIO 3.3 V supply rail as well as the VDDM and VDDA linear regulator inputs. Likewise, the VDDA linear regulator provides
current to both the 1.8 V supply rail as well as the VDDD linear regulator input. The application designer should ensure the
following two conditions are met:
(VDDIO Load Current + VDDM Load Current + VDDA Load Current) < VDDIO Maximum Output Current
(VDDA Load Current + VDDD Load Current) < VDDA Maximum Output Current
DCDC Double FETs Enabled, Inductor Value = 15 μH.
The DCDC Converter is a triple output buck converter. The maximum output current capability of each output of the converter
is dependent on the loads on the other two outputs. For a given output, it may be possible to achieve a maximum output current
higher than that specified by ensuring the load on the other outputs is well below the maximum.
Assumes simultaneous load of IDDD = 250 mA@ 1.55 V and IDDA = 200 [email protected] V.
i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1
Freescale Semiconductor
15
7
Untuned.
3.1.2.1
Recommended Operating Conditions for Specific Clock Targets
Table 14 through Table 18 provide the recommended operating conditions for specific clock targets.
Table 14. System Clocks
Name
Min. Freq. (MHz)
Max. Freq. (MHz)
Description
clk_gpmi
—
TBD
General purpose memory interface clock domain
clk_ssp
—
TBD
SSP interface clock domain
Table 15. Recommended Operating States—289-Pin BGA Package
HW_
DIGCTRL
CPUCLK
/ clk_p
HW_
CLKCTRL
ARMCACH
E1
Frequency
(MHz)
CPU_DIV_CP
U
HW_
CLKCTRL
EMICLK
/ clk_emi
FRAC_
CPUFRC
/ PFD
Frequency
(MHz)
HBUS_DI
V
Frequency
(MHz)
EMI_
DIV_EMI
FRAC_
EMIFRAC
5
27
64
1
130.91
2
33
DDR2
mDDR
261.81
1
33
130.91
2
130.91
2
33
DDR2
mDDR
00
360
1
24
120.00
3
130.91
2
33
DDR2
mDDR
1.350
00
392.72
1
22
130.91
3
160.00
2
27
DDR2
mDDR
1.450
00
454.73
1
19
151.57
3
205.71
2
21
DDR2
mDDR
TBD
TBD
00
64
1.350
1.250
00
1.350
1.250
1.450
1.550
1
HW_
CLKCTRL
AHBCLK
/ clk_h
VDDD
(V)
VDDD
Brown-out
(V)
HW_
HW_
CLKCTRL CLKCTRL
Supported
DRAM
All timing control bit fields in HW_DIGCTRL_ARMCACHE should be set to the same value.
Table 16. Recommended Operating Conditions—CPU Clock (clk_p)
1
HW_CLKCTRL
CPUCLK / clk_p
FRAC_CPUFRC / PFD Frequency max (MHz)
Minimum
VDDD (V)
Minimum
VDDDBrown-out (V)
HW_DIGCTRL
ARMCACHE1
TBD
TBD
00
27 - 35
TBD
1.350
1.250
00
18 - 35
360
1.450
1.350
00
18 - 35
392.72
1.550
1.450
00
18 - 35
454.73
All timing control bit fields in HW_DIGCTRL_ARMCACHE should be set to the same value.
i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1
16
Freescale Semiconductor
Table 17. Recommended Operating Conditions—AHB Clock (clk_h)
1
Minimum
VDDD (V)
Minimum
VDDDBrown-out (V)
HW_DIGCTRL
ARMCACHE1
TBD
TBD
00
27 - 35
TBD
1.350
1.250
00
18 - 35
160
1.450
1.350
00
18 - 35
196
1.550
1.45
00
18 - 35
206
HW_CLKCTRL
AHBCLK / clk_h
FRAC_CPUFRC / PFD Frequency max (MHz)
All timing control bit fields in HW_DIGCTRL_ARMCACHE should be set to the same value.
Table 18. Frequency vs. Voltage for EMICLK—289-Pin BGA Package
3.1.3
EMICLK Fmax (MHz)
Minimum
VDDD (V)
Minimum
VDDDBrownout (V)
DDR2
mDDR
1.550
1.450
205.71
205.71
1.450
1.350
196.36
196.36
1.350
1.250
196.36
196.36
Fusebox Supply Current Parameters
Table 19 lists the fusebox supply current parameters.
Table 19. Fusebox Supply Current Parameters
Parameter
eFuse Program Current1
Current to program one eFuse bit
efuse_vddq=2.5V
eFuse Read Current2
Current to read an 8-bit eFuse word
vdd_fusebox = 3.3 V
1
2
Symbol
Min
Typ
Max
Units
Iprogram
21.39
25.05
33.54
mA
Iread
—
—
4.07
mA
The current Iprogram is during program time.
The current Iread is present for approximately 10 ns of the read access to the 8-bit word.
3.1.4
Interface Frequency Limits
Table 20 provides information for interface frequency limits.
Table 20. Interface Frequency Limits
Parameter
Min.
Typ.
Max.
Units
JTAG: TCK Frequency of Operation
—
—
10
MHz
OSC24M_XTAL Oscillator
—
24.000
—
MHz
OSC32K_XTAL Oscillator
—
32.768/32.0
—
KHz
i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1
Freescale Semiconductor
17
3.1.5
Power Modes
Table 21 describes the core, clock, and module settings for the different power modes of the processor.
Table 21. Power Mode Settings
Core/Clock/Module
3.1.6
Deep-Sleep
Standby
Run
ARM Core
Off
Off
On
USB0 PLL (System PLL)
Off
Off
On
OSC24M
Off
On
On
OSC32K
On
On
On
DCDC
Off
On
On
RTC
On
On
On
Other Modules
Off
On/Off
On/Off
Supply Power-Up/Power-Down Requirements
There is no special power-up sequence. After applying 5 V or battery in any order, the rest of the power
supplies are internally generated and automatically come up in a safe way.
There is no special power-down sequence. 5 V or the battery can be removed at any time.
3.1.7
Reset Timing
Because the i.MX28 is a PMU and an SoC, power-on reset is generated internally and there is no timing
requirement on external pins.
The i.MX28 can be reset by asserting the external pin RESETN for at least 100 mS and later deasserting
RESETN.
If the reset occurs while the device is only powered by the battery, then the reset kills all of the power
supplies and the system reboots on the assertion of PSWITCH. If auto-restart is set up ahead of time, the
system reboots immediately.
If the chip is powered by 5 V, then the reset serves to reset the digital sections of the chip. If the DCDC is
operating at the time of the reset, then power switches back to the default linear regulators powered by 5 V.
RESETN
At least 100ms
Figure 2. RESETN Timing
i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1
18
Freescale Semiconductor
3.2
Thermal Characteristics
The thermal resistance characteristics for the device are given in Table 22. These values are measured
under the following conditions:
• Two layer Substrate
• Substrate solder mask thickness: 0.025 mm
• Substrate metal thicknesses: 0.016 mm
• Substrate core thickness: 0.160 mm
• Core via I.D: 0.068 mm, Core via plating 0.016 mm
• Flag: trace style with ground balls under the die connected to the flag
• Die Attach: 0.033 mm non-conductive die attach, k = 0.3 W/m K
• Mold Compound: generic mold compound, k = 0.9 W/m K
Table 22. Thermal Resistance Data
Rating
Value
Unit
Junction to ambient1 natural convection
Single layer board
(1s)
RθJA
62
°C/W
Junction to ambient1 natural convection
Four layer board (2s2p)
RθJA
36
°C/W
Junction to ambient1 (@200 ft/min)
Single layer board
(1s)
RθJMA
53
°C/W
Junction to ambient1 (@200 ft/min)
Four layer board
(2s2p)
RθJMA
33
°C/W
RθJB
24
°C/W
RθJCtop
15
°C/W
ΨJT
3
°C/W
Junction to boards2
Junction to case
(top)3
Junction to package top4
Natural Convection
1
Junction-to-Ambient Thermal Resistance determined per JEDEC JESD51-2 and JESD51-6. Thermal test board meets
JEDEC specification for this package.
2
Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification
for the specified package.
3 Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is
used for the case temperature. Reported value includes the thermal resistance of the interface layer.
4 Thermal characterization parameter indicating the temperature difference between the package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written
as Psi-JT.
3.3
I/O DC Parameters
This section includes the DC parameters of the following I/O types:
• DDR I/O: Mobile DDR (LPDDR1), standard 1.8 V DDR2, and low-voltage 1.5 V DDR2
(LVDDR2)
• General purpose I/O (GPIO)
i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1
Freescale Semiconductor
19
3.3.1
DDR I/O DC Parameters
Table 23 shows the EMI digital pin DC characteristics.
NOTE
The current values and the I-V curves of the I/O DC characteristics are
estimated based on an overly conservative device model. They are updated
upon the measurement results of the first silicon.
Table 23. EMI Digital Pin DC Characteristics
Parameter
Symbol
Min.
Max.
Units
Input voltage high (dc)
VIH
VREF + 0.125
VDDIO_EMI + 0.3
V
Input voltage low (dc)
VIL
0.3
VREF – 0.125
V
Output voltage high (dc)
VOH
0.8 * VDDIO_EMI
—
V
Output voltage low (dc)
VOL
Output source current (dc)
LVDDR2 Mode
Output sink current (dc)
LVDDR2 Mode
Output source current (dc)
mDDR, DDR2 Mode
Output sink current (dc)
mDDR, DDR2 Mode
1
2
-
0.2 * VDDIO_EMI
V
1—Low
IOH
TBD
TBD
mA
IOH—Medium
TBD
TBD
mA
IOH—High
TBD
TBD
mA
IOL2—Low
TBD
TBD
mA
IOL—Medium
TBD
TBD
mA
IOL—High
TBD
TBD
mA
IOH—Low
TBD
TBD
mA
IOH—Medium
TBD
TBD
mA
IOH—High
TBD
TBD
mA
IOL—Low
TBD
TBD
mA
IOL—Medium
TBD
TBD
mA
IOL—High
TBD
TBD
mA
IOH is the output current at which the VOH specification is met.
IOL is the output current at which the VOL specification is met.
Table 24 shows the ON impedance of EMI drivers for different drive strengths.
Table 24. ON Impedance of EMI Drivers for Different Drive Strengths
Mode
Drive
Min. (Ω)
Typ. (Ω)
Max. (Ω)
1.5
LVDDR2
Low
TBD
TBD
TBD
Medium
TBD
TBD
TBD
High
TBD
TBD
TBD
i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1
20
Freescale Semiconductor
Table 24. ON Impedance of EMI Drivers for Different Drive Strengths (continued)
Mode
Drive
Min. (Ω)
Typ. (Ω)
Max. (Ω)
1.8
DDR2/mDDR
Low
TBD
TBD
TBD
Medium
TBD
TBD
TBD
High
TBD
TBD
TBD
Table 25 shows the external devices supported by the EMI.
Table 25. External Devices Supported by the EMI
1
2
DRAM Device
Max Load1, 2
Pad Voltage
DDR2
15 pF
1.8 V
mDDR
15 pF
1.8 V
LVDDR2
15 pF
1.5 V
Max load includes capacitive load due to PCB traces, pad capacitance and driver self-loading.
Setting is for worst case. Freescale’s EMI interface uses less powerful drivers than those typically used in mDDR devices. A
possible transmission-line effect on the PC board must be suppressed by minimizing the trace length combined with
Freescale’s slower edge-rate drivers. The i.MX28 provides up to 16 mA programmable drive strength. However, the 16-mA
mode is an experimental mode. With the 16-mA mode, the EMI function may be impaired by Simultaneous Switching Output
(SSO) noise. In general, the stronger the driver mode, the noisier the on-chip power supply. Freescale recommends not using
a stronger driver mode than is required. Because on-chip power and ground noise is proportional to the inductance of its return
path, users should make their best effort to reduce inductance between the EMI power and ground balls and the PC board
power and ground planes.
3.3.2
GPIO I/O DC Parameters
Max load includes capacitive load due to PCB traces, pad capacitance and driver self-loading. For the
internal pull up setting of each pad, see the “Pin Control and GPIO” section of the reference manual.
Table 26 shows the digital pin DC characteristics for GPIO in 3.3-V mode. Measurements are valid for
eight pins loaded using the 4mA driver, four pins loaded using the 8mA driver, and two pins loaded using
either the 12mA or 16mA driver.
Table 26. Digital Pin DC Characteristics for GPIO in 3.3-V Mode
Parameter
Symbol
Min
Max
Units
Input voltage high (dc)
VIH
2
VDDIO
V
Input voltage low (dc)
VIL
—
0.8
V
Output voltage high (dc)
VOH
0.8 × VDDIO
—
V
Output voltage low (dc)
VOL
—
0.4
V
Output source current1 (dc)
gpio
IOH – Low
-5.0
—
mA
IOH – Medium
-9.5
—
mA
IOH – High
-11.4
—
mA
i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1
Freescale Semiconductor
21
Table 26. Digital Pin DC Characteristics for GPIO in 3.3-V Mode (continued)
Parameter
Symbol
Min
Max
Units
Output sink current1 (dc)
gpio
IOL – Low
3.8
—
mA
IOL – Medium
7.7
—
mA
IOL – High
9.0
—
mA
IOH – Low
-9.2
—
mA
IOH – High
-15.2
—
mA
IOL – Low
7.6
—
mA
IOL – High
12.0
—
mA
10-K pull-up resistance2
Rpu10k
8
12
KΩ
47-K pull-up resistance2
Rpu47k
39
56
KΩ
Output source current1 (dc)
gpio_clk
Output sink current1 (dc)
gpio_clk
1
The conditions of the current measurements for all different drives are as follows:
IOL: at 0.4 V
IOH: at VDDIO * 0.8 V
Maximum corner for 3.3 V mode: 3.6 V, -40°C, fast process.
Minimum corner for 3.3 V mode: 3.0 V, 105°C, slow process
8 gpio pins (LCD_D0-D7) and 2 gpio_clk pins (LCD_DOTCLK and LCD_WR_RWN) simultaneously loaded.
2 See the i.MX28 reference manual for detailed pull-up configuration of each I/O.
i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1
22
Freescale Semiconductor
Table 27 shows the digital pin DC characteristics for GPIO in 1.8 V mode.
Table 27. Digital Pin DC Characteristics for GPIO in 1.8 V Mode
Symbol
Min
Max
Units
Input voltage high (DC)
VIH
0.7 × VDDIO18
VDDIO18
V
Input voltage low (DC)
VIL
—
0.3 × VDDIO18
V
Output voltage high (DC)
VOH
0.8 * VDDIO18
—
V
Output voltage low (DC)
VOL
—
0.2 × VDDIO18
V
IOH – low
-2.2
—
mA
IOH – medium
-3.5
—
mA
IOH – high
-4.0
—
mA
IOL – low
3.3
—
mA
IOL – medium
7.0
—
mA
IOL – high
7.5
—
mA
IOH – low
-4.2
—
mA
IOH – high
-6.0
—
mA
Output source current
(DC)
gpio
1
Output sink current1
(DC)
gpio
current1
Output source
(DC)
gpio_clk
Output sink current1
(DC)
gpio_clk
IOL – low
6.8
—
mA
IOL – high
11.5
—
mA
10-K pull-up resistance2
Rpu10k
8
12
KΩ
47-K pull-up resistance2
Rpu47k
39
56
KΩ
1
The condition of the current measurements for all different drives are as follows:
Maximum corner for 1.8 V mode: 1.9 V, -40°C, Fast process.
Minimum corner for 1.8 V mode: 1.7 V, 105°C, Slow process.
1 gpio pin (GPMI_D0) and 1 gpio_clk pin (GPMI_WRN) simultaneously loaded.
2 See the i.MX28 reference manual for detailed pull-up configuration of each I/O.
i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1
Freescale Semiconductor
23
3.4
I/O AC Timing and Parameters
Figure 3 and Figure 4 show the Driver Used for AC Simulation Testpoint and the Output Pad Transition
Waveform.
Driver Used for AC simulation
Testpoint
Figure 3. Driver Used for AC Simulation Testpoint
Output Pad Transition Waveform
VDDIO
80%
20%
Figure 4. Output Pad Transition Waveform
Table 28 shows the base GPIO AC timing and parameters.
Table 28. Base GPIO
Parameters
Symbol
Test Voltage
Test Capacitance
Min
Rise/Fall
MaxRise/Fall
Units
Notes
Duty cycle
Fduty
—
—
—
—
%
—
Output pad transition
times (maximum drive)
tpr
1.7~1.9V
10pF
0.82
0.91
1.93
1.97
ns
—
1.7~1.9V
20pF
1.18
1.22
2.69
2.71
—
1.7~1.9V
50pF
2.11
2.03
4.62
4.44
—
3.0~3.6V
10pF
1.04
1.08
2.46
2.18
—
3.0~3.6V
20pF
1.42
1.5
3.29
3
—
3.0~3.6V
50pF
2.46
2.61
5.34
5.12
—
i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1
24
Freescale Semiconductor
Table 28. Base GPIO (continued)
Min
Rise/Fall
Parameters
Symbol
Test Voltage
Test Capacitance
Output pad transition
times (medium drive)
tpr
1.7~1.9V
10pF
1.02
1.08
2.34
2.38
1.7~1.9V
20pF
1.51
1.5
3.34
3.28
—
1.7~1.9V
50pF
2.91
2.62
6.24
5.67
—
3.0~3.6V
10pF
1.26
1.29
2.9
2.6
—
3.0~3.6V
20pF
1.8
1.88
4
3.67
—
3.0~3.6V
50pF
3.3
3.46
6.91
6.64
—
1.7~1.9V
10pF
1.62
1.68
3.65
3.68
1.7~1.9V
20pF
2.55
2.45
5.59
5.37
—
1.7~1.9V
50pF
5.42
4.62
11.46 10.01
—
3.0~3.6V
10pF
1.95
2.12
4.43
4.25
—
3.0~3.6V
20pF
2.96
3.21
6.36
6.25
—
3.0~3.6V
50pF
5.89
6.39
12.02 12.18
—
1.7~1.9V
10pF
1.39
1.25
0.53
0.52
1.7~1.9V
20pF
0.97
0.93
0.38
0.38
—
1.7~1.9V
50pF
0.54
0.56
0.22
0.23
—
3.0~3.6V
10pF
2.08
2.00
0.73
0.83
—
3.0~3.6V
20pF
1.52
1.44
0.55
0.60
—
3.0~3.6V
50pF
0.88
0.83
0.34
0.35
—
1.7~1.9V
10pF
1.12
1.06
0.44
0.43
1.7~1.9V
20pF
0.75
0.76
0.31
0.31
—
1.7~1.9V
50pF
0.39
0.44
0.16
0.18
—
3.0~3.6V
10pF
1.71
1.67
0.62
0.69
—
3.0~3.6V
20pF
1.20
1.15
0.45
0.49
—
3.0~3.6V
50pF
0.65
0.62
0.26
0.27
—
1.7~1.9V
10pF
1.17
1.13
0.47
0.46
1.7~1.9V
20pF
0.75
0.78
0.30
0.32
—
1.7~1.9V
50pF
0.35
0.41
0.15
0.17
—
3.0~3.6V
10pF
1.11
1.02
0.41
0.42
—
3.0~3.6V
20pF
0.73
0.67
0.28
0.29
—
3.0~3.6V
50pF
0.37
0.34
0.15
0.15
—
1.7 V–1.9 V
—
100
75
3.0 V–3.6 V
—
100
50
Output pad transition
times (low drive)
tpr
Output pad slew rate
(maximum drive)
tps
Output pad slew rate
(medium drive)
tps
Output pad slew rate
(low drive)
tps
Input pad average
hysteresis
tih
MaxRise/Fall
Units
Notes
ns
—
ns
V/ns
V/ns
V/ns
mV
—
—
—
—
—
—
i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1
Freescale Semiconductor
25
Table 29 shows the F-type GPIO AC timing and parameters.
Table 29. F-type GPIO
Parameters
Symbol
Test Voltage
Duty cycle
Fduty
—
—
Output pad transition
times (maximum
drive)
tpr
1.7~1.9V
10pF
0.58
0.61
1.29
1.33
1.7~1.9V
20pF
0.89
0.88
1.94
1.88
—
1.7~1.9V
50pF
1.83
1.59
3.88
3.39
—
3.0~3.6V
10pF
0.71
0.68
1.47
1.34
—
3.0~3.6V
20pF
1.02
1.04
2.11
1.99
—
3.0~3.6V
50pF
1.98
2.09
3.97
3.96
—
1.7~1.9V
10pF
0.76
0.76
1.68
1.61
1.7~1.9V
20pF
1.23
1.13
2.63
2.38
—
1.7~1.9V
50pF
2.66
2.18
5.61
4.6
—
3.0~3.6V
10pF
0.9
0.88
1.84
1.7
—
3.0~3.6V
20pF
1.36
1.4
2.76
2.67
—
3.0~3.6V
50pF
2.85
3.02
5.59
5.67
—
1.7~1.9V
10pF
1.32
1.26
2.88
2.72
1.7~1.9V
20pF
2.27
1.98
4.84
4.23
—
1.7~1.9V
50pF
5.23
4.13
10.95
8.8
—
3.0~3.6V
10pF
1.46
1.55
3.05
3
—
3.0~3.6V
20pF
2.46
2.62
4.92
5.02
—
3.0~3.6V
50pF
5.56
5.96
10.78
11.22
—
1.7~1.9V
10pF
1.97
1.87
0.79
0.77
1.7~1.9V
20pF
1.28
1.30
0.53
0.54
—
1.7~1.9V
50pF
0.62
0.72
0.26
0.30
—
3.0~3.6V
10pF
3.04
3.18
1.22
1.34
—
3.0~3.6V
20pF
2.12
2.08
0.85
0.90
—
3.0~3.6V
50pF
1.09
1.03
0.45
0.45
—
1.7~1.9V
1.7~1.9V
10pF
20pF
1.50
0.93
1.50
1.01
0.61
0.39
0.63
0.43
1.7~1.9V
50pF
0.43
0.52
0.18
0.22
—
3.0~3.6V
10pF
2.40
2.45
0.98
1.06
—
3.0~3.6V
20pF
1.59
1.54
0.65
0.67
—
3.0~3.6V
50pF
0.76
0.72
0.32
0.32
—
Output pad transition
times (medium drive)
Output pad transition
times (low drive)
Output pad slew rate
(maximum drive)
Output pad slew rate
(medium drive)
tpr
tpr
tps
tps
Test Capacitance Min Rise/Fall Max Rise/Fall
—
—
Units
Notes
%
—
ns
—
ns
ns
ns
ns
—
—
—
—
—
i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1
26
Freescale Semiconductor
Table 29. F-type GPIO (continued)
Parameters
Symbol
Test Voltage
Output pad slew rate
(low drive)
tps
1.7~1.9V
1.7~1.9V
10pF
20pF
1.44
0.84
1.51
0.96
0.59
0.35
0.63
0.40
1.7~1.9V
50pF
0.36
0.46
0.16
0.19
—
3.0~3.6V
10pF
1.48
1.39
0.59
0.60
—
3.0~3.6V
20pF
0.88
0.82
0.37
0.36
—
3.0~3.6V
50pF
0.39
0.36
0.17
0.16
—
1.7 V–1.9 V
—
100
75
3.0 V–3.6 V
—
100
50
Input pad average
hysteresis
tih
Test Capacitance Min Rise/Fall Max Rise/Fall
Units
Notes
ns
—
—
mV
—
—
Table 30 shows the CLK-type GPIO AC timing and parameters.
Table 30. CLK-Type GPIO
Parameters
Symbol
Duty cycle
Fduty
—
—
Output pad transition
times (maximum
drive)
tpr
1.7~1.9V
10pF
0.48
0.52
1.08
1.12
1.7~1.9V
20pF
0.72
0.74
1.56
1.56
—
1.7~1.9V
50pF
1.41
1.28
3.04
2.7
—
3.0~3.6V
10pF
0.61
0.57
1.25
1.12
—
3.0~3.6V
20pF
0.85
0.85
1.73
1.63
—
3.0~3.6V
50pF
1.56
1.63
3.13
3.08
—
1.7~1.9V
10pF
0.76
0.76
1.67
1.62
1.7~1.9V
20pF
1.22
1.14
2.64
2.41
—
1.7~1.9V
50pF
2.66
2.2
5.61
4.62
—
3.0~3.6V
10pF
0.9
0.89
1.83
1.72
—
3.0~3.6V
20pF
1.37
1.41
2.77
2.69
—
3.0~3.6V
50pF
2.85
3.03
5.59
5.72
—
1.7~1.9V
10pF
2.38
2.19
0.94
0.91
1.7~1.9V
20pF
1.58
1.54
0.65
0.65
—
1.7~1.9V
50pF
0.81
0.89
0.34
0.38
—
3.0~3.6V
10pF
3.54
3.79
1.44
1.61
—
3.0~3.6V
20pF
2.54
2.54
1.04
1.10
—
3.0~3.6V
50pF
1.38
1.33
0.58
0.58
—
Output pad transition
times (medium drive)
tpr
Output pad slew rate
(maximum drive)
tps
Test Voltage Test Capacitance
Min Rise/Fall
Max Rise/Fall
units
Notes
—
—
%
—
ns
—
ns
ns
—
—
i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1
Freescale Semiconductor
27
Table 30. CLK-Type GPIO (continued)
Parameters
Symbol
Output pad slew rate
(medium drive)
tps
Input pad average
hysteresis
3.5
tih
Test Voltage Test Capacitance
Min Rise/Fall
Max Rise/Fall
units
Notes
ns
—
1.7~1.9V
10pF
1.50
1.50
0.61
0.63
1.7~1.9V
20pF
0.93
1.00
0.39
0.42
—
1.7~1.9V
50pF
0.43
0.52
0.18
0.22
—
3.0~3.6V
10pF
2.40
2.43
0.98
1.05
—
3.0~3.6V
20pF
1.58
1.53
0.65
0.67
—
3.0~3.6V
50pF
0.76
0.71
0.32
0.31
—
1.7 V–1.9 V
—
100
75
3.0 V–3.6 V
—
100
50
mV
—
—
Module Timing and Electrical Parameters
3.5.1
ADC Electrical Specifications
This section describes the electrical specifications, including DC and AC information, of Low-Resolution
ADC (LRADC) and High-Speed ADC (HSADC).
3.5.1.1
LRADC Electrical Specifications
Table 31 shows the electrical specifications for the LRADC.
Table 31. LRADC Electrical Specifications
Parameter
Conditions
Min.
Typ.
Max.
Unit
—
0.5
—
pF
AC Electrical Specification
Input capacitance (Cp)
No pin/pad capacitance included
Resolution
—
Maximum sampling rate1
(fs)
—
Power-up time2
—
12
—
—
bits
428
1
kHz
sample
cycles
DC Electrical Specification
DC input voltage
0
3
Current consumption
VDDA
VDDD
—
1.85
V
—
TBD
—
mA
mA
200
—
50000
Ω
Touchscreen Interface
Expected plate resistance
1
—
There is no sample and hold circuit in LRADC, so it is only for DC input voltage or ones with very small slope.
i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1
28
Freescale Semiconductor
2
3
This comprises only the required initial dummy conversion cycle, NOT including the Analog part power-up time.
This value only includes the ADC and the driver switches, but it does not take into account the current consumption in the
touchscreen plate. For example, if the plate resistance is 200 ohm, the total current consumption is about 11 mA.
3.5.1.2
HSADC Electrical Specification
Table 32 shows the electrical specifications for the HSADC
Table 32. HSADC Electrical Specification
Parameter
Conditions
Min.
Typ.
Max.
—
0.5
—
Unit
AC Electrical Specification
No pin/pad capacitance included
Input sampling
capacitance (Cs)
Resolution
—
Maximum sampling rate
(fs)
—
Power-up time
—
12
—
pF
bits
—
2
1
MHz
sample
cycles
DC Electrical Specification
DC input voltage
—
0.5
—
Current Consumption
VDDA
VDDD
—
—
TBD
VDDA-0.5
V
—
mA
mA
DNL
fin = 1 kHz
—
—
TBD
LSB
INL
fin = 1kHz
—
—
TBD
LSB
3.5.2
DPLL Electrical Specifications
This section includes descriptions of the USB PLL electrical specifications and Ethernet PLL electrical
specifications.
3.5.2.1
USB PLL Electrical Specifications
The i.MX28 integrates a high-frequency USB PLL that provides the 480-MHz clock for the USB and other
system blocks.
Table 33 lists the USB PLL output electrical specifications.
Table 33. USB PLL Specifications
Parameter
PLL lock time
Test Conditions
Min
Typ
Max
Unit
—
—
—
10
µs
i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1
Freescale Semiconductor
29
3.5.2.2
Ethernet PLL Electrical Specifications
i.MX28 provides a 50-MHz/25-MHz output clock, called the Ethernet PLL output.
Table 34 lists the Ethernet PLL output electrical specifications.
Table 34. Ethernet PLL Specifications
Parameter
Test Conditions
Min
Typ
Max
Unit
Output Duty Cycle
—
45
50
55
%
PLL lock time
—
—
—
10
µs
Cycle to cycle jitter
—
—
25
—
ps
Clock output frequency tolerance1
—
—
—
+/-20
ppm
1
This Ethernet output clock tolerance specification is the contribution from the PLL only and assumes a perfect 24 MHz
clock/crystal source with 0 ppm deviation. The 24 MHz crystal frequency tolerance/deviation should be added to this number
for the total Ethernet clock output frequency tolerance.
i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1
30
Freescale Semiconductor
3.5.3
EMI AC Timing
This section includes descriptions of the electrical specifications of EMI module which interfaces external
DDR2 and Mobile-DDR1 (LP-DDR1) memory devices.
3.5.3.1
EMI Command & Address AC Timing
Figure 5 and Table 35 specify the timing related to the address and command pins that interfaces DDR2
and Mobile-DDR1 memory devices.
DDR2
DDR3
EMI_CLKN
EMI_CLK
DDR1
EMI_CE0N
DDR4
DDR5
EMI_RASN
EMI_CASN
DDR4
EMI_WEN
DDR5
DDR5
DDR4
bank
row
EMI_ADDR
bank
column
Figure 5. EMI Command/Address AC Timing
Table 35. EMI Command/Address AC Timing
ID
Description
DDR1
CK cycle time
DDR2
CK high level width
Symbol
Min.
Max.
Unit
tCK
4.86
—
ns
tCH
0.5 tCK
–0.5
0.5 tCK
+ 0.5
ns
i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1
Freescale Semiconductor
31
Table 35. EMI Command/Address AC Timing (continued)
ID
Description
DDR3
CK low level width
DDR4
Address and control output setup time
DDR5
Address and control output hold time
3.5.3.2
Symbol
Min.
Max.
Unit
tCL
0.5 tCK
–0.5
0.5 tCK
+ 0.5
ns
tIS
0.5 tCK – 1
0.5 tCK
+ 0.5
ns
tIH
0.5 tCK – 1
0.5 tCK
+ 0.5
ns
DDR Output AC Timing
Figure 6 and Table 36 show the DDR output AC timing defined for all DDR types: LPDDR1, standard
DDR2 (1.8 V), and LVDDR2 (1.5 V)
EMI_CLKN
EMI_CLK
DDR10
DDR11
DDR12
EMI_DQSN
EMI_DQS
DDR13
EMI_DQ & EMI_DQM
DDR14
d0
d1
d2
d3
DDR15
DDR16
Figure 6. DDR Output AC Timing
Table 36. DDR Output AC Timing
ID
Description
Symbol
Min
Max
Unit
DDR10
Positive DQS latching edge to associated CK edge
tDQSS
–0.5
0.5
ns
DDR11
DQS falling edge from CK rising edge—hold time
tDSH
0.5 tCK
–0.5
0.5 tCK
+ 0.5
ns
DDR12
DQS falling edge to CK rising edge—setup time
tDSS
0.5 tCK
–0.5
0.5 tCK
+ 0.5
ns
i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1
32
Freescale Semiconductor
Table 36. DDR Output AC Timing (continued)
ID
Description
Symbol
Min
Max
Unit
DDR13
DQS output high pulse width
tDQSH
0.5 tCK
–0.5
0.5 tCK
+ 0.5
ns
DDR14
DQS output low pulse width
tDQSL
0.5 tCK
–0.5
0.5 tCK
+ 0.5
ns
DDR15
DQ & DQM output setup time relative to DQS
tDS
1/4 tCK
–0.8
1/4 tCK
–0.5
ns
DDR16
DQ & DQM output hold time relative to DQS
tDH
1/4 tCK
–0.8
1/4 tCK
–0.5
ns
3.5.3.3
DDR2 Input AC Timing
Figure 7 and Table 37 show input AC timing for standard DDR2 and LVDDR2.
EMI_CLKN
EMI_CLK
DDR20
EMI_DQSN
EMI_DQS
DDR22
DDR21
EMI_DQ
d0
d1
d2
d3
Figure 7. DDR2 Input AC Timing
Table 37. DDR2 Input AC Timing
ID
DDR20
Description
Positive DQS latching edge to associated CK edge
DDR21
Symbol
DQS to DQ input hold time
Max
Unit
tDQSCK
–0.5
0.5
ns
tDQSQ
0.25 tCK
–0.85
0.25 tCK
–0.5
ns
tQH
0.25 tCK
+0.75
0.25 tCK
+1
ns
DQS to DQ input skew
DDR22
Min
i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1
Freescale Semiconductor
33
3.5.3.4
LPDDR1 Input AC Timing
Figure 8 and Table 38 show input AC timing for LPDDR1.
EMI_CLKN
EMI_CLK
DDR20
EMI_DQSN
EMI_DQS
DDR22
DDR21
EMI_DQ
d0
d1
d2
d3
Figure 8. LPDDR1 Input AC Timing
Table 38. DDR2 Input AC Timing
ID
Description
Symbol
Min
Max
Unit
DDR20
Positive DQS latching edge to associated CK edge
tDQSCK
2
6
ns
DDR21
DQS to DQ input skew
tDQSQ
0.25 tCK
–0.85
0.25 tCK
–0.5
ns
DDR22
DQS to DQ input hold time
tQH
0.25 tCK
+0.75
0.25 tCK
+1
ns
3.5.4
Ethernet MAC Controller (ENET) Timing
The ENET is designed to support both 10- and 100-Mbps Ethernet networks compliant with IEEE 802.3.
An external transceiver interface and transceiver function are required to complete the interface to the
media. The ENET supports 10/100-Mbps MII (18 pins altogether), 10/100-Mbps RMII (10 pins, including
serial management interface), for connection to an external Ethernet transceiver. All signals are compatible
with transceivers operating at a voltage of 3.3 V.
The following subsections describe the timing for MII and RMII modes.
i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1
34
Freescale Semiconductor
3.5.4.1
ENET MII Mode Timing
This subsection describes MII receive, transmit, asynchronous inputs, and serial management signal
timings.
3.5.4.1.1
MII Receive Signal Timing (ENET0_RXD[3:0], ENET0_RX_DV, ENET0_RX_ER,
and ENET0_RX_CLK)
The receiver functions correctly up to an ENET0_RX_CLK maximum frequency of 25 MHz + 1%. There
is no minimum frequency requirement. Additionally, the processor clock frequency must exceed twice the
ENET0_RX_CLK frequency.
Figure 9 shows MII receive signal timings. Table 39 describes the timing parameters (M1–M4) shown in
the figure.
M3
ENET0_RX_CLK (input)
M4
ENET0_RXD[3:0] (inputs)
ENET0_RX_DV
ENET0_RX_ER
M1
M2
Figure 9. MII Receive Signal Timing Diagram
Table 39. MII Receive Signal Timing
Characteristic1
ID
Min.
Max.
Unit
M1
ENET0_RXD[3:0], ENET0_RX_DV, ENET0_RX_ER to
ENET0_RX_CLK setup
5
—
ns
M2
ENET0_RX_CLK to ENET0_RXD[3:0], ENET0_RX_DV,
ENET0_RX_ER hold
5
—
ns
M3
ENET0_RX_CLK pulse width high
35%
65%
ENET0_RX_CLK
period
M4
ENET0_RX_CLK pulse width low
35%
65%
ENET0_RX_CLK
period
1
ENET0_RX_DV, ENET0_RX_CLK, and ENET0_RXD0 have the same timing in 10 Mbps 7-wire interface mode.
3.5.4.1.2
MII Transmit Signal Timing (ENET0_TXD[3:0], ENET0_TX_EN,
ENET0_TX_ER, and ENET0_TX_CLK)
The transmitter functions correctly up to an ENET0_TX_CLK maximum frequency of 25 MHz + 1%.
There is no minimum frequency requirement. Additionally, the processor clock frequency must exceed
twice the ENET0_TX_CLK frequency.
i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1
Freescale Semiconductor
35
Figure 10 shows MII transmit signal timings. Table 40 describes the timing parameters (M5–M8) shown
in the figure.
M7
ENET0_TX_CLK (input)
M5
M8
ENET0_TXD[3:0] (outputs)
ENET0_TX_EN
ENET0_TX_ER
M6
Figure 10. MII Transmit Signal Timing Diagram
Table 40. MII Transmit Signal Timing
Characteristic1
ID
Min.
Max.
Unit
M5
ENET0_TX_CLK to ENET0_TXD[3:0], ENET0_TX_EN,
ENET0_TX_ER invalid
5
—
ns
M6
ENET0_TX_CLK to ENET0_TXD[3:0], ENET0_TX_EN,
ENET0_TX_ER valid
—
20
ns
M7
ENET0_TX_CLK pulse width high
35%
65%
ENET0_TX_CLK
period
M8
ENET0_TX_CLK pulse width low
35%
65%
ENET0_TX_CLK
period
1 ENET0_TX_EN,
ENET0_TX_CLK, and ENET0_TXD0 have the same timing in 10-Mbps 7-wire interface mode.
3.5.4.1.3
MII Asynchronous Inputs Signal Timing (ENET0_CRS and ENET0_COL)
Figure 11 shows MII asynchronous input timings. Table 41 describes the timing parameter (M9) shown in
the figure.
ENET0_CRS, ENET0_COL
M9
Figure 11. MII Async Inputs Timing Diagram
Table 41. MII Asynchronous Inputs Signal Timing
ID
M91
1
Characteristic
ENET0_CRS to ENET0_COL minimum pulse width
Min.
Max.
Unit
1.5
—
ENET0_TX_CLK period
ENET0_COL has the same timing in 10-Mbit 7-wire interface mode.
i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1
36
Freescale Semiconductor
3.5.4.1.4
MII Serial Management Channel Timing (ENET0_MDIO and ENET0_MDC)
The MDC frequency is designed to be equal to or less than 2.5 MHz to be compatible with the IEEE 802.3
MII specification. However the ENET can function correctly with a maximum MDC frequency of
15 MHz.
Figure 12 shows MII asynchronous input timings. Table 42 describes the timing parameters (M10–M15)
shown in the figure.
M14
M15
ENET0_MDC (output)
M10
ENET0_MDIO (output)
M11
ENET0_MDIO (input)
M12
M13
Figure 12. MII Serial Management Channel Timing Diagram
Table 42. MII Serial Management Channel Timing
ID
Characteristic
Min.
Max.
Unit
M10
ENET0_MDC falling edge to ENET0_MDIO output invalid (min.
propagation delay)
0
—
ns
M11
ENET0_MDC falling edge to ENET0_MDIO output valid (max.
propagation delay)
—
5
ns
M12
ENET0_MDIO (input) to ENET0_MDC rising edge setup
18
—
ns
M13
ENET0_MDIO (input) to ENET0_MDC rising edge hold
0
—
ns
M14
ENET0_MDC pulse width high
40%
60%
ENET0_MDC period
M15
ENET0_MDC pulse width low
40%
60%
ENET0_MDC period
3.5.4.2
RMII Mode Timing
In RMII mode, ENET_CLK is used as the REF_CLK, which is a 50 MHz ± 50 ppm continuous reference
clock. ENET0_RX_DV is used as the CRS_DV in RMII. Other signals under RMII mode include
ENET0_TX_EN, ENET0_TXD[1:0], ENET0_RXD[1:0] and ENET0_RX_ER.
i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1
Freescale Semiconductor
37
Figure 13 shows RMII mode timings. Table 43 describes the timing parameters (M16–M21) shown in the
figure.
M16
M17
ENET_CLK (input)
M18
ENET0_TXD[1:0] (output)
ENET0_TX_EN
M19
CRS_DV (input)
ENET0_RXD[1:0]
ENET0_RX_ER
M20
M21
Figure 13. RMII Mode Signal Timing Diagram
Table 43. RMII Signal Timing
ID
Characteristic
Min.
Max.
Unit
M16
ENET_CLK pulse width high
35%
65%
ENET_CLK period
M17
ENET_CLK pulse width low
35%
65%
ENET_CLK period
M18
ENET_CLK to ENET0_TXD[1:0], ENET0_TX_EN invalid
3
—
ns
M19
ENET_CLK to ENET0_TXD[1:0], ENET0_TX_EN valid
—
12
ns
M20
ENET0_RXD[1:0], CRS_DV(ENET0_RX_DV), ENET0_RX_ER to
ENET_CLK setup
2
—
ns
M21
ENET_CLK to ENET0_RXD[1:0], ENET0_RX_DV, ENET0_RX_ER hold
2
—
ns
3.5.5
Coresight ETM9 AC Interface Timing
The following timing specifications are given as a guide for a TPA that supports TRACECLK frequencies
up to 80 MHz.
3.5.5.1
TRACECLK Timing
This section describes TRACECLK timings.
i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1
38
Freescale Semiconductor
Figure 14 shows TRACECLK signal timings. Table 44 describes the timing parameters shown in the
figure.
Figure 14. TRACECLK Signal Timing Diagram
Table 44. MII Receive Signal Timing
Characteristic1
ID
Min.
Max.
Unit
Tr
Clock and data raise time
3
—
ns
Tf
Clock and data fall time
3
—
ns
Twh
High pulse wide
2
—
ns
Twl
Low pulse wide
2
—
ns
Tcyc
Clock period
12.5
—
ns
3.5.5.2
Trace Data Signal Timing
Figure 15 shows the setup and hold requirements of the trace data pins with respect to TRACECLK.
Table 45 describes the timing parameters shown in the figure.
Figure 15. MII Transmit Signal Timing Diagram
Table 45. MII Transmit Signal Timing
Characteristic1
ID
Min.
Max.
Unit
Ts
Data setup
2
—
ns
Th
Data hold
2
—
ns
i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1
Freescale Semiconductor
39
3.5.6
FlexCAN AC Timing
Table 46 and Table 47 show voltage requirements for the FlexCAN transceiver Tx and Rx pins.
Table 46. Tx Pin Characteristics
1
Parameter
Symbol
Min.
Typ.
Max.
Units
High-level output voltage
VOH
2
—
Vcc1 + 0.3
V
Low-level output voltage
VOL
—
0.8
—
V
Vcc = +3.3 V ± 5%
Table 47. Rx Pin Characteristics
1
Parameter
Symbol
Min.
Typ.
Max.
Units
High-level input voltage
VIH
0.8 × Vcc1
—
Vcc1
V
Low-level input voltage
VIL
—
0.4
—
V
Vcc = +3.3 V ± 5%
Figure 16 through Figure 19 show the FlexCAN timing, including timing of the standby and shutdown
signals.
VCC/2
VCC/2
TXD
tOFFTXD
tONTXD
0.9V
VDIFF
0.5V
tONRXD
RXD
tOFFRXD
VCC/2
VCC/2
Figure 16. FlexCAN Timing Diagram
i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1
40
Freescale Semiconductor
VCC x 0.75
RS
Bus Externally
Driven
1.1V
VDIFF
tSBRXDL
tDRXDL
RXD
VCC/2
VCC/2
Figure 17. Timing Diagram for FlexCAN Standby Signal
SHDN
VCC/2
VCC/2
tOFFSHDN
tONSHDN
VDIFF
0.5V
Bus Externally
Driven
VCC/2
RXD
Figure 18. Timing Diagram for FlexCAN Shutdown Signal
SHDN
VCC/2
tSHDNSB
0.75 x VCC
RS
Figure 19. Timing Diagram for FlexCAN Shutdown-to-Standby Signal
i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1
Freescale Semiconductor
41
3.5.7
General-Purpose Media Interface (GPMI) Timing
The i.MX28 GPMI controller is a flexible interface NAND Flash controller with 8-bit data width, up to
50MB/s I/O speed and individual chip select.
It supports normal timing mode, using two Flash clock cycles for one access of RE and WE. AC timings
are provided as multiplications of the clock cycle and fixed delay. Figure 20, Figure 21, Figure 22 and
Figure 23 depict the relative timing between GPMI signals at the module level for different operations
under normal mode. Table 48 describes the timing parameters (NF1–NF17) that are shown in the figures.
CLE
NF2
NF1
NF3
NF4
CEn
NF5
WE
NF6
NF7
ALE
NF8
NF9
Command
IO[7:0]
Figure 20. Command Latch Cycle Timing Diagram
CLE
NF1
NF4
NF3
CEn
NF10
NF11
NF5
WE
NF7
NF6
ALE
NF8
NF9
IO[7:0]
Address
Figure 21. Address Latch Cycle Timing Diagram
i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1
42
Freescale Semiconductor
CLE
NF1
NF3
CEn
NF10
NF11
NF5
WE
NF7
NF6
ALE
NF8
NF9
IO[7:0]
Data to NF
Figure 22. Write Data Latch Cycle Timing Diagram
CLE
CEn
NF14
NF15
NF13
RE
NF16
NF17
RB
NF12
IO[7:0]
Data from NF
Figure 23. Read Data Latch Cycle Timing Diagram
i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1
Freescale Semiconductor
43
Table 48. NFC Timing Parameters1
ID
Parameter
Symbol
Timing
T = GPMI Clock Cycle
Example Timing for
GPMI Clock ≈ 100MHz
T = 10ns
Min.
Max.
Min.
Max.
Unit
NF1
CLE setup time
tCLS
(AS+1)*T
—
10
—
ns
NF2
CLE hold time
tCLH
(DH+1)*T
—
20
—
ns
NF3
CEn setup time
tCS
(AS+1)*T
—
10
—
ns
NF4
CE hold time
tCH
(DH+1)*T
—
20
—
ns
NF5
WE pulse width
tWP
NF6
ALE setup time
tALS
(AS+1)*T
—
10
—
ns
NF7
ALE hold time
tALH
(DH+1)*T
—
20
—
ns
NF8
Data setup time
tDS
DS*T
—
10
—
ns
NF9
Data hold time
tDH
DH*T
—
10
—
ns
NF10
Write cycle time
tWC
(DS+DH)*T
20
ns
NF11
WE hold time
tWH
DH*T
10
ns
NF12
Ready to RE low
tRR
(AS+1)*T
—
10
—
ns
NF13
RE pulse width
tRP
DS*T
—
10
—
ns
NF14
READ cycle time
tRC
(DS+DH)*T
—
20
—
ns
NF15
RE high hold time
tREH
DH*T
10
—
ns
NF16
Data setup on read
tDSR
N/A
10
—
ns
NF17
Data hold on read
tDHR
N/A
10
—
ns
DS*T
10
ns
1
The Flash clock maximum frequency is 100 MHz.
2)GPMI’s output timing could be controlled by module’s internal register, say
HW_GPMI_TIMING0_ADDRESS_SETUP,HW_GPMI_TIMING0_DATA_SETUP,HW_GPMI_TIMING0_DATA_HOLD, this AC
timing depends on these registers’ setting. In the above table we use AS/DS/DH representing these settings each.
3)AS minimum value could be 0, while DS/DH minimum value is 1.
i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1
44
Freescale Semiconductor
3.5.8
LCD AC Output Electrical Specifications
Figure 24 depicts the AC output timing for the LCD module. Table 49 lists the LCD module timing
parameters.
T
PAD_LCD_DOTCK
Falling edge capture
tSF
tHF
tSR
tHR
PAD_LCD_DOTCK
Rising edge capture
tDW
PAD_LCD_D[17:0],
PAD_LCD_VSYNC, etc
DATA/CTRL
Notes:
T = LCD interface clock period
I/O Drive Strength = 4mA
I/O Voltage = 3.3V
Cck = Capacitance load on DOTCK pad
Cd = Capacitance load on DATA/CTRL pad
Figure 24. LCD AC Output Timing Diagram
Table 49. LCD AC Output Timing Parameters
ID
Parameter
Description
tSF
Data setup for falling edge
DOTCK = T/2 – 1.97ns + 0.15*Cck – 0.19*Cd
tHF
Data hold for falling edge
DOTCK = T/2 + 0.29ns + 0.09*Cd – 0.10*Cck
tSR
Data setup for rising edge
DOTCK = T/2 – 2.09ns + 0.18*Cck – 0.19*Cd
tHR
Data hold for rising edge
DOTCK = T/2 + 0.40ns + 0.09*Cd – 0.10*Cck
tDW
Data valid window
tDW = T – 1.45ns
i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1
Freescale Semiconductor
45
3.5.9
Inter IC (I2C) Timing
The I2C module is designed to support up to 400-Kbps I2C connection compliant with I2C bus protocol.
The following section describes I2C SDA and SCL signal timings.
Figure 25 shows the timing of the I2C module. Table 50 describes the I2C module timing parameters
(IC1–IC11) shown in the figure.
I2C_SCL
IC11
IC10
I2C_SDA
IC2
IC10
START
IC7
IC4
IC8
IC11
IC6
IC9
IC3
STOP
START
START
IC5
IC1
Figure 25. I2C Module Timing Diagram
Table 50. I2C Module Timing Parameters: 1.8 V – 3.6 V
Standard Mode
ID
Fast Mode
Parameter
Unit
Min.
Max.
Min.
Max.
IC1
I2C_SCL cycle time
10
—
2.5
—
μs
IC2
Hold time (repeated) START condition
4.0
—
0.6
—
μs
IC3
Set-up time for STOP condition
4.0
—
0.6
—
μs
01
0.92
μs
1
IC4
Data hold time
0
3.452
IC5
HIGH Period of I2C_SCL clock
4.0
—
0.6
—
μs
IC6
LOW Period of the I2C_SCL clock
4.7
—
1.3
—
μs
IC7
Set-up time for a repeated START condition
4.7
—
0.6
—
μs
—
ns
IC8
Data set-up time
250
—
1003
IC9
Bus free time between a STOP and START condition
4.7
—
1.3
—
μs
4
300
ns
IC10
Rise time of both I2C_SDA and I2C_SCL signals
—
1000
20+0.1Cb
IC11
Fall time of both I2C_SDA and I2C_SCL signals
—
300
20+0.1Cb4
300
ns
IC12
Capacitive load for each bus line (Cb)
—
400
—
400
pF
1
A device must internally provide a hold time of at least 300 ns for the I2C_SDA signal in order to bridge the undefined region
of the falling edge of I2C_SCL.
2
The maximum IC4 has to be met only if the device does not stretch the LOW period (ID no IC5) of the I2C_SCL signal.
3
A fast-mode I2C bus device can be used in a standard-mode I2C bus system, but the requirement of Set-up time (ID No IC7)
of 250 ns must then be met. This is automatically the case if the device does not stretch the LOW period of the I2C_SCL signal.
If such a device does stretch the LOW period of the I2C_SCL signal, it must output the next data bit to the I2C_SDA line
max_rise_time (ID No IC9) + data_setup_time (ID No IC7) = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus
specification) before the I2C_SCL line is released.
4
Cb = total capacitance of one bus line in pF.
i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1
46
Freescale Semiconductor
3.5.10
JTAG Interface Timing
Figure 26 through Figure 29 show respectively the test clock input, boundary scan, test access port, and
TRST timings for the SJC. Table 51 describes the SJC timing parameters (SJ1–SJ13) indicated in the
figures.
SJ1
SJ2
TCK
(Input)
SJ2
VM
VIH
VM
VIL
SJ3
SJ3
Figure 26. Test Clock Input Timing Diagram
TCK
(Input)
VIH
VIL
SJ4
Data
Inputs
SJ5
Input Data Valid
SJ6
Data
Outputs
Output Data Valid
SJ7
Data
Outputs
SJ6
Data
Outputs
Output Data Valid
Figure 27. Boundary Scan (JTAG) Timing Diagram
i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1
Freescale Semiconductor
47
TCK
(Input)
VIH
VIL
SJ8
TDI
TMS
(Input)
SJ9
Input Data Valid
SJ10
TDO
(Output)
Output Data Valid
SJ11
TDO
(Output)
SJ10
TDO
(Output)
Output Data Valid
Figure 28. Test Access Port Timing Diagram
TCK
(Input)
SJ13
TRST
(Input)
SJ12
Figure 29. TRST Timing Diagram
Table 51. SJC Timing Parameters
All Frequencies
ID
Parameter
Unit
Min.
Max.
SJ1
TCK cycle time
100
—
ns
SJ2
TCK clock pulse width measured at VM1
40
—
ns
SJ3
TCK rise and fall times
—
3
ns
SJ4
Boundary scan input data set-up time
10
—
ns
SJ5
Boundary scan input data hold time
50
—
ns
SJ6
TCK low to output data valid
—
50
ns
SJ7
TCK low to output high impedance
—
50
ns
SJ8
TMS, TDI data set-up time
10
—
ns
SJ9
TMS, TDI data hold time
50
—
ns
i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1
48
Freescale Semiconductor
Table 51. SJC Timing Parameters (continued)
All Frequencies
ID
1
Parameter
Unit
Min.
Max.
SJ10
TCK low to TDO data valid
—
44
ns
SJ11
TCK low to TDO high impedance
—
44
ns
SJ12
TRST assert time
100
—
ns
SJ13
TRST set-up time to TCK low
40
—
ns
VM – mid point voltage
3.5.11
Pulse Width Modulator (PWM) Timing
Figure 30 depicts the timing of the PWM, and Table 52 lists the PWM timing characteristics.
The PWM can be programmed to select one of two clock signals as its source frequency: xtal clock or
hsadc clock. The selected clock signal is passed through a prescaler before being input to the counter. The
output is available at the pulse width modulator output (PWMO) external pin.
PWM also supports MATT mode. In this mode, it can be programmed to select one of two clock signals
as its source frequency, 24-MHz or 32-KHz crystal clock. For a 32-KHz source clock input, the PWM
outputs the 32-KHz clock directly to PAD.
1
2a
3b
PWM Source Clock
2b
4b
3a
4a
PWM Output
Figure 30. PWM Timing
Table 52. PWM Output Timing Parameter: Xtal clock
1
Ref No.
Parameter
Minimum
Maximum
Unit
1
System CLK frequency1
0
24MHz
MHz
2a
Clock high time
21
—
ns
2b
Clock low time
21
—
ns
3a
Clock fall time
—
0.3
ns
3b
Clock rise time
—
0.3
ns
4a
Output delay time
—
15.08
ns
4b
Output setup time
15.77
—
ns
CL of PWMO = 30 pF
i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1
Freescale Semiconductor
49
1
2a
3b
PWM Source Clock
2b
4b
3a
4a
PWM Output
Figure 31. PWM Timing
Table 53. PWM Output Timing Parameter: HSADC clock
1
Ref No.
Parameter
Minimum
Maximum
Unit
1
System CLK frequency1
0
32
MHz
2a
Clock high time
6.813
—
ns
2b
Clock low time
24.432
—
ns
3a
Clock fall time
—
0.3
ns
3b
Clock rise time
—
0.3
ns
4a
Output delay time
—
14.93
ns
4b
Output setup time
15.71
—
ns
CL of PWMO = 30 pF
2a
PWM Source Clock
4a
3a
2b
3b
4b
PWM Output
Figure 32. PWM Timing
i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1
50
Freescale Semiconductor
Table 54. PWM Output Timing Parameter: MATT Mode 24 MHz Crystal Clock
Ref No.
1
Parameter
1
Minimum
Maximum
Unit
1
System CLK frequency
24
24
MHz
2a
Clock high time
20.99
—
ns
2b
Clock low time
21.01
—
ns
3a
Clock fall time
—
0.3
ns
3b
Clock rise time
—
0.3
ns
4a
Output delay time
—
15.23
ns
4b
Output setup time
15.92
—
ns
CL of PWMO = 30 pF
3.5.12
Serial Audio Interface (SAIF) AC Timing
The following subsections describe SAIF timing in two cases:
• Transmitter
• Receiver
3.5.12.1
SAIF Transmitter Timing
Figure 33 shows the timing for SAIF transmitter with internal clock, and Table 55 describes the timing
parameters (SS1–SS13).
SS1
SS3
SS5
SS2
SS4
BITCLK
SS6
LRCLK
SS7
SS8 SS11
SS9
SDATA0-2
SS10
SS13
SS12
Figure 33. SAIF Transmitter Timing Diagram
i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1
Freescale Semiconductor
51
Table 55. SAIF Transmitter Timing
ID
Parameter
Min.
Max.
Unit
SS1
BITCLK period
81.4
—
ns
SS2
BITCLK high period
36.0
—
ns
SS3
BITCLK rise time
—
6.0
ns
SS4
BITCLK low period
36.0
—
ns
SS5
BITCLK fall time
—
6.0
ns
SS6
BITCLK high to LRCLK high
—
15.0
ns
SS7
BITCLK high to LRCLK low
—
15.0
ns
SS8
LRCLK rise time
—
6.0
ns
SS9
LRCLK fall time
—
6.0
ns
SS10
BITCLK high to SDATA valid from high impedance
—
15.0
ns
SS11
BITCLK high to SDATA high/low
—
15.0
ns
SS12
BITCLK high to SDATA high impedance
—
15.0
ns
SS13
SDATA rise/fall time
—
6.0
ns
3.5.12.1.5
SAIF Receiver Timing
Figure 34 shows the timing for the SAIF receiver with internal clock. Table 56 describes the timing
parameters (SS1–SS17) shown in the figure.
SS1
SS3
SS5
SS2
SS4
BITCLK
SS14
SS15
LRCLK
SS16
SS17
SDATA0-2
Figure 34. SAIF Receiver Timing Diagram
i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1
52
Freescale Semiconductor
Table 56. SAIF Receiver Timing with Internal Clock
ID
Parameter
Min.
Max.
Unit
SS1
BITCLK period
81.4
—
ns
SS2
BITCLK high period
36.0
—
ns
SS3
BITCLK rise time
—
6.0
ns
SS4
BITCLK low period
36.0
—
ns
SS5
BITCLK fall time
—
6.0
ns
SS14
BITCLK high to LRCLK high
—
15.0
ns
SS15
BITCLK high to LRCLK low
—
15.0
ns
SS16
SDATA setup time before BITCLK high
10.0
—
ns
SS17
SDATA hold time after BITCLK high
0.0
—
ns
3.5.13
SPDIF AC Timing
SPDIF data is sent using bi-phase marking code. When encoding, the SPDIF data signal is modulated by
a clock that is twice the bit rate of the data signal.
The following Table 57 shows SPDIF timing parameters, including the timing of the modulating Tx clock
(spdif_clk) in SPDIF transmitter as shown in the Figure 35.
Table 57. SPDIF Timing
Timing Parameter Range
Characteristics
Symbol
SPDIFOUT output (Load = 30pf)
• Skew
• Transition Rising
• Transition Falling
Unit
—
—
—
Min
Max
—
—
—
1.5
13.6
18.0
ns
Modulating Tx clock (spdif_clk) period
spclkp
81.4
—
ns
spdif_clk high period
spclkph
65.1
—
ns
spdif_clk low period
spclkpl
65.1
—
ns
spclkp
spclkpl
spclkph
spdif_clk
(Input)
Figure 35. spdif_clk Timing
i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1
Freescale Semiconductor
53
3.5.14
Synchronous Serial Port (SSP) AC Timing
This section describes the electrical information of the SSP, which includes SD/MMC4.3 (Single Data
Rate) timing, MMC4.4 (Dual Date Rate) timing, MS (Memory Stick) timing, and SPI timing.
3.5.14.1
SD/MMC4.3 (Single Data Rate) AC Timing
Figure 36 depicts the timing of SD/MMC4.3, and Table 58 lists the SD/MMC4.3 timing characteristics.
SD4
SD2
SD1
SD5
SCK
SD3
output from SSP to card
CMD
DAT0
DAT1
......
DAT7
SD6
SD7
input from card to SSP
SD8
CMD
DAT0
DAT1
......
DAT7
Figure 36. SD/MMC4.3 Timing
Table 58. SD/MMC4.3 Interface Timing Specification
ID
Parameter
Symbols
Min
Max
Unit
Clock Frequency (Low Speed)
fPP1
0
400
kHz
Clock Frequency (SD/SDIO Full Speed/High
Speed)
fPP2
0
25/50
MHz
Clock Frequency (MMC Full Speed/High Speed)
fPP3
0
20/52
MHz
Clock Frequency (Identification Mode)
fOD
100
400
kHz
SD2
Clock Low Time
tWL
7
—
ns
SD3
Clock High Time
tWH
7
—
ns
SD4
Clock Rise Time
tTLH
—
3
ns
SD5
Clock Fall Time
tTHL
—
3
ns
tOD
-5
5
ns
Card Input Clock
SD1
SSP Output / Card Inputs CMD, DAT (Reference to CLK)
SD6
SSP Output Delay
SSP Input / Card Outputs CMD, DAT (Reference to CLK)
i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1
54
Freescale Semiconductor
Table 58. SD/MMC4.3 Interface Timing Specification (continued)
ID
Parameter
Symbols
Min
Max
Unit
SD7
SSP Input Setup Time
tISU
2.5
—
ns
SD8
SSP Input Hold Time
tIH4
2.5
—
ns
1
In low speed mode, the card clock must be lower than 400 kHz, and the voltage ranges from 2.7 to 3.6 V.
In normal speed mode for the SD/SDIO card, clock frequency can be any value between 0 ~ 25 MHz. In high speed mode,
clock frequency can be any value between 0 ~ 50 MHz.
3
In normal speed mode for MMC card, clock frequency can be any value between 0 ~ 20 MHz. In high speed mode, clock
frequency can be any value between 0 ~ 52MHz.
4
To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2ns.
2
3.5.14.2
MMC4.4 (Dual Data Rate) AC Timing
Figure 37 depicts the timing of MMC4.4, and Table 59 lists the MMC4.4 timing characteristics. Be aware
that only DATA0–DATA7 are sampled on both edges of the clock (not applicable to CMD).
SD1
SCK
output from SSP to card
DAT0
DAT1
......
DAT7
SD2
SD2
......
SD3
input from card to SSP
SD4
DAT0
DAT1
......
DAT7
......
Figure 37. MMC4.4 Timing
Table 59. MMC4.4 Interface Timing Specification
ID
Parameter
Symbols
Min
Max
Unit
Clock Frequency (MMC Full Speed/High Speed)
fPP
0
52
MHz
tOD
–5
5
ns
Card Input Clock
SD1
SSP Output / Card Inputs CMD, DAT (Reference to CLK)
SD2
SSP Output Delay
SSP Input / Card Outputs CMD, DAT (Reference to CLK)
SD3
SSP Input Setup Time
tISU
2.5
—
ns
SD4
SSP Input Hold Time
tIH
2.5
—
ns
i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1
Freescale Semiconductor
55
3.5.14.3
MS (Memory Stick) AC Timing
The SSP module, which also has the function of a memory stick host controller, is compatible with the
Sony Memory Stick version 1.x and Memory Stick PRO.
Figure 38, Figure 39 and Table 40 show the timing of the Memory Stick. Table 60 and Table 61 list the
Memory Stick timing characteristics.
MS1
80%
50%
20%
80%
50%
20%
SCK
MS2
80%
50%
20%
MS3
MS5
MS4
Figure 38. MS Clock Time Waveforms
MS1
SCK
BS(CMD)
MS6
MS7
MS9
MS8
DATA
(Output)
MS10
DATA
(Input)
Figure 39. MS Serial Transfer Mode Timing Diagram
i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1
56
Freescale Semiconductor
MS1
SCK
BS(CMD)
MS11
MS12
MS14
MS13
DATA
(Output)
MS15
DATA
(Input)
Figure 40. MS Parallel Transfer Mode Timing Diagram
Table 60. MS Serial Transfer Timing Parameters
ID
Parameter
Symbol
Min
Max
Units
MS1
SCK Cycle Time
tCLKc
50
—
ns
MS2
SCK High Pulse Time
tCLKwh
15
—
ns
MS3
SCK Low Pulse Time
tCLKwl
15
—
ns
MS4
SCK Rise Time
tCLKr
—
10
ns
MS5
SCK Fall Time
tCLKf
—
10
ns
MS6
BS Setup Time
tBSsu
5
—
ns
MS7
BS Hold Time
tBSh
5
—
ns
MS8
DATA Setup Time
tDsu
5
—
ns
MS9
DATA Hold Time
tDh
5
—
ns
MS10
DATA Input Delay Time
tDd
—
15
ns
Table 61. MS Parallel Transfer Timing Parameters
ID
Parameter
Symbol
Min
Max
Units
MS1
SCK Cycle Time
tCLKc
25
—
ns
MS2
SCK High Pulse Time
tCLKwh
5
—
ns
MS3
SCK Low Pulse Time
tCLKwl
5
—
ns
i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1
Freescale Semiconductor
57
Table 61. MS Parallel Transfer Timing Parameters (continued)
ID
Parameter
Symbol
Min
Max
Units
MS4
SCK Rise Time
tCLKr
—
10
ns
MS5
SCK Fall Time
tCLKf
—
10
ns
MS11
BS Setup Time
tBSsu
8
—
ns
MS12
BS Hold Time
tBSh
1
—
ns
MS13
DATA Setup Time
tDsu
8
—
ns
MS14
DATA Hold Time
tDh
1
—
ns
MS15
DATA Input Delay Time
tDd
—
15
ns
3.5.14.4
SPI AC Timing
Figure 41 depicts the master mode and slave mode timings of the SPI, and Table 62 lists the timing
parameters.
SSn
CS1
CS3
CS2
CS5
CS6
CS4
SCK
CS9
CS3
CS10
CS2
MISO
CS8
CS7
MOSI
Figure 41. SPI Interface Timing Diagram
Table 62. SPI Interface Timing Parameters
ID
Parameter
Symbol
Min.
Max.
Units
CS1
SCK cycle time
tclk
50
—
ns
CS2
SCK high or low time
tSW
25
—
ns
CS3
SCK rise or fall
tRISE/FALL
—
7.6
ns
CS4
SSn pulse width
tCSLH
25
—
ns
CS5
SSn lead time (CS setup time)
tSCS
25
—
ns
CS6
SSn lag time (CS hold time)
tHCS
25
—
ns
CS7
MOSI setup time
tSmosi
5
—
ns
CS8
MOSI hold time
tHmosi
5
—
ns
CS9
MISO setup time
tSmiso
5
—
ns
CS10
MISO hold time
tHmiso
5
—
ns
i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1
58
Freescale Semiconductor
3.5.15
UART (UARTAPP and DebugUART) AC Timing
This section describes the UART module AC timing which is applicable to both UARTAPP and
DebugUART.
3.5.15.1
UART Transmit Timing
Figure 39 shows the UART transmit timing, showing only eight data bits and one stop bit. Table 63
describes the timing parameter (UA1) shown in the figure.
UA1
TXD
(output)
Start
Bit
Possible
Parity
Bit
UA1
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Par Bit STOP
BIT
UA1
Next
Start
Bit
UA1
Figure 42. UART Transmit Timing Diagram
Table 63. UART Transmit Timing Parameters
ID
UA1
Parameter
Symbol
Transmit Bit Time
Min.
1/Fbaud_rate1
tTbit
– Tref_clk
2
Max.
Units
1/Fbaud_rate + Tref_clk
—
1
Fbaud_rate: Baud rate frequency. The maximum baud rate the UARTAPP can support is 3.25 Mbps. The maximum baud rate of
DebugUART is 115.2 kbps.
2 T
ref_clk: The period of UART reference clock ref_clk (which is APBX clock = 24 MHz).
3.5.15.2
UART Receive Timing
Figure 43 shows the UART receive timing, showing only eight data bits and one stop bit. Table 64
describes the timing parameter (UA2) shown in the figure.
–
UA2
RXD
(input)
Start
Bit
Possible
Parity
Bit
UA2
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Par Bit STOP
BIT
UA2
Next
Start
Bit
UA2
Figure 43. UART Receive Timing Diagram
i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1
Freescale Semiconductor
59
Table 64. UART Receive Timing Parameters
ID
UA2
Parameter
1
Receive bit time
Symbol
Min.
Max.
Units
tRbit
1/Fbaud_rate2 – 1/(16
1/Fbaud_rate + 1/(16
× Fbaud_rate)
—
× Fbaud_rate)
The UART receiver can tolerate 1/(16 × Fbaud_rate) tolerance in each bit. But accumulation tolerance in one frame must not
exceed 3/(16 × Fbaud_rate).
2
Fbaud_rate: Baud rate frequency. The maximum baud rate the UARTAPP can support is 3.25 Mbps. The maximum baud rate of
DebugUART is 115 kbps.
1
4
4.1
Package Information and Contact Assignments
289-Ball MAPBGA—Case 14 x 14 mm, 0.8 mm Pitch
The following notes apply to Figure 44:
• All dimensions are in millimeters.
• Dimensioning and tolerancing per ASME Y14.5M-1994.
• Maximum solder bump diameter measured parallel to datum A.
• Datum A, the seating plane, is determined by the spherical crowns of the solder bumps.
• Parallelism measurement excludes any effect of mark on top surface of package.
i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1
60
Freescale Semiconductor
Figure 44 shows the i.MX28 production package.
Figure 44. i.MX28 Production Package
zzxz
4.2
Ground, Power, Sense, and Reference Contact Assignments
Table 65 shows power and ground contact assignments for the MAPBGA package.
Table 65. MAPBGA Power and Ground Contact Assignments
Contact Name
Contact Assignment
VDDA1
C13
VDDD
G12,G11,F10,F11,K12,F12,G10
VDDIO18
G8,F9,F8,G9
VDDIO33
H8,J8,N3,G3,E6,J9,J10,A7,E16
VDDIO33_EMI
N17
VDDIO_EMI
P11,R13,N13,N15,G17,M12,M10,G13,M11,L13,G15
i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1
Freescale Semiconductor
61
Table 65. MAPBGA Power and Ground Contact Assignments (continued)
Contact Name
Contact Assignment
VDDIO_EMIQ
K15,J13,R15
VDDXTAL
C12
VSS
E15,L11,A1,K10,K11,J11,M14,H11,U1,H9,H12,H3,K9,C16,L10,H16,J12,H10,B7,E5,J15,A9,N4
VSSA1
B13
VSSA2
B11
VSSIO_EMI
F16,R10,H14,M16,F14,L12,P16,U17,T14,P14,R12
4.3
Signal Contact Assignments
Table 66 lists the i.MX287 MAPBGA package signal contact assignments.
Table 66. MAPBGA Contact Assignments
Signal Name
Contact
Assignment
Signal Name
Contact
Assignment
Signal Name
Contact
Assignment
AUART0_CTS
J6
EMI_DQS1N
J16
LCD_D17
R3
AUART0_RTS
J7
EMI_ODT0
R17
LCD_D18
U4
AUART0_RX
G5
EMI_ODT1
T17
LCD_D19
T4
AUART0_TX
H5
EMI_RASN
R16
LCD_D20
R4
AUART1_CTS
K5
EMI_VREF0
R14
LCD_D21
U5
AUART1_RTS
J5
EMI_VREF1
K13
LCD_D22
T5
AUART1_RX
L4
EMI_WEN
T15
LCD_D23
R5
AUART1_TX
K4
ENET0_COL
J4
LCD_DOTCLK
N1
AUART2_CTS
H6
ENET0_CRS
J3
LCD_ENABLE
N5
AUART2_RTS
H7
ENET0_MDC
G4
LCD_HSYNC
M1
AUART2_RX
F6
ENET0_MDIO
H4
LCD_RD_E
P4
AUART2_TX
F5
ENET0_RXD0
H1
LCD_RESET
M6
AUART3_CTS
L6
ENET0_RXD1
H2
LCD_RS
M4
AUART3_RTS
K6
ENET0_RXD2
J1
LCD_VSYNC
L1
AUART3_RX
M5
ENET0_RXD3
J2
LCD_WR_RWN
K1
AUART3_TX
L5
ENET0_RX_CLK F3
LRADC0
C15
BATTERY
A15
ENET0_RX_EN
E4
LRADC1
C9
DCDC_BATT
B15
ENET0_TXD0
F1
LRADC2
C8
DCDC_GND
A17
ENET0_TXD1
F2
LRADC3
D9
DCDC_LN1
B17
ENET0_TXD2
G1
LRADC4
D13
DCDC_LP
A16
ENET0_TXD3
G2
LRADC5
D15
i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1
62
Freescale Semiconductor
Table 66. MAPBGA Contact Assignments (continued)
Signal Name
Contact
Assignment
Signal Name
Contact
Assignment
Signal Name
Contact
Assignment
DCDC_VDDA
B16
ENET0_TX_CLK E3
LRADC6
C14
DCDC_VDDD
D17
ENET0_TX_EN
F4
PSWITCH
A11
DCDC_VDDIO
C17
ENET_CLK
E2
PWM0
K7
DEBUG
B9
GPMI_ALE
P6
PWM1
L7
EMI_A00
U15
GPMI_CE0N
N7
PWM2
K8
EMI_A01
U12
GPMI_CE1N
N9
PWM3
E9
EMI_A02
U14
GPMI_CE2N
M7
PWM4
E10
EMI_A03
T11
GPMI_CE3N
M9
RESETN
A14
EMI_A04
U10
GPMI_CLE
P7
RTC_XTALI
D11
EMI_A05
R11
GPMI_D00
U8
RTC_XTALO
C11
EMI_A06
R9
GPMI_D01
T8
SAIF0_BITCLK
F7
EMI_A07
N11
GPMI_D02
R8
SAIF0_LRCLK
G6
EMI_A08
U9
GPMI_D03
U7
SAIF0_MCLK
G7
EMI_A09
P10
GPMI_D04
T7
SAIF0_SDATA0
E7
EMI_A10
U13
GPMI_D05
R7
SAIF1_SDATA0
E8
EMI_A11
T10
GPMI_D06
U6
SPDIF
D7
EMI_A12
U11
GPMI_D07
T6
SSP0_CMD
A4
EMI_A13
T9
GPMI_RDN
R6
SSP0_DATA0
B6
EMI_A14
N10
GPMI_RDY0
N6
SSP0_DATA1
C6
EMI_BA0
T16
GPMI_RDY1
N8
SSP0_DATA2
D6
EMI_BA1
T12
GPMI_RDY2
M8
SSP0_DATA3
A5
EMI_BA2
N12
GPMI_RDY3
L8
SSP0_DATA4
B5
EMI_CASN
U16
GPMI_RESETN
L9
SSP0_DATA5
C5
EMI_CE0N
P12
GPMI_WRN
P8
SSP0_DATA6
D5
EMI_CE1N
P9
HSADC0
B14
SSP0_DATA7
B4
EMI_CKE
T13
I2C0_SCL
C7
SSP0_DETECT
D10
EMI_CLK
L17
I2C0_SDA
D8
SSP0_SCK
A6
EMI_CLKN
L16
JTAG_RTCK
E14
SSP1_CMD
C1
EMI_D00
N16
JTAG_TCK
E11
SSP1_DATA0
D1
EMI_D01
M13
JTAG_TDI
E12
SSP1_DATA3
E1
EMI_D02
P15
JTAG_TDO
E13
SSP1_SCK
B1
EMI_D03
N14
JTAG_TMS
D12
SSP2_MISO
B3
i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1
Freescale Semiconductor
63
Table 66. MAPBGA Contact Assignments (continued)
Signal Name
Contact
Assignment
Signal Name
Contact
Assignment
Signal Name
Contact
Assignment
EMI_D04
P13
JTAG_TRST
D14
SSP2_MOSI
C3
EMI_D05
P17
LCD_CS
P5
SSP2_SCK
A3
EMI_D06
L14
LCD_D00
K2
SSP2_SS0
C4
EMI_D07
M17
LCD_D01
K3
SSP2_SS1
D3
EMI_D08
G16
LCD_D02
L2
SSP2_SS2
D4
EMI_D09
H15
LCD_D03
L3
SSP3_MISO
B2
EMI_D10
G14
LCD_D04
M2
SSP3_MOSI
C2
EMI_D11
J14
LCD_D05
M3
SSP3_SCK
A2
EMI_D12
H13
LCD_D06
N2
SSP3_SS0
D2
EMI_D13
H17
LCD_D07
P1
TESTMODE
C10
EMI_D14
F13
LCD_D08
P2
USB0DM
A10
EMI_D15
F17
LCD_D09
P3
USB0DP
B10
EMI_DDR_OPE
N
K14
LCD_D10
R1
USB1DM
B8
EMI_DDR_OPE
N_FB
L15
LCD_D11
R2
USB1DP
A8
EMI_DQM0
M15
LCD_D12
T1
VDD1P5
D16
EMI_DQM1
F15
LCD_D13
T2
VDD4P2
A13
EMI_DQS0
K17
LCD_D14
U2
VDD5V
E17
EMI_DQS0N
K16
LCD_D15
U3
XTALI
A12
EMI_DQS1
J17
LCD_D16
T3
XTALO
B12
i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1
64
Freescale Semiconductor
4.4
i.MX287 Ball Map
Figure 45 shows the i.MX287 MAPBGA Ball Map.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A
VSS
SSP3
_SCK
SSP2
_SCK
SSP0
_CMD
SSP0
_DAT
A3
SSP0
_SCK
VDDI
O33
USB1
DP
VSS
USB0
DM
PSWI
TCH
XTALI
VDD4
P2
RESE
TN
BATT
ERY
DCDC DCDC
_LP _GND
A
B
SSP1
_SCK
SSP3
_MIS
O
SSP2
_MIS
O
SSP0
_DAT
A7
SSP0
_DAT
A4
SSP0
_DAT
A0
VSS
USB1
DM
DEBU
G
USB0
DP
VSSA
2
XTAL
O
VSSA
1
HSAD
C0
DCDC DCDC
DCDC
_BAT _VDD
_LN1
T
A
B
C
SSP3 SSP2
SSP1
_MOS _MOS
_CMD
I
I
SSP2
_SS0
SSP0
_DAT
A5
SSP0
_DAT
A1
I2C0_
SCL
LRAD
C2
LRAD
C1
TEST
MOD
E
RTC_
XTAL
O
VDDX VDDA
TAL
1
LRAD
C6
LRAD
C0
VSS
DCDC
_VDD
IO
C
D
SSP1
_DAT
A0
SSP3
_SS0
SSP2
_SS1
SSP2
_SS2
SSP0
_DAT
A6
SSP0
_DAT
A2
SPDI
F
I2C0_
SDA
LRAD
C3
SSP0
_DET
ECT
RTC_
XTALI
JTAG
_TMS
LRAD
C4
JTAG
_TRS
T
LRAD
C5
VDD1
P5
DCDC
_VDD
D
D
E
SSP1
_DAT
A3
ENET
_CLK
ENET
0_TX
_CLK
ENET
0_RX
_EN
VSS
VDDI
O33
SAIF0 SAIF1
_SDA _SDA
TA0
TA0
PWM
3
PWM
4
JTAG
_TCK
JTAG
_TDI
JTAG
_TDO
JTAG
_RTC
K
VSS
VDDI
O33
VDD5
V
E
F
ENET
0_TX
D0
ENET
0_TX
D1
ENET
0_RX
_CLK
ENET
0_TX
_EN
AUAR AUAR SAIF0
T2_T T2_R _BITC
X
X
LK
VDDI
O18
VDDI
O18
VDDD VDDD VDDD
EMI_
D14
VSSI
VSSI
EMI_
O_EM
O_EM
DQM1
I
I
EMI_
D15
F
G
ENET
0_TX
D2
ENET
0_TX
D3
VDDI
O33
ENET
0_MD
C
AUAR SAIF0 SAIF0
T0_R _LRC _MCL
X
LK
K
VDDI
O18
VDDI
O18
VDDI
VDDD VDDD VDDD O_EM
I
EMI_
D10
VDDI
O_EM
I
EMI_
D08
VDDI
O_EM
I
G
H
ENET
0_RX
D0
ENET
0_RX
D1
VSS
ENET
0_MD
IO
AUAR AUAR AUAR
T0_T T2_C T2_R
X
TS
TS
VDDI
O33
VSS
VSS
VSS
VSS
EMI_
D12
VSSI
O_EM
I
EMI_
D09
VSS
EMI_
D13
H
J
ENET
0_RX
D2
ENET
0_RX
D3
ENET
0_CR
S
ENET
0_CO
L
AUAR AUAR AUAR
T1_R T0_C T0_R
TS
TS
TS
VDDI
O33
VDDI
O33
VDDI
O33
VSS
VSS
VDDI
O_EM
IQ
EMI_
D11
VSS
EMI_
DQS1
N
EMI_
DQS1
J
K
LCD_
WR_
RWN
LCD_
D00
LCD_
D01
AUAR AUAR AUAR
T1_T T1_C T3_R
X
TS
TS
PWM
0
PWM
2
VSS
VSS
VSS
VDDD
EMI_
VREF
1
EMI_ VDDI
DDR_ O_EM
OPEN
IQ
EMI_
DQS0
N
EMI_
DQS0
K
L
LCD_
VSYN
C
LCD_
D02
LCD_
D03
AUAR AUAR AUAR
T1_R T3_T T3_C
X
X
TS
PWM
1
GPMI
_RDY
3
GPMI
_RES
ETN
VSS
VSS
VSSI VDDI
O_EM O_EM
I
I
EMI_
D06
EMI_
DDR_ EMI_
OPEN CLKN
_FB
EMI_
CLK
L
M
LCD_
HSYN
C
LCD_
D04
LCD_
D05
LCD_
RS
AUAR LCD_
T3_R RESE
X
T
GPMI
_CE2
N
GPMI
_RDY
2
GPMI
_CE3
N
VDDI VDDI VDDI
O_EM O_EM O_EM
I
I
I
EMI_
D01
VSS
VSSI
EMI_
O_EM
DQM0
I
EMI_
D07
M
N
LCD_
DOTC
LK
LCD_
D06
VDDI
O33
VSS
LCD_
ENAB
LE
GPMI
_RDY
0
GPMI
_CE0
N
GPMI
_RDY
1
GPMI
_CE1
N
EMI_
A14
EMI_
A07
EMI_
BA2
VDDI
O_EM
I
EMI_
D03
VDDI
O_EM
I
EMI_
D00
VDDI
O33_
EMI
N
P
LCD_
D07
LCD_
D08
LCD_
D09
LCD_
RD_E
LCD_
CS
GPMI
_ALE
GPMI
_CLE
GPMI
_WR
N
EMI_
CE1N
EMI_
A09
VDDI
O_EM
I
EMI_
CE0N
EMI_
D04
VSSI
O_EM
I
EMI_
D02
VSSI
O_EM
I
EMI_
D05
P
R
LCD_
D10
LCD_
D11
LCD_
D17
LCD_
D20
LCD_
D23
GPMI
_RDN
GPMI
_D05
GPMI
_D02
EMI_
A06
VSSI
O_EM
I
EMI_
A05
VSSI VDDI
O_EM O_EM
I
I
EMI_
VREF
0
VDDI
EMI_
O_EM
RASN
IQ
EMI_
ODT0
R
T
LCD_
D12
LCD_
D13
LCD_
D16
LCD_
D19
LCD_
D22
GPMI
_D07
GPMI
_D04
GPMI
_D01
EMI_
A13
EMI_
A11
EMI_
A03
EMI_
BA1
EMI_
CKE
VSSI
O_EM
I
EMI_
WEN
EMI_
BA0
EMI_
ODT1
T
U
VSS
LCD_
D14
LCD_
D15
LCD_
D18
LCD_
D21
GPMI
_D06
GPMI
_D03
GPMI
_D00
EMI_
A08
EMI_
A04
EMI_
A12
EMI_
A01
EMI_
A10
EMI_
A02
EMI_
A00
VSSI
EMI_
O_EM
CASN
I
U
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
17
Figure 45. 289-pin i.MX287 MAPBGA Ball Map
i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1
Freescale Semiconductor
65
4.5
i.MX286 Ball Map
Figure 46 shows the i.MX286 MAPBGA ball map.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
A
VSS
NC
SSP2
_SCK
SSP0
_CMD
SSP0
_DAT
A3
SSP0
_SCK
VDDI
O33
USB1
DP
VSS
USB0
DM
PSWI
TCH
XTALI
VDD4
P2
RESE
TN
BATT
ERY
DCDC DCDC
_LP _GND
A
B
NC
NC
SSP2
_MIS
O
SSP0
_DAT
A7
SSP0
_DAT
A4
SSP0
_DAT
A0
VSS
USB1
DM
DEBU
G
USB0
DP
VSSA
2
XTAL
O
VSSA
1
HSAD
C0
DCDC DCDC
DCDC
_BAT _VDD
_LN1
T
A
B
C
NC
NC
SSP2
_MOS
I
SSP2
_SS0
SSP0
_DAT
A5
SSP0
_DAT
A1
I2C0_
SCL
LRAD
C2
LRAD
C1
TEST
MOD
E
RTC_
XTAL
O
VDDX VDDA
TAL
1
LRAD
C6
LRAD
C0
VSS
DCDC
_VDD
IO
C
D
NC
NC
SSP2
_SS1
SSP2
_SS2
SSP0
_DAT
A6
SSP0
_DAT
A2
SPDI
F
I2C0_
SDA
LRAD
C3
SSP0
_DET
ECT
RTC_
XTALI
JTAG
_TMS
LRAD
C4
JTAG
_TRS
T
LRAD
C5
VDD1
P5
DCDC
_VDD
D
D
E
NC
ENET
_CLK
NC
ENET
0_RX
_EN
VSS
VDDI
O33
SAIF0 SAIF1
_SDA _SDA
TA0
TA0
PWM
3
PWM
4
JTAG
_TCK
JTAG
_TDI
JTAG
_TDO
JTAG
_RTC
K
VSS
VDDI
O33
VDD5
V
E
F
ENET
0_TX
D0
ENET
0_TX
D1
NC
ENET
0_TX
_EN
NC
NC
SAIF0
_BITC
LK
VDDI
O18
VDDI
O18
VDDD VDDD VDDD
EMI_
D14
VSSI
VSSI
EMI_
O_EM
O_EM
DQM1
I
I
EMI_
D15
F
G
NC
NC
VDDI
O33
ENET
0_MD
C
AUAR SAIF0 SAIF0
T0_R _LRC _MCL
X
LK
K
VDDI
O18
VDDI
O18
VDDI
VDDD VDDD VDDD O_EM
I
EMI_
D10
VDDI
O_EM
I
EMI_
D08
VDDI
O_EM
I
G
H
ENET
0_RX
D0
ENET
0_RX
D1
VSS
ENET
0_MD
IO
AUAR
T0_T
X
VDDI
O33
VSS
VSS
VSS
VSS
EMI_
D12
VSSI
O_EM
I
EMI_
D09
VSS
EMI_
D13
H
J
NC
NC
NC
NC
NC
AUAR AUAR
T0_C T0_R
TS
TS
VDDI
O33
VDDI
O33
VDDI
O33
VSS
VSS
VDDI
O_EM
IQ
EMI_
D11
VSS
EMI_
DQS1
N
EMI_
DQS1
J
K
LCD_
WR_
RWN
LCD_
D00
LCD_
D01
AUAR
T1_T
X
NC
NC
PWM
0
PWM
2
VSS
VSS
VSS
VDDD
EMI_
VREF
1
EMI_ VDDI
DDR_ O_EM
OPEN
IQ
EMI_
DQS0
N
EMI_
DQS0
K
L
NC
LCD_
D02
LCD_
D03
AUAR
T1_R
X
NC
NC
PWM
1
GPMI
_RDY
3
GPMI
_RES
ETN
VSS
VSS
VSSI VDDI
O_EM O_EM
I
I
EMI_
D06
EMI_
DDR_ EMI_
OPEN CLKN
_FB
EMI_
CLK
L
M
NC
LCD_
D04
LCD_
D05
LCD_
RS
NC
LCD_
RESE
T
GPMI
_CE2
N
GPMI
_RDY
2
GPMI
_CE3
N
VDDI VDDI VDDI
O_EM O_EM O_EM
I
I
I
EMI_
D01
VSS
VSSI
EMI_
O_EM
DQM0
I
EMI_
D07
M
N
NC
LCD_
D06
VDDI
O33
VSS
NC
GPMI
_RDY
0
GPMI
_CE0
N
GPMI
_RDY
1
GPMI
_CE1
N
EMI_
A14
EMI_
A07
EMI_
BA2
VDDI
O_EM
I
EMI_
D03
VDDI
O_EM
I
EMI_
D00
VDDI
O33_
EMI
N
P
LCD_
D07
LCD_
D08
LCD_
D09
LCD_
RD_E
LCD_
CS
GPMI
_ALE
GPMI
_CLE
GPMI
_WR
N
EMI_
CE1N
EMI_
A09
VDDI
O_EM
I
EMI_
CE0N
EMI_
D04
VSSI
O_EM
I
EMI_
D02
VSSI
O_EM
I
EMI_
D05
P
R
LCD_
D10
LCD_
D11
LCD_
D17
LCD_
D20
LCD_
D23
GPMI
_RDN
GPMI
_D05
GPMI
_D02
EMI_
A06
VSSI
O_EM
I
EMI_
A05
VSSI VDDI
O_EM O_EM
I
I
EMI_
VREF
0
VDDI
EMI_
O_EM
RASN
IQ
EMI_
ODT0
R
T
LCD_
D12
LCD_
D13
LCD_
D16
LCD_
D19
LCD_
D22
GPMI
_D07
GPMI
_D04
GPMI
_D01
EMI_
A13
EMI_
A11
EMI_
A03
EMI_
BA1
EMI_
CKE
VSSI
O_EM
I
EMI_
WEN
EMI_
BA0
EMI_
ODT1
T
U
VSS
LCD_
D14
LCD_
D15
LCD_
D18
LCD_
D21
GPMI
_D06
GPMI
_D03
GPMI
_D00
EMI_
A08
EMI_
A04
EMI_
A12
EMI_
A01
EMI_
A10
EMI_
A02
EMI_
A00
VSSI
EMI_
O_EM
CASN
I
U
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
NC
NC
16
16
17
17
Figure 46. 289-pin i.MX286 MAPBGA Ball Map
i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1
66
Freescale Semiconductor
4.6
i.MX283 Ball Map
Figure 47 shows the i.MX283 MAPBGA ball map.
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
SSP2_S SSP0_C SSP0_D SSP0_S VDDIO3
USB0D PSWITC
BATTER DCDC_L DCDC_
USB1DP VSS
XTALI VDD4P2 RESETN
CK
MD
ATA3
CK
3
M
H
Y
P
GND
SSP2_M SSP0_D SSP0_D SSP0_D
USB1D
DCDC_BDCDC_V DCDC_L
NC
NC
VSS
DEBUG USB0DP VSSA2 XTALO VSSA1 HSADC0
ISO
ATA7 ATA4 ATA0
M
ATT
DDA
N1
SSP2_M SSP2_S SSP0_D SSP0_D I2C0_SC
TESTM RTC_XT VDDXT
DCDC_V
NC
NC
LRADC2 LRADC1
VDDA1 LRADC6 LRADC0 VSS
OSI
S0
ATA5 ATA1
L
ODE
ALO
AL
DDIO
SSP2_S SSP2_S SSP0_D SSP0_D
I2C0_SD
SSP0_D RTC_XT JTAG_T
JTAG_T
DCDC_V
NC
NC
NC
LRADC3
LRADC4
LRADC5VDD1P5
S1
S2
ATA6 ATA2
A
ETECT
ALI
MS
RST
DDD
ENET_C
ENET0_
VDDIO3 SAIF0_S SAIF1_S
JTAG_T JTAG_T JTAG_T JTAG_R
VDDIO3
NC
NC
VSS
PWM3 PWM4
VSS
VDD5V
LK
RX_EN
3
DATA0 DATA0
CK
DI
DO
TCK
3
ENET0_ ENET0_
ENET0_
SAIF0_B VDDIO1 VDDIO1
EMI_D1 VSSIO_ EMI_D VSSIO_ EMI_D1
NC
NC
NC
VDDD VDDD VDDD
TXD0 TXD1
TX_EN
ITCLK
8
8
4
EMI
QM1
EMI
5
VDDIO3 ENET0_ AUART SAIF0_L SAIF0_ VDDIO1 VDDIO1
VDDIO_ EMI_D1 VDDIO_ EMI_D0 VDDIO_
NC
NC
VDDD VDDD VDDD
3
MDC 0_RX RCLK MCLK
8
8
EMI
0
EMI
8
EMI
ENET0_ ENET0_
ENET0_ AUART
VDDIO3
EMI_D1 VSSIO_ EMI_D0
EMI_D1
VSS
NC
NC
VSS
VSS
VSS
VSS
VSS
RXD0 RXD1
MDIO 0_TX
3
2
EMI
9
3
AUART AUART VDDIO3 VDDIO3 VDDIO3
VDDIO_ EMI_D1
EMI_D EMI_D
NC
NC
NC
NC
NC
VSS
VSS
VSS
0_CTS 0_RTS
3
3
3
EMIQ
1
QS1N QS1
LCD_W LCD_D0 LCD_D0 AUART
EMI_VR EMI_DD VDDIO_ EMI_D EMI_D
NC
NC PWM0 PWM2 VSS
VSS
VSS VDDD
R_RWN
0
1
1_TX
EF1 R_OPE EMIQ QS0N QS0
LCD_D0 LCD_D0 AUART
GPMI_R
VSSIO_ VDDIO_ EMI_D0 EMI_DD EMI_CL EMI_CL
NC
NC
NC PWM1 NC
VSS
VSS
R_OPE KN
2
3
1_RX
ESETN
EMI
EMI
6
K
LCD_D0 LCD_D0
LCD_RE
VDDIO_ VDDIO_ VDDIO_ EMI_D0
EMI_D VSSIO_ EMI_D0
NC
LCD_RS NC
NC
NC
NC
VSS
4
5
SET
EMI
EMI
EMI
1
QM0
EMI
7
LCD_D0 VDDIO3
GPMI_R GPMI_C GPMI_R GPMI_C EMI_A1 EMI_A0 EMI_BA VDDIO_ EMI_D0 VDDIO_ EMI_D0 VDDIO3
NC
VSS
NC
6
3
DY0
E0N
DY1
E1N
4
7
2
EMI
3
EMI
0
3_EMI
LCD_D0 LCD_D0 LCD_D0 LCD_RD
GPMI_A GPMI_C GPMI_ EMI_CE EMI_A0 VDDIO_ EMI_CE EMI_D0 VSSIO_ EMI_D0 VSSIO_ EMI_D0
LCD_CS
7
8
9
_E
LE
LE
WRN
1N
9
EMI
0N
4
EMI
2
EMI
5
LCD_D1 LCD_D1 LCD_D1 LCD_D2 LCD_D2 GPMI_R GPMI_ GPMI_ EMI_A0 VSSIO_ EMI_A0 VSSIO_ VDDIO_ EMI_VR VDDIO_ EMI_RA EMI_O
0
1
7
0
3
DN
D05
D02
6
EMI
5
EMI
EMI
EF0
EMIQ
SN
DT0
LCD_D1 LCD_D1 LCD_D1 LCD_D1 LCD_D2 GPMI_ GPMI_ GPMI_ EMI_A1 EMI_A1 EMI_A0 EMI_BA EMI_CK VSSIO_ EMI_W EMI_BA EMI_O
2
3
6
9
2
D07
D04
D01
3
1
3
1
E
EMI
EN
0
DT1
LCD_D1 LCD_D1 LCD_D1 LCD_D2 GPMI_ GPMI_ GPMI_ EMI_A0 EMI_A0 EMI_A1 EMI_A0 EMI_A1 EMI_A0 EMI_A0 EMI_CA VSSIO_
VSS
4
5
8
1
D06
D03
D00
8
4
2
1
0
2
0
SN
EMI
VSS
1
NC
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
17
Figure 47. 289-pin i.MX283 MAPBGA Ball Map
i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1
Freescale Semiconductor
67
4.7
i.MX280 Ball Map
Figure 48 shows the i.MX280 MAPBGA ball map.
1
2
A
VSS
NC
SSP2_S SSP0_C SSP0_D SSP0_S VDDIO3 USB1D
CK
MD ATA3
CK
3
P
B
NC
NC
SSP2_ SSP0_D SSP0_D SSP0_D
VSS
MISO ATA7 ATA4 ATA0
C
NC
NC
SSP2_ SSP2_S SSP0_D SSP0_D I2C0_SC
TESTM RTC_XT VDDXT
LRADC2LRADC1
VDDA1 LRADC6LRADC0 VSS
MOSI
S0
ATA5 ATA1
L
ODE
ALO
AL
D
NC
NC
SSP2_S SSP2_S SSP0_D SSP0_D
S1
S2
ATA6 ATA2
E
NC
ENET_C
LK
ENET0_ ENET0_
TXD0 TXD1
F
G
H
J
K
NC
NC
3
4
5
NC
7
8
9
10
11
12
13
14
15
16
17
USB0D PSWITC
VDD4P
BATTER DCDC_L DCDC_
XTALI
RESETN
M
H
2
Y
P
GND
A
USB1D
USB0D
HSADC DCDC_ DCDC_ DCDC_L
DEBUG
VSSA2 XTALO VSSA1
M
P
0
BATT VDDA
N1
B
VSS
DCDC_
VDDIO
C
I2C0_S
SSP0_D RTC_XT JTAG_T
JTAG_T
VDD1P DCDC_
LRADC3
LRADC4
LRADC5
DA
ETECT ALI
MS
RST
5
VDDD
D
NC
ENET0_
VDDIO3SAIF0_S SAIF1_S
JTAG_T JTAG_T JTAG_T JTAG_R
VDDIO3
VSS
PWM3 PWM4
VSS
VDD5V
RX_EN
3
DATA0 DATA0
CK
DI
DO
TCK
3
E
NC
ENET0_
TX_EN
SAIF0_ VDDIO1VDDIO1
EMI_D1 VSSIO_ EMI_D VSSIO_ EMI_D1
VDDD VDDD VDDD
BITCLK
8
8
4
EMI QM1 EMI
5
F
VDDIO3 ENET0_ AUART SAIF0_L SAIF0_ VDDIO1VDDIO1
VDDIO_ EMI_D1 VDDIO_ EMI_D0 VDDIO_
VDDD VDDD VDDD
3
MDC 0_RX RCLK MCLK
8
8
EMI
0
EMI
8
EMI
G
NC
ENET0_ ENET0_
ENET0_ AUART
VSS
RXD0 RXD1
MDIO 0_TX
NC
6
NC
NC
NC
NC
NC
VSS
VSS
EMI_D1 VSSIO_ EMI_D0
EMI_D1
VSS
2
EMI
9
3
H
AUART AUART VDDIO3VDDIO3VDDIO3
VSS
0_CTS 0_RTS
3
3
3
VSS
VDDIO_ EMI_D1
VSS
EMIQ
1
J
NC
NC
VDDIO3
VSS
3
ETM_T ETM_D ETM_D AUART
CLK
A0
A1
1_TX
NC
NC
PWM0 PWM2
L
NC
ETM_D ETM_D AUART
A2
A3
1_RX
NC
NC
PWM1
NC
M
NC
ETM_D ETM_D GPIO_B
A4
A5
1P26
NC
NC
NC
NC
N
NC
ETM_D VDDIO3
VSS
A6
3
P
ETM_D
A7
NC
NC
R
NC
NC
T
NC
U
VSS
VSS
VSS
VSS
GPMI_
VSS
RESETN
VSS
EMI_D EMI_D
QS1N QS1
EMI_D
EMI_VR
VDDIO_ EMI_D EMI_D
DR_OP
EF1
EMIQ QS0N QS0
EN
EMI_D
VSSIO_ VDDIO_ EMI_D0
EMI_CL EMI_CL
DR_OP
EMI
EMI
6
KN
K
EN_FB
VDDD
L
EMI_D VSSIO_ EMI_D0
QM0 EMI
7
M
NC
GPMI_ GPMI_ GPMI_ GPMI_ EMI_A1 EMI_A0 EMI_BAVDDIO_ EMI_D0 VDDIO_ EMI_D0 VDDIO3
RDY0 CE0N RDY1 CE1N
4
7
2
EMI
3
EMI
0
3_EMI
N
ETM_T
CTL
NC
GPMI_ GPMI_ GPMI_ EMI_CE EMI_A0 VDDIO_ EMI_CE EMI_D0 VSSIO_ EMI_D0 VSSIO_ EMI_D0
ALE
CLE
WRN
1N
9
EMI
0N
4
EMI
2
EMI
5
P
NC
NC
NC
GPMI_ GPMI_ GPMI_ EMI_A0 VSSIO_ EMI_A0 VSSIO_ VDDIO_ EMI_VRVDDIO_EMI_RA EMI_O
RDN
D05
D02
6
EMI
5
EMI
EMI
EF0 EMIQ
SN
DT0
R
NC
NC
NC
NC
GPMI_ GPMI_ GPMI_ EMI_A1 EMI_A1 EMI_A0 EMI_BA EMI_CK VSSIO_ EMI_W EMI_BA EMI_O
D07
D04
D01
3
1
3
1
E
EMI
EN
0
DT1
T
VSS
NC
NC
NC
NC
GPMI_ GPMI_ GPMI_ EMI_A0 EMI_A0 EMI_A1 EMI_A0 EMI_A1 EMI_A0 EMI_A0 EMI_CA VSSIO_
D06
D03
D00
8
4
2
1
0
2
0
SN
EMI
U
1
2
3
4
5
6
7
8
NC
9
VDDIO_VDDIO_ VDDIO_ EMI_D0
VSS
EMI
EMI
EMI
1
K
10
11
12
13
14
15
16
17
Figure 48. 289-pin i.MX280 MAPBGA Ball Map
i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1
68
Freescale Semiconductor
5
Revision History
Table 67 summarizes revisions to this document.
Table 67. Revision History
Rev. #
Rev. 1
Date
Revision
04/2011 •
•
•
•
•
•
•
•
•
•
•
•
•
•
Rev. 0
Updated Section 1.1, “Device Features.”
Added Section 3.2, “Thermal Characteristics.”
In Table 1, "Ordering Information," on page 3, added two rows.
Updated Table 2, "i.MX28 Functional Differences," on page 3.
Updated Table 4, "i.MX28 Digital and Analog Modules," on page 6.
In Table 8, "Recommended Power Supply Operating Conditions," on page 13, updated BATT row.
Updated Table 9, "Operating Temperature Conditions," on page 13.
Replaced the term “DC Characteristics” with “Power Consumption” in the title and introduction of
Table 12, "Power Consumption," on page 14. Also changed Dissipation to Consumption in first row.
Updated Table 26, "Digital Pin DC Characteristics for GPIO in 3.3-V Mode," on page 21.
Updated Table 27, "Digital Pin DC Characteristics for GPIO in 1.8 V Mode," on page 23.
Updated and added a footnote to Table 34, "Ethernet PLL Specifications," on page 30.
Updated DDR1 row of Table 35, "EMI Command/Address AC Timing," on page 31.
In Section 4.6, “i.MX283 Ball Map,” replaced Figure 47.
Added Section 4.7, “i.MX280 Ball Map.”
09/2010 Initial release.
i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1
Freescale Semiconductor
69
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