Fairchild FAN6754BMRMY Integrated critical-mode pfc and quasi-resonant Datasheet

FAN6921AMR
Integrated Critical-Mode PFC and Quasi-Resonant
Current-Mode PWM Controller
Features
Description
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The highly integrated FAN6921AMR combines a Power
Factor Correction (PFC) controller and a QuasiResonant PWM controller. Integration provides costeffect design and allows for fewer external components.
Integrated PFC and Flyback Controller
Critical-Mode PFC Controller
Zero-Current Detection for PFC Stage
Quasi-Resonant Operation for PWM Stage
Internal Minimum tOFF 8 µs for QR PWM Stage
Internal 10 ms Soft-Start for PWM
Brownout Protection
High / Low Line Over-Power Compensation
Auto-Recovery Over-Current Protection
Auto-Recovery Open-Loop Protection
Externally Latch Triggering (RT Pin)
Adjustable Over-Temperature Latched (RT Pin)
VDD Pin and Output Voltage OVP (Latched)
Internal Over-Temperature Shutdown (140°C)
Applications



For PFC, FAN6921AMR uses a controlled on-time
technique to provide a regulated DC output voltage and
to perform natural power factor correction. An innovative
THD optimizer reduces input current distortion at zerocrossing duration to improve THD performance.
For PWM, FAN6921AMR provides several functions to
enhance power system performance: valley detection,
green-mode operation, high / low line over-power
compensation. Protection functions include secondaryside open-loop and over-current with auto-recovery
protection, external latch triggering, adjustable overtemperature protection by the RT pin and external NTC
resistor, internal over-temperature shutdown, VDD pin
OVP, DET pin over-voltage for output OVP, and brownin / out for AC input voltage UVP.
The FAN6921AMR controller is available in a 16-pin,
small-outline package (SOP).
AC/DC NB Adapters
Open-Frame SMPS
Battery Charger
Ordering Information
Part Number
OLP
Mode
Operating
Temperature Range
Package
Packing
Method
FAN6921AMRMY
Recovery
-40°C to +105°C
16-Pin, Small-Outline Package (SOP)
Tape & Reel
© 2010 Fairchild Semiconductor Corporation
FAN6921AMR • Rev. 1.0.2
www.fairchildsemi.com
FAN6921AMR — Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode PWM Controller
May 2013
14
6
ZCD
13
4
1
3
16
OPFC CSPFC INV RANGE HV
NC
VIN
FAN6921A
GND
OPWM
15
8
9
COMP
2
RT
FB
12
11
DET VDD
10
7
Figure 1. Typical Application
© 2010 Fairchild Semiconductor Corporation
FAN6921AMR • Rev. 1.0.2
CSPWM
5
FAN6921AMR — Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode PWM Controller
Application Diagram
www.fairchildsemi.com
2
COMP
HV
VDD
2
16
7
RANGE
Multi-Vector Amp.
2 .65V
2 .75V
RANGE
2.75V
2 .9V
27.5V
Latched
S
4
PFC
Current Limit
0.82 V
FB
11
OPFC
CLR
Q
PFC Zero-Current
Detector
Disable
Function
2. 1V/ 1.75V
Inhibit
Timer
0 .2V
ZCD
10V
IZCD
Auto-Recovery Protection
2. 25ms
28µ s
2R
14
0. 65V
FB OLP
Timer
50ms
4 .2 V
Soft- Start
10ms
PFC &
Multi-Vector Amp.
ON / OFF
Debounce
2. 5ms / 500 ms
VCTL - PFC- ON / OFF
ZFB
6
Q
Restarter
Sawtooth
Generator
/ tON -MAX
THD
Optimizer
CSPFC
R
Brownout
2 .5V
SET
15.5V
Latched
3
Blanking
Circuit
NC
DRV
Debounce
70µs
0.45V
15
Two-Step
UVLO
18V/10V/ 7.5 V
UVP
2. 35V
INV
Internal
Bias
OVP
IHV
OVP
VB
Starter
R
CSPWM
5
DRV
Blanking
Circuit
S
PWM
Current Limit
Over-Power
Compensation
R
Latched
I DET
Valley
Detector
st
1
Valley
S /H
Latched
tOFF -MIN
+9µ s
VINV
1V /1.3 V
0. 5V
Latched
Brownout
Comparator
Debounce
100ms
110µs
10ms
Prog. OTP
/ Externally Triggering
2 .1V /2. 45V
9
12
13
GND
RT
VIN
Figure 2. Functional Block Diagram
© 2010 Fairchild Semiconductor Corporation
FAN6921AMR • Rev. 1.0.2
RANGE
Latched
Protection
Debounce
100ms
1. 2V
0 .8 V
I DET
Internal
OTP
1
Q
VB & Clamp
V COMP to 1 .6V
0 .7 V
5V
OPWM
Startup
IRT
100µA
10
CLR
DET Pin OVP
VDD Pin OVP
Internal OTP
Brownout
Protection
Debounce
Time
2 .5V
DET OVP
DET
8
RT Pin Prog. OTP
RT Pin Externally Triggering
Latched
V DET
t OFF
Blanking
(4 µs)
Q
17.5V
IDET
tOFF -MIN
(8 µs/ 37µ s/2 .25ms)
SET
PFC RANGE Control
FAN6921AMR — Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode PWM Controller
Internal Block Diagram
www.fairchildsemi.com
3
16
- Fairchild Logo
Z - Plant Code
X - Year Code (1-Digit for SOP, 2-Digit for DIP)
Y - Week Code (1-Digit for SOP, 2-Digit for DIP)
TT–Die-Run Code
F - Frequency (M=Low, H=High Level)
O - OLP Mode (L=Latch, R=Recovery)
T - Package Type (N=DIP, M=SOP)
P - Y:Green Package
M - Manufacture Flow Code
ZXYTT
FAN6921AFO
TPM
1
Figure 3. Marking Diagram
Pin Configuration
RANGE
1
16
HV
COMP
2
15
NC
3
14
ZCD
CSPFC
4
13
VIN
CSPWM
5
12
RT
OPFC
6
11
FB
VDD
7
10
DET
OPWM
8
9
GND
INV
Figure 4. Pin Configuration
Pin Definitions
Pin #
Name
Description
1
RANGE
RANGE pin’s impedance changes according to the VIN pin voltage level. When the input voltage
detected by the VIN pin is lower than a threshold voltage, it sets to high impedance; whereas it
sets to low impedance if input voltage is at a high level.
2
COMP
Output pin of the error amplifier. Transconductance-type error amplifier for PFC output voltage
feedback. Proprietary multi-vector current is built-in to this amplifier; therefore, the compensation
for PFC voltage feedback loop allows a simple compensation circuit between this pin and GND.
3
INV
Inverting input of the error amplifier. This pin is used to receive PFC voltage level by a voltage
divider and provides PFC output over- and under-voltage protections.
FAN6921AMR — Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode PWM Controller
Marking Information
Input to the PFC over-current protection comparator that provides cycle-by-cycle current limiting
protection. When the sensed voltage across the PFC current-sensing resistor reaches the
internal threshold (0.82 V typical), the PFC switch is turned off to activate cycle-by-cycle current
limiting.
4
CSPFC
5
Input to the comparator of the PWM over-current protection and performs PWM current-mode
control with FB pin voltage. A resistor is used to sense the switching current of the PWM switch
CSPWM and the sensing voltage is applied to the CSPWM pin for the cycle-by-cycle current limit, currentmode control, and high / low line over-power compensation according to the DET pin source
current during PWM tON time.
Continued on the following page…
© 2010 Fairchild Semiconductor Corporation
FAN6921AMR • Rev. 1.0.2
www.fairchildsemi.com
4
Pin #
Name
6
OPFC
7
VDD
8
OPWM
9
GND
The power ground and signal ground.
DET
This pin is connected to an auxiliary winding of the PWM transformer through a resistor divider for
the following purposes:
 Producing an offset voltage to compensate the threshold voltage of PWM current limit for
providing over-power compensation. The offset is generated in accordance with the input
voltage when the PWM switch is on.
 Detecting the valley voltage signal of drain voltage of the PWM switch to achieve the valley
voltage switching and minimize the switching loss on the PWM switch.
 Providing output over-voltage protection. A voltage comparator is built-in to the DET pin. The
DET pin detects the flat voltage through a voltage divider paralleled with auxiliary winding. This
flat voltage is reflected to the secondary winding during PWM inductor discharge time. If output
OVP and this flat voltage is higher than 2.5 V, the controller enters latch mode and stops all
PFC and PWM switching operation.
10
Description
Totem-pole driver output to drive the external power MOSFET. The clamped gate output voltage
is 15.5 V.
Power supply. The threshold voltages for startup and turn-off are 18 V and 7.5 V, respectively.
The startup current is less than 30 µA and the operating current is lower than 10 mA.
Totem-pole output generates the PWM signal to drive the external power MOSFET. The clamped
gate output voltage is 17.5 V.
11
FB
Feedback voltage pin. This pin is used to receive the output voltage level signal to determine
PWM gate duty for regulating output voltage. The FB pin voltage can also activate open-loop,
overload, and output-short circuit protection if the FB pin voltage is higher than a threshold of
around 4.2 V for more than 50 ms.The input impedance of this pin is a 5 kΩequivalent
resistance. A one-third attenuator is connected between the FB pin and the input of the
CSPWM/FB comparator.
12
RT
Adjustable over-temperature protection and external latch triggering. A constant current is flowed
out of the RT pin. When the RT pin voltage is lower than 0.8 V (typical), latch-mode protection is
activated and stops all PFC and PWM switching operation until the AC plug is dicconnected.
13
VIN
Line-voltage detection for brown-in / out protections. This pin can receive the AC input voltage
level through a voltage divider. The voltage level of the VIN pin is not only used to control
RANGE pin’s status; (ZCD) can also perform brown-in / out protection for AC input voltage UVP.
14
ZCD
Zero-current detection for the PFC stage. This pin is connected to an auxiliary winding coupled to
PFC inductor winding to detect the ZCD voltage signal once the PFC inductor current discharges
to zero. When the ZCD voltage signal is detected, the controller starts a new PFC switching
cycle. When the ZCD pin voltage is pulled to under 0.2 V (typical), it disables the PFC stage and
the controller stops PFC switching. This can be achieved with an external circuit if disabling the
PFC stage is desired.
15
NC
No connection
16
HV
High-voltage startup. HV pin is connected to the AC line voltage through a resistor 100 kΩtypical)
for providing a high charging current to VDD capacitor.
© 2010 Fairchild Semiconductor Corporation
FAN6921AMR • Rev. 1.0.2
FAN6921AMR — Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode PWM Controller
Pin Definitions (Continued)
www.fairchildsemi.com
5
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Min.
Max.
Unit
30
V
VDD
DC Supply Voltage
VHV
HV Pin Voltage
500
V
VH
OPFC, OPWM Pin Voltage
-0.3
25.0
V
VL
Other Pins (INV, COMP, CSPFC, DET, FB, CSPWM, RT)
-0.3
7.0
V
Input Voltage to ZCD Pin
-0.3
12.0
V
VZCD
Power Dissipation
800
mW
θJA
PD
Thermal Resistance (Junction-to-Air)
104
°C/W
θJC
Thermal Resistance (Junction-to-Case)
TJ
TSTG
TL
ESD
41
°C/W
Operating Junction Temperature
-40
+150
°C
Storage Temperature Range
-55
+150
°C
+260
°C
Lead Temperature (Soldering 10 Seconds)
Human Body Model, JESD22-A114 (All Pins Except HV Pin)
(3)
Charged Device Model, JESD22-C101 (All Pins Except HV Pin)
5000
(3)
2000
V
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
2. All voltage values, except differential voltages, are given with respect to GND pin.
3. All pins including HV pin: CDM=1000 V, HBM 1000 V.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
TA
Parameter
Operating Ambient Temperature
© 2010 Fairchild Semiconductor Corporation
FAN6921AMR • Rev. 1.0.2
Min.
Max.
Unit
-40
+105
°C
FAN6921AMR — Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode PWM Controller
Absolute Maximum Ratings
www.fairchildsemi.com
6
VDD=15 V, TA=-40°C~105°C (TA=TJ), unless otherwise specified.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
25
V
19.5
V
VDD Section
VOP
Continuously Operating Voltage
VDD-ON
Turn-On Threshold Voltage
16.5
VDD-PWM-OFF
PWM-Off Threshold Voltage
9
10
11
V
VDD-OFF
Turn-Off Threshold Voltage
6.5
7.5
8.5
V
20
30
µA
10
mA
IDD-ST
Startup Current
VDD=VDD-ON - 0.16 V,
Gate Open
IDD-OP
Operating Current
VDD=15 V;
OPFC, OPWM=100 kHz;
CL-PFC, CL-PWM=2 nF
IDD-GREEN
Green-Mode Operating Supply
Current (Average)
VDD=15 V,
OPWM=450 Hz,
CL-PWM=2 nF
IDD-PWM-OFF
Operating Current at PWM-Off
Phase
VDD=VDD-PWM-OFF - 0.5 V
18.0
5.5
mA
70
120
170
µA
VDD-OVP
VDD Over-Voltage Protection
(Latch-Off)
26.5
27.5
28.5
V
tVDD-OVP
VDD OVP Debounce Time
100
150
200
µs
IDD-LATCH
VDD Over-Voltage Protection
Latch-Up Holding Current
VDD=7.5 V
120
µA
HV Startup Current Source Section
VHV-MIN
IHV
Minimum Startup Voltage on HV
Pin
Supply Current Drawn from HV Pin
50
VAC=90 V (VDC=120 V),
VDD=0 V
1.3
HV=500 V,
VDD= VDD-OFF +1 V
V
mA
1
µA
VIN and RANGE Section
VVIN-UVP
Threshold Voltage for AC Input
Under-Voltage Protection
0.95
1.00
1.05
V
VVIN-RE-UVP
Under-Voltage Protection Reset
Voltage (for Startup)
VVIN-UVP
+0.25V
VVIN-UVP
+0.30V
VVIN-UVP
+0.35V
V
70
100
130
ms
tVIN-UVP
Under-Voltage Protection
Debounce Time (No Need at
Startup and Hiccup Mode)
VVIN-RANGE-H
High VVIN Threshold for RANGE
Comparator
2.40
2.45
2.50
V
VVIN-RANGE-L
Low VVIN Threshold for RANGE
Comparator
2.05
2.10
2.15
V
70
100
130
ms
tRANGE
Range Enable / Disable Debounce
Time
VRANGE-OL
Output Low Voltage of RANGE Pin IO=1 mA
0.5
V
IRANGE-OH
Output High Leakage Current of
RANGE Pin
RANGE=5 V
50
nA
PFC Maximum On-Time
RMOT=24 k
28
µs
tON-MAX-PFC
22
25
FAN6921AMR — Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode PWM Controller
Electrical Characteristics
Continued on the following page…
© 2010 Fairchild Semiconductor Corporation
FAN6921AMR • Rev. 1.0.2
www.fairchildsemi.com
7
VDD=15 V, TA=-40°C ~105°C (TA=TJ), unless otherwise specified.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
100
125
150
µmho
2.465
2.500
2.535
V
RANGE=Open
2.70
2.75
2.80
RANGE=Ground
2.60
2.65
2.70
VINVH / VREF,
RANGE=Open
1.06
1.14
VINVH / VREF,
RANGE=Ground
1.04
1.08
PFC Stage
Voltage Error Amplifier Section
(4)
Gm
Transconductance
VREF
Feedback Comparator Reference
Voltage
VINV-H
Clamp High Feedback Voltage
VRATIO
VINV-L
Clamp High Output Voltage Ratio
(4)
Clamp Low Feedback Voltage
V
V/V
2.35
2.45
RANGE=Open
2.25
2.90
2.95
V
RANGE=Ground
2.75
2.80
50
70
90
µs
0.35
0.45
0.55
V
50
70
90
µs
VINV-OVP
Over-Voltage Protection for INV
Input
tINV-OVP
Over-Voltage Protection Debounce
Time
VINV-UVP
Under-Voltage Protection for INV
Input
tINV-UVP
Under-Voltage Protection
Debounce Time
VINV-BO
PWM and PFC Off Threshold for
Brownout Protection
1.15
1.20
1.25
V
VCOMP-BO
Limited Voltage on COMP Pin for
Brownout Protection
1.55
1.60
1.65
V
VCOMP
Comparator Output High Voltage
4.8
6.0
V
Zero Duty Cycle Voltage on COMP
Pin
1.10
1.25
1.40
V
15
30
45
µA
0.50
0.75
1.00
mA
RANGE=Open,
VINV=2.75 V, VCOMP=5 V
20
30
40
RANGE=Ground,
VINV=2.65 V, VCOMP=5 V
20
30
40
VOZ
Comparator Output Source
Current
ICOMP
Comparator Output Sink Current
VINV=2.3 V, VCOMP=1.5 V
VINV=1.5 V
V
µA
PFC Current-Sense Section
VCSPFC
Threshold Voltage for Peak
Current Cycle-by-Cycle Limit
tPD
Propagation Delay
tBNK
Leading-Edge Blanking Time
AV
CSPFC Compensation Ratio for
THD
VCOMP=5 V
0.82
V
110
200
ns
110
180
250
ns
0.90
0.95
1.00
V/V
FAN6921AMR — Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode PWM Controller
Electrical Characteristics (Continued)
Continued on the following page…
© 2010 Fairchild Semiconductor Corporation
FAN6921AMR • Rev. 1.0.2
www.fairchildsemi.com
8
VDD=15 V, TA=-40°C ~105°C (TA=TJ), unless otherwise specified.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
14.0
15.5
17.0
V
1.5
V
PFC Output Section
VZ
PFC Gate Output Clamping
Voltage
VDD=25 V
VOL
PFC Gate Output Voltage Low
VDD=15 V, IO=100 mA
VOH
PFC Gate Output Voltage High
VDD=15 V, IO=100 mA
8
tR
PFC Gate Output Rising Time
VDD=12 V, CL=3 nF,
20~80%
30
65
100
ns
tF
PFC Gate Output Falling Time
VDD=12 V, CL=3 nF,
80~20%
30
50
70
ns
Input Threshold Voltage Rising
Edge
VZCD Increasing
1.9
2.1
2.3
V
VZCD-HYST
Threshold Voltage Hysteresis
VZCD Decreasing
0.25
0.35
0.45
V
VZCD-HIGH
Upper Clamp Voltage
IZCD=3 mA
8
10
VZCD-LOW
Lower Clamp Voltage
0.40
0.65
0.90
V
VZCD-SSC
Starting Source Current
Threshold Voltage
1.3
1.4
1.5
V
200
ns
V
PFC Zero-Current Detection Section
VZCD
tDELAY
tRESTART-PFC
Maximum Delay from ZCD to
Output Turn-On
VCOMP=5 V, fS=60 kHz
100
V
Restart Time
300
500
700
µs
Inhibit Time (Maximum Switching
VCOMP=5 V
Frequency Limit)
1.5
2.5
3.5
µs
VZCD-DIS
PFC Enable / Disable Function
Threshold Voltage
0.15
0.20
0.25
V
tZCD-DIS
PFC Enable / Disable Function
Debounce Time
100
150
200
µs
tINHIB
VZCD=100 mV
Continued on the following page…
© 2010 Fairchild Semiconductor Corporation
FAN6921AMR • Rev. 1.0.2
FAN6921AMR — Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode PWM Controller
Electrical Characteristics (Continued)
www.fairchildsemi.com
9
VDD=15 V, TA=-40°C ~105°C (TA=TJ), unless otherwise specified.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
1/2.75
1/3.00
1/3.25
V/V
3
5
7
kΩ
1.2
2.0
mA
PWM STAGE
Feedback Input Section
AV
Input-Voltage to Current-Sense
(4)
Attenuation
ZFB
Input Impedance
FB>VG
IOZ
Bias Current
FB=VOZ
VOZ
Zero Duty-Cycle Input Voltage
0.7
0.9
1.1
V
VFB-OLP
Open-Loop Protection Threshold
Voltage
3.9
4.2
4.5
V
tFB-OLP
Debounce Time for Open-Loop
Protection
40
50
60
ms
tFB-SS
Internal Soft-Start Time
8.5
9.5
10.5
ms
2.45
2.50
2.55
V
(4)
(4)
AV=△VCSPWM /△VFB,
0<VCSPWM<0.9
VFB=0 V~3.6 V
DET Pin OVP and Valley Detection Section
VDET-OVP
Av
BW
tDET-OVP
IDET-SOURCE
Comparator Reference Voltage
(4)
Open-Loop Gain
Gain Bandwidth
(4)
Output OVP (Latched) Debounce
Time
100
Maximum Source Current
VDET=0 V
VDET-HIGH
Upper Clamp Voltage
IDET=-1 mA
VDET-LOW
Lower Clamp Voltage
IDET=1 mA
60
dB
1
MHz
150
200
µs
1
mA
5
V
0.5
0.7
0.9
V
150
200
250
ns
tOFF-BNK
Leading-Edge Blanking Time for
DET-OVP (2.5V) and Valley
Signal when PWM MOS Turns
(4)
Off
3
4
5
µs
tTIME-OUT
Time-Out After tOFF-MIN
8
9
10
µs
38
45
52
µs
VFB≧VN, TA=25°C
7
8
9
VFB=VG
32
37
42
tVALLEY-DELAY
Delay from Valley Signal
(4)
Detected to Output Turn-on
PWM Oscillator Section
tON-MAX-PWM
Maximum On Time
tOFF-MIN
Minimum Off-Time
µs
VN
Beginning of Green-On Mode at
FB Voltage Level
1.95
2.10
2.25
V
VG
Beginning of Green-Off Mode at
FB Voltage Level
1.00
1.15
1.30
V
ΔVG
Hysteresis for Beginning of
Green-Off Mode at FB Voltage
Level
0.1
FAN6921AMR — Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode PWM Controller
Electrical Characteristics (Continued)
V
Continued on the following page…
© 2010 Fairchild Semiconductor Corporation
FAN6921AMR • Rev. 1.0.2
www.fairchildsemi.com
10
VDD=15V, TA=-40°C ~105°C (TA=TJ), unless otherwise specified.
Symbol
VCTL-PFC-OFF
VCTL-PFC-ON
Parameter
Threshold Voltage on FB Pin for
PFC EnableDisable
Threshold Voltage on FB Pin for
PFC Disable  Enable
Condition
Min.
Typ.
Max.
RANGE Pin Internally
Open
1.80
1.85
1.90
RANGE Pin Internally
Ground
1.75
1.80
1.85
RANGE Pin Internally
Open
1.90
1.95
2.00
RANGE Pin Internally
Ground
1.80
1.85
1.90
Unit
V
V
tPFC-OFF
PFC Disable Debounce Time
PFC Enable 
Disable
400
500
600
ms
tPFC-ON
PFC Enable Debounce Time
PFC Disable 
Enable
2.0
2.5
3.0
ms
VFB ＜VG
1.85
2.25
2.65
ms
22
28
34
µs
16.0
17.5
19.0
V
1.5
V
tSTARTER-PWM Start Timer (Time-Out Timer)
VFB ＞VFB-OLP
PWM Output Section
VCLAMP
PWM Gate Output Clamping
Voltage
VDD=25 V
VOL
PWM Gate Output Voltage Low
VDD=15 V, IO=100 mA
VOH
PWM Gate Output Voltage High
VDD=15 V, IO=100 mA
tR
PWM Gate Output Rising Time
CL=3 nF, VDD=12 V,
20~80%
80
110
ns
tF
PWM Gate Output Falling Time
CL=3 nF, VDD=12 V,
20~80%
40
70
ns
150
200
ns
8
V
Current Sense Section
tPD
VLIMIT
Delay to Output
Limit Voltage on CSPWM Pin for
Over-Power Compensation
(4)
IDET ＜75 µA, TA=25°C
0.81
0.84
0.87
IDET=185 µA, TA=25°C
0.69
0.72
0.75
IDET=350 µA, TA=25°C
0.55
0.58
0.61
IDET=550 µA, TA=25°C
0.37
0.40
0.43
tON=45 µs,
RANGE=Open
0.25
0.30
0.35
tON=0 µs
0.05
0.10
0.15
VSLOPE
Slope Compensation
tON-BNK
Leading-Edge Blanking Time
VCS-FLOATING
CSPWM Pin Floating VCSPWM
Clamped High Voltage
CSPWM Pin Floating
Delay with CSPWM Pin Floating
CSPWM Pin Floating
tCS-H
300
4.5
V
ns
5.0
150
V
V
µs
Continued on the following page…
© 2010 Fairchild Semiconductor Corporation
FAN6921AMR • Rev. 1.0.2
FAN6921AMR — Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode PWM Controller
Electrical Characteristics (Continued)
www.fairchildsemi.com
11
VDD=15 V, TA=-40°C ~105°C (TA=TJ), unless otherwise specified.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
+125
+140
+155
°C
RT Pin Over-Temperature Protection Section
TOTP
TOTP-HYST
IRT
VRT-LATCH
Internal Threshold Temperature
(4)
for OTP
Hysteresis Temperature for
(4)
Internal OTP
30
Internal Source Current of RT Pin
90
Latch-Mode Triggering Voltage
VRT-RE-LATCH
Latch-Mode Release Voltage
VRT-OTP-LEVEL
Threshold Voltage for Two-level
Debounce Time
tRT-OTP-H
Debounce Time for OTP
tRT-OTP-L
Debounce Time for Externally
Triggering
110
µA
0.75
0.80
0.85
V
VRT-LATCH
+0.15
VRT-LATCH
+0.20
VRT-LATCH
+0.25
V
0.45
0.50
0.55
V
10
VRT<VRT-OTP-LEVEL
Note:
4. Guaranteed by design.
© 2010 Fairchild Semiconductor Corporation
FAN6921AMR • Rev. 1.0.2
100
°C
70
110
ms
150
µs
FAN6921AMR — Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode PWM Controller
Electrical Characteristics (Continued)
www.fairchildsemi.com
12
These characteristic graphs are normalized at TA=25°C.
11.0
VDD-PWM-OFF (V)
18.5
VDD-ON (V)
18.0
17.5
17.0
16.5
10.5
10.0
9.5
9.0
-40 -25 -10
5
20
35
50
65
80
95 110 125
-40 -25 -10
5
35
50
65
80
95 110 125
Figure 5. Turn-On Threshold Voltage
Figure 6. PWM Off Threshold Voltage
8.5
29.0
8.0
28.5
7.5
7.0
6.5
28.0
27.5
27.0
-40 -25 -10
5
20
35
50
65
80
95 110 125
-40 -25 -10
5
Temperature(oC)
20
35
50
65
80
95 110 125
Temperature(oC)
Figure 7. Turn-Off Threshold Voltage
Figure 8. VDD Over-Voltage Protection Threshold
16.0
8.0
14.0
7.0
IDD-OP (mA)
IDD-ST (mA)
20
Temperature(oC)
VDD-OVP (V)
VDD-OFF (V)
Temperature(oC)
12.0
10.0
8.0
6.0
6.0
5.0
4.0
-40 -25 -10
5
20
35
50
65
80
95 110 125
-40 -25 -10
5
Temperature(oC)
20
35
50
65
80
95 110 125
Temperature(oC)
Figure 9. Startup Current
Figure 10. Operating Current
2.60
17.0
16.5
16.0
VZ(V)
VREF (V)
2.55
FAN6921AMR — Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode PWM Controller
Typical Performance Characteristics
2.50
15.5
15.0
2.45
14.5
14.0
2.40
-40 -25 -10
5
20
35
50
65
80
-40 -25 -10
95 110 125
Figure 11. PFC Output Feedback Reference Voltage
© 2010 Fairchild Semiconductor Corporation
FAN6921AMR • Rev. 1.0.2
5
20
35
50
65
80
95 110 125
Temperature(oC)
Temperature(oC)
Figure 12. PFC Gate Output Clamping Voltage
www.fairchildsemi.com
13
These characteristic graphs are normalized at TA=25°C.
0.95
27.0
0.90
26.0
VCSPFC (V)
tON-MAX-PFC ( msec)
28.0
25.0
24.0
0.85
0.80
23.0
22.0
0.75
-40 -25 -10
5
20
35
50
65
80
95 110 125
-40 -25 -10
5
Temperature(oC)
65
80
95 110 125
Figure 14. PFC Peak Current Limit Voltage
50.0
tON-MAX-PWM (msec)
18.5
VCLAMP (V)
50
Temperature( C)
19.0
18.0
17.5
17.0
16.5
16.0
48.0
46.0
44.0
42.0
40.0
-40 -25 -10
5
20
35
50
65
80
95 110 125
-40 -25 -10
5
Temperature(oC)
20
35
50
65
80
95 110 125
Temperature(oC)
Figure 15. PWM Gate Output Clamping Voltage
Figure 16. PWM Maximum On-Time
2.3
1.4
2.2
1.3
VG(V)
VN(V)
35
o
Figure 13. PFC Maximum On-Time
2.1
2.0
1.2
1.1
1.9
1.0
-40 -25 -10
5
20
35
50
65
80
95 110 125
-40 -25 -10
5
o
20
35
50
65
80
95 110 125
o
Temperature( C)
Temperature( C)
Figure 17. Beginning of Green-On Mode at VFB
Figure 18. Beginning of Green-Off Mode at VFB
9.0
42.0
8.5
tOFF-MIN (msec)
tOFF-MIN (msec)
20
8.0
7.5
7.0
FAN6921AMR — Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode PWM Controller
Typical Performance Characteristics (Continued)
40.0
38.0
36.0
34.0
32.0
-40 -25 -10
5
20
35
50
65
80
95 110 125
-40 -25 -10
Temperature(oC)
20
35
50
65
80
95 110 125
Temperature(oC)
Figure 19. PWM Minimum Off-Time for VFB > VN
© 2010 Fairchild Semiconductor Corporation
FAN6921AMR • Rev. 1.0.2
5
Figure 20. PWM Minimum Off-Time for VFB=VG
www.fairchildsemi.com
14
These characteristic graphs are normalized at TA=25°C.
1.0
2.60
VDET-OVP (V)
VDET-LOW (V)
0.9
0.8
0.7
0.6
0.5
2.55
2.50
2.45
2.40
-40 -25 -10
5
20
35
50
65
80
95 110 125
-40 -25 -10
5
Temperature(oC)
35
50
65
80
95 110 125
Figure 22. Reference Voltage for Output
Over-Voltage Protection of DET Pin
Figure 21. Lower Clamp Voltage of DET Pin
110
0.90
105
0.85
VRT-LATCH (V)
IRT ( mA)
20
Temperature(oC)
100
95
90
0.80
0.75
0.70
-40 -25 -10
5
20
35
50
65
80
95 110 125
-40 -25 -10
Temperature(oC)
20
35
50
65
80
95 110 125
Temperature(oC)
Figure 24. Over-Temperature Protection
Threshold Voltage of RT Pin
Figure 23. Internal Source Current of RT Pin
© 2010 Fairchild Semiconductor Corporation
FAN6921AMR • Rev. 1.0.2
5
FAN6921AMR — Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode PWM Controller
Typical Performance Characteristics (Continued)
www.fairchildsemi.com
15
between calculated fixed on-time mechanism and fixed
on-time with THD Optimizer during a half AC cycle.
PFC Stage
Multi-Vector Error Amplifier and THD Optimizer
For better dynamic performance, faster transient
response, and precise clamping on PFC output,
FAN6921AMR uses a transconductance-type amplifier
with proprietary multi-vector error amplifier. The
schematic diagram of this amplifier is shown in Figure
25. The PFC output voltage is detected from the INV pin
by an external resistor divider circuit that consists of R 1
and R2. When PFC output variation voltage reaches 6%
over or under the reference voltage 2.5 V, the multivector error amplifier adjusts its output sink or source
current to increase the loop response to simplify the
compensated circuit.
2.65V
VCOMP
PFC VO
Error
Amplifier
RS
PFC
MOS Filp-Flop
R1
2.5V
3
THD
Optimizer
4
RS
+
INV

R2
+
CSPFC
Sawtooth
Generator
FAN6921A
Figure 26. Multi-Vector Error Amplifier with
THD Optimizer
PFC VO
IL,AVG (Fixed On-Time)
IL,AVG (with THD Optimizer)
2.35V
R1
COMP
2
CCOMP
2.5V
CO
INV
3
Error
Amplifier
R2
Gate Signal
with
THD Optimizer
VCOMP
FAN6921A
Sawtooth
Gate Signal with
Fixed On-Time
Figure 25. Multi-Vector Error Amplifier
The feedback voltage signal on the INV pin is compared
with reference voltage 2.5 V, which makes the error
amplifier source or sink current to charge or discharge
its output capacitor CCOMP. The COMP voltage is
compared with the internally generated sawtooth
waveform to determine the on-time of PFC gate.
Normally, with lower feedback loop bandwidth, the
variation of the PFC gate on-time should be very small
and almost constant within one input AC cycle.
However, the power-factor-correction circuit operating at
light-load condition has a defect, zero-crossing
distortion; which distorts input current and makes the
system’s Total Harmonic Distortion (THD) worse. To
improve the result of THD at light-load condition,
especially at high input voltage, an innovative THD
Optimizer is inserted by sampling the voltage across the
current-sense resistor. This sampling voltage is added
into the sawtooth waveform to modulate the on-time of
PFC gate, so it is not constant on-time within a half AC
cycle. The operation block between THD Optimizer and
PWM is shown in Figure 26. After THD Optimizer
processes, around the valley of AC input voltage, the
compensated on-time becomes wider than the original.
The PFC on-time, which is around the peak voltage, is
narrowed by the THD Optimizer. The timing sequences
of the PFC MOS and the shape of the inductor current
are shown in Figure 27. Figure 28 shows the difference
© 2010 Fairchild Semiconductor Corporation
FAN6921AMR • Rev. 1.0.2
OFF
ON
Figure 27. Operation Waveforms of Fixed On-Time
with and without THD Optimizer
Input Current
1.8
1.5
Current (A)
1.2
0.9
0.6
PO : 90W
Input Voltage : 90VAC
PFC Inductor : 460mH
CS Resistor : 0.15
0.3
0
0
0.0014
0.0028
0.0042
0.0056
Time (Seconds)
0.0069
0.0083
Fixed On-time with THD Optimizer
Fixed On time
FAN6921AMR — Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode PWM Controller
Functional Description
Figure 28. Calculated Waveforms of Fixed On-Time
with and without THD Optimizer During a Half
AC Cycle
www.fairchildsemi.com
16
VZCD
A built-in low voltage MOSFET can be turned on or off
according to VVIN voltage level. The drain pin of this
internal MOSFET is connected to the RANGE pin.
Figure 29 shows the status curve of VVIN voltage level
and RANGE impedance (open or ground).
10V
2.1V
1.75V
RANGE=
Ground
VDS
t
PFCVO
RANGE=
Open
VIN,MAX
VVIN-RANGE-L
VVIN
VVIN-RANGE-H
Figure 29. Hysteresis Behavior between RANGE Pin
and VIN Pin Voltage
Zero-Current Detection (ZCD Pin)
Figure 30 shows the internal block of zero-current
detection. The detection function is performed by
sensing the information on an auxiliary winding of the
PFC inductor. Referring to Figure 31, when the PFC
MOS is off, the stored energy of the PFC inductor starts
to release to the output load. Then the drain voltage of
PFC MOS starts to decrease since the PFC inductor
resonates with parasitic capacitance. Once the ZCD pin
voltage is lower than the triggering voltage (1.75 V
typical), the PFC gate signal is sent again to start a new
switching cycle.
If PFC operation needs to be shut down due to
abnormal conditions, pull the ZCD pin LOW, to a voltage
under 0.2 V (typical), to activate the PFC-disable
function to stop PFC switching.
For preventing excessive high-switching frequency at
light load, a built-in inhibit timer is used to limit the
minimum tOFF time. Even if the ZCD signal has been
detected, the PFC gate signal is not sent during the
inhibit time (2.5 µs typical).
t
PFC
Gate
Inhibit
Time
t
Figure 31. Operation Waveforms of PFC
Zero-Current Detection
Protection for PFC Stage
PFC Output Voltage UVP and OVP (INV Pin)
FAN6921AMR provides several kinds of protection for
the PFC stage. PFC output over- and under-voltage are
essential for the PFC stage. Both are detected and
determined by INV pin voltage, as shown in Figure 32.
When the INV pin voltage is over 2.75 V or under 0.45 V
due to overshoot or abnormal conditions and lasts for a
de-bounce time around 70µs, the OVP or UVP circuit is
activated to stop PFC switching operation immediately.
The INV pin is not only used to receive and regulate
PFC output voltage, but can also perform PFC output
OVP/ UVP protection. For failure-mode test, this pin can
shut down PFC switching if pin floating occurs.
1.4V
PFC VO
PFC Gate
Drive
Q
Driver
R
ZCD
0.2V
S
5
1.75V
PFC Gate On
VCOMP
COMP
2
Lb
10V
S
Q R
VREF (2.5V)
VAC
RZCD
Debounce
Time
CCOMP
2.1V
1:n
FAN6921A
Figure 30. Zero-Current Detection
R1
INV
Voltage
Detector
FAN6921 — Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode PWM Controller
RANGE Pin
CO
1
Error
R2
Amplifier
OVP = (VINV ≥ 2.75V)
UVP = (VINV ≤ 0.45V)
FAN6921A
Figure 32. PFC Over-and Under-Voltage Protection
© 2009 Fairchild Semiconductor Corporation
FAN6921A • Rev. 1.0.2
www.fairchildsemi.com
17
During PFC stage switching operation, the PFC
switch current is detected by a current-sense resistor
on the CSPFC pin and the detected voltage on this
resistor is delivered to the input terminal of a
comparator and compared with a threshold voltage of
0.82 V (typical). Once the CSPFC pin voltage is
higher than the threshold voltage, the PFC gate is
turned off immediately.
The PFC peak switching current is adjustable by the
current-sense resistor. Figure 33 shows the measured
waveform of PFC gate and CSPFC pin voltage.
AC Input
1.6V
VVIN-UVP
VVIN
PFC MOS Current Limit
0.82V
CSPFC
VCOMP-BO
VCOMP
VVIN-RE-UVP
0V
VINV-BO
2.5V
VINV
1.2V
OPWM
OPFC
OPFC
Brownout
Protection
Debounce
Time 100ms
Figure 33. Cycle-by-Cycle Current Limiting
© 2009 Fairchild Semiconductor Corporation
FAN6921A • Rev. 1.0.2
Hiccup
Mode
Figure 34. Operation Waveforms of Brown-In /
Out Protection
Brown-In / Out Protection (VIN Pin)
With AC voltage detection, FAN6921AMR can perform
brown-in / out protection (AC voltage UVP). Figure 34
shows the key operation waveforms of brown-in / out
protection. Both use the VIN pin to detect AC input
voltage level and the VIN pin is connected to AC input
by a resistor divider (refer to Figure 1); therefore, the
VVIN voltage is proportional to the AC input voltage.
When the AC voltage drops and VVIN voltage is lower
than 1 V for 100 ms, the UVP protection is activated and
the COMP pin voltage is clamped around 1.6 V.
Because PFC gate duty is determined by comparing the
sawtooth waveform and COMP pin voltage, lower
COMP voltage results in narrow PFC on-time, so that
the energy converged is limited and the PFC output
voltage decreases. When INV pin is lower than 1.2 V,
FAN6921AMR stops all PFC and PWM switching
operation immediately until VDD voltage drops to turn-off
voltage then rises to turn-on voltage again (UVLO).
When the brownout protection is activated, all switching
operation is turned off, and VDD voltage enters “Hiccup”
mode going up and down continuously. Until VVIN
voltage is higher than 1.3 V (typical) and VDD reaches
turn-on voltage again, the PWM and PFC gate is sent
out. The measured waveforms of brown-in / out
protection are shown in Figure 35.
Brownout
Protection
VDD
VDD Hiccup Mode
Brownout
Brown-In
AC Input
OPWM
OPFC
Figure 35. Measured Waveform of Brown-In / Out
Protection (Adapter Application)
FAN6921 — Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode PWM Controller
PFC Peak Current Limiting (CSPFC Pin)
www.fairchildsemi.com
18
HV Startup and Operating Current (HV Pin)
The HV pin is connected to the AC line through a
resistor (refer to Figure 1). With a built-in high-voltage
startup circuit, when AC voltage is applied to power
system, FAN6921AMR provides a high current to
charge external VDD capacitor to reduce the controller’s
startup time and build up normal rated output voltage
within three seconds. To save power consumption, after
VDD voltage exceeds turn-on voltage and enters normal
operation; this high-voltage startup circuit is shut down
to avoid power loss from the startup resistor.
Figure 36 shows the characteristic curve of VDD voltage
and operating current IDD. When VDD voltage is lower
than VDD-PWM-OFF, FAN6921AMR stops all switching
operation and turns off some internal circuits to reduce
operating current. By doing so, the period from VDD-PWMOFF to VDD-OFF can be extended and the Hiccup Mode
frequency can be decreased to reduce the input power
in case of output short circuit. Figure 37 shows the
typical waveforms of VDD voltage and gate signal in
Hiccup Mode.
When the valley signal is detected, FAN6921AMR
outputs PWM gate signal to turn on the switch and
begin a new switching cycle.
With Green Mode and valley detection at light-load
condition; the power system can perform extended
valley switching in DCM operation and can further
reduce switching loss for better conversion efficiency.
The FB pin voltage versus tOFF-MIN time characteristic
curve is shown in Figure 38. Figure 38 shows, tOFF time
narrowed to 2.25 ms, which is around 440 Hz switching
frequency.
Referring to Figure 1 and Figure 2, FB pin voltage is not
only used to receive secondary feedback signal to
determine gate on-time, but also determines PFC stage
on or off status. At no-load or light-load conditions, if PFC
stage is set to be off; that can reduce power consumption
from the PFC stage switching device and increase
conversion efficiency. When output loading is decreased,
the FB pin voltage becomes lower and the FAN6921AMR
can detect the output loading level according to the FB
pin voltage to control the on / off status of the PFC part.
tOFF-MIN
IDD
2.25ms
IDD-OP
PFC On
PFC OFF
IDD-PWM-OFF
37µs
IDD-ST
V CTL-PFC-ON
V CTL-PFC-OFF
8µs
VDD
VDD-OFF VDD-PWM-OFF VDD-ON
1.15V(VG )
Figure 36. VDD vs. IDD-OP Characteristic Curve
Figure 38. VFB vs. tOFF-MIN Characteristic Curve
VDD-ON
VDD-PWM-OFF
IDD-OP
VDD-OFF
Gate
2.1V(VN)
IDD-PWM-OFF IDD-ST
Figure 37. Typical Waveform of VDD Voltage and
Gate Signal in Hiccup Mode
Green Mode and PFC-ON / OFF Control (FB Pin)
Green Mode is used to reduce power loss in the system
(e.g. switching loss). An off-time modulation technique
regulates switching frequency according to FB pin
voltage. When output loading is decreased, FB voltage
becomes lower due to secondary feedback movement
and the tOFF-MIN is extended. After tOFF-MIN (determined by
FB voltage), the internal valley-detection circuit is
activated to detect the valley on the drain voltage of the
PWM switch.
© 2009 Fairchild Semiconductor Corporation
FAN6921A • Rev. 1.0.2
Valley Detection (DET Pin)
When FAN6921AMR operates in Green Mode, tOFF-MIN
time is determined by the Green-Mode circuit, according
to FB pin voltage level. After tOFF-MIN, the internal valleydetection circuit is activated. During the tOFF time of
PWM switch, when transformer inductor current
discharges to zero; the transformer inductor and
parasitic capacitor of PWM switch start to resonate
concurrently. When the drain voltage on the PWM
switch falls, the voltage across on auxiliary winding V AUX
also decreases since auxiliary winding is coupled to
primary winding. Once the VAUX voltage resonates and
falls to negative, VDET voltage is clamped by the DET pin
(refer to Figure 39) and FAN6921AMR is forced to flow
out a current IDET. FAN6921AMR reflects and compares
this IDET current. If this source current rises to a
threshold current, PWM gate signal is sent out after a
fixed delay (200 ns typical).
FAN6921 — Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode PWM Controller
PWM Stage
www.fairchildsemi.com
19
DET
10
0.3V
+
IDET
VDET
FAN6921A
-
+
RDET
VAUX
RA
-
Figure 39. Valley Detection
As the input voltage increases, the reflected voltage on
the auxiliary winding VAUX becomes higher as well as
the current IDET and the controller regulates the VLIMIT to
a lower level.
The RDET resistor is connected from the auxiliary
winding to the DET pin. Engineers can adjust this R DET
resistor to get proper VLIMIT voltage to fit power system
needs. The characteristic curve of IDET current vs. VLIMIT
voltage on CSPWM pin is shown in Figure 42.
I DET  VIN   N A N P  RDET
where VIN is input voltage; NA is turn number of
auxiliary winding; and NP is turn number of primary
winding.
Start to
Idet Flow Out
Detect Valley from DET Pin
VAUX
0V
VAUX
Delay Time
and then
Trigger Gate
Signal
VDET
0V
VDET
Valley
Switching
0V
(1)
VAUX= -[VIN*(NA/NP)]
DET Pin Voltage is
Clamped during ton-time
Period
OPWM
tOFF
0V
tON
tOFF
OPWM
Figure 40. Measured Waveform of Valley Detection
Referring to Figure 41, during tON period of the PWM
switch, the input voltage is applied to primary winding
and the voltage across on auxiliary winding V AUX is
proportional to the primary winding voltage. As the input
voltage increases, the reflected voltage on the auxiliary
winding VAUX becomes higher as well. FAN6921AMR
also clamps the DET pin voltage and flows out a current
IDET. Since the current IDET is in accordance with VAUX
voltage, FAN6921AMR can depend on this current IDET
during tON period to regulate the current-limit level of the
PWM switch to perform high / low line over-power
compensation.
© 2009 Fairchild Semiconductor Corporation
FAN6921A • Rev. 1.0.2
Figure 41. Relationship between VAUX and VIN
900
800
700
VLIMIT(mV)
High / Low Line Over-Power Compensation
(DET Pin)
Generally, when the power switch turns off, there is a
delay from gate signal falling edge to power switch off.
This delay is produced by an internal propagation delay
of the controller and the turn-off delay of PWM switch
due to gate resistor and gate-source capacitor CISS of
PWM switch. At different AC input voltage, this delay
produces different maximum output power under the
same PWM current limit level. Higher input voltage
generates higher maximum output power since applied
voltage on primary winding is higher and causes A
higher rising slope inductor current. It results in a higher
peak inductor current at the same delay. Furthermore,
under the same output wattage, the peak switching
current at high line is lower than that at low line.
Therefore, to make the maximum output power close at
different input voltages, the controller needs to regulate
VLIMIT voltage of the CSPWM pin to control the PWM
switch current.
600
500
400
300
0
100
200
300
400
500
600
IDET(µA)
Figure 42. IDET vs. VLIMIT Characteristic Curve
Leading-Edge Blanking (LEB)
When the PFC or PWM switches are turned on, a
voltage spike is induced on the current-sense resistor
due to the reciprocal effect by reverse-recovery energy
of the output diode and COSS of power MOSFET. To
prevent this spike, a leading-edge blanking time is builtin to FAN6921AMR and a small RC filter is
recommended between the CSPWM pin and GND (e.g.
100 Ω, 470 pF).
FAN6921 — Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode PWM Controller
Auxiliary
Winding
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20
VDD Pin Over-Voltage Protection (OVP)
VDD over-voltage protection is used to prevent device
damage once VDD voltage is higher than device stress
rating voltage. In case of VDD OVP, the controller stops
all switching operation immediately and enters Latch-Off
Mode until the AC plug is disconnected.
Adjustable Over-Temperature Protection and
Externally Latch Triggering (RT Pin)
Figure 43 is a typical application circuit with an internal
block of RT pin. As shown, a constant current IRT flows
out from the RT pin, so the voltage VRT on RT pin can
be obtained as IRT current multiplied by the resistor,
which consists of NTC resistor and RA resistor. If the
RT pin voltage is lower than 0.8 V and lasts for a
debounce time, Latch Mode is activated and stops all
PFC and PWM switching.
The RT pin is usually used to achieve over-temperature
protection with a NTC resistor and provide external latch
triggering for additional protection. Engineers can use
an external triggering circuit (e.g. transistor) to pull the
RT pin LOW and activate controller Latch Mode.
Generally, the external latch triggering needs to activate
rapidly since it is usually used to protect power system
from abnormal conditions. Therefore, the protection
debounce time of the RT pin is set to around 110 µs
once RT pin voltage is lower than 0.5 V.
For over-temperature protection, because the
temperature does not change immediately; the RT pin
voltage is reduced slowly as well. The debounce time
for adjustable OTP does not need a fast reaction. To
prevent improper latch triggering on the RT pin due to
exacting test condition (e.g. lightning test); when the RT
pin triggering voltage is higher than 0.5 V, the protection
debounce time is set to around 10 ms. To avoid
improper triggering on the RT pin, add a small value
capacitor (e.g. 1000 pF) paralleled with NTC and RA
resistor.
FAN6921A
Adjustable Over-Temperature
Protection & External Latch
Triggering
IRT=100µA
12
NTC
RRT
RT
0.8V
0.5V
Debounce
Time
Output Over-Voltage Protection (DET Pin)
Referring to Figure 44, during the discharge time of
PWM transformer inductor; the voltage across on
auxiliary winding is reflected from secondary winding
and, therefore, the flat voltage on the DET pin is
proportional to the output voltage. FAN6921AMR can
sample this flat voltage level after a tOFF blanking time to
perform output over-voltage protection. This tOFF
blanking time is used to ignore the voltage ringing from
leakage inductance of PWM transformer. The sampling
flat voltage level is compared with internal threshold
voltage 2.5 V and, once the protection is activated,
FAN6921AMR enters Latch Mode.
The controller can protect rapidly through this kind of
cycle-by-cycle sampling method in the case of output
over voltage. The protection voltage level can be
determined by the ratio of external resistor divider RA
and RDET. The flat voltage on DET pin can be
expressed by the following equation:
VDET   N A N S   VO 
(2)
RA
RDET  RA
PWM
Gate
VO 
VAUX
t
NA
NS
t
PFC _ VO 
VDET
VO 
NA
NP
NA
RA

N S RDET  R A
Sampling
here
toff
Blanking
Latched
FAN6921 — Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode PWM Controller
Protection for PWM Stage
110µs
10ms
0.3V
Figure 43. Adjustable Over-Temperature Protection
t
Figure 44. Operation Waveform of Output
Over-Voltage Detection
© 2009 Fairchild Semiconductor Corporation
FAN6921A • Rev. 1.0.2
www.fairchildsemi.com
21
VO
FB
Open-Loop
Short-Circuit / Overload
As the output loading is increased, the output voltage is
decreased and the sink current of transistor of optocoupler on primary side is reduced so the FB pin voltage
is increased by internal voltage bias. In the case of an
open-loop, output short-circuit, or overload condition;
this sink current is further reduced and the FB pin
voltage is pulled to high level by internal bias voltage.
When the FB pin voltage is higher than 4.2 V for 50 ms,
the FB pin protection is activated.
Under-Voltage Lockout (UVLO, VDD Pin)
Referring to Figure 36 and Figure 37, the turn-on and
turn-off VDD threshold voltages of FAN6921AMR are
fixed at 18 V and 10 V, respectively. During startup, the
hold-up capacitor (VDD cap.) is charged by the HV
startup current until VDD voltage reaches the turn-on
voltage. Before the output voltage rises to rated voltage
and delivers energy to the VDD capacitor from auxiliary
winding, this hold-up capacitor has to sustain the VDD
voltage energy for operation. When VDD voltage reaches
turn-on voltage, FAN6921AMR starts all switching
operation if no protection is triggered before VDD voltage
drops to turn-off voltage VDD-PWM-OFF.
Figure 45. FB Pin Open-Loop, Short Circuit, and
Overload Protection
© 2009 Fairchild Semiconductor Corporation
FAN6921A • Rev. 1.0.2
FAN6921 — Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode PWM Controller
Open-Loop, Short-Circuit, and Overload Protection
(FB Pin)
Referring to Figure 45, outside of FAN6921AMR, the FB
pin is connected to the collector of transistor of an optocoupler. Inside of FAN6921AMR, the FB pin is
connected to an internal voltage bias through a resistor
of around 5 k.
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22
FAN6921AMR — Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode PWM Controller
Physical Dimensions
Figure 46. 16-Pin Small Outline Package (SOP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/,
© 2010 Fairchild Semiconductor Corporation
FAN6921AMR • Rev. 1.0.2
www.fairchildsemi.com
23
FAN6921AMR — Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode PWM Controller
© 2010 Fairchild Semiconductor Corporation
FAN6921AMR • Rev. 1.0.2
www.fairchildsemi.com
24