PRELIMINARY PRELIMINARY K6R1004C1D CMOS SRAM Document Title 256Kx4 Bit (with OE) High-Speed CMOS Static RAM(5.0V Operating). Revision History Rev. No. History Rev. 0.0 Rev. 0.1 Rev. 0.2 Initial release with Preliminary. Current modify 1. Delete 15ns speed bin. 2. Change Icc for Industrial mode. Item 10ns ICC(Industrial) 12ns Draft Data Previous 85mA 75mA Remark June. 8. 2001 September. 9. 2001 December. 18. 2001 Preliminary Preliminary Preliminary Current 75mA 65mA Rev. 1.0 1. Final datasheet release. 2. Delete UB,LB releated AC characteristics and timing diagram. June. 19. 2002 Final Rev. 2.0 1. Delete 12ns speed bin. July. 8. 2002 Final Rev. 3.0 1. Add the Lead Free Package type. July. 26, 2004 Final The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters. -1- Rev. 3.0 July 2004 PRELIMINARY PRELIMINARY K6R1004C1D CMOS SRAM 1Mb Async. Fast SRAM Ordering Information Org. 256K x4 Part Number K6R1004C1D-J(K)C(I) 10 VDD(V) Speed ( ns ) 5 10 K6R1004V1D-J(K)C(I) 08/10 3.3 8/10 K6R1008C1D-J(K,T,U)C(I) 10 5 10 K6R1008V1D-J(K,T,U)C(I) 08/10 3.3 8/10 K6R1016C1D-J(K,T,U,E)C(I) 10 5 10 3.3 8/10 128K x8 64K x16 K6R1016V1D-J(K,T,U,E)C(I) 08/10 -2- PKG Temp. & Power J : 32-SOJ K: 32-SOJ(LF) J : 32-SOJ K : 32-SOJ(LF) T : 32-TSOP2 U : 32-TSOP2(LF) C : Commercial Temperature ,Normal Power Range I : Industrial Temperature ,Normal Power Range J : 44-SOJ K : 44-SOJ(LF) T : 44-TSOP2 U : 44-TSOP2(LF) E : 48-TBGA Rev. 3.0 July 2004 PRELIMINARY PRELIMINARY K6R1004C1D CMOS SRAM 256K x 4 Bit (with OE) High-Speed CMOS Static RAM FEATURES GENERAL DESCRIPTION • Fast Access Time 10ns(Max.) • Power Dissipation Standby (TTL) : 20mA(Max.) (CMOS) : 5mA(Max.) Operating K6R1004C1D-10: 65mA(Max.) • Single 5.0V±10% Power Supply • TTL Compatible Inputs and Outputs • I/O Compatible with 3.3V Device • Fully Static Operation - No Clock or Refresh required • Three State Outputs • Center Power/Ground Pin Configuration • Standard Pin Configuration : K6R1004C1C-J : 32-SOJ-400 K6R1004C1C-K : 32-SOJ-400(Lead-Free) • Operating in Commercial and Industrial Temperature range. The K6R1004C1D is a 1,048,576-bit high-speed Static Random Access Memory organized as 262,144 words by 4 bits. The K6R1004C1D uses 4 common input and output lines and has an output enable pin which operates faster than address access time at read cycle. The device is fabricated using SAMSUNG′s advanced CMOS process and designed for highspeed circuit technology. It is particularly well suited for use in high-density high-speed system applications. The K6R1004C1D is packaged in a 400 mil 32-pin plastic SOJ. PIN CONFIGURATION(Top View) FUNCTIONAL BLOCK DIAGRAM A0 A1 A2 A3 A4 A5 A6 A7 A8 I/O1 ~ I/O4 Row Select Clk Gen. Data Cont. Pre-Charge Circuit Memory Array 512 Rows 512x4 Columns I/O Circuit & Column Select N.C 1 32 A17 A0 2 31 A16 A1 3 30 A15 A2 4 29 A14 A3 5 28 A13 CS 6 27 I/O1 7 26 I/O4 Vcc 8 Vss 9 25 Vss SOJ 24 Vcc I/O2 10 23 I/O3 WE 11 22 A12 A4 12 21 A5 13 20 A10 A6 14 19 A9 A7 15 18 A8 A11 17 N.C N.C 16 CLK Gen. OE PIN FUNCTION A9 A10 A11 A12 A13 A14 A15 A16 A17 Pin Name A0 - A17 CS WE OE Address Inputs WE Write Enable CS Chip Select OE Output Enable I/O1 ~ I/O4 VCC -3- Pin Function Data Inputs/Outputs Power(+5.0V) VSS Ground N.C No Connection Rev. 3.0 July 2004 PRELIMINARY PRELIMINARY K6R1004C1D CMOS SRAM ABSOLUTE MAXIMUM RATINGS* Parameter Voltage on Any Pin Relative to VSS Symbol Rating Unit VIN, VOUT -0.5 to Vcc+0.5V V VCC -0.5 to 7.0 V Pd 1 W Voltage on VCC Supply Relative to VSS Power Dissipation TSTG -65 to 150 °C Commercial TA 0 to 70 °C Industrial TA -40 to 85 °C Storage Temperature Operating Temperature * Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED DC OPERATING CONDITIONS(TA=0 to 70°C) Parameter Symbol Min Typ Max Unit Supply Voltage VCC 4.5 5.0 5.5 V Ground VSS 0 0 0 V Input High Voltage VIH 2.2 - VCC+0.5** V Input Low Voltage VIL -0.5* - 0.8 V * VIL(Min) = -2.0V a.c (Pulse Width ≤ 8ns) for I ≤ 20mA. ** VIH(Max) = VCC + 2.0V a.c (Pulse Width ≤ 8ns) for I ≤ 20mA. DC AND OPERATING CHARACTERISTICS*(TA=0 to 70°C, Vcc=5.0V±10%, unless otherwise specified) Min Max Unit Input Leakage Current ILI VIN=VSS to VCC -2 2 µA Output Leakage Current ILO CS=VIH or OE=VIH or WE=VIL VOUT=VSS to VCC -2 2 µA Operating Current ICC Min. Cycle, 100% Duty mA Parameter Symbol Test Conditions Com. 10ns - 65 Ind. 10ns - 75 ISB Min. Cycle, CS=VIH - 20 ISB1 f=0MHz, CS≥VCC-0.2V, VIN≥VCC-0.2V or VIN≤0.2V - 5 Output Low Voltage Level VOL IOL=8mA - 0.4 V Output High Voltage Level VOH IOH=-4mA 2.4 - V Standby Current mA * The above parameters are also guaranteed at industrial temperature range. CAPACITANCE*(TA=25°C, f=1.0MHz) Item Symbol Test Conditions TYP Max Unit Input/Output Capacitance CI/O VI/O=0V - 8 pF Input Capacitance CIN VIN=0V - 6 pF * Capacitance is sampled and not 100% tested. -4- Rev. 3.0 July 2004 PRELIMINARY PRELIMINARY K6R1004C1D CMOS SRAM AC CHARACTERISTICS(TA=0 to 70°C, VCC=5.0V±10%, unless otherwise noted.) TEST CONDITIONS Parameter Value Input Pulse Levels 0V to 3V Input Rise and Fall Times 3ns Input and Output timing Reference Levels 1.5V Output Loads See below Output Loads(B) for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ Output Loads(A) +5.0V RL = 50Ω DOUT VL = 1.5V 480Ω DOUT 30pF* ZO = 50Ω 255Ω 5pF* * Including Scope and Jig Capacitance * Capacitive Load consists of all components of the test environment. READ CYCLE* Parameter Symbol K6R1004C1D-10 Min Max Unit Read Cycle Time tRC 10 - ns Address Access Time tAA - 10 ns Chip Select to Output tCO - 10 ns Output Enable to Valid Output tOE - 5 ns Chip Enable to Low-Z Output tLZ 3 - ns tOLZ 0 - ns Chip Disable to High-Z Output tHZ 0 5 ns Output Disable to High-Z Output tOHZ 0 5 ns Output Hold from Address Change tOH 3 - ns Chip Selection to Power Up Time tPU 0 - ns Chip Selection to Power DownTime tPD - 10 ns Output Enable to Low-Z Output * The above parameters are also guaranteed at industrial temperature range. -5- Rev. 3.0 July 2004 PRELIMINARY PRELIMINARY K6R1004C1D CMOS SRAM WRITE CYCLE* Parameter K6R1004C1D-10 Symbol Min Max Unit Write Cycle Time tWC 10 - ns Chip Select to End of Write tCW 7 - ns Address Set-up Time tAS 0 - ns Address Valid to End of Write tAW 7 - ns Write Pulse Width(OE High) tWP 7 - ns Write Pulse Width(OE Low) tWP1 10 - ns Write Recovery Time tWR 0 - ns Write to Output High-Z tWHZ 0 5 ns Data to Write Time Overlap tDW 5 - ns Data Hold from Write Time tDH 0 - ns End of Write to Output Low-Z tOW 3 - ns * The above parameters are also guaranteed at industrial temperature range. TIMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH) tRC Address tAA tOH Data Out Valid Data Previous Valid Data TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH) tRC Address tAA tCO CS tHZ(3,4,5) tOHZ tOE OE tOLZ Data out High-Z VCC ICC Current ISB tDH tLZ(4,5) Valid Data tPU tPD 50% 50% -6- Rev. 3.0 July 2004 PRELIMINARY PRELIMINARY K6R1004C1D CMOS SRAM NOTES(READ CYCLE) 1. WE is high for read cycle. 2. All read cycle timing is referenced from the last valid address to the first transition address. 3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or VOL levels. 4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device. 5. Transition is measured ±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested. 6. Device is continuously selected with CS=VIL. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. TIMING WAVEFORM OF WRITE CYCLE(1) (OE= Clock) tWC Address tWR(5) tAW OE tCW(3) CS tWP(2) tAS(4) WE tDW Data in High-Z tDH Valid Data tOHZ(6) High-Z(8) Data out TIMING WAVEFORM OF WRITE CYCLE(2) (OE=Low Fixed) tWC Address tWR(5) tAW tCW(3) CS tAS(4) tWP1(2) WE tDW Data in High-Z tDH Valid Data tWHZ(6) tOW High-Z(8) Data out -7- (10) (9) Rev. 3.0 July 2004 PRELIMINARY PRELIMINARY K6R1004C1D CMOS SRAM TIMING WAVEFORM OF WRITE CYCLE(3) (CS=Controlled) tWC Address tAW tWR(5) tCW(3) CS tWP(2) tAS(4) WE tDW High-Z Data in Valid Data tLZ High-Z tWHZ(6) High-Z(8) High-Z Data out tDH NOTES(WRITE CYCLE) 1. All write cycle timing is referenced from the last valid address to the first transition address. 2. A write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low ; A write ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write to the end of write. 3. tCW is measured from the later of CS going low to end of write. 4. tAS is measured from the address valid to the beginning of write. 5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high. 6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state. 9. Dout is the read data of the new address. 10.When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied. FUNCTIONAL DESCRIPTION CS WE OE Mode I/O Pin Supply Current H X L H X* Not Select High-Z ISB, ISB1 H Output Disable High-Z ICC L L H L Read DOUT ICC L X Write DIN ICC * X means Don′t Care. -8- Rev. 3.0 July 2004 PRELIMINARY PRELIMINARY K6R1004C1D CMOS SRAM Units:millimeters/Inches PACKAGE DIMENSIONS 32-SOJ-400 #32 10.16 0.400 #17 11.18 ±0.12 0.440 ±0.005 9.40 ±0.25 0.370 ±0.010 0.20 #1 0.69 MIN 0.027 21.36 MAX 0.841 20.95 ±0.12 0.825 ±0.005 ( 1.30 ) 0.051 ( 1.30 ) 0.051 ( 0.95 ) 0.0375 +0.10 -0.05 +0.004 0.017 -0.002 0.43 1.27 0.050 +0.10 -0.05 0.008 +0.004 -0.002 #16 3.76 MAX 0.148 0.10 MAX 0.004 +0.10 -0.05 +0.004 0.028 -0.002 0.71 -9- Rev. 3.0 July 2004