Intersil CDP1852/3 High-reliability byte-wide input/output port Datasheet

CDP1852/3,
CDP1852C/3
TM
High-Reliability Byte-Wide Input/Output Port
March 1997
Features
Description
• Static Silicon-Gate CMOS Circuitry
The CDP1852/3 and CDP1852C/3 are parallel, 8-bit, modeprogrammable input/output ports. They are compatible and
will interface directly with CDP1800-Series microprocessors.
They are also useful as 8-bit address latches when used
with the CDP1800 multiplexed address bus and as I/O ports
in general-purpose applications.
• Parallel 8-Bit Data Register and Buffer
• Handshaking Via Service Request Flip-Flop
• Low Quiescent and Operating Power
• Interfaces Directly with CDP1800-Series Microprocessors
• Single Voltage Supply
• Full Military Temperature Range
(-55oC to +125oC)
Ordering Information
PACKAGE
SBDIP
TEMP.
RANGE
o
5V
10V
o
PKG.
NO
-55 C to +125 C CDP1852CD3 CDP1852D3 D24.6
Pinout
CDP1852/3, CDP1852C/3 (SBDIP)
TOP VIEW
CSI/CSI 1
MODE 2
24 VDD
23 SR/SR
DI0 3
22 DI7
DO0 4
21 DO7
DI1 5
20 DI6
DO1 6
19 DO6
DI2 7
18 DI5
DO2 8
17 DO5
DI3 9
16 DI4
DO3 10
15 DO4
CLOCK 11
VSS 12
14 CLEAR
13 CS2
The mode control is used to program the device as an input
port (mode = 0) or as an output port (mode = 1). The SR/SR
output can be used as a signal to indicate when data is
ready to be transferred. In the input mode, a peripheral
device can strobe data into the CDP1852/3, and microprocessor can read that data by device selection. In the output
mode, a microprocessor strobes data into the CDP1852/3,
and handshaking is established with a peripheral device
when the CDP1852/3 is deselected.
In the input mode, data at the data-in terminals (DI0-DI7) is
strobed into the port’s 8-bit register by a high (1) level on the
clock line. The negative high-to-low transition of the clock
latches the data in the register and sets the service request
output low (SR/SR = 0). When CS1/CS1 and CS2 are high
(CS1/CS1 and CS2 = 1), the three-state output drivers are
enabled and data in the 8-bit register appear at the data-out
terminals (DO0-DO7). When either CS1/CS1 or CS2 goes low
(CS1/CS1 or CS2 = 0), the data-out terminals are tristated
and the service request output returns high (SR/SR =1).
In the output mode, the output drivers are enabled at all
times. Data at the data-in terminals (DI0-DI7) is strobed into
the 8-bit register when CS1/CS1 is low (CS1/CS1 = 0) and
CS2 and the clock are high (1), and are present at the dataout terminals (DO0-DO7). The negative high-to-low transition of the clock latches the data in the register. The SR/SR
output goes high (SR/SR = 1) when the device is deselected
(CS1/CS1 = 1 or CS2 = 0) and returns low (SR/SR = 0) on the
following trailing edge of the clock.
A CLEAR control is provided for resetting the port’s register
(DO0-DO7 = 0) and service request flip-flop (input
mode: SR/SR = 1 and output mode: SR/SR = 0).
The CDP1852/3 is functionally identical to the CDP1852C/3.
The CDP1852/3 has a recommended operating voltage
range of 4V to 10.5V, and the CDP1852C/3 has a recommended operating voltage range of 4V to 6.5V.
The CDP1852/3 and CDP1852C/3 are supplied in 24-lead,
dual-in-line side-brazed ceramic packages (D suffix).
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
1
File Number
1694.2
CDP1852/3, CDP1852C/3
Block Diagram of CDP1852/3
CSI/CSI†
CS2
1
13
DEVICE
SELECT
DECODE
CONTROL
LOGIC
23
24
12
MODE 2
CLOCK 11
CLEAR 14
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
3
5
7
9
16
18
20
22
SR/SR†
RESET
CLOCK
ENABLE
THREESTATE
OUTPUT
DRIVERS
8-BIT
DATA
REGISTER
VDD
VSS
4
6
8
10
15
17
19
21
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
† POLARITY DEPENDS ON MODE
MODE = 1
MODE = 0
P1
CSI
CSI
P23
SR
SR
FIGURE 1.
CS2
13
CSI/CSI
SR/SR
1
23
S
MODE
2
D
VSS
CLEAR
Q
R
CL
SERVICE
REQUEST
LATCH
14
CLOCK
11
VDD
DI0
3
P
TG
N
P
DO0
4
N
P
TG
N
VSS
DI1
DO1
5
6
D17
DO7
22
21
FIGURE 2. CDP1852/3 LOGIC DIAGRAM
2
CDP1852/3, CDP1852C/3
:
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage Range, (VDD):
(All Voltages Referenced to VSS Terminal)
CDP1852/3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to +11V
CDP1852C/3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V
Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V
DC Input Current, any One Input . . . . . . . . . . . . . . . . . . . . . . . . . ±10mA
Thermal Resistance (Typical)
θJA (oC/W) θJC (oC/W)
SBDIP Package. . . . . . . . . . . . . . . . . .
65
20
Device Dissipation Per Output Transistor
TA = Full Package Temperature Range
(All Package Types). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mW
Operating Temperature Range (TA)
Package Type D . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
Storage Temperature Range (TSTG) . . . . . . . . . . . . -65oC to +150oC
Lead Temperature (During Soldering):
At distance 1/16 ± 1/32 in (1.59 ± 0.79mm)
From Case for 10s max . . . . . . . . . . . . . . . . . . . . . . . . . . . +265oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Recommended Operating Conditions
TA = Full-Package Temperature Range. For maximum reliability, operating conditions
should be selected so that operation is always within the following ranges.
LIMITS
CPP1852/3
PARAMETER
MIN
MAX
MIN
MAX
UNITS
4
10.5
4
6.5
V
VSS
VDD
VSS
VDD
V
DC Operating Voltage Range
Input Voltage Range
Static Electrical Specifications
CDP1852C/3
VIN = 0 or VDD, Except as Noted
LIMITS
o
o
+125oC
-55 C, +25 C
PARAMETER
SYMBOL
Quiescent Device Current (Note 1)
IDD
Output Low Drive (Sink) Current
Output High Drive (Source) Current
Output Voltage Low Level
Output Voltage High Level
Input Low Voltage
Input High Voltage
Input Leakage Low
Input Leakage High
IOL
IOH
VOL
VOH
VIL
VIH
IIL
IIH
MIN
MAX
MIN
MAX
UNITS
VDD = 5V
-
10
-
100
µA
VDD = 10V
-
20
-
300
µA
VDD = 5V, VO = 0.4V
2.6
-
1.9
-
mA
VDD = 10V, VO = 0.5V
6.1
-
4.1
-
mA
VDD = 5V, VO = 4.6V
-1.8
-
-1.3
-
mA
VDD = 10V, VO = 9.5V
-4.4
-
-2.9
-
mA
VDD = 5V, IOL = 0µA
-
0.1
-
0.2
V
VDD = 10V, IOL = 0µA
-
0.1
-
0.2
V
VDD = 5V, IOL = 0µA
4.9
-
4.8
-
V
VDD = 10V, IOL = 0µA
9.9
-
9.8
-
V
VDD = 5V, VO = 0.2, 4.8V
-
1.5
-
1.5
V
VDD = 10V, VO = 0.2, 9.8V
-
3
-
3
V
VDD = 5V, VO = 0.2, 4.8V
3.5
-
3.5
-
V
VDD = 10V, VO = 0.2, 9.8V
7
-
7
-
V
VDD = 5V, VIN = 0V
-
-1
-
-5
µA
VDD = 10V, VIN = 0V
-
-1
-
-5
µA
VDD = 5V, VIN = 5V
-
1
-
5
µA
VDD = 10V, VIN = 10V
-
1
-
5
µA
TEST CONDITIONS
3
CDP1852/3, CDP1852C/3
Static Electrical Specifications
VIN = 0 or VDD, Except as Noted (Continued)
LIMITS
-55oC,
PARAMETER
Three-State Output Leakage Low
Three-State Output Leakage High
Input Capacitance
Output Capacitance
SYMBOL
+125oC
MIN
MAX
MIN
MAX
UNITS
VDD = 5V, VO = 0V
-
-1
-
-5
µA
VDD = 10V, VO = 0V
-
-1
-
-5
µA
VDD = 5V, VO = 5V
-
1
-
5
µA
VDD = 10V, VO = 10V
-
1
-
5
µA
CIN
Note 2
-
10
-
10
pF
COUT
Note 2
-
15
-
15
pF
IOZL
IOZH
TEST CONDITIONS
+25oC
NOTES:
1. The CDP1852C/3 meets all 5V static electrical specifications of the CDP1852/3 except +125oC quiescent device current for which the
limit is IDD = 300µA.
2. Input and output capacitance are guaranteed but not tested.
Static Burn-In Circuit
VDD
VDD
VSS
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
ALL RESISTORS 47kΩ (±20%)
Dynamic Electrical Specifications
TYPE NO.
VDD
TEMPERATURE
TIME
CDP1852/3
11V
+125oC
160 Hrs. Min.
CDP1852C/3
7V
+125oC
160 Hrs. Min.
VSS
Mode = 0 Input Port, See Figure 3, Input tr, tf ≤ 15ns; CL = 50pF
LIMITS (NOTE 1)
-55oC,
PARAMETER
Select Duration
Clock Pulse Width
Clear Pulse Width
Data-In to Clock Fall Setup Time
+25oC
+125oC
SYMBOL
VDD
VOLTS
(NOTE 1)
MIN
MAX
(NOTE 1)
MIN
MAX
UNITS
tSW
5
250
-
360
-
ns
10
150
-
180
-
ns
tWW
tCLR
tDS
5
150
-
200
-
ns
10
90
-
110
-
ns
5
110
-
160
-
ns
10
50
-
80
-
ns
5
-10
-
-10
-
ns
10
-5
-
-5
-
ns
4
CDP1852/3, CDP1852C/3
Dynamic Electrical Specifications
Mode = 0 Input Port, See Figure 3, Input tr, tf ≤ 15ns; CL = 50pF (Continued)
LIMITS (NOTE 1)
-55oC,
PARAMETER
+25oC
+125oC
SYMBOL
VDD
VOLTS
(NOTE 1)
MIN
MAX
(NOTE 1)
MIN
MAX
UNITS
tDH
5
150
-
170
-
ns
10
70
-
100
-
ns
5
-
200
-
340
ns
10
-
110
-
170
ns
Data-In After Clock Fall Hold Time
Propagation Delay Times:
Clear to SR
tRSR
Clock to SR
tCSR
Deselect to SR
5
-
175
-
220
ns
10
-
110
-
130
ns
5
-
175
-
240
ns
10
-
110
-
120
ns
tSSR
NOTE:
1. Time required by a device to allow for the indicated function.
(NOTE 1)
CS1 • CS2
tSW
tWW
CLOCK
tDH
DATA IN
tDS
HIGH
IMPEDANCE
DATA BUS
tSSR
SR
tRSR
tCSR
tCLR
CLEAR
NOTE:
1. CS1 • CS2 is the overlap of CS1 = 1 and CS2 = 1.
MODE = 0 TRUTH TABLE
CLOCK
CS1 • CS2 (Note 1)
CLEAR
X
0
X
High Impedance
0
1
0
0
0
1
1
Data Latch
1
1
X
Data In
SERVICE REQUEST
TRUTH TABLE
DATA OUT EQUALS
Clock =
CS1 or CS2 =
or CLEAR = 0
SR = 0
SR = 1
NOTE:
1. CS1 • CS2 = CS1 = 1, CS2 = 1.
FIGURE 3. MODE = 0 INPUT PORT TIMING WAVEFORMS AND TRUTH TABLES
5
CDP1852/3, CDP1852C/3
Dynamic Electrical Specification
Mode = 1 Output Port, See Figure 4, Input tr, tf ≤ 15ns; CL = 50pF
LIMITS (NOTE 1)
-55oC, +25oC
PARAMETER
Clock Pulse Width
Write Width Duration
Clear Pulse Width
Data-In to Clock Fall Setup Time
Data Hold from Write Termination
Select-After Clock-Fall Hold Time
Propagation Delay Times:
Clear to Data
Write to Data Out
Data In to Data Out
Clear to SR
Clock to SR
Deselect to SR
+125oC
SYMBOL
VDD
VOLTS
(NOTE 1)
MIN
MAX
(NOTE 1)
MIN
MAX
UNITS
tCLK
5
170
-
260
-
ns
10
90
-
130
-
ns
5
200
-
260
-
ns
10
110
-
130
-
ns
5
110
-
135
-
ns
10
60
-
75
-
ns
5
-10
-
-10
-
ns
10
-5
-
-5
-
ns
5
130
-
170
-
ns
10
70
-
90
-
ns
5
0
-
0
-
ns
10
0
-
0
-
ns
5
-
215
-
290
ns
10
-
140
-
190
ns
5
-
250
-
350
ns
10
-
130
-
190
ns
5
-
150
-
200
ns
10
-
80
-
100
ns
5
-
175
-
240
ns
10
-
120
-
160
ns
5
-
170
-
240
ns
10
-
90
-
120
ns
5
-
170
-
240
ns
10
-
90
-
120
ns
tWW
tCLR
tDS
tDH
tSH
tRDO
tWDO
tDDO
tRSR
tCSR
tSSR
NOTE:
1. Time required by a device to allow for the indicated function.
6
CDP1852/3, CDP1852C/3
(NOTE 2)
tWW
(NOTE 1)
CS1 • CS2
tSH
tDH
tDS
CLOCK
tCLK
DATA IN
tDDO
DATA OUT
tRDO
SR
tRSR
tWDO
CLEAR
tSSR
tCSR
tCLR
NOTES:
1. CS1 • CS2 is the overlap of the CS1 = 0 and CS2 = 1.
2. Write is the overlap of CS1 • CS2 and clock.
MODE = 1 TRUTH TABLE
SERVICE REQUEST
TRUTH TABLE
CLOCK
CS1 • CS2 (NOTE 1)
CLEAR
0
X
0
0
CS1
Clock • (CS1 • CS2)
0
X
1
Data Latch
or
or
CLEAR = 0
SR = 0
DATA OUT EQUALS
X
0
1
Data Latch
CS2
1
1
X
Data In
SR = 1
NOTE:
1. CS1 • CS2 = CS1 = 0, CS2 = 1
FIGURE 4. MODE = 1 OUTPUT PORT TIMING WAVEFORMS AND TRUTH TABLES
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