2.5 V to 5.5 V, 230 μA, Dual Rail-to-Rail Voltage Output 8-/10-/12-Bit DACs AD5303/AD5313/AD5323 FEATURES GENERAL DESCRIPTION AD5303: 2 buffered 8-bit DACs in 1 package A version: ±1 LSB INL, B version: ±0.5 LSB INL AD5313: 2 buffered 10-bit DACs in 1 package A version: ±4 LSB INL, B version: ±2 LSB INL AD5323: 2 buffered 12-bit DACs in 1 package A version: ±16 LSB INL, B version: ±8 LSB INL 16-lead TSSOP package Micropower operation: 300 μA @ 5 V (including reference current) Power-down to 200 nA @ 5 V, 50 nA @ 3 V 2.5 V to 5.5 V power supply Double-buffered input logic Guaranteed monotonic by design over all codes Buffered/unbuffered reference input options Output range: 0 V to VREF or 0 V to 2 VREF Power-on-reset to 0 V SDO daisy-chaining option Simultaneous update of DAC outputs via LDAC pin Asynchronous CLR facility Low power serial interface with Schmitt-triggered inputs On-chip rail-to-rail output buffer amplifiers The AD5303/AD5313/AD5323 are dual 8-/10-/12-bit buffered voltage output DACs in a 16-lead TSSOP package that operate from a single 2.5 V to 5.5 V supply, consuming 230 μA at 3 V. Their on-chip output amplifiers allow the outputs to swing rail-torail with a slew rate of 0.7 V/μs. The AD5303/AD5313/AD5323 utilize a versatile 3-wire serial interface that operates at clock rates up to 30 MHz and is compatible with standard SPI, QSPI™, MICROWIRE™, and DSP interface standards. The references for the two DACs are derived from two reference pins (one per DAC). These reference inputs may be configured as buffered or unbuffered inputs. The parts incorporate a poweron reset circuit, which ensures that the DAC outputs power up to 0 V and remain there until a valid write to the device takes place. There is also an asynchronous active low CLR pin that clears both DACs to 0 V. The outputs of both DACs may be updated simultaneously using the asynchronous LDAC input. The parts contain a power-down feature that reduces the current consumption of the devices to 200 nA at 5 V (50 nA at 3 V) and provides software-selectable output loads while in power-down mode. The parts may also be used in daisychaining applications using the SDO pin. APPLICATIONS The low power consumption of these parts in normal operation makes them ideally suited to portable battery-operated equipment. The power consumption is 1.5 mW at 5 V and 0.7 mW at 3 V, reducing to 1 μW in power-down mode. Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources Programmable attenuators FUNCTIONAL BLOCK DIAGRAM VDD BUF A VREF A AD5303/AD5313/AD5323 POWER-ON RESET INPUT REGISTER DAC REGISTER STRING DAC VOUTA BUFFER SYNC INTERFACE LOGIC SCLK POWER-DOWN LOGIC RESISTOR NETWORK DIN INPUT REGISTER DAC REGISTER STRING DAC VOUTB BUFFER SDO DCEN LDAC CLR PD BUF B VREF B GND RESISTOR NETWORK 00472-001 GAIN-SELECT LOGIC Figure 1. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©1999–2007 Analog Devices, Inc. All rights reserved. AD5303/AD5313/AD5323 TABLE OF CONTENTS Features .............................................................................................. 1 Input Shift Register .................................................................... 17 Applications....................................................................................... 1 Low Power Serial Interface ....................................................... 17 General Description ......................................................................... 1 Double-Buffered Interface ........................................................ 17 Functional Block Diagram .............................................................. 1 Power-Down Modes ...................................................................... 19 Revision History ............................................................................... 2 Microprocesser Interfacing ........................................................... 20 Specifications..................................................................................... 3 AD5303/AD5313/AD5323 to ADSP-2101 Interface............. 20 AC Characteristics........................................................................ 6 AD5303/AD5313/AD5323 to 68HC11/68L11 Interface ...... 20 Timing Characteristics ................................................................ 6 AD5303/AD5313/AD5323 to 80C51/80L51 Interface.......... 20 Absolute Maximum Ratings............................................................ 8 AD5303/AD5313/AD5323 to MICROWIRE Interface ........ 20 ESD Caution.................................................................................. 8 Applications Information .............................................................. 21 Pin Configuration and Function Descriptions............................. 9 Typical Application Circuit....................................................... 21 Terminology .................................................................................... 10 Bipolar Operation Using the AD5303/AD5313/AD5323..... 21 Typical Performance Characteristics ........................................... 11 Opto-Isolated Interface for Process Control Applications ... 22 Functional Description .................................................................. 15 Decoding Multiple AD5303/AD5313/AD5323s.................... 22 Digital-to-Analog ....................................................................... 15 AD5303/AD5313/AD5323 as a Digitally Programmable Window Detector ....................................................................... 22 Resistor String ............................................................................. 15 DAC Reference Inputs ............................................................... 15 Output Amplifier........................................................................ 15 Power-On Reset .............................................................................. 16 Clear Function (CLR) ................................................................ 16 Serial Interface ................................................................................ 17 Coarse and Fine Adjustment Using the AD5303/AD5313/AD5323 ....................................................... 23 Daisy-Chain Mode ..................................................................... 23 Power Supply Bypassing and Grounding................................ 24 Outline Dimensions ....................................................................... 25 Ordering Guide .......................................................................... 25 REVISION HISTORY 6/07—Rev. A to Rev. B Updated Format..................................................................Universal Changes to Table 4............................................................................ 8 Changes to the Ordering Guide.................................................... 25 8/03—Rev. 0 to Rev. A Added A Version.................................................................Universal Changes to Features.......................................................................... 1 Changes to Specifications ................................................................ 2 Changes to Absolute Maximum Ratings ....................................... 5 Changes to Ordering Guide ............................................................ 5 Updated Outline Dimensions ....................................................... 18 4/99—Revision 0: Initial Version Rev. B | Page 2 of 28 AD5303/AD5313/AD5323 SPECIFICATIONS VDD = 2.5 V to 5.5 V; VREF = 2 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted. Table 1. A Version 1 2 Parameter DC PERFORMANCE 3 , 4 AD5303 Resolution Relative Accuracy Differential Nonlinearity Max 8 ±0.15 ±0.02 ±1 ±0.25 8 ± 0.15 ± 0.02 ±0.5 ±0.25 Bits LSB LSB AD5313 Resolution Relative Accuracy Differential Nonlinearity 10 ±0.5 ±0.05 ±4 ±0.5 10 ± 0.5 ± 0.05 ±2 ±0.5 Bits LSB LSB AD5323 Resolution Relative Accuracy Differential Nonlinearity 12 ±2 ±0.2 ±16 ±1 12 ±2 ±0.2 ±8 ±1 Bits LSB LSB Offset Error ±0.4 ±3 ±0.4 ±3 % of FSR Guaranteed monotonic by design over all codes See Figure 2 and Figure 3 Gain Error ±0.15 ±1 ±0.15 ±1 % of FSR See Figure 2 and Figure 3 Lower Dead Band 10 60 10 60 mV See Figure 2 and Figure 3 Offset Error Drift 5 Gain Error Drift5 −12 −5 Power Supply Rejection Ratio5 −60 −60 dB DC Crosstalk5 30 30 μV VREF Input Impedance Reference Feedthrough Channel-to-Channel Isolation OUTPUT CHARACTERISTICS5 Minimum Output Voltage 6 Maximum Output Voltage6 DC Output Impedance Short-Circuit Current Power-Up Time 1 0 Min Unit Typ DAC REFERENCE INPUTS5 VREF Input Range Min B Version1 Typ Max −12 −5 VDD VDD 1 0 Guaranteed monotonic by design over all codes Guaranteed monotonic by design over all codes ppm of FSR/°C ppm of FSR/°C VDD VDD >10 180 >10 180 V V MΩ kΩ 90 90 kΩ −90 −80 −90 −80 dB dB 0.001 VDD − 0.001 0.001 VDD − 0.001 V min V max 0.5 50 20 2.5 0.5 50 20 2.5 Ω mA mA μs 5 5 μs Rev. B | Page 3 of 28 Conditions/Comments ΔVDD = ±10% Buffered reference mode Unbuffered reference mode Buffered reference mode Unbuffered reference mode 0 V to VREF output range, input impedance = RDAC Unbuffered reference mode 0 V to 2 VREF output range, input impedance = RDAC Frequency = 10 kHz Frequency = 10 kHz This is a measure of the minimum and maximum drive capability of the output amplifier VDD = 5 V VDD = 3 V Coming out of power-down mode; VDD = 5 V Coming out of power-down mode; VDD = 3 V AD5303/AD5313/AD5323 A Version 1 Parameter 2 Min Typ Max Min B Version1 Typ Max Unit Conditions/Comments 5 LOGIC INPUTS Input Current Input Low Voltage, VIL Input High Voltage, VIH VDD IDD (Normal Mode) ±1 μA 0.8 0.6 0.5 0.8 0.6 0.5 V V V V V V pF VDD = 5 V ± 10% VDD = 3 V ± 10% VDD = 2.5 V VDD = 5 V ± 10% VDD = 3 V ± 10% VDD = 2.5 V 0.4 V V ISINK = 2 mA ISOURCE = 2 mA 0.4 V V μA pF ISINK = 2 mA ISOURCE = 2 mA DCEN = GND DCEN = GND 5.5 V IDD specification is valid for all DAC codes Both DACs active and excluding load currents Both DACs in unbuffered mode; VIH = VDD and VIL = GND; in buffered mode, extra current is typically x μA per DAC, where x = 5 μA + VREF/RDAC 2.4 2.1 2.0 Pin Capacitance LOGIC OUTPUT (SDO)5 VDD = 5 V ± 10% Output Low Voltage Output High Voltage VDD = 3 V ± 10% Output Low Voltage Output High Voltage Floating-State Leakage Current Floating-State Output Capacitance POWER REQUIREMENTS ±1 2.4 2.1 2.0 2 3.5 2 0.4 4.0 3.5 4.0 0.4 2.4 2.4 1 1 3 2.5 3 5.5 2.5 VDD = 4.5 V to 5.5 V VDD = 2.5 V to 3.6 V 300 230 450 350 300 230 450 350 μA μA IDD (Full Power-Down) VDD = 4.5 V to 5.5 V VDD = 2.5 V to 3.6 V 0.2 0.05 1 1 0.2 0.05 1 1 μA μA 1 Temperature range for Version A, Version B: −40°C to +105°C. See the Terminology section. DC specifications tested with the outputs unloaded. 4 Linearity is tested using a reduced code range: AD5303 (Code 8 to Code 248); AD5313 (Code 28 to Code 995); AD5323 (Code 115 to Code 3981). 5 Guaranteed by design and characterization, not production tested. 6 In order for the amplifier output to reach its minimum voltage, offset error must be negative. In order for the amplifier output to reach its maximum voltage, VREF = VDD and offset plus gain error must be positive. 2 3 Rev. B | Page 4 of 28 AD5303/AD5313/AD5323 GAIN ERROR PLUS OFFSET ERROR OUTPUT VOLTAGE GAIN ERROR PLUS OFFSET ERROR OUTPUT VOLTAGE IDEAL ACTUAL ACTUAL POSITIVE OFFSET ERROR POSITIVE OFFSET ERROR DAC CODE DAC CODE Figure 3. Transfer Function with Positive Offset DEAD BAND AMPLIFIER FOOTROOM (1mV) 00472-005 NEGATIVE OFFSET ERROR Figure 2. Transfer Function with Negative Offset Rev. B | Page 5 of 28 00472-006 IDEAL AD5303/AD5313/AD5323 AC CHARACTERISTICS 1 VDD = 2.5 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter 2 Output Voltage Settling Time AD5303 AD5313 AD5323 Slew Rate Major-Code Transition Glitch Energy Min Digital Feedthrough Analog Crosstalk DAC-to-DAC Crosstalk Multiplying Bandwidth Total Harmonic Distortion A, B Version 3 Typ Max Unit 6 7 8 0.7 12 μs μs μs V/μs nV-s 8 9 10 0.10 0.01 0.01 200 −70 nV-s nV-s nV-s kHz dB Conditions/Comments VREF = VDD = 5 V ¼ scale to ¾ scale change (0x40 to 0xc0) ¼ scale to ¾ scale change (0x100 to 0x300) ¼ scale to ¾ scale change (0x400 to 0xc00) 1 LSB change around major carry (011 . . . 11 to 100 . . . 00) VREF = 2 V ± 0.1 V p-p, unbuffered mode VREF = 2.5 V ± 0.1 V p-p, frequency = 10 kHz 1 Guaranteed by design and characterization, not production tested. See the Terminology section. 3 Temperature range for Version A and Version B: −40°C to +105°C. 2 TIMING CHARACTERISTICS VDD = 2.5 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter 1, 2, 3 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 4, 5 t134, 5 t145 t155 Limit at TMIN, TMAX (A, B Version) 33 13 13 0 5 4.5 0 100 20 20 20 5 20 0 10 Unit ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns max ns min ns min Conditions/Comments SCLK cycle time SCLK high time SCLK low time SYNC to SCLK rising edge setup time Data setup time Data hold time SCLK falling edge to SYNC rising edge Minimum SYNC high time LDAC pulse width SCLK falling edge to LDAC rising edge CLR pulse width SCLK falling edge to SDO invalid SCLK falling edge to SDO valid SCLK falling edge to SYNC rising edge SYNC rising edge to SCLK rising edge 1 Guaranteed by design and characterization, not production tested. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. 3 See Figure 4 and Figure 5. 4 These are measured with the load circuit of Figure 4. 5 Daisy-chain mode only (see Figure 47). 2 Rev. B | Page 6 of 28 AD5303/AD5313/AD5323 2mA 1.6V CL 50pF 2mA 00472-002 TO OUTPUT PIN IOL IOH Figure 4. Load Circuit for Digital Output (SDO) Timing Specifications t1 SCLK t8 t3 t4 t2 t7 SYNC t6 DIN* t5 DB0 DB15 t9 LDAC t10 LDAC t11 00472-003 CLR *SEE THE INPUT SHIFT REGISTER SECTION. Figure 5. Serial Interface Timing Diagram Rev. B | Page 7 of 28 AD5303/AD5313/AD5323 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted.1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 4. Parameter VDD to GND Digital Input Voltage to GND Digital Output Voltage to GND Reference Input Voltage to GND VOUTA, VOUTB to GND Operating Temperature Range Industrial (A, B Version) Storage Temperature Range Junction Temperature (TJ Max) 16-Lead TSSOP Package Power Dissipation θJA Thermal Impedance Lead Temperature Soldering 1 Rating −0.3 V to +7 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V ESD CAUTION −40°C to +105°C −65°C to +150°C 150°C (TJ max − TA)/θJA 160°C/W JEDEC Industry Standard J-STD-020 Transient currents of up to 100 mA do not cause SCR latch-up. Rev. B | Page 8 of 28 AD5303/AD5313/AD5323 CLR 1 16 SDO LDAC 2 15 GND 14 DIN VDD 3 VREF B 4 VREF A 5 AD5303/ AD5313/ AD5323 TOP VIEW (Not to Scale) 13 SCLK 12 SYNC 11 VOUTB BUF A 7 10 PD BUF B 8 9 VOUTA 6 DCEN 00472-004 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 6. Pin Configuration Table 5. Pin Function Descriptions Pin No. 1 2 Mnemonic CLR LDAC 3 4 VDD VREFB 5 VREFA 6 7 VOUTA BUF A 8 BUF B 9 DCEN 10 PD 11 12 VOUTB SYNC 13 SCLK 14 DIN 15 16 GND SDO Description Active Low Control Input. Loads all zeros to both input and DAC registers. Active Low Control Input. Transfers the contents of the input registers to their respective DAC registers. Pulsing this pin low allows either or both DAC registers to be updated if the input registers have new data. This allows the simultaneous update of both DAC outputs. Power Supply Input. These parts can be operated from 2.5 V to 5.5 V, and the supply should be decoupled to GND. Reference Input Pin for DAC B. It may be configured as a buffered or an unbuffered input, depending on the state of the BUF B pin. It has an input range from 0 V to VDD in unbuffered mode and from 1 V to VDD in buffered mode. Reference Input Pin for DAC A. It may be configured as a buffered or an unbuffered input depending on the state of the BUF A pin. It has an input range from 0 to VDD in unbuffered mode and from 1 V to VDD in buffered mode. Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. Control Pin. Controls whether the reference input for DAC A is unbuffered or buffered. If this pin is tied low, the reference input is unbuffered. If it is tied high, the reference input is buffered. Control Pin. Controls whether the reference input for DAC B is unbuffered or buffered. If this pin is tied low, the reference input is unbuffered. If it is tied high, the reference input is buffered. This pin is used to enable the daisy-chaining option. This should be tied high if the part is being used in a daisy chain. The pin should be tied low if it is being used in standalone mode. Active Low Control Input. Acts as a hardware power-down option. This pin overrides any software power-down option. Both DACs go into power-down mode when this pin is tied low. The DAC outputs go into a high impedance state and the current consumption of the part drops to 200 nA @ 5 V (50 nA @ 3 V). Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on the falling edges of the following 16 clocks. If SYNC is taken high before the 16th falling edge, the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the device. Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates up to 30 MHz. The SCLK input buffer is powered down after each write cycle. Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. The DIN input buffer is powered down after each write cycle. Ground Reference Point for All Circuitry on the Part. Serial Data Output. Can be used for daisy-chaining a number of these devices together or for reading back the data in the shift register for diagnostic purposes. The serial data output is valid on the falling edge of the clock. Rev. B | Page 9 of 28 AD5303/AD5313/AD5323 TERMINOLOGY Relative Accuracy or Integral Nonlinearity (INL) For the DAC, relative accuracy or integral nonlinearity is a measure of the maximum deviation, in LSB, from a straight line passing through the actual endpoints of the DAC transfer function. A typical INL error vs. code plot can be seen in Figure 7, Figure 8, and Figure 9. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified DNL of ±1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. A typical DNL error vs. code plot can be seen in Figure 10, Figure 11, and Figure 12. Offset Error This is a measure of the offset error of the DAC and the output amplifier. It is expressed as a percentage of the full-scale range. Gain Error This is a measure of the span error of the DAC. It is the deviation in slope of the actual DAC transfer characteristic from the ideal expressed as a percentage of the full-scale range. Offset Error Drift This is a measure of the change in offset error with changes in temperature. It is expressed in (ppm of full-scale range)/°C. Gain Error Drift This is a measure of the change in gain error with changes in temperature. It is expressed in (ppm of full-scale range)/°C. Major-Code Transition Glitch Energy Major-code transition glitch energy is the energy of the impulse injected into the analog output when the code in the DAC register changes state. It is normally specified as the area of the glitch in nV-s and is measured when the digital code is changed by 1 LSB at the major carry transition (011 . . . 11 to 100 . . . 00 or 100 . . . 00 to 011 . . . 11). Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital input pins of the device, but is measured when the DAC is not being written to (SYNC held high). It is specified in nV-s and is measured with a full-scale change on the digital input pins, that is, from all 0s to all 1s and vice versa. DAC-to-DAC Crosstalk This is the glitch impulse transferred to the output of one DAC due to a digital code change and subsequent output change of the other DAC. This includes both digital and analog crosstalk. It is measured by loading one of the DACs with a full-scale code change (all 0s to all 1s and vice versa) while keeping LDAC low and monitoring the output of the other DAC. The area of the glitch is expressed in nV-s. DC Crosstalk This is the dc change in the output level of one DAC in response to a change in the output of the other DAC. It is measured with a full-scale output change on one DAC while monitoring the other DAC. It is expressed in microvolts. Power Supply Rejection Ratio (PSRR) This indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in VOUT to a change in VDD for full-scale output of the DAC. It is measured in decibels. VREF is held at 2 V and VDD is varied ±10%. Reference Feedthrough This is the ratio of the amplitude of the signal at the DAC output to the reference input when the DAC output is not being updated (that is, LDAC is high). It is expressed in decibels. Total Harmonic Distortion (THD) This is the difference between an ideal sine wave and its attenuated version using the DAC. The sine wave is used as the reference for the DAC and the THD is a measure of the harmonics present on the DAC output. It is measured in decibels. Multiplying Bandwidth The amplifiers within the DAC have a finite bandwidth. The multiplying bandwidth is a measure of this. A sine wave on the reference (with full-scale code loaded to the DAC) appears on the output. The multiplying bandwidth is the frequency at which the output amplitude falls to 3 dB below the input. Channel-To-Channel Isolation This is a ratio of the amplitude of the signal at the output of one DAC to a sine wave on the reference input of the other DAC. It is measured in decibels. Analog Crosstalk This is the glitch impulse transferred to the output of one DAC due to a change in the output of the other DAC. It is measured by loading one of the input registers with a full-scale code change (all 0s to all 1s and vice versa) while keeping LDAC high. Then pulse LDAC low and monitor the output of the DAC whose digital code was not changed. The area of the glitch is expressed in nV-s. Rev. B | Page 10 of 28 AD5303/AD5313/AD5323 TYPICAL PERFORMANCE CHARACTERISTICS 1.0 0.3 TA = 25°C VDD = 5V TA = 25°C VDD = 5V 0.2 DNL ERROR (LSB) INL ERROR (LSB) 0.5 0 0.1 0 –0.1 –0.5 0 50 100 150 200 250 CODE –0.3 0 0.6 TA = 25°C VDD = 5V 0.4 1 0.2 DNL ERROR (LSB) 200 250 0 –1 TA = 25°C VDD = 5V 0 –0.2 200 400 600 800 1000 CODE 00472-008 0 –0.6 0 200 400 600 800 1000 00472-011 –0.4 –2 4000 00472-012 INL ERROR (LSB) 150 Figure 10. AD5303 Typical DNL Plot 2 –3 100 CODE Figure 7. AD5303 Typical INL Plot 3 50 00472-010 –1.0 00472-007 –0.2 CODE Figure 8. AD5313 Typical INL Plot Figure 11. AD5313 Typical DNL Plot 12 1.0 TA = 25°C VDD = 5V TA = 25°C VDD = 5V 8 DNL ERROR (LSB) 0 –4 0 –0.5 –8 –12 0 1000 2000 CODE 3000 4000 00472-009 INL ERROR (LSB) 0.5 4 –1.0 Figure 9. AD5323 Typical INL Plot 0 1000 2000 CODE 3000 Figure 12. AD5323 Typical DNL Plot Rev. B | Page 11 of 28 AD5303/AD5313/AD5323 1.00 TA = 25°C VDD = 5V 0.75 0.25 FREQUENCY ERROR (LSB) VDD = 5V VDD = 3V 0.50 MAX INL MAX DNL 0 MIN DNL –0.25 MIN INL –0.50 2 3 4 5 VREF (V) 0 100 00472-013 –1.00 Figure 13. AD5303 INL and DNL Error vs. VREF 1.00 200 250 IDD (µA) 300 350 400 Figure 16. IDD Histogram with VDD = 3 V and VDD = 5 V 5 VDD = 5V VREF = 3V 0.75 150 00472-016 –0.75 5V SOURCE 4 MAX DNL MAX INL 0.25 VOUT (V) ERROR (LSB) 0.50 0 –0.25 MIN INL –0.50 3V SOURCE 3 2 MIN DNL 3V SINK 1 5V SINK 0 40 TEMPERATURE (°C) 80 120 –0 0 Figure 14. AD5303 INL Error and DNL Error vs. Temperature 1 2 3 4 SINK/SOURCE CURRENT (mA) 5 6 00472-017 –1.00 –40 00472-014 –0.75 Figure 17. Source and Sink Current Capability 1.0 600 TA = 25°C VDD = 5V VDD = 5V VREF =2V 500 400 IDD (µA) GAIN ERROR 0 300 200 OFFSET ERROR –0.5 –1.0 –40 0 40 TEMPERATURE (°C) 80 120 Figure 15. Offset Error and Gain Error vs. Temperature 0 ZERO SCALE Figure 18. Supply Current vs. Code Rev. B | Page 12 of 28 FULL SCALE 00472-018 100 00472-015 ERROR (%) 0.5 AD5303/AD5313/AD5323 600 VDD = 5V TA = 25°C BOTH DACS IN GAIN-OF-TWO MODE REFERENCE INPUTS BUFFERED 500 CH2 IDD (µA) 400 CLK –40°C 300 +105°C +25°C 200 CH1 VOUT 3.0 3.5 4.0 4.5 5.0 5.5 VDD(V) CH1 1V, CH2 5V, TIME BASE = 5µs/DIV Figure 19. Supply Current vs. Supply Voltage Figure 22. Half-Scale Settling (¼ to ¾ Scale Code Change) 1.0 TA = 25°C BOTH DACS IN THREE-STATE CONDITION 0.9 00472-022 0 2.5 00472-019 100 VDD 0.8 IDD (µA) 0.7 0.6 0.5 0.4 0.3 +25°C –40°C CH1 0.2 VOUTA CH2 3.2 3.7 4.2 VDD (V) 4.7 00472-020 +105°C 0 2.7 5.2 CH1 1V, CH2 1V, TIME BASE = 20µs/DIV Figure 23. Power-On Reset to 0 V Figure 20. Power-Down Current vs. Supply Voltage 700 00472-023 0.1 TA = 25°C TA = 25°C 600 VOUT CH1 400 VDD = 5V 300 CH3 100 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 VLOGIC (V) 5.0 Figure 21. Supply Current vs. Logic Input Voltage CH1 1V, CH3 5V, TIME BASE = 1µs/DIV Figure 24. Exiting Power-Down to Midscale Rev. B | Page 13 of 28 00472-024 CLK VDD = 3V 200 00472-021 IDD (µA) 500 AD5303/AD5313/AD5323 2.50 VOUT (V) 2mV/DIV 2.49 2.47 1µs/DIV 00472-027 00472-025 2.48 500ns/DIV Figure 27. DAC-to-DAC Crosstalk Figure 25. AD5323 Major-Code Transition 10 0.10 TA = 25°C VDD = 5V FULL-SCALE ERROR (V) 0 –10 (dB) –20 –30 –40 0.05 0 –0.05 100 1k 10k 100k FREQUENCY(Hz) 1M 10M Figure 26. Multiplying Bandwidth (Small-Signal Frequency Response) Rev. B | Page 14 of 28 –0.10 0 1 2 3 4 VREF (V) Figure 28. Full-Scale Error vs. VREF (Buffered) 5 00472-028 –60 10 00472-026 –50 AD5303/AD5313/AD5323 FUNCTIONAL DESCRIPTION The AD5303/AD5313/AD5323 are dual resistor-string DACs fabricated on a CMOS process with resolutions of 8-/10-/12-bits respectively. They contain reference buffers and output buffer amplifiers, and are written to via a 3-wire serial interface. They operate from single supplies of 2.5 V to 5.5 V and the output buffer amplifiers provide rail-to-rail output swing with a slew rate of 0.7 V/μs. Each DAC is provided with a separate reference input, which may be buffered to draw virtually no current from the reference source, or unbuffered to give a reference input range from GND to VDD. The devices have three programmable power-down modes, in which one or both DACs may be turned off completely with a high impedance output, or the output may be pulled low by an on-chip resistor. RESISTOR STRING The resistor string section of the AD5303/AD5313/AD5323 is shown in Figure 30. It is simply a string of resistors, each of value R. The digital code loaded to the DAC register determines at what node on the string the voltage is tapped off to be fed into the output amplifier. The voltage is tapped off by closing one of the switches connecting the string to the amplifier. Because it is a string of resistors, it is guaranteed monotonic. R R TO OUTPUT AMPLIFIER R DIGITAL-TO-ANALOG The architecture of one DAC channel consists of a reference buffer and a resistor-string DAC followed by an output buffer amplifier. The voltage at the VREF pin provides the reference voltage for the DAC. Figure 29 shows a block diagram of the DAC architecture. Because the input coding to the DAC is straight binary, the ideal output voltage is given by VOUT = R Figure 30. Resistor String DAC REFERENCE INPUTS VREF × D 2N where: D is the decimal equivalent of the binary code, which is loaded to the DAC register: 0 to 255 for AD5303 (8 bits) 0 to 1023 for AD5313 (10 bits) 0 to 4095 for AD5323 (12 bits) N is the DAC resolution. VREF A INPUT REGISTER DAC REGISTER SWITCH CONTROLLED BY CONTROL LOGIC RESISTOR STRING VOUTA OUTPUT BUFFER AMPLIFIER Figure 29. Single DAC Channel Architecture 00472-029 REFERENCE BUFFER 00472-030 R There is a reference input pin for each of the two DACs. The reference inputs are buffered, but can also be configured as unbuffered. The advantage with the buffered input is the high impedance it presents to the voltage source driving it. However, if the unbuffered mode is used, the user can have a reference voltage as low as GND and as high as VDD since there is no restriction due to headroom and footroom of the reference amplifier. If there is a buffered reference in the circuit (for example, REF192), there is no need to use the on-chip buffers of the AD5303/AD5313/AD5323. In unbuffered mode, the input impedance is still large at typically 180 kΩ per reference input for 0 V to VREF mode and 90 kΩ for 0 V to 2 VREF mode. The buffered/unbuffered option is controlled by the BUF A and BUF B pins. If a BUF pin is tied high, the reference input is buffered; if tied low, it is unbuffered. OUTPUT AMPLIFIER The output buffer amplifier is capable of generating output voltages to within 1 mV of either rail, which gives an output range of 0.001 V to VDD − 0.001 V when the reference is VDD. It is capable of driving a load of 2 kΩ in parallel with 500 pF to GND and VDD. The source and sink capabilities of the output amplifier can be seen in Figure 17. The slew rate is 0.7 V/μs with a half-scale settling time to ±0.5 LSB (at eight bits) of 6 μs. Rev. B | Page 15 of 28 AD5303/AD5313/AD5323 POWER-ON RESET The AD5303/AD5313/AD5323 are provided with a power-on reset function, so that they power up in a defined state. The power-on state is with 0V to VREF output range and the output set to 0 V. Both input and DAC registers are filled with zeros and remain so until a valid write sequence is made to the device. This is particularly useful in applications where it is important to know the state of the DAC outputs while the device is powering up. CLEAR FUNCTION (CLR) The CLR pin is an active low input that, when pulled low, loads all zeros to both input registers and both DAC registers. This enables both analog outputs to be cleared to 0 V. Rev. B | Page 16 of 28 AD5303/AD5313/AD5323 SERIAL INTERFACE The AD5303/AD5313/AD5323 are controlled over a versatile, 3-wire serial interface, which operates at clock rates up to 30 MHz and is compatible with SPI, QSPI, MICROWIRE, and DSP interface standards. INPUT SHIFT REGISTER The input shift register is 16 bits wide. Data is loaded into the device as a 16-bit word under the control of a serial clock input, SCLK. The timing diagram for this operation is shown in Figure 5. The 16-bit word consists of four control bits followed by 8 /10 /12 bits of DAC data, depending on the device type. The first bit loaded is the MSB (Bit 15), which determines whether the data is for DAC A or DAC B. Bit 14 determines the output range (0 V to VREF or 0 V to 2 VREF). Bit 13 and Bit 12 control the operating mode of the DAC. Table 6. Control Bits Bit 15 Name A/B Function 0: data written to DAC A 1: data written to DAC B 14 GAIN 13 12 PD1 PD0 0: output range of 0 V to VREF 1: output range of 0 V to 2 VREF Mode bit Mode bit After the end of serial data transfer, data is automatically transferred from the input shift register to the input register of the selected DAC. If SYNC is taken high before the 16th falling edge of SCLK, the data transfer is aborted and the input registers are not updated. When data has been transferred into both input registers, the DAC registers of both DACs may be simultaneously updated, by taking LDAC low. CLR is an active low, asynchronous clear that clears the input and DAC registers of both DACs to all 0s. LOW POWER SERIAL INTERFACE To reduce the power consumption of the device even further, the interface only powers up fully when the device is being written to. As soon as the 16-bit control word has been written to the part, the SCLK and DIN input buffers are powered down. They only power up again following a falling edge of SYNC. DOUBLE-BUFFERED INTERFACE Power-On Default N/A The DACs all have double-buffered interfaces consisting of two banks of registers—input registers and DAC registers. The input register is connected directly to the input shift register and the digital code is transferred to the relevant input register on completion of a valid write sequence. The DAC register contains the digital code used by the resistor string. 0 0 0 The remaining bits are DAC data bits, starting with the MSB and ending with the LSB. The AD5323 uses all 12 bits of DAC data; the AD5313 uses 10 bits and ignores the 2 LSBs. The AD5303 uses eight bits and ignores the last four bits. The data format is straight binary, with all 0s corresponding to 0 V output, and all 1s corresponding to full-scale output (VREF − 1 LSB). The SYNC input is a level-triggered input that acts as a frame synchronization signal and chip enable. Data can be transferred into the device only while SYNC is low. To start the serial data transfer, SYNC should be taken low, observing the minimum SYNC to SCLK rising edge setup time, t4. After SYNC goes low, serial data is shifted into the device’s input shift register on the falling edges of SCLK for 16 clock pulses. Any data and clock pulses after the 16th are ignored, and no further serial data transfer occurs until SYNC is taken high and low again. SYNC may be taken high after the falling edge of the 16th SCLK pulse, observing the minimum SCLK falling edge to SYNC rising edge time, t7. Access to the DAC register is controlled by the LDAC function. When LDAC is high, the DAC register is latched and the input register may change state without affecting the contents of the DAC register. However, when LDAC is brought low, the DAC register becomes transparent and the contents of the input register are transferred to it. This is useful if the user requires simultaneous updating of both DAC outputs. The user may write to both input registers individually and then, by pulsing the LDAC input low, both outputs update simultaneously. These parts contain an extra feature whereby the DAC register is not updated unless its input register has been updated since the last time that LDAC was brought low. Normally, when LDAC is brought low, the DAC registers are filled with the contents of the input registers. In the case of the AD5303/AD5313/AD5323, the part only updates the DAC register if the input register has been changed since the last time the DAC register was updated, thereby removing unnecessary digital crosstalk. Rev. B | Page 17 of 28 AD5303/AD5313/AD5323 DB0 (LSB) A/B GAIN PD1 PD0 D7 D6 D5 D4 D3 D2 D1 D0 X X X X DATA BITS 00472-031 DB15 (MSB) Figure 31. AD5303 Input Shift Register Contents DB0 (LSB) A/B GAIN PD1 PD0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X DATA BITS 00472-032 DB15 (MSB) Figure 32. AD5313 Input Shift Register Contents DB0 (LSB) A/B GAIN PD1 PD0 D11 D10 D9 D8 D7 D6 D5 D4 D3 DATA BITS Figure 33. AD5323 Input Shift Register Contents Rev. B | Page 18 of 28 D2 D1 D0 00472-033 DB15 (MSB) AD5303/AD5313/AD5323 POWER-DOWN MODES The AD5303/AD5313/AD5323 have very low power consumption, dissipating only 0.7 mW with a 3 V supply and 1.5 mW with a 5 V supply. Power consumption can be further reduced when the DACs are not in use by putting them into one of three power-down modes, which are selected by Bit 13 and Bit 12 (PD1 and PD0) of the control word. Table 7 shows how the state of the bits corresponds to the mode of operation of that particular DAC. Table 7. PD1/PD0 Operating Modes PD0 0 1 0 1 Operating Mode Normal operation Power-down (1 kΩ load to GND) Power-down (100 kΩ load to GND) Power-down (high impedance output) The bias generator, the output amplifier, the resistor string, and all other associated linear circuitry are shut down when the power-down mode is activated. However, the contents of the registers are unaffected when in power-down. The time to exit power-down is typically 2.5 μs for VDD = 5 V and 5 μs when VDD = 3 V (see Figure 24 for a plot). The software power-down modes programmed by PD0 and PD1 are overridden by the PD pin. Taking this pin low puts both DACs into power-down mode simultaneously and both outputs are put into a high impedance state. If PD is not used, it should be tied high. When both bits are set to 0, the DACs work normally with their normal power consumption of 300 μA at 5 V. However, for the three power-down modes, the supply current falls to 200 nA at 5 V (50 nA at 3 V) when both DACs are powered down. Not only does the supply current drop, but the output stage is also internally switched from the output of the amplifier to a resistor network of known values. This has the advantage that the output impedance of the part is known while the part is in power-down mode and provides a defined input condition for whatever is connected to the output of the DAC amplifier. Rev. B | Page 19 of 28 AMPLIFIER RESISTOR STRING DAC POWER-DOWN CIRCUITRY VOUT RESISTOR NETWORK Figure 34. Output Stage During Power-Down 00472-034 PD1 0 0 1 1 There are three different power-down options. The output is connected internally to GND through either a 1 kΩ resistor or a 100 kΩ resistor, or it is left in a high impedance state (threestate). The output stage is illustrated in Figure 34. AD5303/AD5313/AD5323 MICROPROCESSER INTERFACING AD5303/AD5313/AD5323 TO ADSP-2101 INTERFACE AD5303/AD5313/AD5323 TO 80C51/80L51 INTERFACE Figure 35 shows a serial interface between the AD5303/AD5313/ AD5323 and the ADSP-2101. The ADSP-2101 should be set up to operate in the SPORT transmit alternate framing mode. The ADSP-2101 sport is programmed through the SPORT control register and should be configured as follows: internal clock operation, active-low framing, 16-bit word length. Transmission is initiated by writing a word to the Tx register after the SPORT has been enabled. Figure 37 shows a serial interface between the AD5303/ AD5313/AD5323 and the 80C51/80L51 microcontroller. The setup for the interface is as follows: TXD of the 80C51/80L51 drives SCLK of the AD5303/AD5313/AD5323, while RXD drives the serial data line of the part. The SYNC signal is again derived from a bit programmable pin on the port. In this case, port line P3.3 is used. When data is to be transmitted to the AD5303/AD5313/AD5323, P3.3 is taken low. The 80C51/80L51 transmits data only in 8-bit bytes; thus only eight falling clock edges occur in the transmit cycle. To load data to the DAC, P3.3 is left low after the first eight bits are transmitted and a second write cycle is initiated to transmit the second byte of data. P3.3 is taken high following the completion of this cycle. The 80C51/ 80L51 output the serial data in a format that has the LSB first. The AD5303/AD5313/AD5323 require data with MSB as the first bit received. The 80C51/80L51 transmit routine should take this into account. DIN SCLK *ADDITIONAL PINS OMITTED FOR CLARITY Figure 35. AD5303/AD5313/AD5323 to ADSP-2101 Interface AD5303/AD5313/AD5323 TO 68HC11/68L11 INTERFACE Figure 36 shows a serial interface between the AD5303/ AD5313/AD5323 and the 68HC11/68L11 microcontroller. SCK of the 68HC11/68L11 drives the SCLK of the AD5303/ AD5313/AD5323, while the MOSI output drives the serial data line (DIN) of the DAC. The SYNC signal is derived from a port line (PC7). The setup conditions for correct operation of this interface are as follows: the 68HC11/68L11 should be configured so that its CPOL bit is a 0 and its CPHA bit is a 1. When data is being transmitted to the DAC, the SYNC line is taken low (PC7). When the 68HC11/68L11 is configured as previously mentioned, data appearing on the MOSI output is valid on the falling edge of SCK. Serial data from the 68HC11/ 68L11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. Data is transmitted MSB first. To load data to the AD5303/AD5313/ AD5323, PC7 is left low after the first eight bits are transferred and a second serial write operation is performed to the DAC; PC7 is taken high at the end of this procedure. SCK MOSI SCLK RXD DIN AD5303/AD5313/AD5323 TO MICROWIRE INTERFACE Figure 38 shows an interface between the AD5303/AD5313/ AD5323 and any MICROWIRE-compatible device. Serial data is shifted out on the falling edge of the serial clock and is clocked into the AD5303/AD5313/AD5323 on the rising edge of the SK. MICROWIRE* AD5303/ AD5313/ AD5323* CS SYNC SK SCLK SO DIN *ADDITIONAL PINS OMITTED FOR CLARITY. SYNC Figure 38. AD5303/AD5313/AD5323 to MICROWIRE Interface SCLK DIN *ADDITIONAL PINS OMITTED FOR CLARITY SYNC TXD *ADDITIONAL PINS OMITTED FOR CLARITY. 00472-036 PC7 P3.3 Figure 37. AD5303/AD5313/AD5323 to 80C51/80L51 Interface AD5303/ AD5313/ AD5323* 68HC11/68L11* AD5303/ AD5313/ AD5323* 80C51/80L51* 00472-037 DT SCLK SYNC 00472-035 TFS 00472-038 AD5303/ AD5313/ AD5323* ADSP-2101 Figure 36. AD5303/AD5313/AD5323 to 68HC11/68L11 Interface Rev. B | Page 20 of 28 AD5303/AD5313/AD5323 APPLICATIONS INFORMATION 15V TYPICAL APPLICATION CIRCUIT VS The AD5303/AD5313/AD5323 can be used with a wide range of reference voltages, especially if the reference inputs are configured to be unbuffered, in which case the devices offer a full, one-quadrant multiplying capability over a reference range of 0 V to VDD. VDD = 2.5V to 5.5V VREF A AD780/REF192 WITH VDD = 5V OR REF191 WITH VDD = 2.5V 1µF VOUTA VREF B AD5303/AD5313/ AD5323 SCLK DIN SYNC 1µF VOUTA VREF B AD5303/AD5313/ AD5323 SCLK DIN SYNC VOUTB GND BUF A BUF B SERIAL INTERFACE Figure 40. Using an REF195 as Power and Reference to the AD5303/AD5313/AD5323 BIPOLAR OPERATION USING THE AD5303/ AD5313/AD5323 VOUTB 6V to 16V GND BUF A BUF B VDD = 5V 00472-039 SERIAL INTERFACE VREF A The AD5303/AD5313/AD5323 have been designed for singlesupply operation, but bipolar operation is also achievable using the circuit shown in Figure 41. The circuit shown has been configured to achieve an output voltage range of −5 V < VOUT < +5 V. Rail-to-rail operation at the amplifier output is achievable using an AD820 or OP295 as the output amplifier. VDD VOUT VDD OUTPUT GND 0.1µF 10µF R1 10kΩ VS Figure 39. AD5303/AD5313/AD5323 Using External Reference If an output range of 0 V to VDD is required when the reference inputs are configured as unbuffered (for example, 0 V to 5 V), the simplest solution is to connect the reference inputs to VDD. As this supply may not be very accurate and may be noisy, the AD5303/AD5313/AD5323 can be powered from the reference voltage, for example, using a 5 V reference such as the REF195, as shown in Figure 40. The REF195 outputs a steady supply voltage for the AD5303/AD5313/AD5323. The supply current required from the REF195 is 300 μA and approximately 30 μA or 60 μA into each of the reference inputs (if unbuffered). This is with no load on the DAC outputs. When the DAC outputs are loaded, the REF195 also needs to supply the current to the loads. The total current required (with a 10 kΩ load on each output) is 360 μA + 2(5 V/10 kΩ) = 1.36 mA The load regulation of the REF195 is typically 2 ppm/mA, which results in an error of 2.7 ppm (13.5 μV) for the 1.36 mA current drawn from it. This corresponds to a 0.0007 LSB error at eight bits and 0.011 LSB error at 12 bits. +5V ±5V REF195 VDD OUTPUT GND R2 10kΩ VREF A/B –5V 1µF AD820/ OP295 AD5303/AD5313/ AD5323 SCLK DIN SYNC VOUTA/B GND BUF A BUF B 00472-041 EXT REF 10µF 00472-040 More typically, the AD5303/AD5313/AD5323 may be used with a fixed precision reference voltage. Figure 39 shows a typical setup for the AD5303/AD5313/AD5323 when using an external reference. If the reference inputs are unbuffered, the reference input range is from 0 V to VDD, but if the on-chip reference buffers are used, the reference range is reduced. Suitable references for 5 V operation are the AD780 and REF192 (2.5 V references). For 2.5 V operation, a suitable external reference is the REF191, a 2.048 V reference. 0.1µF REF195 SERIAL INTERFACE Figure 41. Bipolar Operation Using the AD5303/AD5313/AD5323 The output voltage for any input code can be calculated as follows: [ ] VOUT = (V REF ) × (D / 2 N ) × (R1 + R2) / R1 − V REF × (R2 / R1) where: D is the decimal equivalent of the code loaded to the DAC. N is the DAC resolution. VREF is the reference voltage input, and gain bit = 0, with VREF = 5 V R1 = R2 = 10 kΩ and VDD = 5 V, VOUT = (10 × D / 2 N ) − 5 V Rev. B | Page 21 of 28 AD5303/AD5313/AD5323 OPTO-ISOLATED INTERFACE FOR PROCESS CONTROL APPLICATIONS SCLK DIN 0.1µF 10kΩ SYNC VDD VREF A AD5303/AD5313/ AD5323 1Y2 1Y3 1B SYNC DIN SCLK SYNC DIN SCLK AD5303/ AD5313/ AD5323 AD5303/ AD5313/ AD5323 AD5303/ AD5313/ AD5323 5V 0.1µF VOUTB VREF VDD 10µF VIN DIN SYNC GND BUF A BUF B 00472-042 DIN SCLK 1kΩ FAIL VDD VREF A VREF B 1kΩ PASS VOUTA AD5303/AD5313/ AD5323 10kΩ DIN SYNC DIN SCLK 1Y1 DGND VOUTA SYNC 1Y0 A digitally programmable upper/lower limit detector using the two DACs in the AD5303/AD5313/AD5323 is shown in Figure 44. The upper and lower limits for the test are loaded to DAC A and DAC B, which, in turn, set the limits on the CMP04. If the signal at the VIN input is not within the programmed window, an LED indicates the fail condition. VREF B VDD 74HC139 AD5303/AD5313/AD5323 AS A DIGITALLY PROGRAMMABLE WINDOW DETECTOR VDD SCLK 1A CODED ADDRESS SYNC 1/2 CMP04 PASS/FAIL DIN VOUTB SCLK GND 1/6 74HC05 Figure 42. AD5303/AD5313/AD5323 in an Opto-Isolated Interface DECODING MULTIPLE AD5303/AD5313/AD5323s The SYNC pin on the AD5303/AD5313/AD5323 can be used in applications to decode a number of DACs. In this application, all the DACs in the system receive the same serial clock and serial data, but only the SYNC to one of the devices is active at any one time, allowing access to two channels in this 8-channel system. The 74HC139 is used as a 2-to-4 line decoder to address any of the DACs in the system. To prevent timing errors from occurring, the enable input should be brought to its inactive state while the coded address inputs are changing state. Figure 43 shows a diagram of a typical setup for decoding multiple AD5303/AD5313/AD5323 devices in a system. Rev. B | Page 22 of 28 Figure 44. Window Detector Using AD5303/AD5313/AD5323 00472-044 10µF POWER SCLK VCC 1G ENABLE Figure 43. Decoding Multiple AD5303/AD5313/AD5323 Devices in a System 5V REGULATOR 10kΩ VDD AD5303/ AD5313/ AD5323 00472-043 The AD5303/AD5313/AD5323 has a versatile 3-wire serial interface making it ideal for generating accurate voltages in process control and industrial applications. Due to noise, safety requirements, or distance, it may be necessary to isolate the AD5303/AD5313/AD5323 from the controller. This can easily be achieved by using opto-isolators, which provides isolation in excess of 3 kV. The serial loading structure of the AD5303/ AD5313/AD5323 makes it ideally suited for use in opto-isolated applications. Figure 42 shows an opto-isolated interface to the AD5303/AD5313/AD5323 where DIN, SCLK, and SYNC are driven from opto-couplers. The power supply to the part also needs to be isolated. This is done by using a transformer. On the DAC side of the transformer, a 5 V regulator provides the 5 V supply required for the AD5303/AD5313/AD5323. SYNC DIN SCLK AD5303/AD5313/AD5323 A continuous SCLK source may be used if it can be arranged that SYNC is held low for the correct number of clock cycles. Alternatively, a burst clock containing the exact number of clock cycles may be used and SYNC may be taken high some time later. COARSE AND FINE ADJUSTMENT USING THE AD5303/AD5313/AD5323 The DACs in the AD5303/AD5313/AD5323 can be paired together to form a coarse and fine adjustment function, as shown in Figure 45. DAC A provides the coarse adjustment while DAC B provides the fine adjustment. Varying the ratio of R1 and R2 changes the relative effect of the coarse and fine adjustments. With the resistor values and external reference shown, the output amplifier has unity gain for the DAC A output, so the output range is 0 V to 2.5 V − 1 LSB. For DAC B, the amplifier has a gain of 7.6 × 10–3, giving DAC B a range equal to 19 mV. When the transfer to all input registers is complete, a common LDAC signal updates all DAC registers and all analog outputs are updated simultaneously. 68HC111 MOSI The circuit is shown with a 2.5 V reference, but reference voltages up to VDD may be used. The op amps indicated allow a rail-to-rail output swing. MISO DIN SCK SCLK PC7 SYNC PC6 LDAC VDD = 5V 10µF R4 900Ω +5V VIN VDD VOUT AD780/REF192 WITH VDD = 5V VREF A VOUTA 1µF VOUT R1 390Ω SYNC AD820/ OP295 LDAC AD5303/AD5313/ AD5323 VREF B VOUTB AD5303/ AD5313/ AD53231 (DAC 2) SDO DIN R2 51.2kΩ GND 00472-045 GND SDO DIN SCLK EXT 2.5V REF (DAC 1) Figure 45. Coarse and Fine Adjustment SCLK SYNC LDAC DAISY-CHAIN MODE This mode is used for updating serially connected or standalone devices on the rising edge of SYNC. For systems that contain several DACs, or where the user wishes to read back the DAC contents for diagnostic purposes, the SDO pin may be used to daisy-chain several devices together and provide serial readback. By connecting the daisy-chain enable (DCEN) pin high, the daisy-chain mode is enabled. It is tied low in standalone mode. In daisy-chain mode, the internal gating on SCLK is disabled. The SCLK is continuously applied to the input shift register when SYNC is low. If more than 16 clock pulses are applied, the data ripples out of the shift register and appears on the SDO line. This data is clocked out after the falling edge of SCLK and is valid on the subsequent rising and falling edges. By connecting this line to the DIN input on the next DAC in the chain, a multiDAC interface is constructed. Sixteen clock pulses are required for each DAC in the system. Therefore, the total number of clock cycles must equal 16N, where N is the total number of devices in the chain. When the serial transfer to all devices is complete, SYNC should be taken high. This prevents any further data from being clocked into the input shift register. Rev. B | Page 23 of 28 AD5303/ AD5313/ AD53231 (DAC N) SDO 1ADDITIONAL PINS OMITTED FOR CLARITY. Figure 46. Daisy-Chain Mode 00472-046 0.1µF R3 51.2kΩ AD5303/ AD5313/ AD53231 AD5303/AD5313/AD5323 t1 SCLK t8 t3 t4 t2 t14 SYNC t6 DIN t15 t5 DB15 DB0 DB15 INPUT WORD FOR DAC N DB0 INPUT WORD FOR DAC (N+1) DB15 SDO UNDEFINED DB0 INPUT WORD FOR DAC N SCLK t13 SDO VIH 00472-047 VIL t12 Figure 47. Daisy-Chaining Timing Diagram POWER SUPPLY BYPASSING AND GROUNDING In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the AD5303/AD5313/AD5323 are mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. If the AD5303/ AD5313/AD5323 are in a system where multiple devices require an AGND-to-DGND connection, the connection should be made at one point only. The star ground point should be established as close as possible to the AD5303/ AD5313/AD5323. The AD5303/AD5313/AD5323 should have ample supply bypassing of 10 μF in parallel with 0.1 μF on the supply located as close to the package as possible, ideally right up against the device. Use 10 μF capacitors that are of the tantalum bead type. The 0.1 μF capacitor should have low effective series resistance (ESR) and effective series inductance (ESI), like the common ceramic types that provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. The power supply lines of the AD5303/AD5313/AD5323 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board, and should never be run near the reference inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip technique is by far the best, but is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to the ground plane while signal traces are placed on the solder side. Rev. B | Page 24 of 28 AD5303/AD5313/AD5323 OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.30 0.19 0.65 BSC COPLANARITY 0.10 0.20 0.09 SEATING PLANE 8° 0° 0.75 0.60 0.45 COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 48. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters ORDERING GUIDE Model AD5303ARU AD5303ARU-REEL7 AD5303ARUZ 1 AD5303BRU AD5303BRU-REEL AD5303BRU-REEL7 AD5303BRUZ1 AD5303BRUZ-REEL71 AD5313ARU AD5313ARU-REEL7 AD5313ARUZ1 AD5313BRU AD5313BRU-REEL AD5313BRU-REEL7 AD5313BRUZ1 AD5323ARU AD5323ARU-REEL7 AD5323ARUZ1 AD5323ARUZ-REEL71 AD5323BRU AD5323BRU-REEL AD5323BRU-REEL7 AD5323BRUZ1 AD5323BRUZ-REEL1 AD5323BRUZ-REEL71 1 Temperature Range –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C Package Description 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) Z = RoHS Compliant Part. Rev. B | Page 25 of 28 Package Option RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 AD5303/AD5313/AD5323 NOTES Rev. B | Page 26 of 28 AD5303/AD5313/AD5323 NOTES Rev. B | Page 27 of 28 AD5303/AD5313/AD5323 NOTES ©1999–2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C00472-0-6/07(B) Rev. B | Page 28 of 28