NXP MK65FN2M0VMI18 Kinetis k65 sub-family Datasheet

NXP Semiconductors
Data Sheet: Technical Data
K65P169M180SF5V2
Rev. 4, 04/2017
Kinetis K65 Sub-Family
MK65FN2M0VMI18
MK65FX1M0VMI18
180 MHz ARM® Cortex®-M4F Microcontroller.
The K65 sub-family members provide greater performance,
memory options up to 2 MB total flash and 256 KB of SRAM, as
well as higher peripheral integration with features such as Dual
USB and a 10/100 Mbit/s Ethernet MAC. These devices maintain
hardware and software compatibility with the existing Kinetis
family. This product also offers:
• Integration of a High Speed USB Physical Transceiver
• Greater performance flexibility with a High Speed Run
mode
• Smarter peripherals with operation in Stop modes
169 MAPBGA (MI)
9 mm x 9 mm Pitch 0.65 mm
Performance
Memories and memory expansion
• Up to 180 MHz ARM Cortex-M4 based core with DSP
• Up to 2 MB program flash memory on noninstructions and Single Precision Floating Point unit
FlexMemory devices with 256 KB RAM
• Up to 1 MB program flash memory and 256 KB of
System and Clocks
FlexNVM on FlexMemory devices
• Multiple low-power modes to provide power
• 4 KB FlexRAM on FlexMemory devices
optimization based on application requirements
• FlexBus external bus interface and SDRAM controller
• Memory protection unit with multi-master protection
Analog modules
• 3 to 32 MHz main crystal oscillator
• 32 kHz low power crystal oscillator
• Two 16-bit SAR ADCs and two 12-bit DAC
• 48 MHz internal reference
• Four analog comparators (CMP) containing a 6-bit
DAC and programmable reference input
Security
• Voltage reference 1.2V
• Hardware random-number generator
Communication interfaces
• Supports DES, AES, SHA accelerator (CAU)
• Multiple levels of embedded flash security
• Ethernet controller with MII and RMII interface to
external PHY and hardware IEEE 1588 capability
Timers
• USB high-/full-/low-speed On-the-Go with on-chip
• Four Periodic interrupt timers
high speed transceiver
• 16-bit low-power timer
• USB full-/low-speed OTG with on-chip transceiver
• Two 16-bit low-power timer PWM modules
• Two CAN, three SPI and four I2C modules
• Two 8-channel motor control/general purpose/PWM
• Low Power Universal Asynchronous Receiver/
timers
Transmitter 0 (LPUART0) and five standard UARTs
• Two 2-ch quad decoder/general purpose timers
• Secure Digital Host Controller (SDHC)
• Real-time clock
• I2S module
Human-machine interface
• Low-power hardware touch sensor interface (TSI)
• General-purpose input/output
Operating Characteristics
• Voltage/Flash write voltage range:1.71 to 3.6 V
• Temperature range (ambient): -40 to 105°C
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
Ordering Information 1
Part Number
Memory
Maximum number of I\O's
Flash
SRAM
MK65FN2M0VMI18
2 MB
256 KB
116
MK65FX1M0VMI18
1.25 MB
256 KB
116
1. To confirm current availability of orderable part numbers, go to http://www.nxp.com and perform a part number search.
Related Resources
Type
Description
Resource
Selector
Guide
The NXP Solution Advisor is a web-based tool that features interactive
application wizards and a dynamic product selector.
Solution Advisor
Reference
Manual
The Reference Manual contains a comprehensive description of the
structure and function (operation) of a device.
K65P169M180SF5RMV21
Data Sheet
The Data Sheet includes electrical characteristics and signal
connections.
This document.
Chip Errata
The chip mask set Errata provides additional or corrective information for Kinetis_K_0N65N 1
a particular device mask set.
Package
drawing
Package dimensions are provided in package drawings.
MAPBGA 169-pin :
98ASA00628D1
1. To find the associated resource, go to http://www.nxp.com and perform a search using this term.
2
NXP Semiconductors
Kinetis K65 Sub-Family, Rev. 4, 04/2017
Kinetis K65 Sub-Family
ARM ® Cortex® -M4
Core
System
Memories and Memory Interfaces
Clocks
Internal
and external
watchdogs
Program
flash
RAM
Phaselocked loop
Debug
interfaces
DSP
Memory
protection
FlexMemory
Cache
Frequencylocked loop
Interrupt
controller
Floatingpoint unit
DMA
Serial
programming
interface
External
bus
Low/high
frequency
oscillators
Low-leakage
wakeup
SDRAM
controller
Internal
reference
clocks
Human-Machine
Interface (HMI)
Communication Interfaces
Security
Analog
Timers
CRC
16-bit ADC
x2
Timers
x4 (20ch)
I C
x4
I S
x1
GPIO
Random
number
generator
Analog
comparator
x4
Carrier
modulator
transmitter
UART
x5
Secure
Digital
Xtrinsic
touch-sensing
interface
Hardware
encryption
6-bit DAC
x4
Programmable
delay block
SPI
x3
12-bit DAC
x2
Periodic
interrupt
timers
CAN
x2
USB LS/FS
OTG
controller
with
transceiver
Voltage
reference
Low power
timer
IEEE 1588
Ethernet
Independent
real-time
clock
LPUART
and Integrity
2
IEEE 1588
Timers
Low power
TPM x 2 (4ch)
2
USB LS/FS/HS
OTG
controller
with
transceiver
USB DCD/
USBHSDCD
USB voltage
regulator
Figure 1. K65 Block Diagram
Kinetis K65 Sub-Family, Rev. 4, 04/2017
3
NXP Semiconductors
Table of Contents
1 Ratings.................................................................................... 5
1.1 Thermal handling ratings................................................. 5
1.2 Moisture handling ratings................................................ 5
1.3 ESD handling ratings....................................................... 5
1.4 Voltage and current operating ratings............................. 5
2 General................................................................................... 6
2.1 AC electrical characteristics.............................................6
2.2 Nonswitching electrical specifications..............................7
2.2.1
Voltage and current operating requirements.....7
2.2.2
LVD and POR operating requirements............. 8
2.2.3
Voltage and current operating behaviors.......... 9
2.2.4
Power mode transition operating behaviors......10
2.2.5
Power consumption operating behaviors.......... 12
2.2.6
EMC radiated emissions operating behaviors...16
2.2.7
Designing with radiated emissions in mind....... 17
2.2.8
Capacitance attributes...................................... 17
2.3 Switching specifications...................................................17
2.3.1
Device clock specifications............................... 17
2.3.2
General switching specifications....................... 18
2.4 Thermal specifications..................................................... 19
2.4.1
Thermal operating requirements....................... 19
2.4.2
Thermal attributes............................................. 19
3 Peripheral operating requirements and behaviors.................. 20
3.1 Core modules.................................................................. 21
3.1.1
Debug trace timing specifications..................... 21
3.1.2
JTAG electricals................................................ 21
3.2 System modules.............................................................. 24
3.3 Clock modules................................................................. 24
3.3.1
MCG specifications........................................... 24
3.3.2
IRC48M specifications...................................... 27
3.3.3
Oscillator electrical specifications..................... 28
3.3.4
32 kHz oscillator electrical characteristics.........31
3.4 Memories and memory interfaces................................... 31
3.4.1
Flash (FTFE) electrical specifications............... 31
3.4.2
EzPort switching specifications......................... 36
3.4.3
Flexbus switching specifications....................... 37
3.4.4
SDRAM controller specifications.......................40
3.5 Security and integrity modules........................................ 43
3.6 Analog............................................................................. 43
3.6.1
ADC electrical specifications.............................43
3.6.2
CMP and 6-bit DAC electrical specifications.....48
3.6.3
12-bit DAC electrical characteristics................. 50
3.6.4
Voltage reference electrical specifications........ 53
4
NXP Semiconductors
4
5
6
7
3.7 Timers..............................................................................54
3.8 Communication interfaces............................................... 54
3.8.1
Ethernet switching specifications...................... 55
3.8.2
USB Voltage Regulator Electrical
Specifications.................................................... 58
3.8.3
USB Full Speed Transceiver and High Speed
PHY specifications............................................ 59
3.8.4
USB DCD electrical specifications.................... 60
3.8.5
CAN switching specifications............................ 60
3.8.6
DSPI switching specifications (limited voltage
range)................................................................60
3.8.7
DSPI switching specifications (full voltage
range)................................................................62
3.8.8
Inter-Integrated Circuit Interface (I2C) timing....64
3.8.9
UART switching specifications.......................... 65
3.8.10 Low Power UART switching specifications....... 65
3.8.11 SDHC specifications......................................... 66
3.8.12 I2S switching specifications.............................. 67
3.9 Human-machine interfaces (HMI)....................................73
3.9.1
TSI electrical specifications...............................73
Dimensions............................................................................. 73
4.1 Obtaining package dimensions....................................... 73
Pinout...................................................................................... 74
5.1 K65_169BGA Signal Multiplexing and Pin Assignments. 74
5.2 Recommended connection for unused analog and
digital pins........................................................................81
5.3 K65 Pinouts..................................................................... 83
Ordering parts......................................................................... 84
6.1 Determining valid orderable parts....................................84
Part identification.....................................................................85
7.1 Description.......................................................................85
7.2 Format............................................................................. 85
7.3 Fields............................................................................... 85
7.4 Example...........................................................................86
8 Terminology and guidelines.................................................... 86
8.1 Definitions........................................................................ 86
8.2 Examples......................................................................... 87
8.3 Typical-value conditions.................................................. 87
8.4 Relationship between ratings and operating
requirements....................................................................88
8.5 Guidelines for ratings and operating requirements..........88
9 Revision History...................................................................... 89
Kinetis K65 Sub-Family, Rev. 4, 04/2017
Ratings
1 Ratings
1.1 Thermal handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
TSTG
Storage temperature
–55
150
°C
1
TSDR
Solder temperature, lead-free
—
260
°C
2
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.2 Moisture handling ratings
Symbol
MSL
Description
Moisture sensitivity level
Min.
Max.
Unit
Notes
—
3
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.3 ESD handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
VHBM
Electrostatic discharge voltage, human body model
-2000
+2000
V
1
VCDM
Electrostatic discharge voltage, charged-device
model
-500
+500
V
2
Latch-up current at ambient temperature of 105°C
-100
+100
mA
3
ILAT
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human
Body Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
1.4 Voltage and current operating ratings
Kinetis K65 Sub-Family, Rev. 4, 04/2017
5
NXP Semiconductors
General
Symbol
Description
Min.
Max.
Unit
VDD
Digital supply voltage
–0.3
3.8
V
IDD
Digital supply current
—
300
mA
–0.3
VDD + 0.3
V
–0.3
VDD + 0.3
V
VDIO
Digital1
VAIO
Analog1 input
ID
VDDA
input voltage,including RESET_b
voltage, including EXTAL32 and XTAL32
Maximum current single pin limit (digital output pins)
Analog supply voltage
–25
25
mA
VDD – 0.3
VDD + 0.3
V
VUSB0_DP
USB0_DP input voltage
–0.3
3.63
V
VUSB1_DP
USB1_DP input voltage
–0.3
3.63
V
VUSB0_DM
USB0_DM input voltage
–0.3
3.63
V
VUSB1_DM
USB1_DM input voltage
–0.3
3.63
V
VUSB1_VBUS
USB1_VBUS detect voltage
–0.3
6.0
V
VREG_IN0,
VREG_IN1
USB regulator input
–0.3
6.0
V
RTC battery supply voltage
–0.3
3.8
V
VBAT
1. Digital pins have a general purpose I/O port assigned (e.g. PTA0). Analog pins do not have an associated general
purpose I/O port.
2 General
2.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
VIH
Input Signal
Low
High
80%
50%
20%
Midpoint1
Fall Time
VIL
Rise Time
The midpoint is VIL + (VIH - VIL) / 2
Figure 2. Input signal measurement reference
All digital I/O switching characteristics assume:
1. output pins
6
NXP Semiconductors
Kinetis K65 Sub-Family, Rev. 4, 04/2017
General
• have CL=30pF loads,
• are slew rate disabled, and
• are normal drive strength
2. input pins
• have their passive filter disabled (PORTx_PCRn[PFE]=0)
2.2 Nonswitching electrical specifications
2.2.1 Voltage and current operating requirements
Table 1. Voltage and current operating requirements
Symbol
Description
Min.
Max.
Unit
VDD
Supply voltage
1.71
3.6
V
VDDA
Analog supply voltage
1.71
3.6
V
VDD – VDDA VDD-to-VDDA differential voltage
–0.1
0.1
V
VSS – VSSA VSS-to-VSSA differential voltage
–0.1
0.1
V
1.71
3.6
V
• 2.7 V ≤ VDD ≤ 3.6 V
0.7 × VDD
—
V
• 1.71 V ≤ VDD ≤ 2.7 V
0.75 × VDD
—
V
• 2.7 V ≤ VDD ≤ 3.6 V
—
0.35 × VDD
V
• 1.71 V ≤ VDD ≤ 2.7 V
—
0.3 × VDD
V
0.06 × VDD
—
V
-5
—
mA
VBAT
VIH
VIL
RTC battery supply voltage
Notes
Input high voltage
Input low voltage
VHYS
Input hysteresis
IICDIO
Digital1
input pin negative DC injection current —
single pin
2
• VIN < VSS-0.3V
IICAIO
Analog1 input pin DC injection current — single pin
• VIN < VSS-0.3V (Negative current injection)
IICcont
Contiguous pin DC injection current —regional limit,
includes sum of negative injection currents of 16
contiguous pin
• Negative current injection
2
mA
-5
—
-25
—
mA
VODPU
Pseudo Open drain pullup voltage level
VDD
VDD
V
VRAM
VDD voltage required to retain RAM
1.2
—
V
VPOR_VBAT
—
V
VRFVBAT
VBAT voltage required to retain the VBAT register file
Kinetis K65 Sub-Family, Rev. 4, 04/2017
3
7
NXP Semiconductors
General
1. Digital pins have a general purpose I/O port assigned (e.g. PTA0). Analog pins do not have an associated general
purpose I/O port.
2. All digital and analog I/O pins are internally clamped to VSS through an ESD protection diode. There is no diode
connection to VDD. If VIN is less than VSS-0.3V, a current limiting resistor is required. The minimum negative DC
injection current limiting resistor value is calculated as R=(-0.3-VIN)/|IICDIO| or R=(-0.3-VIN)/|IICAIO|. The actual resistor
should be an order of magnitude higher to tolerate transient voltages.
3. Open drain outputs must be pulled to VDD.
2.2.2 LVD and POR operating requirements
Table 2. VDD supply LVD and POR operating requirements
Symbol
Description
Min.
Typ.
Max.
Unit
VPOR
Falling VDD POR detect voltage
0.8
1.1
1.5
V
VLVDH
Falling low-voltage detect threshold — high
range (LVDV=01)
2.48
2.56
2.64
V
Low-voltage warning thresholds — high range
1
VLVW1H
• Level 1 falling (LVWV=00)
2.62
2.70
2.78
V
VLVW2H
• Level 2 falling (LVWV=01)
2.72
2.80
2.88
V
VLVW3H
• Level 3 falling (LVWV=10)
2.82
2.90
2.98
V
VLVW4H
• Level 4 falling (LVWV=11)
2.92
3.00
3.08
V
—
80
—
mV
1.54
1.60
1.66
V
VHYSH
Low-voltage inhibit reset/recover hysteresis —
high range
VLVDL
Falling low-voltage detect threshold — low
range (LVDV=00)
Low-voltage warning thresholds — low range
1
VLVW1L
• Level 1 falling (LVWV=00)
1.74
1.80
1.86
V
VLVW2L
• Level 2 falling (LVWV=01)
1.84
1.90
1.96
V
VLVW3L
• Level 3 falling (LVWV=10)
1.94
2.00
2.06
V
VLVW4L
• Level 4 falling (LVWV=11)
2.04
2.10
2.16
V
—
60
—
mV
VHYSL
Low-voltage inhibit reset/recover hysteresis —
low range
Notes
VBG
Bandgap voltage reference
0.97
1.00
1.03
V
tLPO
Internal low power oscillator period — factory
trimmed
900
1000
1100
μs
1. Rising threshold is the sum of falling threshold and hysteresis voltage
Table 3. VBAT power operating requirements
Symbol
Description
VPOR_VBAT Falling VBAT supply POR detect voltage
8
NXP Semiconductors
Min.
Typ.
Max.
Unit
0.8
1.1
1.5
V
Notes
Kinetis K65 Sub-Family, Rev. 4, 04/2017
General
2.2.3 Voltage and current operating behaviors
Table 4. Voltage and current operating behaviors
Symbol
VOH
Description
Min.
Typ.
Max.
Unit
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -10mA
VDD – 0.5
—
—
V
• 1.71 V ≤VDD ≤ 2.7 V, IOH = -5mA
VDD – 0.5
—
—
V
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -20mA
VDD – 0.5
—
—
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -10mA
VDD – 0.5
—
—
V
—
—
100
mA
VBAT – 0.5
—
VBAT – 0.5
—
—
—
100
mA
—
—
0.5
V
—
—
0.5
V
—
—
0.5
V
—
—
0.5
V
—
—
100
mA
Notes
Output high voltage — normal drive pad
Output high voltage — High drive pad
IOHT
Output high current total for all ports
VOH_RTC_WAKEUP Output high voltage— normal drive pad
• 2.7 V ≤ VBAT ≤ 3.6 V, IOH = -5 mA
• 1.71 V ≤ VBAT ≤ 2.7 V, IOH = -2.5
mA
IOH_RTC_WAKEUP Output high current total for
RTC_WAKEUP pins
VOL
Output low voltage — normal drive pad
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 10 mA
V
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 5 mA
Output low voltage — high drive pad
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 20 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 10 mA
IOLT
Output low current total for all ports
VOL_RTC_WAKEUP Output low voltage— normal drive pad
—
0.5
• 2.7 V ≤ VBAT ≤ 3.6 V, IOL = 5 mA
—
0.5
V
V
• 1.71 V ≤ VBAT ≤ 2.7 V, IOL = 2.5mA
IOL_RTC_WAKEUP Output low current total for
RTC_WAKEUPpins
IIN
Input leakage current, analog and digital
pins
• VSS ≤ VIN ≤ VDD
IOZ_RTC_WAKEUP Hi-Z (off-state) leakage current (per
RTC_WAKEUP pin)
—
—
100
mA
—
0.002
0.5
µA
—
—
0.25
µA
1
RPU
Internal pullup resistors
20
—
50
kΩ
2
RPD
Internal pulldown resistors
20
—
50
kΩ
3
1. Measured at VDD=3.6V
2. Measured at VDD supply voltage = VDD min and Vinput = VSS
Kinetis K65 Sub-Family, Rev. 4, 04/2017
9
NXP Semiconductors
General
3. Measured at VDD supply voltage = VDD min and Vinput = VDD
2.2.4 Power mode transition operating behaviors
All specifications except tPOR, and VLLSx –> RUN recovery times in the following
table assume this clock configuration:
•
•
•
•
•
CPU and system clocks = 100MHz
Bus clock = 50MHz
FlexBus clock = 50 MHz
Flash clock = 25 MHz
MCG mode=FEI
Table 5. Power mode transition operating behaviors
Symbol
tPOR
Description
After a POR event, amount of time from the point VDD
reaches 1.71 V to execution of the first instruction
across the operating temperature range of the chip.
• VLLS0 –> RUN
• VLLS1 –> RUN
• VLLS2 –> RUN
• VLLS3 –> RUN
• LLS2 –> RUN
• LLS3 –> RUN
• VLPS –> RUN
• STOP –> RUN
Min.
Max.
Unit
—
300
µs
—
172
µs
—
172
µs
—
94
µs
—
94
µs
—
5.8
µs
—
5.8
µs
—
5.4
µs
—
5.4
µs
Notes
Table 6. Low power mode peripheral adders — typical value
Symbol
Description
Temperature (°C)
IIREFSTEN4MHz 4 MHz internal reference clock (IRC) adder.
Measured by entering STOP or VLPS mode
with 4 MHz IRC enabled.
Unit
-40
25
50
70
85
105
56
56
56
56
56
56
µA
Table continues on the next page...
10
NXP Semiconductors
Kinetis K65 Sub-Family, Rev. 4, 04/2017
General
Table 6. Low power mode peripheral adders — typical value (continued)
Symbol
Description
Temperature (°C)
Unit
-40
25
50
70
85
105
IIREFSTEN32KH 32 kHz internal reference clock (IRC) adder.
Measured by entering STOP mode with the
z
32 kHz IRC enabled.
52
52
52
52
52
52
µA
IEREFSTEN4MH External 4 MHz crystal clock adder. Measured
by entering STOP or VLPS mode with the
z
crystal enabled.
206
228
237
245
251
258
uA
IEREFSTEN32K External 32 kHz crystal clock adder by means
of the OSC0_CR[EREFSTEN and
Hz
EREFSTEN] bits. Measured by entering all
modes with the crystal enabled.
nA
VLLS1
440
490
540
560
570
580
VLLS3
440
490
540
560
570
580
LLS2
490
490
540
560
570
680
LLS3
490
490
540
560
570
680
VLPS
510
560
560
560
610
680
STOP
510
560
560
560
610
680
48MHz IRC
511
520
545
556
563
576
µA
ICMP
CMP peripheral adder measured by placing
the device in VLLS1 mode with CMP enabled
using the 6-bit DAC and a single external
input for compare. Includes 6-bit DAC power
consumption.
22
22
22
22
22
22
µA
IRTC
RTC peripheral adder measured by placing
the device in VLLS1 mode with external 32
kHz crystal enabled by means of the
RTC_CR[OSCE] bit and the RTC ALARM set
for 1 minute. Includes ERCLK32K (32 kHz
external crystal) power consumption.
432
357
388
475
532
810
nA
IUART
UART peripheral adder measured by placing
the device in STOP or VLPS mode with
selected clock source waiting for RX data at
115200 baud rate. Includes selected clock
source power consumption.
I48MIRC
µA
66
66
66
66
66
66
OSCERCLK (4 MHz external crystal)
214
234
246
254
260
268
IBG
Bandgap adder when BGEN bit is set and
device is placed in VLPx, LLS, or VLLSx
mode.
45
45
45
45
45
45
µA
IADC
ADC peripheral adder combining the
measured values at VDD and VDDA by placing
the device in STOP or VLPS mode. ADC is
configured for low power mode using the
internal clock and continuous conversions.
366
366
366
366
366
366
µA
MCGIRCLK (4 MHz internal reference clock)
Kinetis K65 Sub-Family, Rev. 4, 04/2017
11
NXP Semiconductors
General
2.2.5 Power consumption operating behaviors
NOTE
The maximum values represent characterized results
equivalent to the mean plus three times the standard deviation
(mean + 3 sigma)
Table 7. Power consumption operating behaviors
Symbol
IDDA
IDD_RUN
Description
Analog supply current
Typ.
Max.
Unit
Notes
—
—
See note
mA
1
Run mode current — all peripheral clocks
disabled, code executing from flash
• @ 1.8V
• @ 3.0V
IDD_RUN
Min.
2
—
32.3
71.03
mA
—
32.4
71.81
mA
Run mode current — all peripheral clocks
enabled, code executing from flash
• @ 1.8V
• @ 3.0V
• @ 25°C
• @ 105°C
IDD_RUNC Run mode current in compute operation - 120
MHz core / 24 MHz flash / bus clock disabled,
O
code of while(1) loop executing from flash
3, 4
—
50.5
89.58
mA
—
50.6
55.95
mA
—
69.7
99.85
mA
—
28.5
67.74
mA
5
• at 3.0 V
IDD_HSRUN Run mode current — all peripheral clocks
disabled, code executing from flash
• @ 1.8V
• @ 3.0V
6
—
47.2
91.25
mA
—
47.3
91.62
mA
IDD_HSRUN Run mode current — all peripheral clocks
enabled, code executing from flash
7, 4
—
• @ 1.8V
• @ 3.0V
—
• @ 25°C
—
• @ 105°C
71.4
103.58
mA
71.5
79.13
mA
93.3
115.08
mA
IDD_HSRUN HSRun mode current in compute operation – 168
MHz core/ 28 MHz flash / bus clock disabled,
CO
code of while(1) loop executing from flash at 3.0V
—
42.9
91.97
mA
5
IDD_WAIT Wait mode high frequency current at 3.0 V — all
peripheral clocks disabled
—
16.9
45.2
mA
8
Table continues on the next page...
12
NXP Semiconductors
Kinetis K65 Sub-Family, Rev. 4, 04/2017
General
Table 7. Power consumption operating behaviors (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
IDD_WAIT Wait mode reduced frequency current at 3.0 V —
all peripheral clocks enabled
—
35
62.81
mA
8
IDD_VLPR Very-low-power run mode current at 3.0 V — all
peripheral clocks disabled
—
1.1
9.56
mA
9
IDD_VLPR Very-low-power run mode current at 3.0 V — all
peripheral clocks enabled
—
2
9.88
mA
10
—
986
9.47
μA
IDD_VLPW Very-low-power wait mode current at 3.0 V — all
peripheral clocks disabled
—
0.690
9.25
mA
IDD_VLPW Very-low-power wait mode current at 3.0 V — all
peripheral clocks enabled
—
1.5
10.00
mA
• @ –40 to 25°C
—
0.791
2.39
mA
• @ 70°C
—
3.8
6.91
mA
• @ 105°C
—
13.2
18.91
mA
—
202
353.77
μA
—
1400
2464.54
μA
—
5100
8949.06
μA
—
9.0
16.5
μA
—
76.3
88.63
μA
—
402
656.08
μA
—
5.7
9.7
μA
—
41.3
55.80
—
229
276.81
μA
• @ –40 to 25°C
—
5.5
7.31
μA
• @ 70°C
—
46.3
58.33
μA
• @ 105°C
—
249
380.77
μA
• @ –40 to 25°C
—
2.7
3.24
μA
• @ 70°C
—
13.1
18.72
μA
• @ 105°C
—
76.6
84.77
μA
IDD_VLPRC Very-low-power run mode current in compute
operation - 4 MHz core / 1 MHz flash / bus clock
O
disabled, LPTMR running with 4 MHz internal
reference clock
• at 3.0 V
11
12
IDD_STOP Stop mode current at 3.0 V
IDD_VLPS Very-low-power stop mode current at 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C
IDD_LLS3 Low leakage stop mode current at 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C
IDD_LLS2 Low leakage stop mode current at 3.0 V
• @ –40 to 25°C
μA
• @ 70°C
• @ 105°C
IDD_VLLS3 Very low-leakage stop mode 3 current at 3.0 V
IDD_VLLS2 Very low-leakage stop mode 2 current at 3.0 V
Table continues on the next page...
Kinetis K65 Sub-Family, Rev. 4, 04/2017
13
NXP Semiconductors
General
Table 7. Power consumption operating behaviors (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
• @ –40 to 25°C
—
0.847
1.48
μA
• @ 70°C
—
6.5
11.31
μA
• @ 105°C
—
46.7
81.78
μA
—
0.551
.65
μA
—
6.3
7.12
μA
—
49.6
53.68
μA
—
0.254
0.445
μA
—
6.3
10.99
μA
—
48.7
85.27
μA
• @ –40 to 25°C
—
0.19
0.22
μA
• @ 70°C
—
0.49
0.64
μA
• @ 105°C
—
2.2
3.2
μA
Notes
IDD_VLLS1 Very low-leakage stop mode 1 current at 3.0 V
IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V
with POR detect circuit enabled
• @ –40 to 25°C
• @ 70°C
• @ 105°C
IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V
with POR detect circuit disabled
• @ –40 to 25°C
• @ 70°C
• @ 105°C
IDD_VBAT Average current with RTC and 32kHz disabled at
3.0 V
IDD_VBAT Average current when CPU is not accessing RTC
registers
13
• @ 1.8V
• @ –40 to 25°C
• @ 70°C
• @ 105°C
• @ 3.0V
• @ –40 to 25°C
• @ 70°C
• @ 105°C
—
0.68
0.8
—
1.2
1.56
—
3.6
5.3
μA
μA
μA
—
0.81
0.96
—
1.45
1.89
—
4.3
6.33
μA
μA
μA
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See
each module's specification for its supply current.
2. 120 MHz core and system clock, 60 MHz bus and FlexBus clock, and 24 MHz flash clock. MCG configured for PEE
mode. All peripheral clocks disabled.
3. 120 MHz core and system clock, 60 MHz bus and FlexBus clock, and 24 MHz flash clock. MCG configured for PEE
mode. All peripheral clocks enabled.
4. Max values are measured with CPU executing DSP instructions.
5. MCG configured for PEE mode.
6. 168 MHz core and system clock, 56 MHz bus and FlexBus clock, and 28 MHz flash clock. MCG configured for PEE
mode. All peripheral clocks disabled.
7. 168 MHz core and system clock, 56 MHz bus and FlexBus clock, and 28 MHz flash clock. MCG configured for PEE
mode. All peripheral clocks enabled.
14
NXP Semiconductors
Kinetis K65 Sub-Family, Rev. 4, 04/2017
General
8. 120 MHz core and system clock, 60MHz bus clock, and FlexBus. MCG configured for PEE mode.
9. 4 MHz core, system, FlexBus, and bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral
clocks disabled. Code executing from flash.
10. 4 MHz core, system, FlexBus, and bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral
clocks enabled but peripherals are not in active operation. Code executing from flash.
11. MCG configured for BLPI mode. CoreMark benchmark compiled using IAR 6.40 with optimization level high,
optimized for balanced.
12. 4 MHz core, system, FlexBus, and bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral
clocks disabled.
13. Includes 32kHz oscillator current and RTC operation.
2.2.5.1
Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
•
•
•
•
USB regulator disabled
No GPIOs toggled
Code execution from flash with cache enabled
For the ALLOFF curve, all peripheral clocks are disabled except FTFE
Figure 3. Run mode supply current vs. core frequency
Kinetis K65 Sub-Family, Rev. 4, 04/2017
15
NXP Semiconductors
General
Figure 4. VLPR mode supply current vs. core frequency
2.2.6 EMC radiated emissions operating behaviors
Table 8. EMC radiated emissions operating behaviors
Symbol
Description
Frequency
band
(MHz)
Typ.
Unit
Notes
1, 2
VRE1
Radiated emissions voltage, band 1
0.15–50
23
dBμV
VRE2
Radiated emissions voltage, band 2
50–150
27
dBμV
VRE3
Radiated emissions voltage, band 3
150–500
28
dBμV
VRE4
Radiated emissions voltage, band 4
500–1000
14
dBμV
IEC level
0.15–1000
K
—
VRE_IEC
2, 3
1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150
kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits - Measurement
of Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM Cell and
Wideband TEM Cell Method. Measurements were made while the microcontroller was running basic application code.
16
NXP Semiconductors
Kinetis K65 Sub-Family, Rev. 4, 04/2017
General
The reported emission level is the value of the maximum measured emission, rounded up to the next whole number,
from among the measured orientations in each frequency range.
2. VDD = 3.3 V, TA = 25 °C, fOSC = 12 MHz (crystal), fSYS = MHz, fBUS = MHz
3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and
Wideband TEM Cell Method
2.2.7 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions.
1. Go to nxp.com
2. Perform a keyword search for “EMC design.”
2.2.8 Capacitance attributes
Table 9. Capacitance attributes
Symbol
Description
Min.
Max.
Unit
CIN_A
Input capacitance: analog pins
—
7
pF
CIN_D
Input capacitance: digital pins
—
7
pF
2.3 Switching specifications
2.3.1 Device clock specifications
Table 10. Device clock specifications
Symbol
Description
Min.
Max.
Unit
—
180
MHz
Notes
High Speed run mode
fSYS
System and core clock
Normal run mode (and High Speed run mode unless otherwise specified above)
fSYS
System and core clock
—
120
MHz
System and core clock when Full Speed USB in
operation
20
—
MHz
fSYS_USBHS
System and core clock when High Speed USB in
operation
100
—
MHz
fENET
System and core clock when ethernet in operation
• 10 Mbps
• 100 Mbps
MHz
5
—
50
—
Table continues on the next page...
Kinetis K65 Sub-Family, Rev. 4, 04/2017
17
NXP Semiconductors
General
Table 10. Device clock specifications (continued)
Symbol
Min.
Max.
Unit
Bus clock
—
60
MHz
FlexBus clock
—
60
MHz
fFLASH
Flash clock
—
28
MHz
fLPTMR
LPTMR clock
—
25
MHz
fBUS
FB_CLK
Description
Notes
VLPR mode1
fSYS
System and core clock
—
4
MHz
fBUS
Bus clock
—
4
MHz
FlexBus clock
—
4
MHz
fFLASH
Flash clock
—
1
MHz
fERCLK
External reference clock
—
16
MHz
LPTMR clock
—
25
MHz
FB_CLK
fLPTMR_pin
fFlexCAN_ERCLK FlexCAN external reference clock
—
8
MHz
fI2S_MCLK
I2S master clock
—
12.5
MHz
fI2S_BCLK
I2S bit clock
—
4
MHz
1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for
any other module.
2.3.2 General switching specifications
These general purpose specifications apply to all signals configured for GPIO, UART,
CAN, CMT, IEEE 1588 timer, timers, and I2C signals.
Table 11. General switching specifications
Symbol
Description
Min.
Max.
Unit
Notes
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
1.5
—
Bus clock
cycles
1, 2
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter enabled) — Asynchronous path
100
—
ns
3
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter disabled) — Asynchronous path
50
—
ns
3
External reset pulse width (digital glitch filter disabled)
100
—
ns
3
2
—
Bus clock
cycles
Mode select (EZP_CS) hold time after reset
deassertion
Port rise and fall time (high drive strength)
4
• Slew enabled
—
25
ns
—
15
ns
Table continues on the next page...
18
NXP Semiconductors
Kinetis K65 Sub-Family, Rev. 4, 04/2017
General
Table 11. General switching specifications (continued)
Symbol
Description
Min.
Max.
Unit
—
7
ns
—
7
ns
Notes
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
• Slew disabled
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
Port rise and fall time (low drive strength)
5
• Slew enabled
• 1.71 ≤ VDD ≤ 2.7V
—
25
ns
• 2.7 ≤ VDD ≤ 3.6V
—
15
ns
• 1.71 ≤ VDD ≤ 2.7V
—
7
ns
• 2.7 ≤ VDD ≤ 3.6V
—
7
ns
• Slew disabled
1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses
may or may not be recognized. In Stop, VLPS, LLS, and VLLSx modes, the synchronizer is bypassed so shorter
pulses can be recognized in that case.
2. The greater synchronous and asynchronous timing must be met.
3. This is the minimum pulse width that is guaranteed to be recognized as a pin interrupt request in Stop, VLPS, LLS,
and VLLSx modes.
4. 75 pF load
5. 15 pF load
2.4 Thermal specifications
2.4.1 Thermal operating requirements
Table 12. Thermal operating requirements
Symbol
Description
Min.
Max.
Unit
TJ
Die junction temperature
–40
125
°C
TA
Ambient temperature
–40
105
°C
Notes
1
1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed maximum TJ. The simplest method to
determine TJ is: TJ = TA + RθJA x chip power dissipation.
Kinetis K65 Sub-Family, Rev. 4, 04/2017
19
NXP Semiconductors
Peripheral operating requirements and behaviors
2.4.2 Thermal attributes
Board type
Symbol
Description
169 MAPBGA
Unit
Notes
Single-layer (1s)
RθJA
Thermal
38
resistance,
junction to ambient
(natural
convection)
°C/W
1
Four-layer (2s2p)
RθJA
Thermal
21.9
resistance,
junction to ambient
(natural
convection)
°C/W
1
Single-layer (1s)
RθJMA
Thermal
30
resistance,
junction to ambient
(200 ft./min. air
speed)
°C/W
1
Four-layer (2s2p)
RθJMA
Thermal
18.6
resistance,
junction to ambient
(200 ft./min. air
speed)
°C/W
1
—
RθJB
Thermal
resistance,
junction to board
14.4
°C/W
2
—
RθJC
Thermal
resistance,
junction to case
8.2
°C/W
3
—
ΨJT
Thermal
characterization
parameter,
junction to
package top
outside center
(natural
convection)
0.2
°C/W
4
1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method
Environmental Conditions—Forced Convection (Moving Air).
2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental
Conditions—Junction-to-Board.
3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate
temperature used for the case temperature. The value includes the thermal resistance of the interface material between
the top of the package and the cold plate.
4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air).
3 Peripheral operating requirements and behaviors
20
NXP Semiconductors
Kinetis K65 Sub-Family, Rev. 4, 04/2017
Peripheral operating requirements and behaviors
3.1 Core modules
3.1.1 Debug trace timing specifications
Table 13. Debug trace operating behaviors
Symbol
Description
Min.
Max.
Unit
Tcyc
Clock period
Frequency dependent
MHz
Twl
Low pulse width
2
—
ns
Twh
High pulse width
2
—
ns
Tr
Clock and data rise time
—
3
ns
Tf
Clock and data fall time
—
3
ns
Ts
Data setup
1.5
—
ns
Th
Data hold
1.0
—
ns
TRACECLK
Tr
Tf
Twh
Twl
Tcyc
Figure 5. TRACE_CLKOUT specifications
TRACE_CLKOUT
Ts
Th
Ts
Th
TRACE_D[3:0]
Figure 6. Trace data specifications
3.1.2 JTAG electricals
Table 14. JTAG limited voltage range electricals
Symbol
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
Table continues on the next page...
Kinetis K65 Sub-Family, Rev. 4, 04/2017
21
NXP Semiconductors
Peripheral operating requirements and behaviors
Table 14. JTAG limited voltage range electricals (continued)
Symbol
J1
Description
Min.
Max.
TCLK frequency of operation
Unit
MHz
• Boundary Scan
0
10
• JTAG and CJTAG
0
25
• Serial Wire Debug
0
50
1/J1
—
ns
• Boundary Scan
50
—
ns
• JTAG and CJTAG
20
—
ns
• Serial Wire Debug
10
—
ns
J4
TCLK rise and fall times
—
3
ns
J5
Boundary scan input data setup time to TCLK rise
20
—
ns
J6
Boundary scan input data hold time after TCLK rise
2.0
—
ns
J7
TCLK low to boundary scan output data valid
—
28
ns
J8
TCLK low to boundary scan output high-Z
—
25
ns
J9
TMS, TDI input data setup time to TCLK rise
8
—
ns
J10
TMS, TDI input data hold time after TCLK rise
1
—
ns
J11
TCLK low to TDO data valid
—
19
ns
J12
TCLK low to TDO high-Z
—
17
ns
J13
TRST assert time
100
—
ns
J14
TRST setup time (negation) to TCLK high
8
—
ns
J2
TCLK cycle period
J3
TCLK clock pulse width
Table 15. JTAG full voltage range electricals
Symbol
J1
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
TCLK frequency of operation
MHz
• Boundary Scan
0
10
• JTAG and CJTAG
0
20
• Serial Wire Debug
0
40
1/J1
—
ns
• Boundary Scan
50
—
ns
• JTAG and CJTAG
25
—
ns
• Serial Wire Debug
12.5
—
ns
J2
TCLK cycle period
J3
TCLK clock pulse width
J4
TCLK rise and fall times
—
3
ns
J5
Boundary scan input data setup time to TCLK rise
20
—
ns
Table continues on the next page...
22
NXP Semiconductors
Kinetis K65 Sub-Family, Rev. 4, 04/2017
Peripheral operating requirements and behaviors
Table 15. JTAG full voltage range electricals (continued)
Symbol
Description
Min.
Max.
Unit
J6
Boundary scan input data hold time after TCLK rise
2.0
—
ns
J7
TCLK low to boundary scan output data valid
—
30.6
ns
J8
TCLK low to boundary scan output high-Z
—
25
ns
J9
TMS, TDI input data setup time to TCLK rise
8
—
ns
J10
TMS, TDI input data hold time after TCLK rise
1.0
—
ns
J11
TCLK low to TDO data valid
—
19.0
ns
J12
TCLK low to TDO high-Z
—
17.0
ns
J13
TRST assert time
100
—
ns
J14
TRST setup time (negation) to TCLK high
8
—
ns
J2
J3
J3
TCLK (input)
J4
J4
Figure 7. Test clock input timing
TCLK
J5
Data inputs
J6
Input data valid
J7
Data outputs
Output data valid
J8
Data outputs
J7
Data outputs
Output data valid
Figure 8. Boundary scan (JTAG) timing
Kinetis K65 Sub-Family, Rev. 4, 04/2017
23
NXP Semiconductors
Peripheral operating requirements and behaviors
TCLK
J9
TDI/TMS
J10
Input data valid
J11
TDO
Output data valid
J12
TDO
J11
TDO
Output data valid
Figure 9. Test Access Port timing
TCLK
J14
J13
TRST
Figure 10. TRST timing
3.2 System modules
There are no specifications necessary for the device's system modules.
3.3 Clock modules
24
NXP Semiconductors
Kinetis K65 Sub-Family, Rev. 4, 04/2017
Peripheral operating requirements and behaviors
3.3.1 MCG specifications
Table 16. MCG specifications
Symbol
Description
Min.
Typ.
Max.
Unit
fints_ft
Internal reference frequency (slow clock) —
factory trimmed at nominal VDD and 25 °C
—
32.768
—
kHz
fints_t
Internal reference frequency (slow clock) —
user trimmed
31.25
—
39.0625
kHz
Iints
Internal reference (slow clock) current
Notes
—
20
—
µA
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM and SCFTRIM
—
± 0.3
± 0.6
%fdco
1
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM only
—
± 0.2
± 0.5
%fdco
1
Δfdco_t
Total deviation of trimmed average DCO output
frequency over voltage and temperature
—
± 0.5
±2
%fdco
1
Δfdco_t
Total deviation of trimmed average DCO output
frequency over fixed voltage and temperature
range of 0–70°C
—
± 0.3
1.5
%fdco
1
fintf_ft
Internal reference frequency (fast clock) —
factory trimmed at nominal VDD and 25°C
—
4
—
MHz
fintf_t
Internal reference frequency (fast clock) —
user trimmed at nominal VDD and 25 °C
3
—
5
MHz
Internal reference (fast clock) current
—
25
—
µA
(3/5) x
fints_t
—
—
kHz
(16/5) x
fints_t
—
—
kHz
Iintf
floc_low
Loss of external clock minimum frequency —
RANGE = 00
ext clk freq: above (3/5)fint never reset
ext clk freq: between (2/5)fint and (3/5)fint
maybe reset (phase dependency)
ext clk freq: below (2/5)fint always reset
floc_high
Loss of external clock minimum frequency —
RANGE = 01, 10, or 11
ext clk freq: above (16/5)fint never reset
ext clk freq: between (15/5)fint and (16/5)fint
maybe reset (phase dependency)
ext clk freq: below (15/5)fint always reset
FLL
ffll_ref
FLL reference frequency range
31.25
—
39.0625
kHz
fdco_ut
DCO output
frequency range
— untrimmed
16.0
23.04
26.66
MHz
32.0
46.08
53.32
Low range
2
(DRS=00, DMX32=0)
640 × fints_ut
Mid range
(DRS=01, DMX32=0)
1280 × fints_ut
Table continues on the next page...
Kinetis K65 Sub-Family, Rev. 4, 04/2017
25
NXP Semiconductors
Peripheral operating requirements and behaviors
Table 16. MCG specifications (continued)
Symbol
Description
Mid-high range
Min.
Typ.
Max.
Unit
Notes
48.0
69.12
79.99
64.0
92.16
106.65
18.3
26.35
30.50
36.6
52.70
60.99
54.93
79.09
91.53
73.23
105.44
122.02
20
20.97
25
MHz
3, 4
40
41.94
50
MHz
60
62.91
75
MHz
80
83.89
100
MHz
—
23.99
—
MHz
—
47.97
—
MHz
—
71.99
—
MHz
—
95.98
—
MHz
—
180
—
—
150
—
(DRS=10, DMX32=0)
1920 × fints_ut
High range
(DRS=11, DMX32=0)
2560 × fints_ut
Low range
(DRS=00, DMX32=1)
732 × fints_ut
Mid range
(DRS=01, DMX32=1)
1464 × fints_ut
Mid-high range
(DRS=10, DMX32=1)
2197 × fints_ut
High range
(DRS=11, DMX32=1)
2929 × fints_ut
fdco
DCO output
frequency range
Low range (DRS=00)
640 × ffll_ref
Mid range (DRS=01)
1280 × ffll_ref
Mid-high range (DRS=10)
1920 × ffll_ref
High range (DRS=11)
2560 × ffll_ref
fdco_t_DMX3 DCO output
frequency
2
Low range (DRS=00)
5, 6
732 × ffll_ref
Mid range (DRS=01)
1464 × ffll_ref
Mid-high range (DRS=10)
2197 × ffll_ref
High range (DRS=11)
2929 × ffll_ref
Jcyc_fll
FLL period jitter
• fDCO = 48 MHz
• fDCO = 98 MHz
ps
Table continues on the next page...
26
NXP Semiconductors
Kinetis K65 Sub-Family, Rev. 4, 04/2017
Peripheral operating requirements and behaviors
Table 16. MCG specifications (continued)
Symbol
Description
tfll_acquire
FLL target frequency acquisition time
Min.
Typ.
Max.
Unit
Notes
—
—
1
ms
7
8
—
16
MHz
PLL
fpll_ref
PLL reference frequency range
fvcoclk_2x
VCO output frequency
fvcoclk
PLL output frequency
fvcoclk_90
PLL quadrature output frequency
Ipll
PLL operating current
• VCO @ 184 MHz (fosc_hi_1 = 32 MHz,
fpll_ref = 8 MHz, VDIV multiplier = 23)
Ipll
PLL operating current
• VCO @ 360 MHz (fosc_hi_1 = 32 MHz,
fpll_ref = 8 MHz, VDIV multiplier = 45)
Jcyc_pll
Jacc_pll
Dunl
tpll_lock
180
90
90
—
—
—
360
180
180
MHz
MHz
MHz
—
2.8
—
mA
—
3.6
—
mA
PLL period jitter (RMS)
—
100
—
ps
• fvco = 360 MHz
—
75
—
ps
PLL accumulated jitter over 1µs (RMS)
9
• fvco = 180 MHz
—
600
—
ps
• fvco = 360 MHz
—
300
—
ps
± 4.47
—
± 5.97
Lock detector detection time
8
9
• fvco = 180 MHz
Lock exit frequency tolerance
8
—
—
10-6
150 ×
+ 1075(1/
fpll_ref)
%
s
10
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
mode).
2. This applies when SCTRIM at value (0x80) and SCFTRIM control bit at value (0x0).
3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0.
4. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency
deviation (Δfdco_t) over voltage and temperature should be considered.
5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1.
6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
7. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
8. Excludes any oscillator currents that are also consuming power while PLL is in operation.
9. This specification was obtained using a NXP developed PCB. PLL jitter is dependent on the noise characteristics of
each PCB and results will vary.
10. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL
disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this
specification assumes it is already running.
Kinetis K65 Sub-Family, Rev. 4, 04/2017
27
NXP Semiconductors
Peripheral operating requirements and behaviors
3.3.2 IRC48M specifications
Table 17. IRC48M specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VDD
Supply voltage
1.71
—
3.6
V
IDD48M
Supply current
—
520
—
μA
firc48m
Internal reference frequency
—
48
—
MHz
Δfirc48m_ol_lv Open loop total deviation of IRC48M frequency at
low voltage (VDD=1.71V-1.89V) over full
temperature
• Regulator disable
(USB_CLK_RECOVER_IRC_EN[REG_EN]=0
)
• Regulator enable
(USB_CLK_RECOVER_IRC_EN[REG_EN]=1
)
Δfirc48m_ol_hv Open loop total deviation of IRC48M frequency at
high voltage (VDD=1.89V-3.6V) over 0—70°C
• Regulator enable
(USB_CLK_RECOVER_IRC_EN[REG_EN]=1
)
Δfirc48m_ol_hv Open loop total deviation of IRC48M frequency at
high voltage (VDD=1.89V-3.6V) over full
temperature
• Regulator enable
(USB_CLK_RECOVER_IRC_EN[REG_EN]=1
)
1
—
± 0.4
± 1.0
—
± 0.5
± 1.5
%firc48m
1
—
± 0.2
± 0.5
%firc48m
1
—
± 0.4
± 1.0
%firc48m
Δfirc48m_cl
Closed loop total deviation of IRC48M frequency
over voltage and temperature
—
—
± 0.1
%fhost
Jcyc_irc48m
Period Jitter (RMS)
—
35
150
ps
Startup time
—
2
3
μs
tirc48mst
Notes
2
3
1. The maximum value represents characterized results equivalent to mean plus or minus three times the standard
deviation (mean ± 3 sigma)
2. Closed loop operation of the IRC48M is only feasible for USB device operation; it is not usable for USB host operation. It
is enabled by configuring for USB Device, selecting IRC48M as USB clock source, and enabling the clock recover
function (USB_CLK_RECOVER_IRC_CTRL[CLOCK_RECOVER_EN]=1, USB_CLK_RECOVER_IRC_EN[IRC_EN]=1).
3. IRC48M startup time is defined as the time between clock enablement and clock availability for system use. Enable the
clock by one of the following settings:
• USB_CLK_RECOVER_IRC_EN[IRC_EN]=1, or
• MCG_C7[OSCSEL]=10, or
• SIM_SOPT2[PLLFLLSEL]=11
3.3.3 Oscillator electrical specifications
28
NXP Semiconductors
Kinetis K65 Sub-Family, Rev. 4, 04/2017
Peripheral operating requirements and behaviors
3.3.3.1
Oscillator DC electrical specifications
Table 18. Oscillator DC electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VDD
Supply voltage
1.71
—
3.6
V
IDDOSC
IDDOSC
Supply current — low-power mode (HGO=0)
Notes
1
• 32 kHz
—
600
—
nA
• 4 MHz
—
200
—
μA
• 8 MHz (RANGE=01)
—
300
—
μA
• 16 MHz
—
950
—
μA
• 24 MHz
—
1.2
—
mA
• 32 MHz
—
1.5
—
mA
Supply current — high gain mode (HGO=1)
1
• 32 kHz
—
7.5
—
μA
• 4 MHz
—
500
—
μA
• 8 MHz (RANGE=01)
—
650
—
μA
• 16 MHz
—
2.5
—
mA
• 24 MHz
—
3.25
—
mA
• 32 MHz
—
4
—
mA
Cx
EXTAL load capacitance
—
—
—
2, 3
Cy
XTAL load capacitance
—
—
—
2, 3
RF
Feedback resistor — low-frequency, low-power
mode (HGO=0)
—
—
—
MΩ
Feedback resistor — low-frequency, high-gain
mode (HGO=1)
—
10
—
MΩ
Feedback resistor — high-frequency, lowpower mode (HGO=0)
—
—
—
MΩ
Feedback resistor — high-frequency, high-gain
mode (HGO=1)
—
1
—
MΩ
Series resistor — low-frequency, low-power
mode (HGO=0)
—
—
—
kΩ
Series resistor — low-frequency, high-gain
mode (HGO=1)
—
200
—
kΩ
Series resistor — high-frequency, low-power
mode (HGO=0)
—
—
—
kΩ
—
0
—
kΩ
—
0.6
—
V
RS
2, 4
Series resistor — high-frequency, high-gain
mode (HGO=1)
Vpp5
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, low-power mode
(HGO=0)
Table continues on the next page...
Kinetis K65 Sub-Family, Rev. 4, 04/2017
29
NXP Semiconductors
Peripheral operating requirements and behaviors
Table 18. Oscillator DC electrical specifications (continued)
Symbol
1.
2.
3.
4.
5.
Description
Min.
Typ.
Max.
Unit
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, high-gain mode
(HGO=1)
—
VDD
—
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, low-power mode
(HGO=0)
—
0.6
—
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, high-gain mode
(HGO=1)
—
VDD
—
V
Notes
VDD=3.3 V, Temperature =25 °C, Internal capacitance = 20 pf
See crystal or resonator manufacturer's recommendation
Cx,Cy can be provided by using either the integrated capacitors or by using external components.
When low power mode is selected, RF is integrated and must not be attached externally.
The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to
any other devices.
3.3.3.2
Symbol
Oscillator frequency specifications
Table 19. Oscillator frequency specifications
Description
Min.
Typ.
Max.
Unit
fosc_lo
Oscillator crystal or resonator frequency — lowfrequency mode (MCG_C2[RANGE]=00)
32
—
40
kHz
fosc_hi_1
Oscillator crystal or resonator frequency — highfrequency mode (low range)
(MCG_C2[RANGE]=01)
3
—
8
MHz
fosc_hi_2
Oscillator crystal or resonator frequency — high
frequency mode (high range)
(MCG_C2[RANGE]=1x)
8
—
32
MHz
fec_extal
Input clock frequency (external clock mode)
—
—
50
MHz
tdc_extal
Input clock duty cycle (external clock mode)
40
50
60
%
Crystal startup time — 32 kHz low-frequency,
low-power mode (HGO=0)
—
750
—
ms
Crystal startup time — 32 kHz low-frequency,
high-gain mode (HGO=1)
—
250
—
ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), low-power mode
(HGO=0)
—
0.6
—
ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), high-gain mode
(HGO=1)
—
1
—
ms
tcst
Notes
1, 2
3, 4
1. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL.
2. When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by
FRDIV, it remains within the limits of the DCO input clock frequency.
3. Proper PC board layout procedures must be followed to achieve specifications.
30
NXP Semiconductors
Kinetis K65 Sub-Family, Rev. 4, 04/2017
Peripheral operating requirements and behaviors
4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S
register being set.
NOTE
The 32 kHz oscillator works in low power mode by default
and cannot be moved into high power/gain mode.
3.3.4 32 kHz oscillator electrical characteristics
3.3.4.1
32 kHz oscillator DC electrical specifications
Table 20. 32kHz oscillator DC electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VBAT
Supply voltage
1.71
—
3.6
V
Internal feedback resistor
—
100
—
MΩ
Cpara
Parasitical capacitance of EXTAL32 and
XTAL32
—
5
7
pF
Vpp1
Peak-to-peak amplitude of oscillation
—
0.6
—
V
RF
1. When a crystal is being used with the 32 kHz oscillator, the EXTAL32 and XTAL32 pins should only be connected to
required oscillator components and must not be connected to any other devices.
3.3.4.2
Symbol
32 kHz oscillator frequency specifications
Table 21. 32 kHz oscillator frequency specifications
Min.
Typ.
Max.
Unit
Oscillator crystal
—
32.768
—
kHz
Crystal start-up time
—
1000
—
ms
fec_extal32 Externally provided input clock frequency
—
32.768
—
kHz
2
vec_extal32 Externally provided input clock amplitude
700
—
VBAT
mV
2, 3
fosc_lo
tstart
Description
Notes
1
1. Proper PC board layout procedures must be followed to achieve specifications.
2. This specification is for an externally supplied clock driven to EXTAL32 and does not apply to any other clock input.
The oscillator remains enabled and XTAL32 must be left unconnected.
3. The parameter specified is a peak-to-peak value and VIH and VIL specifications do not apply. The voltage of the
applied clock must be within the range of VSS to VBAT.
3.4 Memories and memory interfaces
Kinetis K65 Sub-Family, Rev. 4, 04/2017
31
NXP Semiconductors
Peripheral operating requirements and behaviors
3.4.1 Flash (FTFE) electrical specifications
This section describes the electrical characteristics of the FTFE module.
3.4.1.1
Flash timing specifications — program and erase
The following specifications represent the amount of time the internal charge pumps are
active and do not include command overhead.
Table 22. NVM program/erase timing specifications
Symbol
Description
Min.
Typ.
Max.
Unit
thvpgm8
thversscr
Notes
Program Phrase high-voltage time
—
7.5
18
μs
Erase Flash Sector high-voltage time
—
13
113
ms
1
thversblk256k Erase Flash Block high-voltage time for 256 KB
—
208
1808
ms
1
thversblk512k Erase Flash Block high-voltage time for 512 KB
—
416
3616
ms
1
Notes
1. Maximum time based on expectations at cycling end-of-life.
3.4.1.2
Symbol
Flash timing specifications — commands
Table 23. Flash command timing specifications
Description
Min.
Typ.
Max.
Unit
Read 1s Block execution time
trd1blk256k
• 256 KB data flash
—
—
1.0
ms
trd1blk512k
• 512 KB program flash
—
—
1.8
ms
trd1sec4k
Read 1s Section execution time (4 KB flash)
—
—
100
μs
1
tpgmchk
Program Check execution time
—
—
95
μs
1
trdrsrc
Read Resource execution time
—
—
40
μs
1
tpgm8
Program Phrase execution time
—
90
150
μs
Erase Flash Block execution time
2
tersblk256k
• 256 KB data flash
—
220
1850
ms
tersblk512k
• 512 KB program flash
—
435
3700
ms
Erase Flash Sector execution time
—
15
115
ms
Program Section execution time (1 KB flash)
—
5
—
ms
tersscr
tpgmsec1k
2
Read 1s All Blocks execution time
trd1allx
• FlexNVM devices
—
—
5.9
ms
trd1alln
• Program flash only devices
—
—
6.7
ms
Read Once execution time
—
—
30
μs
Program Once execution time
—
90
—
μs
Erase All Blocks execution time
—
1750
14,800
ms
trdonce
tpgmonce
tersall
1
2
Table continues on the next page...
32
NXP Semiconductors
Kinetis K65 Sub-Family, Rev. 4, 04/2017
Peripheral operating requirements and behaviors
Table 23. Flash command timing specifications (continued)
Symbol
tvfykey
Description
Verify Backdoor Access Key execution time
Min.
Typ.
Max.
Unit
Notes
—
—
30
μs
1
Swap Control execution time
tswapx01
• control code 0x01
—
200
—
μs
tswapx02
• control code 0x02
—
90
150
μs
tswapx04
• control code 0x04
—
90
150
μs
tswapx08
• control code 0x08
—
—
30
μs
tswapx10
• control code 0x10
—
90
150
μs
Program Partition for EEPROM execution time
tpgmpart32k
• 32 KB EEPROM backup
—
70
—
ms
tpgmpart256k
• 256 KB EEPROM backup
—
78
—
ms
• Control Code 0xFF
—
70
—
μs
tsetram32k
• 32 KB EEPROM backup
—
0.8
1.2
ms
tsetram64k
• 64 KB EEPROM backup
—
1.3
1.9
ms
tsetram128k
• 128 KB EEPROM backup
—
2.4
3.1
ms
tsetram256k
• 256 KB EEPROM backup
—
4.5
5.5
ms
Set FlexRAM Function execution time:
tsetramff
Byte-write to FlexRAM execution time:
teewr8b32k
• 32 KB EEPROM backup
—
385
1700
μs
teewr8b64k
• 64 KB EEPROM backup
—
475
2000
μs
teewr8b128k
• 128 KB EEPROM backup
—
650
2350
μs
teewr8b256k
• 256 KB EEPROM backup
—
1000
3250
μs
16-bit write to FlexRAM execution time:
teewr16b32k
• 32 KB EEPROM backup
—
385
1700
μs
teewr16b64k
• 64 KB EEPROM backup
—
475
2000
μs
teewr16b128k
• 128 KB EEPROM backup
—
650
2350
μs
teewr16b256k
• 256 KB EEPROM backup
—
1000
3250
μs
—
360
1500
μs
teewr32bers 32-bit write to erased FlexRAM location
execution time
32-bit write to FlexRAM execution time:
teewr32b32k
• 32 KB EEPROM backup
—
630
2000
μs
teewr32b64k
• 64 KB EEPROM backup
—
810
2250
μs
teewr32b128k
• 128 KB EEPROM backup
—
1200
2650
μs
teewr32b256k
• 256 KB EEPROM backup
—
1900
3500
μs
1. Assumes 25MHz or greater flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
Kinetis K65 Sub-Family, Rev. 4, 04/2017
33
NXP Semiconductors
Peripheral operating requirements and behaviors
3.4.1.3
Flash high voltage current behaviors
Table 24. Flash high voltage current behaviors
Symbol
Description
IDD_PGM
IDD_ERS
3.4.1.4
Symbol
Min.
Typ.
Max.
Unit
Average current adder during high voltage flash
programming operation
—
3.5
7.5
mA
Average current adder during high voltage flash
erase operation
—
1.5
4.0
mA
Reliability specifications
Table 25. NVM reliability specifications
Description
Min.
Typ.1
Max.
Unit
Notes
Program Flash
tnvmretp10k Data retention after up to 10 K cycles
5
50
—
years
tnvmretp1k
Data retention after up to 1 K cycles
20
100
—
years
nnvmcycp
Cycling endurance
10 K
50 K
—
cycles
tnvmretd10k Data retention after up to 10 K cycles
5
50
—
years
tnvmretd1k
Data retention after up to 1 K cycles
20
100
—
years
nnvmcycd
Cycling endurance
10 K
50 K
—
cycles
2
Data Flash
2
FlexRAM as EEPROM
tnvmretee100 Data retention up to 100% of write endurance
5
50
—
years
tnvmretee10 Data retention up to 10% of write endurance
20
100
—
years
20 K
50 K
—
cycles
nnvmcycee
Cycling endurance for EEPROM backup
Write endurance
2
3
nnvmwree16
• EEPROM backup to FlexRAM ratio = 16
140 K
400 K
—
writes
nnvmwree128
• EEPROM backup to FlexRAM ratio = 128
1.26 M
3.2 M
—
writes
nnvmwree512
• EEPROM backup to FlexRAM ratio = 512
5M
12.8 M
—
writes
nnvmwree2k
• EEPROM backup to FlexRAM ratio = 2,048
20 M
50 M
—
writes
nnvmwree8k
• EEPROM backup to FlexRAM ratio = 8,192
80 M
200 M
—
writes
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a
constant 25°C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in
Engineering Bulletin EB619.
2. Cycling endurance represents number of program/erase cycles at -40°C ≤ Tj ≤ 125°C.
3. Write endurance represents the number of writes to each FlexRAM location at -40°C ≤Tj ≤ 125°C influenced by the
cycling endurance of the FlexNVM and the allocated EEPROM backup per subsystem. Minimum and typical values
assume all 16-bit or 32-bit writes to FlexRAM; all 8-bit writes result in 50% less endurance.
34
NXP Semiconductors
Kinetis K65 Sub-Family, Rev. 4, 04/2017
Peripheral operating requirements and behaviors
3.4.1.5
Write endurance to FlexRAM for EEPROM
When the FlexNVM partition code is not set to full data flash, the EEPROM data set
size can be set to any of several non-zero values.
The bytes not assigned to data flash via the FlexNVM partition code are used by the
FTFE to obtain an effective endurance increase for the EEPROM data. The built-in
EEPROM record management system raises the number of program/erase cycles that
can be attained prior to device wear-out by cycling the EEPROM data through a larger
EEPROM NVM storage space.
While different partitions of the FlexNVM are available, the intention is that a single
choice for the FlexNVM partition code and EEPROM data set size is used throughout
the entire lifetime of a given application. The EEPROM endurance equation and graph
shown below assume that only one configuration is ever used.
Writes_subsystem =
EEPROM – 2 × EEESPLIT × EEESIZE
EEESPLIT × EEESIZE
× Write_efficiency × n nvmcycee
where
• Writes_subsystem — minimum number of writes to each FlexRAM location for
subsystem (each subsystem can have different endurance)
• EEPROM — allocated FlexNVM for each EEPROM subsystem based on
DEPART; entered with the Program Partition command
• EEESPLIT — FlexRAM split factor for subsystem; entered with the Program
Partition command
• EEESIZE — allocated FlexRAM based on DEPART; entered with the Program
Partition command
• Write_efficiency —
• 0.25 for 8-bit writes to FlexRAM
• 0.50 for 16-bit or 32-bit writes to FlexRAM
• nnvmcycee — EEPROM-backup cycling endurance
Kinetis K65 Sub-Family, Rev. 4, 04/2017
35
NXP Semiconductors
Average Writes per FlexRAM Location
Peripheral operating requirements and behaviors
16/32-bit
8-bit
Ratio of EEPROM Backup to FlexRAM
Figure 11. EEPROM backup writes to FlexRAM
3.4.2 EzPort switching specifications
Table 26. EzPort full voltage range switching specifications
Num
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
EP1
EZP_CK frequency of operation (all commands except
READ)
—
fSYS/2
MHz
EP1a
EZP_CK frequency of operation (READ command)
—
fSYS/8
MHz
EP2
EZP_CS negation to next EZP_CS assertion
2 x tEZP_CK
—
ns
EP3
EZP_CS input valid to EZP_CK high (setup)
5
—
ns
EP4
EZP_CK high to EZP_CS input invalid (hold)
5
—
ns
EP5
EZP_D input valid to EZP_CK high (setup)
2
—
ns
EP6
EZP_CK high to EZP_D input invalid (hold)
5
—
ns
EP7
EZP_CK low to EZP_Q output valid
—
14
ns
EP8
EZP_CK low to EZP_Q output invalid (hold)
0
—
ns
EP9
EZP_CS negation to EZP_Q tri-state
—
12
ns
36
NXP Semiconductors
Kinetis K65 Sub-Family, Rev. 4, 04/2017
Peripheral operating requirements and behaviors
EZP_CK
EP3
EP2
EP4
EZP_CS
EP9
EP7
EP8
EZP_Q (output)
EP5
EP6
EZP_D (input)
Figure 12. EzPort Timing Diagram
3.4.3 Flexbus switching specifications
All processor bus timings are synchronous; input setup/hold and output delay are
given in respect to the rising edge of a reference clock, FB_CLK. The FB_CLK
frequency may be the same as the internal system bus frequency or an integer divider
of that frequency.
The following timing numbers indicate when data is latched or driven onto the
external bus, relative to the Flexbus output clock (FB_CLK). All other timing
relationships can be derived from these values.
Table 27. Flexbus limited voltage range switching specifications
Num
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
Frequency of operation
—
FB_CLK
MHz
1/FB_CLK
—
ns
FB1
Clock period
FB2
Address, data, and control output valid
—
11.8
ns
FB3
Address, data, and control output hold
1.0
—
ns
FB4
Data and FB_TA input setup
11.9
—
ns
FB5
Data and FB_TA input hold
0.0
—
ns
Notes
1
2
1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0],
FB_ALE, and FB_TS.
Kinetis K65 Sub-Family, Rev. 4, 04/2017
37
NXP Semiconductors
Peripheral operating requirements and behaviors
2. Specification is valid for all FB_AD[31:0] and FB_TA.
Table 28. Flexbus full voltage range switching specifications
Num
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
—
FB_CLK
MHz
1/FB_CLK
—
ns
Frequency of operation
FB1
Clock period
FB2
Address, data, and control output valid
—
12.6
ns
FB3
Address, data, and control output hold
1.0
—
ns
FB4
Data and FB_TA input setup
12.5
—
ns
FB5
Data and FB_TA input hold
0
—
ns
Notes
1
2
1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE,
and FB_TS.
2. Specification is valid for all FB_AD[31:0] and FB_TA.
38
NXP Semiconductors
Kinetis K65 Sub-Family, Rev. 4, 04/2017
Peripheral operating requirements and behaviors
Read Timing Parameters
S0
S1
S2
S3
S0
FB1
FB_CLK
FB5
FB_A[Y]
Address
FB4
FB2
FB_D[X]
FB3
Address
Data
FB_RW
FB_TS
FB_ALE
AA=1
FB_CSn
AA=0
FB_OEn
electricals_read.svg
FB4
FB_BEn
FB5
AA=1
FB_TA
AA=0
FB_TSIZ[1:0]
TSIZ
S0
S1
S2
S3
S0
Figure 13. FlexBus read timing diagram
Kinetis K65 Sub-Family, Rev. 4, 04/2017
39
NXP Semiconductors
Peripheral operating requirements and behaviors
Write Timing Parameters
FB1
FB_CLK
FB2
FB3
FB_A[Y]
FB_D[X]
Address
Address
Data
FB_RW
FB_TS
FB_ALE
AA=1
FB_CSn
AA=0
FB_OEn
FB_BEn
electricals_write.svg
FB4
FB5
AA=1
FB_TA
FB_TSIZ[1:0]
AA=0
TSIZ
Figure 14. FlexBus write timing diagram
3.4.4 SDRAM controller specifications
Following figure shows SDRAM read cycle.
40
NXP Semiconductors
Kinetis K65 Sub-Family, Rev. 4, 04/2017
Peripheral operating requirements and behaviors
0
1
D0
2
3
4
5
6
7
8
9
10
11
12
13
CLKOUT
D3
D1
Row
A[23:0]
Column
D4
SRAS
D2
SCAS 1
D4
DRAMW
D5
D[31:0]
D6
SDRAM_CS[1:0]
D4
BS[3:0]
ACTV
1DACR[CASL]
NOP
READ
NOP
PRE
=2
Figure 15. SDRAM read timing diagram
Table 29. SDRAM Timing (Full voltage range)
NUM
Characteristic 1
Symbol
MIn
Max
Operating voltage
1.71
3.6
V
Frequency of operation
Unit
—
CLKOUT
MHz
1/CLKOUT
—
ns
2
CLKOUT high to SDRAM address valid
tCHDAV
-
11.2
ns
D2
CLKOUT high to SDRAM control valid
tCHDCV
11.1
ns
D3
CLKOUT high to SDRAM address invalid
tCHDAI
1.0
-
ns
D4
CLKOUT high to SDRAM control invalid
tCHDCI
1.0
-
ns
D5
SDRAM data valid to CLKOUT high
tDDVCH
12.0
-
ns
D6
CLKOUT high to SDRAM data invalid
tCHDDI
1.0
-
ns
D73
CLKOUT high to SDRAM data valid
tCHDDVW
-
12.0
ns
D83
CLKOUT high to SDRAM data invalid
tCHDDIW
1.0
-
ns
D0
Clock period
D1
1. All timing specifications are based on taking into account, a 25pF load on the SDRAM output pins.
2. CLKOUT is same as FB_CLK, maximum frequency can be 60 MHz
Kinetis K65 Sub-Family, Rev. 4, 04/2017
41
NXP Semiconductors
Peripheral operating requirements and behaviors
3. D7 and D8 are for write cycles only.
Table 30. SDRAM Timing (Limited voltage range)
NUM
Characteristic 1
Symbol
MIn
Max
Operating voltage
2.7
3.6
V
Frequency of operation
—
CLKOUT
MHz
1/CLKOUT
—
ns
2
-
11.1
ns
11.1
ns
Unit
D0
Clock period
D1
CLKOUT high to SDRAM address valid
tCHDAV
D2
CLKOUT high to SDRAM control valid
tCHDCV
D3
CLKOUT high to SDRAM address invalid
tCHDAI
1.0
-
ns
D4
CLKOUT high to SDRAM control invalid
tCHDCI
1.0
-
ns
D5
SDRAM data valid to CLKOUT high
tDDVCH
11.3
-
ns
D6
CLKOUT high to SDRAM data invalid
tCHDDI
1.0
-
ns
D73
CLKOUT high to SDRAM data valid
tCHDDVW
-
11.1
ns
D83
CLKOUT high to SDRAM data invalid
tCHDDIW
1.0
-
ns
1. All timing specifications are based on taking into account, a 25pF load on the SDRAM output pins.
2. CLKOUT is same as FB_CLK, maximum frequency can be 60 MHz
3. D7 and D8 are for write cycles only.
Following figure shows an SDRAM write cycle.
42
NXP Semiconductors
Kinetis K65 Sub-Family, Rev. 4, 04/2017
Peripheral operating requirements and behaviors
0
D0
1
2
3
4
5
6
7
8
9
10
11
12
CLKOUT
D3
D1
Row
A[23:0]
Column
SRAS
D2
SCAS1
D4
DRAMW
D7
D[31:0]
D8
SDRAM_CS[1:0]
D2
D4
D4
BS[3:0]
D4
ACTV
1
NOP
WRITE
NOP
PALL
DACR[CASL] = 2
Figure 16. SDRAM read timing diagram
3.5 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
3.6 Analog
3.6.1 ADC electrical specifications
The 16-bit accuracy specifications listed in Table 31 and Table 32 are achievable on
the differential pins ADCx_DP0, ADCx_DM0.
Kinetis K65 Sub-Family, Rev. 4, 04/2017
43
NXP Semiconductors
Peripheral operating requirements and behaviors
All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy
specifications.
3.6.1.1
16-bit ADC operating conditions
Table 31. 16-bit ADC operating conditions
Symbol
Description
Conditions
Min.
Typ.1
Max.
Unit
Notes
VDDA
Supply voltage
Absolute
1.71
—
3.6
V
—
ΔVDDA
Supply voltage
Delta to VDD (VDD – VDDA)
-100
0
+100
mV
2
ΔVSSA
Ground voltage
Delta to VSS (VSS – VSSA)
-100
0
+100
mV
2
VREFH
ADC reference
voltage high
1.13
VDDA
VDDA
V
VREFL
ADC reference
voltage low
VSSA
VSSA
VSSA
V
VADIN
Input voltage
• 16-bit differential mode
VREFL
—
31/32 *
VREFH
V
—
• All other modes
VREFL
—
• 16-bit mode
—
8
10
pF
—
• 8-bit / 10-bit / 12-bit
modes
—
4
5
—
2
5
kΩ
—
—
—
5
kΩ
3
CADIN
RADIN
RAS
Input
capacitance
Input series
resistance
VREFH
Analog source
resistance
(external)
13-bit / 12-bit modes
fADCK
ADC conversion
clock frequency
≤ 13-bit mode
1.0
—
24
MHz
4
fADCK
ADC conversion
clock frequency
16-bit mode
2.0
—
12.0
MHz
4
Crate
ADC conversion
rate
≤ 13-bit modes
20.000
—
1200
kS/s
37.037
—
461.467
kS/s
fADCK < 4 MHz
5
No ADC hardware averaging
Continuous conversions
enabled, subsequent
conversion time
Crate
ADC conversion
rate
16-bit mode
5
No ADC hardware averaging
Continuous conversions
enabled, subsequent
conversion time
1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for
reference only, and are not tested in production.
2. DC potential difference.
3. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as
possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The
RAS/CAS time constant should be kept to < 1 ns.
44
NXP Semiconductors
Kinetis K65 Sub-Family, Rev. 4, 04/2017
Peripheral operating requirements and behaviors
4. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.
5. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
ZADIN
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
leakage
ZAS
RAS
ADC SAR
ENGINE
RADIN
VADIN
CAS
VAS
RADIN
INPUT PIN
RADIN
INPUT PIN
RADIN
INPUT PIN
CADIN
Figure 17. ADC input impedance equivalency diagram
3.6.1.2
16-bit ADC electrical characteristics
Table 32. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA)
Symbol Description
Conditions1
Min.
Typ.2
Max.
Unit
Notes
0.215
—
1.7
mA
3
• ADLPC = 1, ADHSC = 0
1.2
2.4
3.9
MHz
• ADLPC = 1, ADHSC = 1
2.4
4.0
6.1
MHz
tADACK = 1/
fADACK
• ADLPC = 0, ADHSC = 0
3.0
5.2
7.3
MHz
• ADLPC = 0, ADHSC = 1
4.4
6.2
9.5
MHz
LSB4
5
LSB4
5
IDDA_ADC Supply current
ADC asynchronous
clock source
fADACK
Sample Time
TUE
DNL
See Reference Manual chapter for sample times
Total unadjusted
error
• 12-bit modes
—
±4
±6.8
• <12-bit modes
—
±1.4
±2.1
Differential nonlinearity
• 12-bit modes
—
±0.7
–1.1 to
+1.9
• <12-bit modes
—
±0.2
–0.3 to
0.5
Table continues on the next page...
Kinetis K65 Sub-Family, Rev. 4, 04/2017
45
NXP Semiconductors
Peripheral operating requirements and behaviors
Table 32. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol Description
INL
Integral non-linearity
EFS
Full-scale error
EQ
Quantization error
ENOB
Effective number of
bits
Conditions1
Min.
Typ.2
Max.
Unit
Notes
–2.7 to
+1.9
LSB4
5
LSB4
VADIN = VDDA5
• 12-bit modes
—
±1.0
• <12-bit modes
—
±0.5
• 12-bit modes
—
–4
–5.4
• <12-bit modes
—
–1.4
–1.8
• 16-bit modes
—
–1 to 0
—
• ≤13-bit modes
—
—
±0.5
–0.7 to
+0.5
LSB4
16-bit differential mode
6
• Avg = 32
12.8
14.5
• Avg = 4
11.9
13.8
—
—
bits
bits
16-bit single-ended mode
• Avg = 32
• Avg = 4
SINAD
THD
Signal-to-noise plus See ENOB
distortion
Total harmonic
distortion
12.2
13.9
11.4
13.1
—
—
6.02 × ENOB + 1.76
16-bit differential mode
• Avg = 32
bits
bits
dB
dB
—
-94
7
—
dB
16-bit single-ended mode
• Avg = 32
SFDR
Spurious free
dynamic range
—
-85
82
95
—
16-bit differential mode
• Avg = 32
16-bit single-ended mode
78
—
dB
—
dB
7
90
• Avg = 32
EIL
Input leakage error
IIn × RAS
mV
IIn = leakage
current
(refer to the
MCU's
voltage and
current
operating
ratings)
Temp sensor slope
VTEMP25 Temp sensor
voltage
Across the full temperature
range of the device
1.55
1.62
1.69
mV/°C
8
25 °C
706
716
726
mV
8
1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA
46
NXP Semiconductors
Kinetis K65 Sub-Family, Rev. 4, 04/2017
Peripheral operating requirements and behaviors
2. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low
power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with
1 MHz ADC conversion clock speed.
4. 1 LSB = (VREFH - VREFL)/2N
5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11)
6. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz.
7. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz.
8. ADC conversion clock < 3 MHz
Typical ADC 16-bit Differential ENOB vs ADC Clock
100Hz, 90% FS Sine Input
15.00
14.70
14.40
14.10
ENOB
13.80
13.50
13.20
12.90
12.60
Hardware Averaging Disabled
Averaging of 4 samples
Averaging of 8 samples
Averaging of 32 samples
12.30
12.00
1
2
3
4
5
6
7
8
9
10
11
12
ADC Clock Frequency (MHz)
Figure 18. Typical ENOB vs. ADC_CLK for 16-bit differential mode
Typical ADC 16-bit Single-Ended ENOB vs ADC Clock
100Hz, 90% FS Sine Input
14.00
13.75
13.50
13.25
13.00
ENOB
12.75
12.50
12.25
12.00
11.75
11.50
11.25
11.00
Averaging of 4 samples
Averaging of 32 samples
1
2
3
4
5
6
7
8
9
10
11
12
ADC Clock Frequency (MHz)
Figure 19. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode
Kinetis K65 Sub-Family, Rev. 4, 04/2017
47
NXP Semiconductors
Peripheral operating requirements and behaviors
3.6.2 CMP and 6-bit DAC electrical specifications
Table 33. Comparator and 6-bit DAC electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VDD
Supply voltage
1.71
—
3.6
V
IDDHS
Supply current, High-speed mode (EN=1, PMODE=1)
—
—
200
μA
IDDLS
Supply current, low-speed mode (EN=1, PMODE=0)
—
—
20
μA
VAIN
Analog input voltage
VSS – 0.3
—
VDD
V
VAIO
Analog input offset voltage
—
—
20
mV
• CR0[HYSTCTR] = 00
—
5
—
mV
• CR0[HYSTCTR] = 01
—
10
—
mV
• CR0[HYSTCTR] = 10
—
20
—
mV
• CR0[HYSTCTR] = 11
—
30
—
mV
VH
Analog comparator
hysteresis1
VCMPOh
Output high
VDD – 0.5
—
—
V
VCMPOl
Output low
—
—
0.5
V
tDHS
Propagation delay, high-speed mode (EN=1, PMODE=1)
20
50
200
ns
tDLS
Propagation delay, low-speed mode (EN=1, PMODE=0)
80
250
600
ns
—
—
40
μs
—
7
—
μA
Analog comparator initialization
IDAC6b
delay2
6-bit DAC current adder (enabled)
INL
6-bit DAC integral non-linearity
–0.5
—
0.5
LSB3
DNL
6-bit DAC differential non-linearity
–0.3
—
0.3
LSB
1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD–0.6 V.
2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to
CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and
CMP_MUXCR[MSEL]) and the comparator output settling to a stable level.
3. 1 LSB = Vreference/64
48
NXP Semiconductors
Kinetis K65 Sub-Family, Rev. 4, 04/2017
Peripheral operating requirements and behaviors
0.08
0.07
CMP Hystereris (V)
0.06
HYSTCTR
Setting
0.05
00
0.04
01
10
11
0.03
0.02
0.01
0
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vin level (V)
Figure 20. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)
Kinetis K65 Sub-Family, Rev. 4, 04/2017
49
NXP Semiconductors
Peripheral operating requirements and behaviors
0.18
0.16
0.14
CMP Hysteresis (V)
0.12
HYSTCTR
Setting
0.1
00
01
10
11
0.08
0.06
0.04
0.02
0
0.1
0.4
0.7
1
1.3
1.6
1.9
Vin level (V)
2.2
2.5
2.8
3.1
Figure 21. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1)
3.6.3 12-bit DAC electrical characteristics
3.6.3.1
Symbol
12-bit DAC operating requirements
Table 34. 12-bit DAC operating requirements
Desciption
VDDA
Supply voltage
VDACR
Reference voltage
Min.
Max.
Unit
Notes
3.6
V
1.13
3.6
V
1
2
CL
Output load capacitance
—
100
pF
IL
Output load current
—
1
mA
1. The DAC reference can be selected to be VDDA or VREFH.
2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC.
50
NXP Semiconductors
Kinetis K65 Sub-Family, Rev. 4, 04/2017
Peripheral operating requirements and behaviors
3.6.3.2
Symbol
12-bit DAC operating behaviors
Table 35. 12-bit DAC operating behaviors
Description
IDDA_DACL Supply current — low-power mode
Min.
Typ.
Max.
Unit
—
—
150
μA
—
—
700
μA
Notes
P
IDDA_DACH Supply current — high-speed mode
P
tDACLP
Full-scale settling time (0x080 to 0xF7F) —
low-power mode
—
100
200
μs
1
tDACHP
Full-scale settling time (0x080 to 0xF7F) —
high-power mode
—
15
30
μs
1
—
0.7
1
μs
1
tCCDACLP Code-to-code settling time (0xBF8 to
0xC08) — low-power mode and highspeed mode
Vdacoutl
DAC output voltage range low — highspeed mode, no load, DAC set to 0x000
—
—
100
mV
Vdacouth
DAC output voltage range high — highspeed mode, no load, DAC set to 0xFFF
VDACR
−100
—
VDACR
mV
INL
Integral non-linearity error — high speed
mode
—
—
±8
LSB
2
DNL
Differential non-linearity error — VDACR > 2
V
—
—
±1
LSB
3
DNL
Differential non-linearity error — VDACR =
VREF_OUT
—
—
±1
LSB
4
—
±0.4
±0.8
%FSR
5
Gain error
—
±0.1
±0.6
%FSR
5
Power supply rejection ratio, VDDA ≥ 2.4 V
60
—
90
dB
TCO
Temperature coefficient offset voltage
—
3.7
—
μV/C
TGE
Temperature coefficient gain error
—
0.000421
—
%FSR/C
AC
Offset aging coefficient
—
—
100
μV/yr
Rop
Output resistance (load = 3 kΩ)
—
—
250
Ω
SR
Slew rate -80h→ F7Fh→ 80h
VOFFSET Offset error
EG
PSRR
1.
2.
3.
4.
5.
V/μs
• High power (SPHP)
1.2
1.7
—
• Low power (SPLP)
0.05
0.12
—
—
—
-80
CT
Channel to channel cross talk
BW
3dB bandwidth
6
dB
kHz
• High power (SPHP)
550
—
—
• Low power (SPLP)
40
—
—
Settling within ±1 LSB
The INL is measured for 0 + 100 mV to VDACR −100 mV
The DNL is measured for 0 + 100 mV to VDACR −100 mV
The DNL is measured for 0 + 100 mV to VDACR −100 mV with VDDA > 2.4 V
Calculated by a best fit curve from VSS + 100 mV to VDACR − 100 mV
Kinetis K65 Sub-Family, Rev. 4, 04/2017
51
NXP Semiconductors
Peripheral operating requirements and behaviors
6. VDDA = 3.0 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC set
to 0x800, temperature range is across the full range of the device
8
6
4
DAC12 INL (LSB)
2
0
-2
-4
-6
-8
0
500
1000
1500
2000
2500
3000
3500
4000
Digital Code
Figure 22. Typical INL error vs. digital code
52
NXP Semiconductors
Kinetis K65 Sub-Family, Rev. 4, 04/2017
Peripheral operating requirements and behaviors
1.499
DAC12 Mid Level Code Voltage
1.4985
1.498
1.4975
1.497
1.4965
1.496
25
-40
55
85
105
125
Temperature °C
Figure 23. Offset at half scale vs. temperature
3.6.4 Voltage reference electrical specifications
Table 36. VREF full-range operating requirements
Symbol
Description
VDDA
Supply voltage
TA
Temperature
CL
Output load capacitance
Min.
Max.
Unit
3.6
V
Operating temperature
range of the device
°C
100
nF
Notes
1, 2
1. CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external
reference.
2. The load capacitance should not exceed +/-25% of the nominal specified CL value over the operating temperature
range of the device.
Kinetis K65 Sub-Family, Rev. 4, 04/2017
53
NXP Semiconductors
Peripheral operating requirements and behaviors
Table 37. VREF full-range operating behaviors
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
Vout
Voltage reference output with factory trim at
nominal VDDA and temperature=25C
1.190
1.195
1.200
V
1
Vout
Voltage reference output — factory trim
1.1584
—
1.2376
V
1
Vout
Voltage reference output — user trim
1.193
—
1.197
V
1
Vstep
Voltage reference trim step
—
0.5
—
mV
1
Vtdrift
Temperature drift (Vmax -Vmin across the full
temperature range)
—
—
80
mV
1
Ac
Aging coefficient
—
—
400
uV/yr
—
Ibg
Bandgap only current
—
—
80
µA
1
µV
1, 2
ΔVLOAD
Load regulation
• current = ± 1.0 mA
Tstup
Buffer startup time
Tchop_osc_st Internal bandgap start-up delay with chop
oscillator enabled
up
Vvdrift
Voltage drift (Vmax -Vmin across the full voltage
range)
—
200
—
—
—
100
µs
—
—
35
ms
—
—
2
—
mV
1
1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register.
2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load
Table 38. VREF limited-range operating requirements
Symbol
Description
Min.
Max.
Unit
TA
Temperature
0
50
°C
Notes
Table 39. VREF limited-range operating behaviors
Symbol
Vout
Description
Voltage reference output with factory trim
Min.
Max.
Unit
1.173
1.225
V
Notes
3.7 Timers
See General switching specifications.
3.8 Communication interfaces
54
NXP Semiconductors
Kinetis K65 Sub-Family, Rev. 4, 04/2017
Peripheral operating requirements and behaviors
3.8.1 Ethernet switching specifications
The following timing specs are defined at the chip I/O pin and must be translated
appropriately to arrive at timing specs/constraints for the physical interface.
3.8.1.1
MII signal switching specifications
The following timing specs meet the requirements for MII style interfaces for a range
of transceiver devices.
Table 40. MII signal switching specifications (limited voltage range)
Symbol
Description
Min.
Max.
Unit
—
Operating Voltage
2.7
3.6
V
—
RXCLK frequency
—
25
MHz
35%
65%
RXCLK
MII1
RXCLK pulse width high
period
MII2
RXCLK pulse width low
35%
65%
RXCLK
period
MII3
RXD[3:0], RXDV, RXER to RXCLK setup
5
—
ns
MII4
RXCLK to RXD[3:0], RXDV, RXER hold
5
—
ns
—
25
MHz
MII5
—
TXCLK frequency
TXCLK pulse width high
35%
65%
TXCLK
MII6
TXCLK pulse width low
35%
65%
TXCLK
MII7
TXCLK to TXD[3:0], TXEN, TXER invalid
2
—
ns
MII8
TXCLK to TXD[3:0], TXEN, TXER valid
—
25
ns
period
period
Table 41. MII signal switching specifications (full voltage range)
Symbol
Description
Min.
Max.
Unit
—
Operating Voltage
1.7
3.6
V
—
RXCLK frequency
—
25
MHz
35%
65%
RXCLK
MII1
RXCLK pulse width high
period
MII2
RXCLK pulse width low
MII3
RXD[3:0], RXDV, RXER to RXCLK setup
35%
65%
5
—
RXCLK
period
ns
Table continues on the next page...
Kinetis K65 Sub-Family, Rev. 4, 04/2017
55
NXP Semiconductors
Peripheral operating requirements and behaviors
Table 41. MII signal switching specifications (full voltage range)
(continued)
Symbol
MII4
—
MII5
Description
Min.
Max.
Unit
RXCLK to RXD[3:0], RXDV, RXER hold
5
—
ns
TXCLK frequency
—
25
MHz
35%
65%
TXCLK
TXCLK pulse width high
period
MII6
TXCLK pulse width low
35%
65%
TXCLK
period
MII7
TXCLK to TXD[3:0], TXEN, TXER invalid
2
—
ns
MII8
TXCLK to TXD[3:0], TXEN, TXER valid
—
25
ns
MII6
MII5
TXCLK (input)
MII8
MII7
TXD[n:0]
Valid data
TXEN
Valid data
TXER
Valid data
Figure 24. RMII/MII transmit signal timing diagram
MII2
MII1
MII3
MII4
RXCLK (input)
RXD[n:0]
Valid data
RXDV
Valid data
RXER
Valid data
Figure 25. RMII/MII receive signal timing diagram
56
NXP Semiconductors
Kinetis K65 Sub-Family, Rev. 4, 04/2017
Peripheral operating requirements and behaviors
3.8.1.2
RMII signal switching specifications
The following timing specs meet the requirements for RMII style interfaces for a
range of transceiver devices.
Table 42. RMII signal switching specifications (limited voltage range)
Num
Description
Min.
Max.
Unit
—
Operating Voltage
2.7
3.6
—
EXTAL frequency (RMII input clock RMII_CLK)
—
50
MHz
RMII1
RMII_CLK pulse width high
35%
65%
RMII_CLK
period
RMII2
RMII_CLK pulse width low
35%
65%
RMII_CLK
period
RMII3
RXD[1:0], CRS_DV, RXER to RMII_CLK setup
4
—
ns
RMII4
RMII_CLK to RXD[1:0], CRS_DV, RXER hold
2
—
ns
RMII7
RMII_CLK to TXD[1:0], TXEN invalid
4
—
ns
RMII8
RMII_CLK to TXD[1:0], TXEN valid
—
15.4
ns
Table 43. RMII signal switching specifications (full voltage range)
Num
Description
Min.
Max.
Unit
—
Operating Voltage
1.7
3.6
—
EXTAL frequency (RMII input clock RMII_CLK)
—
50
MHz
RMII1
RMII_CLK pulse width high
35%
65%
RMII_CLK
period
RMII2
RMII_CLK pulse width low
35%
65%
RMII_CLK
period
RMII3
RXD[1:0], CRS_DV, RXER to RMII_CLK setup
4
—
ns
RMII4
RMII_CLK to RXD[1:0], CRS_DV, RXER hold
2
—
ns
RMII7
RMII_CLK to TXD[1:0], TXEN invalid
4
—
ns
RMII8
RMII_CLK to TXD[1:0], TXEN valid
—
17.5
ns
3.8.1.3
MDIO serial management timing specifications
Table 44. MDIO serial management channel signal timing
Num
Characteristic
Symbol
Min
Max
Unit
E10
MDC cycle time
tMDC
400
—
ns
E11
MDC pulse width
40
60
% tMDC
E12
MDC to MDIO output valid
—
375
ns
E13
MDC to MDIO output invalid
25
—
ns
E14
MDIO input to MDC setup
10
—
ns
E15
MDIO input to MDC hold
0
—
ns
Kinetis K65 Sub-Family, Rev. 4, 04/2017
57
NXP Semiconductors
Peripheral operating requirements and behaviors
E10
E11
MDC (Output)
E11
E12
E13
MDIO (Output)
Valid Data
E14
MDIO (Input)
E15
Valid Data
Figure 26. MDIO serial management channel timing diagram
3.8.2 USB Voltage Regulator Electrical Specifications
Table 45. USB VREG electrical specifications
Symbol
VREG_IN0
Description
Min.
Typ.1
Max.
Unit
Notes
Regulator selectable input supply voltages
2.7
—
5.5
V
2
Quiescent current — Run mode, load current
equal zero, input supply (VREG_IN*) > 3.6 V
—
VREG_IN1
IDDon
VREG_IN0
μA
—
VREG_IN1
—
157
—
157
IDDstby
VREG_IN0
Quiescent current — Standby mode, load
current equal zero
2
—
2
—
—
680
—
—
920
—
—
—
μA
VREG_IN1
IDDoff
VREG_IN0
Quiescent current — Shutdown mode
• VREG_IN*= 5.0 V and temperature=25 °C
VREG_IN1
nA
ILOADrun
Maximum load current — Run mode
—
—
150
mA
ILOADstby
Maximum load current — Standby mode
—
—
1
mA
300
—
—
mV
3
3.3
3.6
V
2.1
2.8
3.6
V
VDROPOUT
Regulator drop-out voltage — Run mode at
maximum load current with inrush current limit
disabled
VREG_OUT Regulator programmable output target voltage
— Selected input supply > programmed output
target voltage + VDROPOUT
3
4
• Run mode
• Standby mode
Table continues on the next page...
58
NXP Semiconductors
Kinetis K65 Sub-Family, Rev. 4, 04/2017
Peripheral operating requirements and behaviors
Table 45. USB VREG electrical specifications
(continued)
Description
Min.
Typ.1
Max.
Unit
COUT
External output capacitor
1.76
2.2
8.16
μF
ESR
External output capacitor equivalent series
resistance
1
—
100
mΩ
ILIM
Short circuit current
—
350
—
mA
5
IINRUSH
Inrush current limit
40
—
100
mA
6, 7, 8,
9, 10
Symbol
Notes
1. Typical values assume the selected input supply is 5.0 V, Temp = 25 °C unless otherwise stated.
2. Operation range is 2.7 V to 5.5 V; tolerance voltage is up to 6 V.
3. 150mA is inclusive of the run mode current of the on-chip USB modules. Available load outside of the chip depends on
USB operation and device power dissipation limits.
4. The target voltage for the regulator is programmable, accounting for the range of the max and min values
5. Current limit disabled.
6. Current limit should be disabled after the powers have stabilized to allow full functionality of the regulator.
7. Limited Characterization
8. IINRUSH with VREGINx=4.0 V to 5.5 V
9. The minimum value of IINRUSH is stated for operation when only one of VREG_IN0 / VREG_IN1 is powered, or when
VREG_IN0 and VREG_IN1 both have the same voltage level. When VREG_IN0 and VREG_IN1 are operated at
different voltage levels with the selected VREG_IN lower than the non-selected VREG_IN, the minumum value of
IINRUSH may decrease to a lower value.
10. Total current load on startup should be less than IINRUSH min over full input voltage range of the regulator.
3.8.3 USB Full Speed Transceiver and High Speed PHY
specifications
This section describes the USB0 port Full Speed/Low Speed transceiver and USB1
port USB-PHY High Speed Phy parameters. The high speed phy is capable of full and
low speed signalling as well.
The USB0 (FS/LS Transceiver) and USB1 ((USB HS/FS/LS) meet the electrical
compliance requirements defined in the Universal Serial Bus Revision 2.0
Specification with the amendments below.
• USB ENGINEERING CHANGE NOTICE
• Title: 5V Short Circuit Withstand Requirement Change
• Applies to: Universal Serial Bus Specification, Revision 2.0
• Errata for USB Revision 2.0 April 27, 2000 as of 12/7/2000
• USB ENGINEERING CHANGE NOTICE
• Title: Pull-up/Pull-down resistors
• Applies to: Universal Serial Bus Specification, Revision 2.0
• USB ENGINEERING CHANGE NOTICE
Kinetis K65 Sub-Family, Rev. 4, 04/2017
59
NXP Semiconductors
Peripheral operating requirements and behaviors
• Title: Suspend Current Limit Changes
• Applies to: Universal Serial Bus Specification, Revision 2.0
• On-The-Go and Embedded Host Supplement to the USB Revision 2.0 Specification
• Revision 2.0 version 1.1a July 27, 2012
• Battery Charging Specification (available from USB-IF)
• Revision 1.2 (including errata and ECNs through March 15, 2012), March 15,
2012
USB1_VBUS pin is a detector function which is 5v tolerant and complies with the
above specifications without needing any external voltage division components.
3.8.4 USB DCD electrical specifications
Table 46. USB DCD electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VDP_SRC,
VDM_SRC
USB_DP and USB_DM source voltages (up to 250
μA)
0.5
—
0.7
V
Threshold voltage for logic high
0.8
—
2.0
V
VLGC
IDP_SRC
USB_DP source current
7
10
13
μA
IDM_SINK,
IDP_SINK
USB_DM and USB_DP sink currents
50
100
150
μA
RDM_DWN
D- pulldown resistance for data pin contact detect
14.25
—
24.8
kΩ
VDAT_REF
Data detect voltage
0.25
0.33
0.4
V
3.8.5 CAN switching specifications
See General switching specifications.
60
NXP Semiconductors
Kinetis K65 Sub-Family, Rev. 4, 04/2017
Peripheral operating requirements and behaviors
3.8.6 DSPI switching specifications (limited voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The
tables below provide DSPI timing characteristics for classic SPI timing modes. Refer
to the DSPI chapter of the Reference Manual for information on the modified transfer
formats used for communicating with slower peripheral devices.
Table 47. Master mode DSPI timing (limited voltage range)
Num
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
Frequency of operation
—
30
MHz
2 x tBUS
—
ns
Notes
DS1
DSPI_SCK output cycle time
DS2
DSPI_SCK output high/low time
(tSCK/2) − 2 (tSCK/2) + 2
ns
DS3
DSPI_PCSn valid to DSPI_SCK delay
(tBUS x 2) −
2
—
ns
1
DS4
DSPI_SCK to DSPI_PCSn invalid delay
(tBUS x 2) −
2
—
ns
2
DS5
DSPI_SCK to DSPI_SOUT valid
—
15.0
ns
DS6
DSPI_SCK to DSPI_SOUT invalid
1.0
—
ns
DS7
DSPI_SIN to DSPI_SCK input setup
15.8
—
ns
DS8
DSPI_SCK to DSPI_SIN input hold
0
—
ns
1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
DSPI_PCSn
DS3
(CPOL=0)
DS4
DS8
DS7
DSPI_SIN
DS1
DS2
DSPI_SCK
First data
DSPI_SOUT
Data
Last data
DS5
First data
DS6
Data
Last data
Figure 27. DSPI classic SPI timing — master mode
Table 48. Slave mode DSPI timing (limited voltage range)
Num
Description
Operating voltage
Frequency of operation
Min.
Max.
Unit
2.7
3.6
V
15
1
MHz
Table continues on the next page...
Kinetis K65 Sub-Family, Rev. 4, 04/2017
61
NXP Semiconductors
Peripheral operating requirements and behaviors
Table 48. Slave mode DSPI timing (limited voltage range) (continued)
Num
Description
Min.
Max.
Unit
4 x tBUS
—
ns
(tSCK/2) − 2
(tSCK/2) + 2
ns
—
23.0
ns
DS9
DSPI_SCK input cycle time
DS10
DSPI_SCK input high/low time
DS11
DSPI_SCK to DSPI_SOUT valid
DS12
DSPI_SCK to DSPI_SOUT invalid
0
—
ns
DS13
DSPI_SIN to DSPI_SCK input setup
2.7
—
ns
DS14
DSPI_SCK to DSPI_SIN input hold
7.0
—
ns
DS15
DSPI_SS active to DSPI_SOUT driven
—
13
ns
DS16
DSPI_SS inactive to DSPI_SOUT not driven
—
13
ns
1. The maximum operating frequency is measured with non-continuous CS and SCK. When DSPI is configured with
continuous CS and SCK, there is a constraint that SPI clock should not be greater than 1/6 of bus clock, for example,
when bus clock is 60MHz, SPI clock should not be greater than 10MHz.
DSPI_SS
DS10
DS9
DSPI_SCK
DS15
(CPOL=0)
DSPI_SOUT
DS12
First data
DS13
DSPI_SIN
DS16
DS11
Last data
Data
DS14
First data
Data
Last data
Figure 28. DSPI classic SPI timing — slave mode
3.8.7 DSPI switching specifications (full voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The
tables below provides DSPI timing characteristics for classic SPI timing modes. Refer
to the DSPI chapter of the Reference Manual for information on the modified transfer
formats used for communicating with slower peripheral devices.
Table 49. Master mode DSPI timing (full voltage range)
Num
Description
Operating voltage
Frequency of operation
Min.
Max.
Unit
Notes
1.71
—
3.6
V
1
15
MHz
Table continues on the next page...
62
NXP Semiconductors
Kinetis K65 Sub-Family, Rev. 4, 04/2017
Peripheral operating requirements and behaviors
Table 49. Master mode DSPI timing (full voltage range) (continued)
Num
Description
Min.
Max.
Unit
4 x tBUS
—
ns
Notes
DS1
DSPI_SCK output cycle time
DS2
DSPI_SCK output high/low time
(tSCK/2) - 4
(tSCK/2) + 4
ns
DS3
DSPI_PCSn valid to DSPI_SCK delay
(tBUS x 2) −
4
—
ns
2
DS4
DSPI_SCK to DSPI_PCSn invalid delay
(tBUS x 2) −
4
—
ns
3
DS5
DSPI_SCK to DSPI_SOUT valid
—
15
ns
DS6
DSPI_SCK to DSPI_SOUT invalid
1.0
—
ns
DS7
DSPI_SIN to DSPI_SCK input setup
15.8
—
ns
DS8
DSPI_SCK to DSPI_SIN input hold
0
—
ns
1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage
range the maximum frequency of operation is reduced.
2. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
3. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
DSPI_PCSn
DS3
DSPI_SCK
(CPOL=0)
DS4
DS8
DS7
DSPI_SIN
DS1
DS2
First data
DSPI_SOUT
Data
Last data
DS5
First data
DS6
Data
Last data
Figure 29. DSPI classic SPI timing — master mode
Table 50. Slave mode DSPI timing (full voltage range)
Num
Description
Operating voltage
Frequency of operation
Min.
Max.
Unit
1.71
3.6
V
—
7.5
MHz
8 x tBUS
—
ns
DS9
DSPI_SCK input cycle time
DS10
DSPI_SCK input high/low time
(tSCK/2) - 4
(tSCK/2) + 4
ns
DS11
DSPI_SCK to DSPI_SOUT valid
—
23.1
ns
DS12
DSPI_SCK to DSPI_SOUT invalid
0
—
ns
DS13
DSPI_SIN to DSPI_SCK input setup
2.6
—
ns
DS14
DSPI_SCK to DSPI_SIN input hold
7.0
—
ns
DS15
DSPI_SS active to DSPI_SOUT driven
—
13.0
ns
DS16
DSPI_SS inactive to DSPI_SOUT not driven
—
13.0
ns
Kinetis K65 Sub-Family, Rev. 4, 04/2017
63
NXP Semiconductors
Peripheral operating requirements and behaviors
DSPI_SS
DS10
DS9
DSPI_SCK
DS15
(CPOL=0)
DSPI_SOUT
DS12
First data
DS13
DSPI_SIN
DS16
DS11
Last data
Data
DS14
First data
Data
Last data
Figure 30. DSPI classic SPI timing — slave mode
3.8.8 Inter-Integrated Circuit Interface (I2C) timing
Table 51. I 2C timing
Characteristic
Symbol
Standard Mode
Fast Mode
Minimum
Maximum
Minimum
Maximum
Unit
SCL Clock Frequency
fSCL
0
100
0
400
kHz
Hold time (repeated) START condition.
After this period, the first clock pulse is
generated.
tHD; STA
4
—
0.6
—
µs
LOW period of the SCL clock
tLOW
4.7
—
1.25
—
µs
HIGH period of the SCL clock
tHIGH
4
—
0.6
—
µs
Set-up time for a repeated START
condition
tSU; STA
4.7
—
0.6
—
µs
Data hold time for I2C bus devices
tHD; DAT
01
3.452
03
0.91
µs
tSU; DAT
2504
—
1002, 5
Data set-up time
Rise time of SDA and SCL signals
tr
—
1000
—
ns
6
300
ns
5
20 +0.1Cb
Fall time of SDA and SCL signals
tf
—
300
20 +0.1Cb
300
ns
Set-up time for STOP condition
tSU; STO
4
—
0.6
—
µs
Bus free time between STOP and
START condition
tBUF
4.7
—
1.3
—
µs
Pulse width of spikes that must be
suppressed by the input filter
tSP
N/A
N/A
0
50
ns
1. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and SCL
lines.
2. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
3. Input signal Slew = 10 ns and Output Load = 50 pF
4. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.
5. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT ≥ 250 ns
must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such
64
NXP Semiconductors
Kinetis K65 Sub-Family, Rev. 4, 04/2017
Peripheral operating requirements and behaviors
a device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line trmax + tSU;
2
DAT = 1000 + 250 = 1250 ns (according to the Standard mode I C bus specification) before the SCL line is released.
6. Cb = total capacitance of the one bus line in pF.
Table 52. I 2C 1 Mbps timing
Characteristic
Symbol
Minimum
Maximum
Unit
MHz
SCL Clock Frequency
fSCL
0
11
Hold time (repeated) START condition. After this
period, the first clock pulse is generated.
tHD; STA
0.26
—
LOW period of the SCL clock
tLOW
0.5
—
HIGH period of the SCL clock
tHIGH
0.26
—
Set-up time for a repeated START condition
tSU; STA
0.26
—
µs
Data hold time for I2C bus devices
tHD; DAT
0
—
µs
Data set-up time
tSU; DAT
50


µs
µs
µs
—
ns
,2
Rise time of SDA and SCL signals
tr
20 +0.1Cb
120
ns
Fall time of SDA and SCL signals
tf
20 +0.1Cb2
120
ns
Set-up time for STOP condition
tSU; STO
0.26
—
µs
Bus free time between STOP and START
condition
tBUF
0.5
—
µs
Pulse width of spikes that must be suppressed by
the input filter
tSP
0
50
ns
1. The maximum SCL clock frequency of 1 Mbps can support maximum bus loading when using the High drive pins
across the full voltage range.
2. Cb = total capacitance of the one bus line in pF.
SDA
tf
tLOW
tSU; DAT
tr
tf
tHD; STA
tSP
tr
tBUF
SCL
S
HD; STA
tHD; DAT
tHIGH
tSU; STA
SR
tSU; STO
P
S
Figure 31. Timing definition for devices on the I2C bus
3.8.9 UART switching specifications
See General switching specifications.
Kinetis K65 Sub-Family, Rev. 4, 04/2017
65
NXP Semiconductors
Peripheral operating requirements and behaviors
3.8.10 Low Power UART switching specifications
See General switching specifications.
3.8.11 SDHC specifications
The following timing specs are defined at the chip I/O pin and must be translated
appropriately to arrive at timing specs/constraints for the physical interface.
Table 53. SDHC full voltage range switching specifications
Num
Symbol
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
Card input clock
SD1
fpp
Clock frequency (low speed)
0
400
kHz
fpp
Clock frequency (SD\SDIO full speed\high speed)
0
25\50
MHz
fpp
Clock frequency (MMC full speed\high speed)
0
20\50
MHz
fOD
Clock frequency (identification mode)
0
400
kHz
tWL
Clock low time
7
—
ns
SD3
tWH
Clock high time
7
—
ns
SD4
tTLH
Clock rise time
—
3
ns
SD5
tTHL
Clock fall time
—
3
ns
SD2
SDHC output / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SD6
tOD
SDHC output delay (output valid)
-5
8.6 8.3
ns
SDHC input / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SD7
tISU
SDHC input setup time
5
—
ns
SD8
tIH
SDHC input hold time
0
—
ns
Table 54. SDHC limited voltage range switching specifications
Num
Symbol
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
Card input clock
SD1
fpp
Clock frequency (low speed)
0
400
kHz
fpp
Clock frequency (SD\SDIO full speed\high speed)
0
25\50
MHz
fpp
Clock frequency (MMC full speed\high speed)
0
20\50
MHz
fOD
Clock frequency (identification mode)
0
400
kHz
SD2
tWL
Clock low time
7
—
ns
SD3
tWH
Clock high time
7
—
ns
SD4
tTLH
Clock rise time
—
3
ns
SD5
tTHL
Clock fall time
—
3
ns
Table continues on the next page...
66
NXP Semiconductors
Kinetis K65 Sub-Family, Rev. 4, 04/2017
Peripheral operating requirements and behaviors
Table 54. SDHC limited voltage range switching specifications (continued)
Num
Symbol
Description
Min.
Max.
Unit
SDHC output / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SD6
tOD
SDHC output delay (output valid)
-5
7.6 8.3
ns
SDHC input / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SD7
tISU
SDHC input setup time
5
—
ns
SD8
tIH
SDHC input hold time
0
—
ns
SD3
SD2
SD1
SDHC_CLK
SD6
Output SDHC_CMD
Output SDHC_DAT[3:0]
SD7
SD8
Input SDHC_CMD
Input SDHC_DAT[3:0]
Figure 32. SDHC timing
3.8.12 I2S switching specifications
This section provides the AC timings for the I2S in master (clocks driven) and slave
modes (clocks input). All timings are given for non-inverted serial clock polarity
(TCR[TSCKP] = 0, RCR[RSCKP] = 0) and a non-inverted frame sync (TCR[TFSI] =
0, RCR[RFSI] = 0). If the polarity of the clock and/or the frame sync have been
inverted, all the timings remain valid by inverting the clock signal (I2S_BCLK) and/or
the frame sync (I2S_FS) shown in the figures below.
Table 55. I2S master mode timing (limited voltage range)
Num
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
S1
I2S_MCLK cycle time
40
—
ns
S2
I2S_MCLK pulse width high/low
45%
55%
MCLK period
S3
I2S_BCLK cycle time
80
—
ns
Table continues on the next page...
Kinetis K65 Sub-Family, Rev. 4, 04/2017
67
NXP Semiconductors
Peripheral operating requirements and behaviors
Table 55. I2S master mode timing (limited voltage range) (continued)
Num
Description
Min.
Max.
Unit
S4
I2S_BCLK pulse width high/low
45%
55%
BCLK period
S5
I2S_BCLK to I2S_FS output valid
—
15
ns
S6
I2S_BCLK to I2S_FS output invalid
0
—
ns
S7
I2S_BCLK to I2S_TXD valid
—
15
ns
S8
I2S_BCLK to I2S_TXD invalid
0
—
ns
S9
I2S_RXD/I2S_FS input setup before I2S_BCLK
15
—
ns
S10
I2S_RXD/I2S_FS input hold after I2S_BCLK
0
—
ns
S1
S2
S2
I2S_MCLK (output)
S3
I2S_BCLK (output)
S4
S4
S6
S5
I2S_FS (output)
S10
S9
I2S_FS (input)
S7
S8
S7
S8
I2S_TXD
S9
S10
I2S_RXD
Figure 33. I2S timing — master mode
Table 56. I2S slave mode timing (limited voltage range)
Num
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
S11
I2S_BCLK cycle time (input)
80
—
ns
S12
I2S_BCLK pulse width high/low (input)
45%
55%
MCLK period
S13
I2S_FS input setup before I2S_BCLK
4.5
—
ns
S14
I2S_FS input hold after I2S_BCLK
2
—
ns
S15
I2S_BCLK to I2S_TXD/I2S_FS output valid
—
20
ns
S16
I2S_BCLK to I2S_TXD/I2S_FS output invalid
0
—
ns
S17
I2S_RXD setup before I2S_BCLK
4.5
—
ns
S18
I2S_RXD hold after I2S_BCLK
—
ns
S19
I2S_TX_FS input assertion to I2S_TXD output valid1
25
ns
2
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
68
NXP Semiconductors
Kinetis K65 Sub-Family, Rev. 4, 04/2017
Peripheral operating requirements and behaviors
S11
S12
I2S_BCLK (input)
S12
S15
S16
I2S_FS (output)
S13
I2S_FS (input)
S14
S15
S19
S16
S15
S16
I2S_TXD
S17
S18
I2S_RXD
Figure 34. I2S timing — slave modes
3.8.12.1
Normal Run, Wait and Stop mode performance over the full
operating voltage range
This section provides the operating performance over the full operating voltage for the
device in Normal Run, Wait and Stop modes.
Table 57. I2S/SAI master mode timing
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
S1
I2S_MCLK cycle time
40
—
ns
S2
I2S_MCLK (as an input) pulse width high/low
45%
55%
MCLK period
S3
I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)
80
—
ns
S4
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
45%
55%
BCLK period
S5
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
—
15
ns
S6
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
0
—
ns
S7
I2S_TX_BCLK to I2S_TXD valid
—
15
ns
S8
I2S_TX_BCLK to I2S_TXD invalid
0
—
ns
S9
I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
15
—
ns
S10
I2S_RXD/I2S_RX_FS input hold after
I2S_RX_BCLK
0
—
ns
Kinetis K65 Sub-Family, Rev. 4, 04/2017
69
NXP Semiconductors
Peripheral operating requirements and behaviors
S1
S2
S2
I2S_MCLK (output)
S3
I2S_TX_BCLK/
I2S_RX_BCLK (output)
S4
S4
S6
S5
I2S_TX_FS/
I2S_RX_FS (output)
S10
S9
I2S_TX_FS/
I2S_RX_FS (input)
S7
S8
S7
S8
I2S_TXD
S9
S10
I2S_RXD
Figure 35. I2S/SAI timing — master modes
Table 58. I2S/SAI slave mode timing
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
S11
I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)
80
—
ns
S12
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
(input)
45%
55%
MCLK period
S13
I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
4.5
—
ns
S14
I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
2
—
ns
S15
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
—
23.1
ns
S16
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid 0
—
ns
S17
I2S_RXD setup before I2S_RX_BCLK
4.5
—
ns
S18
I2S_RXD hold after I2S_RX_BCLK
2
—
ns
—
25
ns
S19
I2S_TX_FS input assertion to I2S_TXD output
valid1
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
70
NXP Semiconductors
Kinetis K65 Sub-Family, Rev. 4, 04/2017
Peripheral operating requirements and behaviors
S11
S12
I2S_TX_BCLK/
I2S_RX_BCLK (input)
S12
S15
S16
I2S_TX_FS/
I2S_RX_FS (output)
S13
I2S_TX_FS/
I2S_RX_FS (input)
S19
S14
S15
S16
S15
S16
I2S_TXD
S17
S18
I2S_RXD
Figure 36. I2S/SAI timing — slave modes
3.8.12.2
VLPR, VLPW, and VLPS mode performance over the full
operating voltage range
This section provides the operating performance over the full operating voltage for the
device in VLPR, VLPW, and VLPS modes.
Table 59. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes (full voltage range)
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
S1
I2S_MCLK cycle time
62.5
—
ns
S2
I2S_MCLK pulse width high/low
45%
55%
MCLK period
S3
I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)
250
—
ns
S4
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
45%
55%
BCLK period
S5
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
—
45
ns
S6
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
0
—
ns
S7
I2S_TX_BCLK to I2S_TXD valid
—
45
ns
S8
I2S_TX_BCLK to I2S_TXD invalid
0
—
ns
S9
I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
45
—
ns
S10
I2S_RXD/I2S_RX_FS input hold after
I2S_RX_BCLK
0
—
ns
Kinetis K65 Sub-Family, Rev. 4, 04/2017
71
NXP Semiconductors
Peripheral operating requirements and behaviors
S1
S2
S2
I2S_MCLK (output)
S3
I2S_TX_BCLK/
I2S_RX_BCLK (output)
S4
S4
S6
S5
I2S_TX_FS/
I2S_RX_FS (output)
S10
S9
I2S_TX_FS/
I2S_RX_FS (input)
S7
S8
S7
S8
I2S_TXD
S9
S10
I2S_RXD
Figure 37. I2S/SAI timing — master modes
Table 60. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full voltage range)
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
S11
I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)
250
—
ns
S12
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
(input)
45%
55%
MCLK period
S13
I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
30
—
ns
S14
I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
5
—
ns
S15
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
—
56.5
ns
S16
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid 0
—
ns
S17
I2S_RXD setup before I2S_RX_BCLK
30
—
ns
S18
I2S_RXD hold after I2S_RX_BCLK
5
—
ns
—
72
ns
S19
I2S_TX_FS input assertion to I2S_TXD output
valid1
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
72
NXP Semiconductors
Kinetis K65 Sub-Family, Rev. 4, 04/2017
Dimensions
S11
S12
I2S_TX_BCLK/
I2S_RX_BCLK (input)
S12
S15
S16
I2S_TX_FS/
I2S_RX_FS (output)
S13
I2S_TX_FS/
I2S_RX_FS (input)
S19
S14
S15
S16
S15
S16
I2S_TXD
S17
S18
I2S_RXD
Figure 38. I2S/SAI timing — slave modes
3.9 Human-machine interfaces (HMI)
3.9.1 TSI electrical specifications
Table 61. TSI electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
TSI_RUNF
Fixed power consumption in run mode
—
100
—
µA
TSI_RUNV
Variable power consumption in run mode
(depends on oscillator's current selection)
1.0
—
128
µA
TSI_EN
Power consumption in enable mode
—
100
—
µA
TSI_DIS
Power consumption in disable mode
—
1.2
—
µA
TSI_TEN
TSI analog enable time
—
66
—
µs
TSI_CREF
TSI reference capacitor
—
1.0
—
pF
TSI_DVOLT
Voltage variation of VP & VM around nominal
values
0.19
—
1.03
V
4 Dimensions
4.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
Kinetis K65 Sub-Family, Rev. 4, 04/2017
73
NXP Semiconductors
Pinout
To find a package drawing, go to nxp.com and perform a keyword search for the
drawing’s document number:
If you want the drawing for this package
169-pin MAPBGA
Then use this document number
98ASA00628D
5 Pinout
5.1 K65_169BGA Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
169
MAP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
A1
PTE0
ADC1_SE4a
ADC1_SE4a
PTE0
SPI1_PCS1
UART1_TX
SDHC0_D1
TRACE_
CLKOUT
I2C1_SDA
RTC_
CLKOUT
B1
PTE1/
LLWU_P0
ADC1_SE5a
ADC1_SE5a
PTE1/
LLWU_P0
SPI1_SOUT
UART1_RX
SDHC0_D0
TRACE_D3
I2C1_SCL
SPI1_SIN
C1
PTE2/
LLWU_P1
ADC1_SE6a
ADC1_SE6a
PTE2/
LLWU_P1
SPI1_SCK
UART1_CTS_ SDHC0_
b
DCLK
D1
PTE3
ADC1_SE7a
ADC1_SE7a
PTE3
SPI1_SIN
UART1_RTS_ SDHC0_CMD TRACE_D1
b
G5
VDD
VDD
VDD
C3
VSS
VSS
VSS
E1
PTE4/
LLWU_P2
DISABLED
PTE4/
LLWU_P2
SPI1_PCS0
UART3_TX
SDHC0_D3
D2
PTE5
DISABLED
PTE5
SPI1_PCS2
UART3_RX
SDHC0_D2
FTM3_CH0
E2
PTE6/
LLWU_P16
DISABLED
PTE6/
LLWU_P16
SPI1_PCS3
UART3_CTS_ I2S0_MCLK
b
FTM3_CH1
E3
PTE7
DISABLED
PTE7
UART3_RTS_ I2S0_RXD0
b
FTM3_CH2
E4
PTE8
DISABLED
PTE8
I2S0_RXD1
I2S0_RX_FS
LPUART0_TX FTM3_CH3
F3
PTE9/
LLWU_P17
DISABLED
PTE9/
LLWU_P17
I2S0_TXD1
I2S0_RX_
BCLK
LPUART0_RX FTM3_CH4
F4
PTE10/
LLWU_P18
DISABLED
PTE10/
LLWU_P18
I2C3_SDA
I2S0_TXD0
LPUART0_
CTS_b
FTM3_CH5
G4
PTE11
DISABLED
PTE11
I2C3_SCL
I2S0_TX_FS
LPUART0_
RTS_b
FTM3_CH6
74
NXP Semiconductors
EzPort
TRACE_D2
SPI1_SOUT
TRACE_D0
USB0_SOF_
OUT
USB1_ID
Kinetis K65 Sub-Family, Rev. 4, 04/2017
Pinout
169
MAP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
H4
PTE12
DISABLED
G6
VDD
VDD
VDD
G8
VSS
VSS
VSS
H3
PTE16
ADC0_SE4a
ADC0_SE4a
PTE16
SPI0_PCS0
F5
PTE17/
LLWU_P19
ADC0_SE5a
ADC0_SE5a
PTE17/
LLWU_P19
F6
PTE18/
LLWU_P20
ADC0_SE6a
ADC0_SE6a
F7
PTE19
ADC0_SE7a
ADC0_SE7a
G3
VSS
VSS
VSS
G1
USB0_DP
USB0_DP
USB0_DP
F1
USB0_DM
USB0_DM
USB0_DM
G2
VREG_OUT
VREG_OUT
VREG_OUT
F2
VREG_IN0
VREG_IN0
VREG_IN0
H2
VREG_IN1
DISABLED
VREG_IN1
K1
USB1_VSS
DISABLED
USB1_VSS
J1
USB1_DP
DISABLED
USB1_DP
H1
USB1_DM
DISABLED
USB1_DM
J2
USB1_VBUS
DISABLED
USB1_VBUS
L1
ADC1_DP1
ADC1_DP1
ADC1_DP1
M1
ADC1_DM1
ADC1_DM1
ADC1_DM1
M2
ADC0_DP0/
ADC1_DP3
ADC0_DP0/
ADC1_DP3
ADC0_DP0/
ADC1_DP3
L2
ADC0_DM0/
ADC1_DM3
ADC0_DM0/
ADC1_DM3
ADC0_DM0/
ADC1_DM3
N1
ADC1_DP0/
ADC0_DP3
ADC1_DP0/
ADC0_DP3
ADC1_DP0/
ADC0_DP3
N2
ADC1_DM0/
ADC0_DM3
ADC1_DM0/
ADC0_DM3
ADC1_DM0/
ADC0_DM3
ALT3
PTE12
J3
VDDA
VDDA
VDDA
K3
VREFH
VREFH
VREFH
K4
VREFL
VREFL
VREFL
J4
VSSA
VSSA
VSSA
M3
ADC1_SE16/
CMP2_IN2/
ADC0_SE22
ADC1_SE16/
CMP2_IN2/
ADC0_SE22
ADC1_SE16/
CMP2_IN2/
ADC0_SE22
L3
ADC0_SE16/
CMP1_IN2/
ADC0_SE21
ADC0_SE16/
CMP1_IN2/
ADC0_SE21
ADC0_SE16/
CMP1_IN2/
ADC0_SE21
ALT4
ALT5
ALT6
ALT7
I2S0_TX_
BCLK
FTM3_CH7
UART2_TX
FTM_CLKIN0
FTM0_FLT3
TPM_CLKIN0
SPI0_SCK
UART2_RX
FTM_CLKIN1
LPTMR0_
ALT3
TPM_CLKIN1
PTE18/
LLWU_P20
SPI0_SOUT
UART2_CTS_ I2C0_SDA
b
PTE19
SPI0_SIN
UART2_RTS_ I2C0_SCL
b
Kinetis K65 Sub-Family, Rev. 4, 04/2017
EzPort
CMP3_OUT
75
NXP Semiconductors
Pinout
169
MAP
BGA
Pin Name
Default
ALT0
N3
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
M4
DAC0_OUT/
CMP1_IN3/
ADC0_SE23
DAC0_OUT/
CMP1_IN3/
ADC0_SE23
DAC0_OUT/
CMP1_IN3/
ADC0_SE23
N4
DAC1_OUT/
CMP0_IN4/
CMP2_IN3/
ADC1_SE23
DAC1_OUT/
CMP0_IN4/
CMP2_IN3/
ADC1_SE23
DAC1_OUT/
CMP0_IN4/
CMP2_IN3/
ADC1_SE23
M5
TAMPER0/
RTC_
WAKEUP_B
TAMPER0/
RTC_
WAKEUP_B
TAMPER0/
RTC_
WAKEUP_B
L4
TAMPER1
TAMPER1
TAMPER1
L5
TAMPER2
TAMPER2
TAMPER2
K5
TAMPER3
TAMPER3
TAMPER3
L6
TAMPER4
TAMPER4
TAMPER4
K6
TAMPER5
TAMPER5
TAMPER5
N5
XTAL32
XTAL32
XTAL32
N6
EXTAL32
EXTAL32
EXTAL32
M6
VBAT
VBAT
VBAT
J6
TAMPER6
TAMPER6
TAMPER6
J5
TAMPER7
TAMPER7
TAMPER7
G7
VDD
VDD
VDD
N7
VSS
VSS
VSS
L7
PTE24
ADC0_SE17
ADC0_SE17
PTE24
CAN1_TX
UART4_TX
I2C0_SCL
EWM_OUT_b
K7
PTE25/
LLWU_P21
ADC0_SE18
ADC0_SE18
PTE25/
LLWU_P21
CAN1_RX
UART4_RX
I2C0_SDA
EWM_IN
K8
PTE26
DISABLED
PTE26
ENET_1588_
CLKIN
UART4_CTS_
b
L8
PTE27
DISABLED
PTE27
M7
PTE28
DISABLED
PTE28
N8
PTA0
JTAG_TCLK/
SWD_CLK/
EZP_CLK
TSI0_CH1
PTA0
UART0_CTS_ FTM0_CH5
b/
UART0_COL_
b
N9
PTA1
JTAG_TDI/
EZP_DI
TSI0_CH2
PTA1
UART0_RX
FTM0_CH6
M9
PTA2
JTAG_TDO/
TRACE_
SWO/
EZP_DO
TSI0_CH3
PTA2
UART0_TX
FTM0_CH7
76
NXP Semiconductors
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
RTC_
CLKOUT
ALT7
EzPort
USB0_CLKIN
UART4_RTS_
b
LPUART0_
CTS_b
JTAG_TCLK/
SWD_CLK
EZP_CLK
I2C3_SDA
LPUART0_RX
JTAG_TDI
EZP_DI
I2C3_SCL
LPUART0_TX
JTAG_TDO/ EZP_DO
TRACE_SWO
Kinetis K65 Sub-Family, Rev. 4, 04/2017
Pinout
169
MAP
BGA
Pin Name
Default
ALT0
ALT1
M8
PTA3
JTAG_TMS/
SWD_DIO
TSI0_CH4
PTA3
L9
PTA4/
LLWU_P3
NMI_b/
EZP_CS_b
TSI0_CH5
PTA4/
LLWU_P3
N10 PTA5
DISABLED
H5
VDD
VDD
VDD
H8
VSS
VSS
VSS
ALT2
ALT3
ALT4
UART0_RTS_ FTM0_CH0
b
ALT5
ALT6
ALT7
LPUART0_
RTS_b
JTAG_TMS/
SWD_DIO
FTM0_CH1
NMI_b
RMII0_RXER/ CMP2_OUT
MII0_RXER
PTA5
USB0_CLKIN FTM0_CH2
PTA6
FTM0_CH3
CLKOUT
TRACE_
CLKOUT
TRACE_D3
M10 PTA6
DISABLED
L10
PTA7
ADC0_SE10
ADC0_SE10
PTA7
FTM0_CH4
RMII0_MDIO/
MII0_MDIO
K9
PTA8
ADC0_SE11
ADC0_SE11
PTA8
FTM1_CH0
RMII0_MDC/
MII0_MDC
K10
PTA9
DISABLED
PTA9
FTM1_CH1
N11 PTA10/
LLWU_P22
DISABLED
PTA10/
LLWU_P22
M11 PTA11/
LLWU_P23
DISABLED
PTA11/
LLWU_P23
L12
PTA12
CMP2_IN0
CMP2_IN0
PTA12
L11
PTA13/
LLWU_P4
CMP2_IN1
CMP2_IN1
K13
PTA14
DISABLED
K12
PTA15
CMP3_IN1
J13
PTA16
J12
PTA17
I2S0_TX_
BCLK
TRACE_D2
MII0_RXD3
FTM1_QD_
PHB/
TPM1_CH1
TRACE_D1
FTM2_CH0
MII0_RXD2
FTM2_QD_
PHA/
TPM2_CH0
TRACE_D0
FTM2_CH1
MII0_RXCLK
I2C2_SDA
FTM2_QD_
PHB/
TPM2_CH1
CAN0_TX
FTM1_CH0
RMII0_RXD1/ I2C2_SCL
MII0_RXD1
I2S0_TXD0
FTM1_QD_
PHA/
TPM1_CH0
PTA13/
LLWU_P4
CAN0_RX
FTM1_CH1
RMII0_RXD0/ I2C2_SDA
MII0_RXD0
I2S0_TX_FS
FTM1_QD_
PHB/
TPM1_CH1
PTA14
SPI0_PCS0
UART0_TX
RMII0_CRS_
DV/
MII0_RXDV
I2S0_RX_
BCLK
I2S0_TXD1
CMP3_IN1
PTA15
SPI0_SCK
UART0_RX
RMII0_TXEN/
MII0_TXEN
CMP3_IN2
CMP3_IN2
PTA16
SPI0_SOUT
UART0_CTS_ RMII0_TXD0/
b/
MII0_TXD0
UART0_COL_
b
I2S0_RX_FS
ADC1_SE17
ADC1_SE17
PTA17
SPI0_SIN
UART0_RTS_ RMII0_TXD1/
b
MII0_TXD1
I2S0_MCLK
N12 VDD
VDD
VDD
M12 VSS
VSS
VSS
N13 PTA18
EXTAL0
EXTAL0
PTA18
FTM0_FLT2
FTM_CLKIN0
M13 PTA19
XTAL0
XTAL0
PTA19
FTM1_FLT0
FTM_CLKIN1
Kinetis K65 Sub-Family, Rev. 4, 04/2017
EZP_CS_b
JTAG_TRST_
b
FTM1_QD_
PHA/
TPM1_CH0
I2C2_SCL
EzPort
I2S0_RXD0
I2S0_RXD1
TPM_CLKIN0
LPTMR0_
ALT1
TPM_CLKIN1
77
NXP Semiconductors
Pinout
169
MAP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
L13
RESET_b
RESET_b
RESET_b
K11
PTA24
CMP3_IN4
CMP3_IN4
PTA24
MII0_TXD2
FB_A15/
SDRAM_D15
FB_A29
J11
PTA25
CMP3_IN5
CMP3_IN5
PTA25
MII0_TXCLK
FB_A14/
SDRAM_D14
FB_A28
J10
PTA26
DISABLED
PTA26
MII0_TXD3
FB_A13/
SDRAM_D13
FB_A27
H13 PTA27
DISABLED
PTA27
MII0_CRS
FB_A12/
SDRAM_D12
FB_A26
H12 PTA28
DISABLED
PTA28
MII0_TXER
FB_A25
H11 PTA29
DISABLED
PTA29
MII0_COL
FB_A24
H10 PTA30
DISABLED
PTA30
CAN0_TX
FB_A11/
SDRAM_D11
J9
DISABLED
PTA31
CAN0_RX
FB_A10/
SDRAM_D10
PTA31
G13 PTB0/
LLWU_P5
ADC0_SE8/
ADC1_SE8/
TSI0_CH0
ADC0_SE8/
ADC1_SE8/
TSI0_CH0
PTB0/
LLWU_P5
I2C0_SCL
FTM1_CH0
RMII0_MDIO/ SDRAM_
MII0_MDIO
CAS_b
FTM1_QD_
PHA/
TPM1_CH0
G12 PTB1
ADC0_SE9/
ADC1_SE9/
TSI0_CH6
ADC0_SE9/
ADC1_SE9/
TSI0_CH6
PTB1
I2C0_SDA
FTM1_CH1
RMII0_MDC/
MII0_MDC
SDRAM_
RAS_b
FTM1_QD_
PHB/
TPM1_CH1
G11 PTB2
ADC0_SE12/
TSI0_CH7
ADC0_SE12/
TSI0_CH7
PTB2
I2C0_SCL
UART0_RTS_ ENET0_
b
1588_TMR0
SDRAM_WE
FTM0_FLT3
G10 PTB3
ADC0_SE13/
TSI0_CH8
ADC0_SE13/
TSI0_CH8
PTB3
I2C0_SDA
UART0_CTS_ ENET0_
b/
1588_TMR1
UART0_COL_
b
SDRAM_
CS0_b
FTM0_FLT0
H9
PTB4
ADC1_SE10
ADC1_SE10
PTB4
ENET0_
1588_TMR2
SDRAM_
CS1_b
FTM1_FLT0
F13
PTB5
ADC1_SE11
ADC1_SE11
PTB5
ENET0_
1588_TMR3
F12
PTB6
ADC1_SE12
ADC1_SE12
PTB6
FB_AD23/
SDRAM_D23
F11
PTB7
ADC1_SE13
ADC1_SE13
PTB7
FB_AD22/
SDRAM_D22
F10
PTB8
DISABLED
PTB8
F9
PTB9
DISABLED
PTB9
G9
PTB10
ADC1_SE14
ADC1_SE14
E13
PTB11
ADC1_SE15
ADC1_SE15
E12
PTB12
DISABLED
78
NXP Semiconductors
EzPort
FTM2_FLT0
UART3_RTS_
b
FB_AD21/
SDRAM_D21
SPI1_PCS1
UART3_CTS_
b
FB_AD20/
SDRAM_D20
PTB10
SPI1_PCS0
UART3_RX
FB_AD19/
SDRAM_D19
FTM0_FLT1
PTB11
SPI1_SCK
UART3_TX
FB_AD18/
SDRAM_D18
FTM0_FLT2
PTB12
UART3_RTS_ FTM1_CH0
b
FB_A9/
SDRAM_D9
FTM1_QD_
PHA/
TPM1_CH0
FTM0_CH4
ALT7
Kinetis K65 Sub-Family, Rev. 4, 04/2017
Pinout
169
MAP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT7
PTB13
DISABLED
PTB13
UART3_CTS_ FTM1_CH1
b
E10
PTB14
DISABLED
PTB14
CAN1_TX
FB_A7/
SDRAM_D7
E9
PTB15
DISABLED
PTB15
CAN1_RX
FB_A6/
SDRAM_D6
F8
PTB16
TSI0_CH9
TSI0_CH9
PTB16
SPI1_SOUT
UART0_RX
FTM_CLKIN0 FB_AD17/
SDRAM_D17
EWM_IN
D13 PTB17
TSI0_CH10
TSI0_CH10
PTB17
SPI1_SIN
UART0_TX
FTM_CLKIN1 FB_AD16/
SDRAM_D16
EWM_OUT_b TPM_CLKIN1
D12 PTB18
TSI0_CH11
TSI0_CH11
PTB18
CAN0_TX
FTM2_CH0
I2S0_TX_
BCLK
FB_AD15/
SDRAM_A23
FTM2_QD_
PHA/
TPM2_CH0
D11 PTB19
TSI0_CH12
TSI0_CH12
PTB19
CAN0_RX
FTM2_CH1
I2S0_TX_FS
FB_OE_b
FTM2_QD_
PHB/
TPM2_CH1
D10 PTB20
DISABLED
PTB20
SPI2_PCS0
FB_AD31/
SDRAM_D31
CMP0_OUT
D9
PTB21
DISABLED
PTB21
SPI2_SCK
FB_AD30/
SDRAM_D30
CMP1_OUT
C13 PTB22
DISABLED
PTB22
SPI2_SOUT
FB_AD29/
SDRAM_D29
CMP2_OUT
C12 PTB23
DISABLED
PTB23
SPI2_SIN
SPI0_PCS5
FB_AD28/
SDRAM_D28
CMP3_OUT
B13
PTC0
ADC0_SE14/
TSI0_CH13
ADC0_SE14/
TSI0_CH13
PTC0
SPI0_PCS4
PDB0_
EXTRG
FB_AD14/
SDRAM_A22
I2S0_TXD1
B12
PTC1/
LLWU_P6
ADC0_SE15/
TSI0_CH14
ADC0_SE15/
TSI0_CH14
PTC1/
LLWU_P6
SPI0_PCS3
UART1_RTS_ FTM0_CH0
b
FB_AD13/
SDRAM_A21
I2S0_TXD0
A13
PTC2
ADC0_SE4b/
CMP1_IN0/
TSI0_CH15
ADC0_SE4b/
CMP1_IN0/
TSI0_CH15
PTC2
SPI0_PCS2
UART1_CTS_ FTM0_CH1
b
FB_AD12/
SDRAM_A20
I2S0_TX_FS
A12
PTC3/
LLWU_P7
CMP1_IN1
CMP1_IN1
PTC3/
LLWU_P7
SPI0_PCS1
UART1_RX
FTM0_CH2
CLKOUT
I2S0_TX_
BCLK
C11 VSS
VSS
VSS
H6
VDD
VDD
VDD
B11
PTC4/
LLWU_P8
DISABLED
PTC4/
LLWU_P8
SPI0_PCS0
UART1_TX
FTM0_CH3
FB_AD11/
SDRAM_A19
CMP1_OUT
A11
PTC5/
LLWU_P9
DISABLED
PTC5/
LLWU_P9
SPI0_SCK
LPTMR0_
ALT2
I2S0_RXD0
FB_AD10/
SDRAM_A18
CMP0_OUT
A10
PTC6/
LLWU_P10
CMP0_IN0
CMP0_IN0
PTC6/
LLWU_P10
SPI0_SOUT
PDB0_
EXTRG
I2S0_RX_
BCLK
FB_AD9/
SDRAM_A17
I2S0_MCLK
B10
PTC7
CMP0_IN1
CMP0_IN1
PTC7
SPI0_SIN
USB0_SOF_
OUT
I2S0_RX_FS
FB_AD8/
SDRAM_A16
ADC1_SE4b/
CMP0_IN2
ADC1_SE4b/
CMP0_IN2
PTC8
FTM3_CH4
I2S0_MCLK
FB_AD7/
SDRAM_A15
Kinetis K65 Sub-Family, Rev. 4, 04/2017
USB0_SOF_
OUT
FB_A8/
SDRAM_D8
ALT6
E11
C10 PTC8
FTM0_CH5
ALT5
EzPort
FTM1_QD_
PHB/
TPM1_CH1
TPM_CLKIN0
FTM0_CH2
79
NXP Semiconductors
Pinout
169
MAP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
C9
PTC9
ADC1_SE5b/
CMP0_IN3
ADC1_SE5b/
CMP0_IN3
PTC9
A8
PTC10
ADC1_SE6b
ADC1_SE6b
PTC10
A9
PTC11/
LLWU_P11
ADC1_SE7b
ADC1_SE7b
PTC11/
LLWU_P11
B9
PTC12
DISABLED
PTC12
UART4_RTS_ FTM_CLKIN0 FB_AD27/
b
SDRAM_D27
B8
PTC13
DISABLED
PTC13
UART4_CTS_ FTM_CLKIN1 FB_AD26/
b
SDRAM_D26
C8
PTC14
DISABLED
PTC14
UART4_RX
FB_AD25/
SDRAM_D25
D8
PTC15
DISABLED
PTC15
UART4_TX
FB_AD24/
SDRAM_D24
E8
PTC16
DISABLED
PTC16
CAN1_RX
UART3_RX
ENET0_
1588_TMR0
FB_CS5_b/
FB_TSIZ1/
FB_BE23_
16_BLS15_8_
b/
SDRAM_
DQM2
E7
PTC17
DISABLED
PTC17
CAN1_TX
UART3_TX
ENET0_
1588_TMR1
FB_CS4_b/
FB_TSIZ0/
FB_BE31_
24_BLS7_0_
b/
SDRAM_
DQM3
D7
PTC18
DISABLED
PTC18
UART3_RTS_ ENET0_
b
1588_TMR2
FB_TBST_b/
FB_CS2_b/
FB_BE15_8_
BLS23_16_b/
SDRAM_
DQM1
C7
PTC19
DISABLED
PTC19
UART3_CTS_ ENET0_
b
1588_TMR3
FB_CS3_b/
FB_TA_b
FB_BE7_0_
BLS31_24_b/
SDRAM_
DQM0
B7
PTC24
DISABLED
PTC24
LPUART0_TX
FB_A5/
SDRAM_D5
A7
PTC25
DISABLED
PTC25
LPUART0_RX
FB_A4/
SDRAM_D4
E6
PTC26
DISABLED
PTC26
LPUART0_
CTS_b
ENET0_
1588_TMR0
FB_A3/
SDRAM_D3
D6
PTC27
DISABLED
PTC27
LPUART0_
RTS_b
ENET0_
1588_TMR1
FB_A2/
SDRAM_D2
80
NXP Semiconductors
FTM3_CH5
I2S0_RX_
BCLK
FB_AD6/
SDRAM_A14
I2C1_SCL
FTM3_CH6
I2S0_RX_FS
FB_AD5/
SDRAM_A13
I2C1_SDA
FTM3_CH7
I2S0_RXD1
FB_RW_b
ALT6
ALT7
EzPort
FTM2_FLT0
FTM3_FLT0
TPM_CLKIN0
TPM_CLKIN1
Kinetis K65 Sub-Family, Rev. 4, 04/2017
Pinout
169
MAP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
C6
PTC28
DISABLED
PTC28
I2C3_SDA
ENET0_
1588_TMR2
FB_A1/
SDRAM_D1
B6
PTC29
DISABLED
PTC29
I2C3_SCL
ENET0_
1588_TMR3
FB_A0/
SDRAM_D0
A6
PTD0/
LLWU_P12
DISABLED
PTD0/
LLWU_P12
SPI0_PCS0
UART2_RTS_ FTM3_CH0
b
FB_ALE/
FB_CS1_b/
FB_TS_b
A5
PTD1
ADC0_SE5b
PTD1
SPI0_SCK
UART2_CTS_ FTM3_CH1
b
FB_CS0_b
A4
PTD2/
LLWU_P13
DISABLED
PTD2/
LLWU_P13
SPI0_SOUT
UART2_RX
FTM3_CH2
FB_AD4/
SDRAM_A12
I2C0_SCL
B4
PTD3
DISABLED
PTD3
SPI0_SIN
UART2_TX
FTM3_CH3
FB_AD3/
SDRAM_A11
I2C0_SDA
B5
PTD4/
LLWU_P14
DISABLED
PTD4/
LLWU_P14
SPI0_PCS1
UART0_RTS_ FTM0_CH4
b
FB_AD2/
SDRAM_A10
EWM_IN
C4
PTD5
ADC0_SE6b
ADC0_SE6b
PTD5
SPI0_PCS2
UART0_CTS_ FTM0_CH5
b/
UART0_COL_
b
FB_AD1/
SDRAM_A9
EWM_OUT_b SPI1_SCK
C5
PTD6/
LLWU_P15
ADC0_SE7b
ADC0_SE7b
PTD6/
LLWU_P15
SPI0_PCS3
UART0_RX
FTM0_CH6
FB_AD0
FTM0_FLT0
J8
VSS
VSS
VSS
H7
VDD
VDD
VDD
E5
PTD7
DISABLED
PTD7
CMT_IRO
UART0_TX
FTM0_CH7
SDRAM_CKE FTM0_FLT1
D5
PTD8/
LLWU_P24
DISABLED
PTD8/
LLWU_P24
I2C0_SCL
LPUART0_RX FB_A16
D4
PTD9
DISABLED
PTD9
I2C0_SDA
LPUART0_TX FB_A17
D3
PTD10
DISABLED
PTD10
C2
PTD11/
LLWU_P25
DISABLED
PTD11/
LLWU_P25
SPI2_PCS0
B2
PTD12
DISABLED
PTD12
SPI2_SCK
B3
PTD13
DISABLED
PTD13
A2
PTD14
DISABLED
PTD14
A3
PTD15
DISABLED
PTD15
J7
NC
NC
NC
K2
NC
NC
NC
ADC0_SE5b
SDHC0_
CLKIN
FTM3_FLT0
LPUART0_
RTS_b
FB_A18
LPUART0_
CTS_b
FB_A19
SDHC0_D4
FB_A20
SPI2_SOUT
SDHC0_D5
FB_A21
SPI2_SIN
SDHC0_D6
FB_A22
SPI2_PCS1
SDHC0_D7
FB_A23
EzPort
SPI1_PCS0
SPI1_SOUT
SPI1_SIN
5.2 Recommended connection for unused analog and digital
pins
Table 62 shows the recommended connections for analog interface pins if those
analog interfaces are not used in the customer's application
Kinetis K65 Sub-Family, Rev. 4, 04/2017
81
NXP Semiconductors
Pinout
Table 62. Recommended connection for unused analog interfaces
Pin Type
K65
Short recommendation
Detailed recommendation
Analog/non GPIO
ADCx/CMPx
Float
Analog input - Float
Analog/non GPIO
VREF_OUT
Float
Analog output - Float
Analog/non GPIO
DAC0_OUT, DAC1_OUT
Float
Analog output - Float
Analog/non GPIO
RTC_WAKEUP_B
Float
Analog output - Float
Analog/non GPIO
XTAL32
Float
Analog output - Float
Analog/non GPIO
EXTAL32
Float
Analog input - Float
GPIO/Analog
PTA18/EXTAL0
Float
Analog input - Float
GPIO/Analog
PTA19/XTAL0
Float
Analog output - Float
GPIO/Analog
PTx/ADCx
Float
Float (default is analog input)
GPIO/Analog
PTx/CMPx
Float
Float (default is analog input)
GPIO/Analog
PTx/TSIOx
Float
Float (default is analog input)
GPIO/Digital
PTA0/JTAG_TCLK
Float
Float (default is JTAG with
pulldown)
GPIO/Digital
PTA1/JTAG_TDI
Float
Float (default is JTAG with
pullup)
GPIO/Digital
PTA2/JTAG_TDO
Float
Float (default is JTAG with
pullup)
GPIO/Digital
PTA3/JTAG_TMS
Float
Float (default is JTAG with
pullup)
GPIO/Digital
PTA4/NMI_b
10kΩ pullup or disable and
float
Pull high or disable in PCR &
FOPT and float
GPIO/Digital
PTx
Float
Float (default is disabled)
USB
USB0_DP
Float
Float
USB
USB0_DM
Float
Float
USB
VREG_OUT
Tie to input and ground
through 10kΩ
Tie to input and ground
through 10kΩ
USB
VREG_IN0
Tie to output and ground
through 10kΩ
Tie to output and ground
through 10kΩ
USB
VREG_IN1
Tie to output and ground
through 10kΩ
Tie to output and ground
through 10kΩ
USB
USB1_VSS
Always connect to VSS
Always connect to VSS
USB
USB1_DP
Float
Float
USB
USB1_DM
Float
Float
USB
USB1_VBUS
Float
Float
VBAT
VBAT
Float
Float
VDDA
VDDA
Always connect to VDD
potential
Always connect to VDD
potential
VREFH
VREFH
Always connect to VDD
potential
Always connect to VDD
potential
VREFL
VREFL
Always connect to VSS
potential
Always connect to VSS
potential
Table continues on the next page...
82
NXP Semiconductors
Kinetis K65 Sub-Family, Rev. 4, 04/2017
Pinout
Table 62. Recommended connection for unused analog interfaces (continued)
Pin Type
VSSA
K65
VSSA
Short recommendation
Always connect to VSS
potential
Detailed recommendation
Always connect to VSS
potential
5.3 K65 Pinouts
The below figure shows the pinout diagram for the devices supported by this
document. Many signals may be multiplexed onto a single pin. To determine what
signals can be used on which pin, see the previous section.
Kinetis K65 Sub-Family, Rev. 4, 04/2017
83
NXP Semiconductors
Ordering parts
1
2
3
4
5
6
7
8
A
PTE0
PTD14
PTD15
PTD2/
LLWU_P13
PTD1
PTD0/
LLWU_P12
PTC25
PTC10
B
PTE1/
LLWU_P0
PTD12
PTD13
PTD3
PTD4/
LLWU_P14
PTC29
PTC24
PTC13
PTC12
PTC7
C
PTE2/
PTD11/
LLWU_P1 LLWU_P25
VSS
PTD5
PTD6/
LLWU_P15
PTC28
PTC19
PTC14
PTC9
PTD10
PTD9
PTD8/
LLWU_P24
PTC27
PTC18
PTC15
PTE7
PTE8
PTD7
PTC26
PTC17
D
PTE3
PTE5
9
10
11
12
13
PTC3/
LLWU_P7
PTC2
A
PTC4/
LLWU_P8
PTC1/
LLWU_P6
PTC0
B
PTC8
VSS
PTB23
PTB22
C
PTB21
PTB20
PTB19
PTB18
PTB17
D
PTC16
PTB15
PTB14
PTB13
PTB12
PTB11
E
PTE19
PTB16
PTB9
PTB8
PTB7
PTB6
PTB5
F
PTC11/
PTC6/
PTC5/
LLWU_P11 LLWU_P10 LLWU_P9
E
PTE4/
PTE6/
LLWU_P2 LLWU_P16
F
USB0_DM VREG_IN0
G
USB0_DP VREG_OUT
VSS
PTE11
VDD
VDD
VDD
VSS
PTB10
PTB3
PTB2
PTB1
PTB0/
LLWU_P5
G
H
USB1_DM VREG_IN1
PTE16
PTE12
VDD
VDD
VDD
VSS
PTB4
PTA30
PTA29
PTA28
PTA27
H
J
USB1_DP USB1_VBUS
VDDA
VSSA
TAMPER7
TAMPER6
NC
VSS
PTA31
PTA26
PTA25
PTA17
PTA16
J
VREFH
VREFL
TAMPER3
TAMPER5
PTE25/
LLWU_P21
PTE26
PTA8
PTA9
PTA24
PTA15
PTA14
K
PTE24
PTE27
PTA4/
LLWU_P3
PTA7
PTA13/
LLWU_P4
PTA12
RESET_b
L
VBAT
PTE28
PTA3
PTA2
PTA6
PTA11/
LLWU_P23
VSS
PTA19
M
XTAL32
EXTAL32
VSS
PTA0
PTA1
PTA5
PTA10/
LLWU_P22
VDD
PTA18
N
5
6
7
8
9
10
11
12
13
K
USB1_VSS
L
ADC1_DP1
NC
PTE9/
PTE10/
PTE17/
PTE18/
LLWU_P17 LLWU_P18 LLWU_P19 LLWU_P20
ADC0_DM0/ ADC0_SE16/
TAMPER1 TAMPER2 TAMPER4
ADC1_DM3 CMP1_IN2/
ADC0_SE21
ADC0_DP0/ ADC1_SE16/ DAC0_OUT/ TAMPER0/
RTC_
ADC1_DP3 CMP2_IN2/ CMP1_IN3/
ADC0_SE22 ADC0_SE23 WAKEUP_B
M
ADC1_DM1
N
VREF_OUT/ DAC1_OUT/
ADC1_DP0/ ADC1_DM0/ CMP1_IN5/ CMP0_IN4/
ADC0_DP3 ADC0_DM3 CMP0_IN5/ CMP2_IN3/
ADC1_SE18 ADC1_SE23
1
2
3
4
Figure 39. K65 169 MAPBGA Pinout Diagram
6 Ordering parts
84
NXP Semiconductors
Kinetis K65 Sub-Family, Rev. 4, 04/2017
Part identification
6.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable
part numbers for this device, go to nxp.com and perform a part number search for the
following device numbers: PK65 and MK65
7 Part identification
7.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
7.2 Format
Part numbers for this device have the following format:
Q K## A M FFF R T PP CC N
7.3 Fields
This table lists the possible values for each field in the part number (not all
combinations are valid):
Field
Description
Values
Q
Qualification status
• M = Fully qualified, general market flow
• P = Prequalification
K##
Kinetis family
• K65
• K66
A
Key attribute
• D = Cortex-M4 w/ DSP
• F = Cortex-M4 w/ DSP and FPU
M
Flash memory type
• N = Program flash only
• X = Program flash and FlexMemory
FFF
Program flash memory size
•
•
•
•
•
•
32 = 32 KB
64 = 64 KB
128 = 128 KB
256 = 256 KB
512 = 512 KB
768 = 768 KB
Table continues on the next page...
Kinetis K65 Sub-Family, Rev. 4, 04/2017
85
NXP Semiconductors
Terminology and guidelines
Field
Description
Values
• 1M0 = 1 MB
• 2M0 = 2 MB
R
Silicon revision
• Z = Initial
• (Blank) = Main
• A = Revision after main
T
Temperature range (°C)
• V = –40 to 105
• C = –40 to 85
PP
Package identifier
•
•
•
•
•
•
•
•
•
•
•
•
FM = 32 QFN (5 mm x 5 mm)
FT = 48 QFN (7 mm x 7 mm)
LF = 48 LQFP (7 mm x 7 mm)
LH = 64 LQFP (10 mm x 10 mm)
MP = 64 MAPBGA (5 mm x 5 mm)
LK = 80 LQFP (12 mm x 12 mm)
LL = 100 LQFP (14 mm x 14 mm)
MC = 121 MAPBGA (8 mm x 8 mm)
LQ = 144 LQFP (20 mm x 20 mm)
MD = 144 MAPBGA (13 mm x 13 mm)
MI= 169 MAPBGA (9 mm x 9 mm)
AC= 169 WLCSP (5.6 mm x 5.5 mm)
CC
Maximum CPU frequency (MHz)
•
•
•
•
•
•
•
5 = 50 MHz
7 = 72 MHz
10 = 100 MHz
12 = 120 MHz
15 = 150 MHz
16 = 168 MHz
18 = 180 MHz
N
Packaging type
• R = Tape and reel
• (Blank) = Trays
7.4 Example
This is an example part number:
MK65FN2M0VMI18
8 Terminology and guidelines
8.1 Definitions
Key terms are defined in the following table:
86
NXP Semiconductors
Kinetis K65 Sub-Family, Rev. 4, 04/2017
Terminology and guidelines
Term
Rating
Definition
A minimum or maximum value of a technical characteristic that, if exceeded, may cause
permanent chip failure:
• Operating ratings apply during operation of the chip.
• Handling ratings apply when the chip is not powered.
NOTE: The likelihood of permanent chip failure increases rapidly as soon as a characteristic
begins to exceed one of its operating ratings.
Operating requirement A specified value or range of values for a technical characteristic that you must guarantee during
operation to avoid incorrect operation and possibly decreasing the useful life of the chip
Operating behavior
A specified value or range of values for a technical characteristic that are guaranteed during
operation if you meet the operating requirements and any other specified conditions
Typical value
A specified value for a technical characteristic that:
• Lies within the range of values specified by the operating behavior
• Is representative of that characteristic during operation when you meet the typical-value
conditions or other specified conditions
NOTE: Typical values are provided as design guidelines and are neither tested nor
guaranteed.
8.2 Examples
EX
AM
PL
E
Operating rating:
EX
AM
PL
E
Operating requirement:
EX
AM
PL
E
Operating behavior that includes a typical value:
Kinetis K65 Sub-Family, Rev. 4, 04/2017
87
NXP Semiconductors
Terminology and guidelines
8.3 Typical-value conditions
Typical values assume you meet the following conditions (or other conditions as
specified):
Symbol
Description
Value
Unit
TA
Ambient temperature
25
°C
VDD
Supply voltage
3.3
V
8.4 Relationship between ratings and operating requirements
g(
g
tin
era
Op
in
rat
)
in.
)
in.
m
t (m
en
m
g
tin
era
Op
e
uir
req
g
tin
era
Op
t
en
em
uir
q
re
ax
(m
.)
x
ma
g(
g
tin
era
in
rat
.)
Op
Fatal range
Degraded operating range
Normal operating range
Degraded operating range
Fatal range
Expected permanent failure
- No permanent failure
- Possible decreased life
- Possible incorrect operation
- No permanent failure
- Correct operation
- No permanent failure
- Possible decreased life
- Possible incorrect operation
Expected permanent failure
–∞
∞
Operating (power on)
dli
n
Ha
ng
x.)
n.)
mi
g(
in
rat
li
nd
Ha
ng
a
(m
ing
rat
Fatal range
Handling range
Fatal range
Expected permanent failure
No permanent failure
Expected permanent failure
–∞
∞
Handling (power off)
8.5 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
• Never exceed any of the chip’s ratings.
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal
operation (for example, during power sequencing), limit the duration as much as
possible.
88
NXP Semiconductors
Kinetis K65 Sub-Family, Rev. 4, 04/2017
Revision History
9 Revision History
The following table provides a revision history for this document.
Table 63. Revision History
Rev. No.
Date
Substantial Changes
0
02/2015
1
04/2015
• Editorial change
• Updated OTG/EH and BC rev. 1.2 specification references in USB Full Speed
Transceiver and High Speed PHY specifications section
• Updated USBDCD electrical specifications table
• Updated the typical values and maximum values of specs in Power consumption
operating behaviors table
• Removed PSTOP2 current from Power consumption operating behaviors table
• Updated the values of DS5 and DS7 in Master mode DSPI timing (full voltage
range) table
• Updated the footnote and description of VDIO, VAIO and ID in Voltage and current
operating ratings table
• Updated the values and description of specs in Voltage and current operating
requirements table
• Updated the leakage current specs in Voltage and current operating behaviors table
• Added Notes column in Thermal operating requirements
• Updated the values of 48MHz IRC in Low power mode peripheral adders table
• Added new footnotes for IINRUSH in USB VREG electrical specifications table to
better document operation.
• Updated the figures "SDRAM write timing diagram" and SDRAM read timing
diagram" in the section "SDRAM controller specifications."
• Updated the pinout table, and pinout diagrams in the section "Pinouts."
2
05/2015
• Added new footnotes for IINRUSH in USB VREG electrical specifications table to
better document operation.
3
01/2016
•
•
•
•
•
•
4
03/2017
• Removed the verbiage of "except RTC_WAKEUP pins" from the description for RPU
and RPD in Voltage and current operating behaviors table
• Updated the unit of ADC conversion rate from "Kbps" to "kS/s" in 16-bit ADC
operating conditions table
• Added MII signal switching specifications table and RMII signal switching
specifications table for full voltage range
• Added MDIO serial management timing specifications section
• Updated I2C switching specifications section
• Updated the minimum and maximum value of Voltage reference output with factory
trim in VREF full-range operating requirements table in Voltage reference electrical
specifications section
Initial Release
Updated the symbol in footnote of Thermal Operating specs
Updated the description of PLL operating current in MCG specifications table
Updated the values of IRC48M specifications table
Added USB FS and USB HS logo in front page
Updated Terminology and guidelines section
Updated the maximum values of IDD_LLS2 and IDD_LLS3 in Power consumption
operating behaviors table
Kinetis K65 Sub-Family, Rev. 4, 04/2017
89
NXP Semiconductors
How to Reach Us:
Home Page:
nxp.com
Web Support:
nxp.com/support
Information in this document is provided solely to enable system and software
implementers to use NXP products. There are no express or implied copyright
licenses granted hereunder to design or fabricate any integrated circuits based
on the information in this document. NXP reserves the right to make changes
without further notice to any products herein.
NXP makes no warranty, representation, or guarantee regarding the suitability of
its products for any particular purpose, nor does NXP assume any liability arising
out of the application or use of any product or circuit, and specifically disclaims
any and all liability, including without limitation consequential or incidental
damages. “Typical” parameters that may be provided in NXP data sheets and/or
specifications can and do vary in different applications, and actual performance
may vary over time. All operating parameters, including “typicals,” must be
validated for each customer application by customer's technical experts. NXP
does not convey any license under its patent rights nor the rights of others. NXP
sells products pursuant to standard terms and conditions of sale, which can be
found at the following address: nxp.com/SalesTermsandConditions.
NXP, the NXP logo, NXP SECURE CONNECTIONS FOR A SMARTER
WORLD, Freescale, the Freescale logo, and Kinetis are trademarks of NXP B.V.
All other product or service names are the property of their respective owners.
ARM, the ARM powered logo, and Cortex are registered trademarks of ARM
Limited (or its subsidiaries) in the EU and/or elsewhere. The USB-IF Logo is a
registered trademark of USB Implementers Forum, Inc. All rights reserved.
© 2013–2017 NXP B.V.
Document Number K65P169M180SF5V2
Revision 4, 04/2017