Micron MT48LC8M32B2TG Synchronous dram Datasheet

PRELIMINARY
256Mb: x32
SDRAM
SYNCHRONOUS
DRAM
MT48LC8M32B2 - 2 Meg x 32 x 4 banks
For the latest data sheet, please refer to the Micron Web
site: www.micron.com/sdramds
FEATURES
• PC100 functionality
• Fully synchronous; all signals registered on
positive edge of system clock
• Internal pipelined operation; column address can
be changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto Precharge, includes CONCURRENT AUTO
PRECHARGE, and Auto Refresh Modes
• Self Refresh Mode
• 64ms, 4,096-cycle refresh (15.6µs/row)
• LVTTL-compatible inputs and outputs
• Single +3.3V ±0.3V power supply
• Supports CAS latency of 1, 2, and 3
OPTIONS
Pin Assignment (Top View)
86-Pin TSOP
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDD
DQM0
WE#
CAS#
RAS#
CS#
A11
BA0
BA1
A10
A0
A1
A2
DQM2
VDD
NC
DQ16
VSSQ
DQ17
DQ18
VDDQ
DQ19
DQ20
VSSQ
DQ21
DQ22
VDDQ
DQ23
VDD
MARKING
• Configuration
8 Meg x 32 (2 Meg x 32 x 4 banks)
8M32B2
• Package
86-pin TSOP (400 mil)
86-pin TSOP (400 mil) Lead-free
90-ball FBGA (8mm x 13mm)
90-ball FBGA (8mm x 13mm) Lead-free
• Timing (Cycle Time)
6ns (166 MHz)
7ns (143 MHz)
TG
P
F5 1
B5 1
-6
-7
• Operating Temperature Range
Commercial (0° to +70°C)
Industrial (-40°C to +85°C)
None
IT 1
NOTE: 1. Available on -7 only
Part Number Example:
MT48LC8M32B2TG-7
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VSS
DQM1
NC
NC
CLK
CKE
A9
A8
A7
A6
A5
A4
A3
DQM3
VSS
NC
DQ31
VDDQ
DQ30
DQ29
VSSQ
DQ28
DQ27
VDDQ
DQ26
DQ25
VSSQ
DQ24
VSS
Note: The # symbol indicates signal is active LOW.
KEY TIMING PARAMETERS
SPEED
GRADE
-6
-7
CLOCK
ACCESS TIME
FREQUENCY
CL = 3*
166 MHz
143 MHz
5.5ns
6.0ns
SETUP
TIME
HOLD
TIME
1.5ns
2ns
1ns
1ns
8 Meg x 32
Configuration
Refresh Count
*CL = CAS (READ) latency
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256MbSDRAMx32.p65 – Rev. B; Pub. 03/04
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2 Meg x 32 x 4 banks
4K
Row Addressing
Bank Addressing
4K (A0–A11)
4 (BA0, BA1)
Column Addressing
512 (A0–A8)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS.
PRELIMINARY
256Mb: x32
SDRAM
90-Ball FBGA Assignment
(Top View)
1
2
3
DQ26
DQ24
DQ28
4
5
6
7
8
9
VSS
VDD
DQ23
DQ21
VDDQ
VSSQ
VDDQ
VSSQ
DQ19
VSSQ
DQ27
DQ25
DQ22
DQ20
VDDQ
VSSQ
DQ29
DQ30
DQ17
DQ18
VDDQ
VDDQ
DQ31
NC
NC
DQ16
VSSQ
VSS
DQM3
A3
A2
DQM2
VDD
A4
A5
A6
A10
A0
A1
A7
A8
NC
NC
BA1
A11
CLK
CKE
A9
BA0
CS#
RAS#
DQM1
NC
NC
CAS#
WE#
DQM0
VDDQ
DQ8
VSS
VDD
DQ7
VSSQ
VSSQ
DQ10
DQ9
DQ6
DQ5
VDDQ
VSSQ
DQ12
DQ14
DQ1
DQ3
VDDQ
DQ11
VDDQ
VSSQ
VDDQ
VSSQ
DQ4
DQ13
DQ15
VSS
VDD
DQ0
DQ2
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
09005aef80cd8e48
256MbSDRAMx32.p65 – Rev. B; Pub. 03/04
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
PRELIMINARY
256Mb: x32
SDRAM
The SDRAM provides for programmable READ or
WRITE burst lengths of 1, 2, 4, or 8 locations, or the full
page, with a burst terminate option. An auto precharge
function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst sequence.
The 256Mb SDRAM uses an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch
architectures, but it also allows the column address to
be changed on every clock cycle to achieve a highspeed, fully random access. Precharging one bank
while accessing one of the other three banks will hide
the precharge cycles and provide seamless, highspeed, random-access operation.
The 256Mb SDRAM is designed to operate in 3.3V
memory systems. An auto refresh mode is provided,
along with a power-saving, power-down mode. All inputs and outputs are LVTTL-compatible.
SDRAMs offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic
column-address generation, the ability to interleave
between internal banks to hide precharge time and
the capability to randomly change column addresses
on each clock cycle during a burst access.
256Mb (x32) SDRAM PART NUMBER
PART NUMBER
MT48LC8M32B2TG
ARCHITECTURE
8 Meg x 32
GENERAL DESCRIPTION
The 256Mb SDRAM is a high-speed CMOS, dynamic
random-access memory containing 268,435,456-bits.
It is internally configured as a quad-bank DRAM with a
synchronous interface (all signals are registered on the
positive edge of the clock signal, CLK). Each of the
67,108,864-bit banks is organized as 4,096 rows by 512
columns by 32 bits.
Read and write accesses to the SDRAM are burst
oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by
a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used
to select the bank and row to be accessed (BA0, BA1
select the bank, A0–A11 select the row). The address
bits registered coincident with the READ or WRITE command are used to select the starting column location
for the burst access.
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256MbSDRAMx32.p65 – Rev. B; Pub. 03/04
3
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©2003 Micron Technology, Inc.
PRELIMINARY
256Mb: x32
SDRAM
TABLE OF CONTENTS
Functional Block Diagram - 8 Meg x 32 .................
Pin Descriptions ...........................................................
5
6
Functional Description ..........................................
Initialization ...........................................................
Register Definition .................................................
Mode Register ...................................................
Burst Length ................................................
Burst Type ....................................................
CAS Latency ................................................
Operating Mode .........................................
Write Burst Mode .......................................
Commands ..................................................................
Truth Table 1 (Commands and DQM Operation) ...........
Command Inhibit .................................................
No Operation (NOP) ............................................
Load Mode Register ...............................................
Active .......................................................................
Read .......................................................................
Write .......................................................................
Precharge .................................................................
Auto Precharge .......................................................
Burst Terminate ......................................................
Auto Refresh ...........................................................
Self Refresh ..............................................................
Operation ....................................................................
Bank/Row Activation ...........................................
Reads .......................................................................
Writes .......................................................................
Precharge .................................................................
Power-Down ..........................................................
Clock Suspend ........................................................
Burst Read/Single Write ........................................
Concurrent Auto Precharge .................................
Write With Auto Precharge .................................
9
9
9
9
9
10
11
11
11
12
12
13
13
13
13
13
13
13
13
14
14
14
15
15
16
22
24
24
25
25
26
27
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256MbSDRAMx32.p65 – Rev. B; Pub. 03/04
Truth Table 2 (CKE) .....................................................
Truth Table 3 (Current State, Same Bank) ......................
Truth Table 4 (Current State, Different Bank) .................
28
29
31
Absolute Maximum Ratings ...................................... 33
DC Electrical Characteristics
and Operating Conditions ......................................... 33
IDD Specifications and Conditions ........................... 33
Capacitance .................................................................. 34
AC Electrical Characteristics (Timing Table) ..... 34
AC Functional Characteristics ............................ 35
Timing Waveforms
Initialize and Load Mode Register ......................
Power-Down Mode ...............................................
Clock Suspend Mode ............................................
Auto Refresh Mode ...............................................
Self Refresh Mode ..................................................
Reads
Read – Single Read ...........................................
Read – Without Auto Precharge ...................
Read – With Auto Precharge ..........................
Alternating Bank Read Accesses .....................
Read – Full-Page Burst .....................................
Read – DQM Operation .................................
Writes
Write – Single Write .........................................
Write – Without Auto Precharge ..................
Write – With Auto Precharge ........................
Alternating Bank Write Accesses ...................
Write – Full-Page Burst ....................................
Write – DQM Operation ................................
Package
86-Pin TSOP ......................................................
90-Ball FBGA ....................................................
4
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
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©2003 Micron Technology, Inc.
PRELIMINARY
256Mb: x32
SDRAM
FUNCTIONAL BLOCK DIAGRAM
8 Meg x 32 SDRAM
CKE
CLK
COMMAND
DECODE
CS#
WE#
CAS#
RAS#
CONTROL
LOGIC
BANK3
BANK2
BANK1
BANK0
MODE REGISTER
REFRESH 12
COUNTER
12
ROWADDRESS
MUX
12
12
BANK0
ROWADDRESS
LATCH
&
DECODER
4096
BANK0
MEMORY
ARRAY
(4,096 x 512 x 32)
4
DQM0–
DQM3
SENSE AMPLIFIERS
32
4,096
14
ADDRESS
REGISTER
2
DATA
OUTPUT
REGISTER
I/O GATING
DQM MASK LOGIC
READ DATA LATCH
WRITE DRIVERS
2
A0–A11,
BA0, BA1
4
BANK
CONTROL
LOGIC
32
32
512
(x32)
DQ0–
DQ31
DATA
INPUT
REGISTER
COLUMN
DECODER
89
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256MbSDRAMx32.p65 – Rev. B; Pub. 03/04
COLUMNADDRESS
COUNTER/
LATCH
9
5
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©2003 Micron Technology, Inc.
PRELIMINARY
256Mb: x32
SDRAM
PIN DESCRIPTIONS
PIN NUMBERS
DESCRIPTION
68
CLK
Input
Clock: CLK is driven by the system clock. All SDRAM input signals
are sampled on the positive edge of CLK. CLK also increments
the internal burst counter and controls the output registers.
67
CKE
Input
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the
CLK signal. Deactivating the clock provides PRECHARGE POWERDOWN and SELF REFRESH operation (all banks idle), ACTIVE
POWER-DOWN (row active in any bank) or CLOCK SUSPEND
operation (burst/access in progress). CKE is synchronous except
after the device enters power-down and self refresh modes,
where CKE becomes asynchronous until after exiting the same
mode. The input buffers, including CLK, are disabled during
power-down and self refresh modes, providing low standby
power. CKE may be tied HIGH.
20
CS#
Input
Chip Select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked
when CS# is registered HIGH. CS# provides for external bank
selection on systems with multiple banks. CS# is considered part
of the command code.
17, 18, 19
WE#,
CAS#,
RAS#
Input
Command Inputs: WE# , CAS#, and RAS# (along with CS#)
define the command being entered.
16, 71, 28, 59
DQM0–
DQM3
Input
Input/Output Mask: DQM is sampled HIGH and is an input mask
signal for write accesses and an output enable signal for read
accesses. Input data is masked during a WRITE cycle. The output
buffers are placed in a High-Z state (two-clock latency) during a
READ cycle. DQM0 corresponds to DQ0–DQ7, DQM1 corresponds
to DQ8-DQ15, DQM2 corresponds to DQ16–DQ23 and DQM3
corresponds to DQ24–DQ31. DQM0–DQM3 are considered same
state when referenced as DQM.
22, 23
25-27, 60-66, 24, 21
2,
74,
85,
40,
SYMBOL TYPE
4, 5, 7, 8, 10, 11, 13,
76, 77, 79, 80, 82, 83,
31, 33, 34, 36, 37, 39,
42, 45, 47, 48, 50, 51,
53, 54, 56
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256MbSDRAMx32.p65 – Rev. B; Pub. 03/04
BA0, BA1 Input
A0-A11
DQ0–
DQ31
Input
Bank Address Input(s): BA0 and BA1 define to which bank the
ACTIVE, READ, WRITE, or PRECHARGE command is being
applied.
Address Inputs: A0–A11 are sampled during the ACTIVE command (row-address A0–A10) and READ/WRITE command
(column-address A0–A8 with A10 defining auto precharge) to
select one location out of the memory array in the respective
bank. A10 is sampled during a PRECHARGE command to
determine if all banks are to be precharged (A10 [HIGH]) or
bank selected by BA0, BA1 (LOW). The address inputs also
provide the op-code during a LOAD MODE REGISTER command.
Input/ Data I/Os: Data bus.
Output
6
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©2003 Micron Technology, Inc.
PRELIMINARY
256Mb: x32
SDRAM
PIN DESCRIPTIONS (continued)
PIN NUMBERS
14, 30, 57, 69, 70, 73
3, 9, 35, 41, 49, 55,
75, 81
6, 12, 32, 38, 46, 52,
78, 84
1, 15, 29, 43
44, 58, 72, 86
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256MbSDRAMx32.p65 – Rev. B; Pub. 03/04
SYMBOL TYPE
NC
–
VDDQ
Supply
V SS Q
Supply
VDD
VSS
Supply
Supply
DESCRIPTION
No Connect: These pins should be left unconnected. Pin 70 is
reserved for SSTL reference voltage supply.
DQ Power Supply: Isolated on the die for improved noise
immunity.
DQ Ground: Provide isolated ground to DQs for improved noise
immunity.
Power Supply: +3.3V ±0.3V.
Ground.
7
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©2003 Micron Technology, Inc.
PRELIMINARY
256Mb: x32
SDRAM
BALL DESCRIPTIONS
90-BALL FBGA
SYMBOL
TYPE
J1
CLK
Input
Clock: CLK is driven by the system clock. All SDRAM input signals are sampled
on the positive edge of CLK. CLK also increments the internal burst counter
and controls the output registers.
J2
CKE
Input
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal.
Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH
operation (all banks idle), ACTIVE POWER-DOWN (row active in any bank) or
CLOCK SUSPEND operation (burst/access in progress). CKE is synchronous except
after the device enters power-down and self refresh modes, where CKE
becomes asynchronous until after exiting the same mode. The input buffers,
including CLK, are disabled during power-down and self refresh modes,
providing low standby power. CKE may be tied HIGH.
J8
CS#
Input
Chip Select: CS# enables (registered LOW) and disables (registered HIGH) the
command decoder. All commands are masked when CS# is registered HIGH. CS#
provides for external bank selection on systems with multiple banks. CS# is
considered part of the command code.
J9, K7, K8
RAS#, CAS#
WE#
Input
Command Inputs: RAS#, CAS#, and WE# (along with CS#) define the
command being entered.
K9, K1, F8, F2
DQM0–3
Input
Input/Output Mask: DQM is sampled HIGH and is an input mask signal for write
accesses and an output enable signal for read accesses. Input data is masked
during a WRITE cycle. The output buffers are placed in a High-Z state (twoclock latency) when during a READ cycle. DQM0 corresponds to DQ0–DQ7,
DQM1 corresponds to DQ8–DQ15, DQM2 corresponds to DQ16–DQ23 and DQM3
corresponds to DQ24–DQ31. DQM0-3 are considered same state when
referenced as DQM.
J7, H8
BA0, BA1
Input
Bank Address Input(s): BA0 and BA1 define to which bank the ACTIVE, READ,
WRITE or PRECHARGE command is being applied. These pins also provide the
op-code during a LOAD MODE REGISTER command
G8, G9, F7, F3, G1, G2,
G3, H1, H2, J3, G7, H9
A0–A11
Input
Address Inputs: A0–A11 are sampled during the ACTIVE command (rowaddress A0–A11) and READ/WRITE command (column-address A0–A8; with A10
defining auto precharge) to select one location out of the memory array in the
respective bank. A10 is sampled during a PRECHARGE command to determine if
all banks are to be precharged (A10 HIGH) or bank selected by BA0, BA1 (LOW).
The address inputs also provide the op-code during a LOAD MODE REGISTER
command.
R8, N7, R9, N8, P9, M8,
M7, L8, L2, M3, M2, P1, N2,
R1, N3, R2, E8, D7, D8, B9,
C8, A9, C7, A8, A2, C3, A1,
C2, B1, D2, D3, E2
DQ0–DQ31
I/O
E3, E7, H3, H7, K2, K3
NC
–
B2, B7, C9, D9, E1,
L1, M9, N9, P2, P7
VDDQ
Supply
DQ Power: Provide isolated power to DQs for improved noise immunity.
B8, B3, C1, D1, E9,
L9, M1, N1, P3, P8
V SS Q
Supply
DQ Ground: Provide isolated ground to DQs for improved noise immunity.
A7, F9, L7, R7
VDD
Supply
Power Supply: Voltage dependant on option.
A3, F1, L3, R3
V SS
Supply
Ground.
09005aef80cd8e48
256MbSDRAMx32.p65 – Rev. B; Pub. 03/04
DESCRIPTION
Data Input/Output: Data bus
No Connect: These pins should be left unconnected.
H3 is a not connect for this part but may be used as A12 in future designs.
8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
PRELIMINARY
256Mb: x32
SDRAM
FUNCTIONAL DESCRIPTION
REGISTER DEFINITION
In general, this 256Mb SDRAM (2 Meg x 32 x 4 banks)
is a quad-bank DRAM that operates at 3.3V and includes a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK).
Each of the 67,108,864-bit banks is organized as 4,096
rows by 512 columns by 32-bits.
Read and write accesses to the SDRAM are burst
oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by
a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used
to select the bank and row to be accessed (BA0 and BA1
select the bank, A0–A11 select the row). The address
bits (A0–A8) registered coincident with the READ or
WRITE command are used to select the starting column location for the burst access.
Prior to normal operation, the SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions and device operation.
Mode Register
The Mode Register is used to define the specific
mode of operation of the SDRAM. This definition includes the selection of a burst length, a burst type, a
CAS latency, an operating mode and a write burst mode,
as shown in Figure 1. The Mode Register is programmed
via the LOAD MODE REGISTER command and will retain the stored information until it is programmed again
or the device loses power.
Mode Register bits M0–M2 specify the burst length,
M3 specifies the type of burst (sequential or interleaved), M4–M6 specify the CAS latency, M7 and M8
specify the operating mode, M9 specifies the write burst
mode, and M10, M11, BA0, and BA1 are reserved for
future use.
The Mode Register must be loaded when all banks
are idle, and the controller must wait the specified time
before initiating the subsequent operation. Violating
either of these requirements will result in unspecified
operation.
Burst Length
Read and write accesses to the SDRAM are burst
oriented, with the burst length being programmable,
as shown in Figure 1. The burst length determines the
maximum number of column locations that can be accessed for a given READ or WRITE command. Burst
lengths of 1, 2, 4, or 8 locations are available for both the
sequential and the interleaved burst types, and a fullpage burst is available for the sequential type. The
full-page burst is used in conjunction with the BURST
TERMINATE command to generate arbitrary burst
lengths.
Reserved states should not be used, as unknown
operation or incompatibility with future versions may
result.
When a READ or WRITE command is issued, a block
of columns equal to the burst length is effectively selected. All accesses for that burst take place within this
block, meaning that the burst will wrap within the block
if a boundary is reached. The block is uniquely selected by A1–A8 when the burst length is set to two; by
A2–A8 when the burst length is set to four; and by A3–
A8 when the burst length is set to eight. The remaining
(least significant) address bit(s) is (are) used to select
the starting location within the block. Full-page bursts
wrap within the page if the boundary is reached.
INITIALIZATION
SDRAMs must be powered up and initialized in a
predefined manner. Operational procedures other
than those specified may result in undefined operation. Once power is applied to VDD and VDDQ (simultaneously) and the clock is stable (stable clock is defined
as a signal cycling within timing constraints specified
for the clock pin), the SDRAM requires a 100µs delay
prior to issuing any command other than a COMMAND
INHIBIT or a NOP. Starting at some point during this
100µs period and continuing at least through the end
of this period, COMMAND INHIBIT or NOP commands
should be applied.
Once the 100µs delay has been satisfied with at
least one COMMAND INHIBIT or NOP command having been applied, a PRECHARGE command should be
applied. All banks must then be precharged, thereby
placing the device in the all banks idle state.
Once in the idle state, two AUTO REFRESH cycles
must be performed. After the AUTO REFRESH cycles
are complete, the SDRAM is ready for Mode Register
programming. Because the Mode Register will power
up in an unknown state, it should be loaded prior to
applying any operational command.
09005aef80cd8e48
256MbSDRAMx32.p65 – Rev. B; Pub. 03/04
9
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
PRELIMINARY
256Mb: x32
SDRAM
Burst Type
Accesses within a given burst may be programmed
to be either sequential or interleaved; this is referred to
as the burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 1.
Table 1
Burst Definition
Burst
Length
2
Figure 1
Mode Register Definition
4
A11
11
A10 A9
10
9
A8
8
A6
A7
6
7
A5
5
A4
A3
4
Reserved* WB Op Mode CAS Latency
3
2
BT
A1
A2
1
Address Bus
A0
0
Mode Register (Mx)
Burst length
8
*Should program
M10, M11, BA0,
BA1 = “0” to ensure
compatibility with
future devices.
Burst Length
M2 M1 M0
M3 = 0
M3 = 1
0 0 0
1
1
0 0 1
2
2
0 1 0
4
4
0 1 1
8
8
1 0 0
Reserved
Reserved
1 0 1
Reserved
Reserved
1 1 0
Reserved
Reserved
1 1 1
Full Page
Reserved
Full
Page
(256)
NOTE:
Burst Type
M3
0
Sequential
1
Interleave
M6 M5 M4
CAS Latency
0 0 0
Reserved
0 0 1
1
0 1 0
2
0 1 1
3
1 0 0
Reserved
1 0 1
Reserved
1 1 0
Reserved
1 1 1
Reserved
M8
M7
M6 - M0
Operating Mode
0
0
Defined
Standard operation
-
-
-
M9
Write Burst Mode
0
Programmed Burst Length
1
Single Location Access
09005aef80cd8e48
256MbSDRAMx32.p65 – Rev. B; Pub. 03/04
Starting Column
Address
A0
0
1
A1 A0
0
0
0
1
1
0
1
1
A2 A1 A0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Order of Accesses Within a Burst
Type = Sequential Type = Interleaved
0-1
1-0
0-1
1-0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
Cn, Cn + 1, Cn + 2
n = A0–A8
Cn + 3, Cn + 4...
…Cn - 1,
(Location 0 –256)
Cn…
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
Not Supported
1. For a burst length of two, A1–A8 select the blockof-two burst; A0 selects the starting column
within the block.
2. For a burst length of four, A2–A8 select the blockof-four burst; A0–A1 select the starting column
within the block.
3. For a burst length of eight, A3–A8 select the blockof-eight burst; A0–A2 select the starting column
within the block.
4. For a full-page burst, the full row is selected and
A0–A8 select the starting column.
5. Whenever a boundary of the block is reached
within a given sequence above, the following
access wraps within the block.
6. For a burst length of one, A0–A8 select the unique
column to be accessed, and mode register bit M3
is ignored.
All other states reserved
10
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SDRAM
CAS Latency
The CAS latency is the delay, in clock cycles, between the registration of a READ command and the
availability of the first piece of output data. The latency can be set to one, two or three clocks.
If a READ command is registered at clock edge n,
and the latency is m clocks, the data will be available by
clock edge n + m. The DQs will start driving as a result of
the clock edge one cycle earlier (n + m - 1), and provided
that the relevant access times are met, the data will be
valid by clock edge n + m. For example, assuming that
the clock cycle time is such that all relevant access times
are met, if a READ command is registered at T0 and the
latency is programmed to two clocks, the DQs will start
driving after T1 and the data will be valid by T2, as
shown in Figure 2. Table 2 below indicates the operating frequencies at which each CAS latency setting can
be used.
Reserved states should not be used as unknown
operation or incompatibility with future versions may
result.
Operating Mode
The normal operating mode is selected by setting
M7 and M8 to zero; the other combinations of values for
M7 and M8 are reserved for future use and/or test
modes. The programmed burst length applies to both
READ and WRITE bursts.
Test modes and reserved states should not be used
because unknown operation or incompatibility with
future versions may result.
Write Burst Mode
When M9 = 0, the burst length programmed via
M0–M2 applies to both READ and WRITE bursts; when
M9 = 1, the programmed burst length applies to READ
bursts, but write accesses are single-location (nonburst)
accesses.
Figure 2
CAS Latency
T0
T1
Table 2
CAS Latency
T2
CLK
COMMAND
READ
ALLOWABLE OPERATING
FREQUENCY (MHz)
NOP
tLZ
tOH
DOUT
DQ
tAC
SPEED
-6
-7
CAS Latency = 1
T0
T1
T2
NOP
NOP
CAS
LATENCY = 1
≤ 50
≤ 50
CAS
LATENCY = 2
≤ 100
≤ 100
CAS
LATENCY = 3
≤ 166
≤ 143
T3
CLK
COMMAND
READ
tLZ
tOH
DOUT
DQ
tAC
CAS Latency = 2
T0
T1
T2
T3
T4
NOP
NOP
NOP
CLK
COMMAND
READ
tLZ
tOH
DOUT
DQ
tAC
CAS Latency = 3
DON’T CARE
UNDEFINED
09005aef80cd8e48
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SDRAM
COMMANDS
Truth Table 1 provides a quick reference of available commands. This is followed by a written description of each command. Three additional Truth Tables
appear following the Operation section; these tables
provide current state/next state information.
TRUTH TABLE 1 – COMMANDS AND DQM OPERATION
(Note: 1)
NAME (FUNCTION)
CS# RAS# CAS# WE# DQM
ADDR
DQs
NOTES
COMMAND INHIBIT (NOP)
H
X
X
X
X
X
X
NO OPERATION (NOP)
L
H
H
H
X
X
X
ACTIVE (Select bank and activate row)
L
L
H
H
X
Bank/Row
X
3
H
L/H 8
Bank/Col
X
4
Bank/Col
Valid
4
READ (Select bank and column, and start READ burst)
L
H
L
WRITE (Select bank and column, and start WRITE burst)
L
H
L
L
L/H 8
BURST TERMINATE
L
H
H
L
X
X
Active
PRECHARGE (Deactivate row in bank or banks)
L
L
H
L
X
Code
X
5
AUTO REFRESH or SELF REFRESH
(Enter self refresh mode)
L
L
L
H
X
X
X
6, 7
LOAD MODE REGISTER
L
L
L
L
X
Op-Code
X
2
Write Enable/Output Enable
–
–
–
–
L
–
Active
8
Write Inhibit/Output High-Z
–
–
–
–
H
–
High-Z
8
NOTE: 1.
2.
3.
4.
5.
6.
7.
8.
CKE is HIGH for all commands shown except SELF REFRESH.
A0–A11 define the op-code written to the Mode Register.
A0–A11 provide row address, BA0 and BA1 determine which bank is made active.
A0–A8 provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while
A10 LOW disables the auto precharge feature; BA0 and BA1 determine which bank is being read from
or written to.
A10 LOW: BA0 and BA1 determine the bank being precharged. A10 HIGH: All banks precharged and
BA0 and BA1 are “Don’t Care.”
This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is LOW.
Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay). DQM0
controls DQ0–DQ7; DQM1 controls DQ8–DQ15; DQM2 controls DQ16–DQ23; and DQM3 controls
DQ24–DQ31.
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PRELIMINARY
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SDRAM
COMMAND INHIBIT
The COMMAND INHIBIT function prevents new
commands from being executed by the SDRAM, regardless of whether the CLK signal is enabled. The
SDRAM is effectively deselected. Operations already
in progress are not affected.
WRITE
The WRITE command is used to initiate a burst write
access to an active row. The value on the BA0 and BA1
inputs selects the bank, and the address provided on
inputs A0-A8 selects the starting column location. The
value on input A10 determines whether or not auto
precharge is used. If auto precharge is selected, the row
being accessed will be precharged at the end of the
WRITE burst; if auto precharge is not selected, the row
will remain open for subsequent accesses. Input data
appearing on the DQs is written to the memory array
subject to the DQM input logic level appearing coincident with the data. If a given DQM signal is registered
LOW, the corresponding data will be written to memory;
if the DQM signal is registered HIGH, the corresponding data inputs will be ignored, and a WRITE will not be
executed to that byte/column location.
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to
perform a NOP to an SDRAM which is selected (CS# is
LOW). This prevents unwanted commands from being
registered during idle or wait states. Operations already
in progress are not affected.
LOAD MODE REGISTER
The mode register is loaded via inputs A0-A11. See
mode register heading in the Register Definition section. The LOAD MODE REGISTER command can only
be issued when all banks are idle, and a subsequent
executable command cannot be issued until tMRD is
met.
PRECHARGE
The PRECHARGE command is used to deactivate
the open row in a particular bank or the open row in all
banks. The bank(s) will be available for a subsequent
row access a specified time (tRP) after the PRECHARGE
command is issued. Input A10 determines whether
one or all banks are to be precharged, and in the case
where only one bank is to be precharged, inputs BA0
and BA1 select the bank. Otherwise BA0 and BA1 are
treated as “Don’t Care.” Once a bank has been
precharged, it is in the idle state and must be activated
prior to any READ or WRITE commands being issued to
that bank.
ACTIVE
The ACTIVE command is used to open (or activate)
a row in a particular bank for a subsequent access. The
value on the BA0 and BA1 inputs selects the bank, and
the address provided on inputs A0–A11 selects the row.
This row remains active (or open) for accesses until a
PRECHARGE command is issued to that bank. A
PRECHARGE command must be issued before opening a different row in the same bank.
READ
The READ command is used to initiate a burst read
access to an active row. The value on the BA0 and BA1
(B1) inputs selects the bank, and the address provided
on inputs A0–A8 selects the starting column location.
The value on input A10 determines whether or not auto
precharge is used. If auto precharge is selected, the row
being accessed will be precharged at the end of the
READ burst; if auto precharge is not selected, the row
will remain open for subsequent accesses. Read data
appears on the DQs subject to the logic level on the
DQM inputs two clocks earlier. If a given DQMx signal
was registered HIGH, the corresponding DQs will be
High-Z two clocks later; if the DQMx signal was registered LOW, the corresponding DQs will provide valid
data. DQM0 corresponds to DQ0–DQ7, DQM1 corresponds to DQ8–DQ15, DQM2 corresponds to DQ16–
DQ23 and DQM3 corresponds to DQ24–DQ31.
09005aef80cd8e48
256MbSDRAMx32.p65 – Rev. B; Pub. 03/04
AUTO PRECHARGE
Auto precharge is a feature which performs the
same individual-bank PRECHARGE function described above, without requiring an explicit command.
This is accomplished by using A10 to enable auto
precharge in conjunction with a specific READ or WRITE
command. A PRECHARGE of the bank/row that is addressed with the READ or WRITE command is automatically performed upon completion of the READ or
WRITE burst, except in the full-page burst mode, where
auto precharge does not apply. Auto precharge is nonpersistent in that it is either enabled or disabled for
each individual READ or WRITE command.
Auto precharge ensures that the precharge is initiated at the earliest valid stage within a burst. The user
must not issue another command to the same bank
until the precharge time (tRP) is completed. This is
determined as if an explicit PRECHARGE command
was issued at the earliest possible time, as described
for each burst type in the Operation section of this data
sheet.
13
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SDRAM
BURST TERMINATE
The BURST TERMINATE command is used to truncate either fixed-length or full-page bursts. The most
recently registered READ or WRITE command prior to
the BURST TERMINATE command will be truncated,
as shown in the Operation section of this data sheet.
SELF REFRESH
The SELF REFRESH command can be used to retain
data in the SDRAM, even if the rest of the system is
powered down. When in the self refresh mode, the
SDRAM retains data without external clocking. The SELF
REFRESH command is initiated like an AUTO REFRESH
command except CKE is disabled (LOW). Once the SELF
REFRESH command is registered, all the inputs to the
SDRAM become “Don’t Care” with the exception of
CKE, which must remain LOW.
Once self refresh mode is engaged, the SDRAM provides its own internal clocking, causing it to perform its
own AUTO REFRESH cycles. The SDRAM must remain
in self refresh mode for a minimum period equal to
tRAS and may remain in self refresh mode for an indefinite period beyond that.
The procedure for exiting self refresh requires a sequence of commands. First, CLK must be stable (stable
clock is defined as a signal cycling within timing constraints specified for the clock pin) prior to CKE going
back HIGH. Once CKE is HIGH, the SDRAM must have
NOP commands issued (a minimum of two clocks) for
tXSR because time is required for the completion of any
internal refresh in progress.
Upon exiting SELF REFRESH mode, AUTO REFRESH
commands must be issued every 15.625ms or less as
both SELF REFRESH and AUTO REFRESH utililze the
row refresh counter.
AUTO REFRESH
AUTO REFRESH is used during normal operation of
the SDRAM and is analagous to CAS#-BEFORE-RAS#
(CBR) REFRESH in conventional DRAMs. This command is nonpersistent, so it must be issued each time
a refresh is required.
The addressing is generated by the internal refresh
controller. This makes the address bits “Don’t Care”
during an AUTO REFRESH command. The 256Mb
SDRAM requires 4,096 AUTO REFRESH cycles every
64ms (tREF), regardless of width option. Providing a
distributed AUTO REFRESH command every 15.625µs
will meet the refresh requirement and ensure that each
row is refreshed. Alternatively, 4,096 AUTO REFRESH
commands can be issued in a burst at the minimum
cycle rate (tRFC), once every 64ms.
09005aef80cd8e48
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PRELIMINARY
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SDRAM
OPERATION
Figure 3
Activating a Specific Row in a
Specific Bank
BANK/ROW ACTIVATION
Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row in that bank
must be “opened.” This is accomplished via the ACTIVE command, which selects both the bank and the
row to be activated. See Figure 3.
After opening a row (issuing an ACTIVE command),
a READ or WRITE command may be issued to that row,
subject to the tRCD specification. tRCD (MIN) should
be divided by the clock period and rounded up to the
next whole number to determine the earliest clock edge
after the ACTIVE command on which a READ or WRITE
command can be issued. For example, a tRCD specification of 20ns with a 125 MHz clock (8ns period) results
in 2.5 clocks, rounded to 3. This is reflected in Figure 4,
which covers any case where 2 < tRCD (MIN)/tCK - 3.
(The same procedure is used to convert other specification limits from time units to clock cycles.)
A subsequent ACTIVE command to a different row
in the same bank can only be issued after the previous
active row has been “closed” (precharged). The minimum time interval between successive ACTIVE commands to the same bank is defined by tRC.
A subsequent ACTIVE command to another bank
can be issued while the first bank is being accessed,
which results in a reduction of total row-access overhead. The minimum time interval between successive
ACTIVE commands to different banks is defined by
t RRD.
Example: Meeting
tRCD
CLK
CKE
HIGH
CS#
RAS#
CAS#
WE#
ROW
ADDRESS
A0-A11
BANK
ADDRESS
BA0, BA1
Figure 4
(MIN) When 2 < tRCD (MIN)/tCK - 3
T0
T1
T2
T3
CLK
tCK
tCK
COMMAND
ACTIVE
NOP
tCK
NOP
READ or
WRITE
tRCD (MIN)
tRCD (MIN) +0.5 tCK
tRCD (MIN) = 20ns, tCK = 8ns
tRCD (MIN) x tCK
DON’T CARE
where x = number of clocks for equation to be true.
09005aef80cd8e48
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PRELIMINARY
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SDRAM
READs
READ bursts are initiated with a READ command,
as shown in Figure 5.
The starting column and bank addresses are provided with the READ command, and auto precharge is
either enabled or disabled for that burst access. If auto
precharge is enabled, the row being accessed is
precharged at the completion of the burst. For the generic READ commands used in the following illustrations, auto precharge is disabled.
During READ bursts, the valid data-out element
from the starting column address will be available following the CAS latency after the READ command. Each
subsequent data-out element will be valid by the next
positive clock edge. Figure 6 shows general timing for
each possible CAS latency setting.
Upon completion of a burst, assuming no other commands have been initiated, the DQs will go High-Z. A
full-page burst will continue until terminated. (At the
end of the page, it will wrap to column 0 and continue.)
Data from any READ burst may be truncated with a
subsequent READ command, and data from a fixedlength READ burst may be immediately followed by
data from a READ command. In either case, a continuous flow of data can be maintained. The first data element from the new burst follows either the last element
of a completed burst or the last desired data element of
a longer burst that is being truncated. The new READ
command should be issued x cycles before the clock
edge at which the last desired data element is valid,
where x equals the CAS latency minus one. This is shown
in Figure 7 for CAS latencies of one, two and three; data
Figure 5
READ Command
Figure 6
CAS Latency
CLK
CKE
T0
T1
T2
READ
NOP
CLK
HIGH
COMMAND
tLZ
CS#
tOH
DOUT
DQ
tAC
CAS Latency = 1
RAS#
CAS#
T0
T1
T2
COMMAND
WE#
READ
NOP
NOP
tLZ
tOH
DOUT
DQ
A0-A7
T3
CLK
tAC
COLUMN
ADDRESS
CAS Latency = 2
A8, A9, A11
ENABLE AUTO PRECHARGE
A10
T0
T1
T2
T3
T4
READ
NOP
NOP
NOP
CLK
DISABLE AUTO PRECHARGE
COMMAND
BA0,1
tLZ
BANK
ADDRESS
tOH
DOUT
DQ
tAC
CAS Latency = 3
DON’T CARE
UNDEFINED
09005aef80cd8e48
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PRELIMINARY
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SDRAM
element n + 3 is either the last of a burst of four or the last
desired of a longer burst. This 256Mb SDRAM uses a
pipelined architecture and therefore does not require
the 2n rule associated with a prefetch architecture.
A READ command can be initiated on any clock cycle
following a previous READ command. Full-speed random read accesses can be performed to the same bank,
as shown in Figure 8, or each subsequent READ may be
performed to a different bank.
Figure 7
Consecutive READ Bursts
T0
T1
T2
T3
T4
T5
CLK
COMMAND
READ
NOP
NOP
NOP
READ
NOP
X = 0 cycles
ADDRESS
BANK,
COL n
BANK,
COL b
DOUT
n
DQ
DOUT
n+2
DOUT
n+1
DOUT
n+3
DOUT
b
CAS Latency = 1
T0
T1
T2
T3
T4
T5
T6
CLK
COMMAND
READ
ADDRESS
BANK,
COL n
NOP
NOP
NOP
READ
NOP
NOP
X = 1 cycle
BANK,
COL b
DOUT
n
DQ
DOUT
n+2
DOUT
n+1
DOUT
n+3
DOUT
b
CAS Latency = 2
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
READ
ADDRESS
BANK,
COL n
NOP
NOP
NOP
READ
NOP
NOP
NOP
X = 2 cycles
BANK,
COL b
DOUT
n
DQ
DOUT
n+1
DOUT
n+2
DOUT
n+3
DOUT
b
CAS Latency = 3
NOTE: Each READ command may be to either bank. DQM is LOW.
DON’T CARE
09005aef80cd8e48
256MbSDRAMx32.p65 – Rev. B; Pub. 03/04
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PRELIMINARY
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SDRAM
Figure 8
Random READ Accesses
T0
T1
T2
T3
T4
CLK
COMMAND
READ
READ
READ
READ
ADDRESS
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
DOUT
n
DQ
NOP
DOUT
x
DOUT
a
DOUT
m
CAS Latency = 1
T0
T1
T2
T3
T4
T5
CLK
COMMAND
READ
READ
READ
READ
ADDRESS
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
DOUT
n
DQ
NOP
NOP
DOUT
x
DOUT
a
DOUT
m
CAS Latency = 2
T0
T1
T2
T3
T4
T5
T6
CLK
COMMAND
READ
READ
READ
READ
ADDRESS
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
NOP
DOUT
a
DOUT
n
DQ
NOP
DOUT
x
NOP
DOUT
m
CAS Latency = 3
NOTE: Each READ command may be to either bank. DQM is LOW.
DON’T CARE
09005aef80cd8e48
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PRELIMINARY
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SDRAM
Data from any READ burst may be truncated with a
subsequent WRITE command, and data from a fixedlength READ burst may be immediately followed by
data from a WRITE command (subject to bus turnaround limitations). The WRITE burst may be initiated
on the clock edge immediately following the last (or last
desired) data element from the READ burst, provided
that I/O contention can be avoided. In a given system
design, there may be a possibility that the device driving the input data will go Low-Z before the SDRAM DQs
go High-Z. In this case, at least a single-cycle delay
should occur between the last read data and the WRITE
command.
The DQM input is used to avoid I/O contention, as
shown in Figures 9 and 10. The DQM signal must be
asserted (HIGH) at least two clocks prior to the WRITE
command (DQM latency is two clocks for output buffers) to suppress data-out from the READ. Once the
WRITE command is registered, the DQs will go High-Z
(or remain High-Z), regardless of the state of the DQM
signal; provided the DQM was active on the clock just
prior to the WRITE command that truncated the READ
command. If not, the second WRITE will be an invalid
WRITE. For example, if DQM was low during T4 in Figure 10, then the WRITEs at T5 and T7 would be valid,
while the WRITE at T6 would be invalid.
The DQM signal must be de-asserted prior to the
WRITE command (DQM latency is zero clocks for input
buffers) to ensure that the written data is not masked.
Figure 9 shows the case where the clock frequency allows for bus contention to be avoided without adding a
NOP cycle, and Figure 10 shows the case where the
additional NOP is needed.
Figure 9
READ to WRITE
T0
T1
T2
T3
T4
CLK
DQM
COMMAND
READ
ADDRESS
BANK,
COL n
NOP
NOP
NOP
Figure 10
READ to WRITE with
Extra Clock Cycle
WRITE
BANK,
COL b
tCK
tHZ
T0
T1
T2
T3
T4
T5
CLK
DOUT n
DQ
DIN b
tDS
DQM
DON’T CARE
NOTE:
A CAS latency of three is used for illustration. The READ
command may be to any bank, and the WRITE command
may be to any bank. If a burst of one is used, then DQM is
not required.
COMMAND
READ
ADDRESS
BANK,
COL n
NOP
NOP
NOP
NOP
WRITE
BANK,
COL b
tHZ
DQ
DOUT n
DIN b
tDS
DON’T CARE
NOTE:
09005aef80cd8e48
256MbSDRAMx32.p65 – Rev. B; Pub. 03/04
19
A CAS latency of three is used for illustration. The READ command
may be to any bank, and the WRITE command may be to any bank.
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PRELIMINARY
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SDRAM
A fixed-length READ burst may be followed by, or
truncated with, a PRECHARGE command to the same
bank (provided that auto precharge was not activated), and a full-page burst may be truncated with a
PRECHARGE command to the same bank. The
PRECHARGE command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minus
one. This is shown in Figure 11 for each possible CAS
latency; data element n + 3 is either the last of a burst of
four or the last desired of a longer burst. Following the
PRECHARGE command, a subsequent command to
the same bank cannot be issued until tRP is met. Note
that part of the row precharge time is hidden during
the access of the last data element(s).
In the case of a fixed-length burst being executed to
completion, a PRECHARGE command issued at the
optimum time (as described above) provides the same
Figure 11
READ to PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
t RP
COMMAND
READ
NOP
NOP
NOP
PRECHARGE
NOP
NOP
ACTIVE
X = 0 cycles
ADDRESS
BANK
(a or all)
BANK a,
COL n
DOUT
n
DQ
DOUT
n+2
DOUT
n+1
BANK a,
ROW
DOUT
n+3
CAS Latency = 1
T0
T1
T2
T3
T4
T5
T6
T7
CLK
t RP
COMMAND
READ
NOP
NOP
NOP
PRECHARGE
NOP
NOP
ACTIVE
X = 1 cycle
ADDRESS
BANK
(a or all)
BANK a,
COL n
DOUT
n
DQ
BANK a,
ROW
DOUT
n+2
DOUT
n+1
DOUT
n+3
CAS Latency = 2
T0
T1
T2
T3
T4
T5
T6
T7
CLK
t RP
COMMAND
READ
NOP
NOP
NOP
PRECHARGE
NOP
NOP
ACTIVE
X = 2 cycles
ADDRESS
BANK
(a or all)
BANK a,
COL n
DOUT
n
DQ
DOUT
n+1
BANK a,
ROW
DOUT
n+2
DOUT
n+3
CAS Latency = 3
NOTE: DQM is LOW.
09005aef80cd8e48
256MbSDRAMx32.p65 – Rev. B; Pub. 03/04
DON’T CARE
20
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©2003 Micron Technology, Inc.
PRELIMINARY
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SDRAM
operation that would result from the same fixed-length
burst with auto precharge. The disadvantage of the
PRECHARGE command is that it requires that the command and address buses be available at the appropriate time to issue the command; the advantage of the
PRECHARGE command is that it can be used to truncate fixed-length or full-page bursts.
Full-page READ bursts can be truncated with the
BURST TERMINATE command, and fixed-length READ
bursts may be truncated with a BURST TERMINATE
command, provided that auto precharge was not activated. The BURST TERMINATE command should be
issued x cycles before the clock edge at which the last
desired data element is valid, where x equals the CAS
latency minus one. This is shown in Figure 12 for each
possible CAS latency; data element n + 3 is the last
desired data element of a longer burst.
Figure 12
Terminating a READ Burst
T0
T1
T2
T3
T4
T5
T6
CLK
COMMAND
READ
NOP
NOP
NOP
BURST
TERMINATE
NOP
NOP
X = 0 cycles
ADDRESS
BANK,
COL n
DOUT
n
DQ
DOUT
n+2
DOUT
n+1
DOUT
n+3
CAS Latency = 1
T0
T1
T2
T3
T4
T5
T6
CLK
COMMAND
READ
ADDRESS
BANK,
COL n
NOP
NOP
NOP
BURST
TERMINATE
NOP
NOP
X = 1 cycle
DOUT
n
DQ
DOUT
n+2
DOUT
n+1
DOUT
n+3
CAS Latency = 2
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
READ
ADDRESS
BANK,
COL n
NOP
NOP
NOP
BURST
TERMINATE
NOP
NOP
NOP
X = 2 cycles
DOUT
n
DQ
DOUT
n+1
DOUT
n+2
DOUT
n+3
CAS Latency = 3
NOTE: DQM is LOW.
09005aef80cd8e48
256MbSDRAMx32.p65 – Rev. B; Pub. 03/04
DON’T CARE
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PRELIMINARY
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SDRAM
WRITEs
WRITE bursts are initiated with a WRITE command,
as shown in Figure 13.
The starting column and bank addresses are provided with the WRITE command, and auto precharge
is either enabled or disabled for that access. If auto
precharge is enabled, the row being accessed is
precharged at the completion of the burst. For the generic WRITE commands used in the following
illustrations,auto precharge is disabled.
During WRITE bursts, the first valid data-in element will be registered coincident with the WRITE command. Subsequent data elements will be registered on
each successive positive clock edge. Upon completion
of a fixed-length burst, assuming no other commands
have been initiated, the DQs will remain High-Z and
any additional input data will be ignored (see Figure
14). A full-page burst will continue until terminated.
(At the end of the page, it will wrap to column 0 and
continue.)
Data for any WRITE burst may be truncated with a
subsequent WRITE command, and data for a fixedlength WRITE burst may be immediately followed by
data for a WRITE command. The new WRITE command
can be issued on any clock following the previous WRITE
command, and the data provided coincident with the
new command applies to the new command. An example is shown in Figure 15. Data n + 1 is either the last
of a burst of two or the last desired of a longer burst.
This 256Mb SDRAM uses a pipelined architecture and
therefore does not require the 2n rule associated with a
prefetch architecture. A WRITE command can be initiated on any clock cycle following a previous WRITE
command. Full-speed random write accesses within a
page can be performed to the same bank, as shown in
Figure 16, or each subsequent WRITE may be performed to a different bank.
Figure 14
WRITE Burst
T0
T1
T2
T3
COMMAND
WRITE
NOP
NOP
NOP
ADDRESS
BANK,
COL n
CLK
Figure 13
WRITE Command
DIN
n
DQ
DIN
n+1
CLK
CKE HIGH
Figure 15
WRITE to WRITE
CS#
T0
T1
T2
COMMAND
WRITE
NOP
WRITE
ADDRESS
BANK,
COL n
RAS#
CLK
CAS#
WE#
A0-A7
COLUMN
ADDRESS
A8, A9, A11
DQ
DIN
n
BANK,
COL b
DIN
n+1
DIN
b
ENABLE AUTO PRECHARGE
A10
TRANSITIONING DATA
DISABLE AUTO PRECHARGE
BA0,1
09005aef80cd8e48
256MbSDRAMx32.p65 – Rev. B; Pub. 03/04
DON’T CARE
NOTE: DQM is LOW. Each WRITE command may
be to any bank.
BANK
ADDRESS
22
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PRELIMINARY
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SDRAM
Data for any WRITE burst may be truncated with a
subsequent READ command, and data for a fixedlength WRITE burst may be immediately followed by a
READ command. Once the READ command is registered, the data inputs will be ignored, and WRITEs will
not be executed. An example is shown in Figure 17.
Data n + 1 is either the last of a burst of two or the last
desired of a longer burst.
Data for a fixed-length WRITE burst may be followed by, or truncated with, a PRECHARGE command
to the same bank (provided that auto precharge was
not activated), and a full-page WRITE burst may be
truncated with a PRECHARGE command to the same
bank. The PRECHARGE command should be issued
tWR after the clock edge at which the last desired input
data element is registered. The “two-clock” write-back
requires at least one clock plus time, regardless of frequency, in auto precharge mode. In addition, when
truncating a WRITE burst, the DQM signal must be
used to mask input data for the clock edge prior to, and
the clock edge coincident with, the PRECHARGE command. An example is shown in Figure 18. Data n + 1 is
either the last of a burst of two or the last desired of a
longer burst. Following the PRECHARGE command, a
subsequent command to the same bank cannot be
issued until tRP is met. The precharge will actually begin coincident with the clock-edge (T2 in Figure 18) on
a “one-clock” tWR and sometime between the first and
second clock on a “two-clock” tWR (between T2 and T3
in Figure 18.)
In the case of a fixed-length burst being executed to
completion, a PRECHARGE command issued at the
optimum time (as described above) provides the same
operation that would result from the same fixed-length
burst with auto precharge. The disadvantage of the
PRECHARGE command is that it requires that the command and address buses be available at the appropriate time to issue the command; the advantage of the
PRECHARGE command is that it can be used to truncate fixed-length or full-page bursts.
Figure 16
Random WRITE Cycles
T0
T1
T2
T3
WRITE
WRITE
WRITE
WRITE
Figure 18
WRITE to PRECHARGE
CLK
COMMAND
T0
T1
T2
T3
NOP
PRECHARGE
NOP
T4
T5
T6
NOP
ACTIVE
NOP
CLK
ADDRESS
BANK,
COL n
BANK,
COL a
BANK,
COL x
tWR = 1 CLK (tCK > tWR)
BANK,
COL m
DQM
DQ
DIN
n
DIN
a
DIN
x
t RP
DIN
m
COMMAND
DON’T CARE
ADDRESS
WRITE
BANK
(a or all)
BANK a,
COL n
BANK a,
ROW
t WR
DQ
Figure 17
WRITE to READ
T0
T1
T2
T3
DIN
n
DIN
n+1
tWR = 2 CLK (when tWR > tCK)
T4
DQM
T5
t RP
CLK
COMMAND
COMMAND
WRITE
ADDRESS
BANK,
COL n
NOP
READ
NOP
NOP
ADDRESS
NOP
WRITE
NOP
NOP
PRECHARGE
BANK
(a or all)
BANK a,
COL n
NOP
NOP
ACTIVE
BANK a,
ROW
t WR
DQ
DIN
n
DQ
BANK,
COL b
DOUT
b
DIN
n+1
NOTE:
DOUT
b+1
DIN
n
DIN
n+1
DQM could remain LOW in this example if the WRITE burst is a fixed
length of two.
DON’T CARE
TRANSITIONING DATA
09005aef80cd8e48
256MbSDRAMx32.p65 – Rev. B; Pub. 03/04
DON’T CARE
23
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PRELIMINARY
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SDRAM
PRECHARGE
The PRECHARGE command (Figure 20) is used to
deactivate the open row in a particular bank or the
open row in all banks. The bank(s) will be available for
a subsequent row access some specified time (tRP) after the PRECHARGE command is issued. Input A10
determines whether one or all banks are to be
precharged, and in the case where only one bank is to
be precharged, inputs BA0 and BA1 select the bank.
When all banks are to be precharged, inputs BA0 and
BA1 are treated as “Don’t Care.” Once a bank has been
precharged, it is in the idle state and must be activated
prior to any READ or WRITE commands being issued to
that bank.
Fixed-length or full-page WRITE bursts can be truncated with the BURST TERMINATE command. When
truncating a WRITE burst, the input data applied coincident with the BURST TERMINATE command will be
ignored. The last data written (provided that DQM is
LOW at that time) will be the input data applied one
clock previous to the BURST TERMINATE command.
This is shown in Figure 19, where data n is the last
desired data element of a longer burst.
Figure 19
Terminating a WRITE Burst
T0
T1
T2
POWER-DOWN
Power-down occurs if CKE is registered LOW coincident with a NOP or COMMAND INHIBIT when no accesses are in progress (see Figure 21). If power-down
occurs when all banks are idle, this mode is referred to
as precharge power-down; if power-down occurs when
there is a row active in either bank, this mode is referred
to as active power-down. Entering power-down deactivates the input and output buffers, excluding CKE, for
maximum power savings while in standby. The device
may not remain in the power-down state longer than
the refresh period (64ms) since no refresh operations
are performed in this mode.
The power-down state is exited by registering a NOP
or COMMAND INHIBIT and CKE HIGH at the desired
clock edge (meeting tCKS).
CLK
BURST
TERMINATE
NEXT
COMMAND
COMMAND
WRITE
ADDRESS
BANK,
COL n
(ADDRESS)
DIN
n
(DATA)
DQ
NOTE: DQMs are LOW.
Figure 20
PRECHARGE Command
Figure 21
Power-Down
CLK
CKE
HIGH
((
))
((
))
CLK
tCKS
CS#
CKE
RAS#
> tCKS
((
))
COMMAND
((
))
((
))
NOP
NOP
All banks idle
Input buffers gated off
CAS#
Enter power-down mode.
WE#
Exit power-down mode.
ACTIVE
tRCD
tRAS
tRC
DON’T CARE
A0-A9, A11
All Banks
A10
Bank Selected
BA0,1
09005aef80cd8e48
256MbSDRAMx32.p65 – Rev. B; Pub. 03/04
BANK
ADDRESS
24
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PRELIMINARY
256Mb: x32
SDRAM
CLOCK SUSPEND
The clock suspend mode occurs when a column access/burst is in progress and CKE is registered LOW. In
the clock suspend mode, the internal clock is deactivated, “freezing” the synchronous logic.
For each positive clock edge on which CKE is
sampled LOW, the next internal positive clock edge is
suspended. Any command or data present on the input pins at the time of a suspended internal clock edge
is ignored; any data present on the DQ pins remains
driven; and burst counters are not incremented, as
long as the clock is suspended. (See examples in Figures 22 and 23.)
Clock suspend mode is exited by registering CKE
HIGH; the internal clock and related operation will resume on the subsequent positive clock edge.
BURST READ/SINGLE WRITE
The burst read/single write mode is entered by programming the write burst mode bit (M9) in the Mode
Register to a logic 1. In this mode, all WRITE commands
result in the access of a single column location (burst of
one), regardless of the programmed burst length. READ
commands access columns according to the programmed burst length and sequence, just as in the
normal mode of operation (M9 = 0).
Figure 22
CLOCK SUSPEND During WRITE Burst
T0
T1
T2
T3
T4
Figure 23
CLOCK SUSPEND During READ Burst
T0
T5
T1
T2
T3
T4
T5
T6
CLK
CLK
CKE
CKE
INTERNAL
CLOCK
INTERNAL
CLOCK
COMMAND
ADDRESS
DIN
NOP
WRITE
NOP
ADDRESS
BANK,
COL n
DQ
DIN
n+1
DIN
n+2
NOP
NOP
NOP
NOP
NOP
DOUT
n
DOUT
n+1
DOUT
n+2
DOUT
n+3
DON’T CARE
NOTE: For this example, CAS latency = 2, burst length = 4 or greater, and
DQM is LOW.
DON’T CARE
09005aef80cd8e48
256MbSDRAMx32.p65 – Rev. B; Pub. 03/04
READ
NOP
BANK,
COL n
DIN
n
COMMAND
25
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PRELIMINARY
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SDRAM
CONCURRENT AUTO PRECHARGE
An access command to (READ or WRITE) another
bank while an access command with auto precharge
enabled is executing is not allowed by SDRAMs, unless
the SDRAM supports CONCURRENT AUTO
PRECHARGE. Micron SDRAMs support CONCURRENT
AUTO PRECHARGE. Four cases where CONCURRENT
AUTO PRECHARGE occurs are defined below.
on bank n, CAS latency later. The PRECHARGE to
bank n will begin when the READ to bank m is registered (Figure 24).
2. Interrupted by a WRITE (with or without auto
precharge): A WRITE to bank m will interrupt a READ
on bank n when registered. DQM should be used
two clocks prior to the WRITE command to prevent
bus contention. The PRECHARGE to bank n
will begin when the WRITE to bank m is registered
(Figure 25).
READ with auto precharge
1. Interrupted by a READ (with or without auto
precharge): A READ to bank m will interrupt a READ
Figure 24
READ With Auto Precharge Interrupted by a READ
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
NOP
BANK n
Internal
States
Page Active
READ - AP
BANK n
READ - AP
BANK m
NOP
READ with Burst of 4
NOP
NOP
NOP
Idle
Interrupt Burst, Precharge
tRP - BANK m
t RP - BANK n
Page Active
BANK m
Precharge
READ with Burst of 4
BANK n,
COL a
ADDRESS
NOP
BANK m,
COL d
DOUT
a+1
DOUT
a
DQ
DOUT
d
DOUT
d+1
CAS Latency = 3 (BANK n)
CAS Latency = 3 (BANK m)
NOTE: DQM is LOW.
Figure 25
READ With Auto Precharge Interrupted by a WRITE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
BANK n
Internal
States
READ - AP
BANK n
Page
Active
NOP
NOP
NOP
READ with Burst of 4
WRITE - AP
BANK m
NOP
NOP
Interrupt Burst, Precharge
Idle
tRP - BANK n
Page Active
BANK m
ADDRESS
NOP
Write-Back
WRITE with Burst of 4
BANK n,
COL a
t WR - BANK m
BANK m,
COL d
1
DQM
DOUT
a
DQ
DIN
d
DIN
d+1
DIN
d+2
DIN
d+3
CAS Latency = 3 (BANK n)
NOTE: 1. DQM is HIGH at T2 to prevent DOUT-a+1 from contending with DIN-d at T4.
DON’T CARE
09005aef80cd8e48
256MbSDRAMx32.p65 – Rev. B; Pub. 03/04
26
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PRELIMINARY
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SDRAM
WRITE WITH AUTO PRECHARGE
3. Interrupted by a READ (with or without auto
precharge): A READ to bank m will interrupt a WRITE
on bank n when registered, with the data-out appearing CAS latency later. The PRECHARGE to bank
n will begin after tWR is met, where tWR begins when
the READ to bank m is registered. The last valid
WRITE to bank n will be data-in registered one clock
prior to the READ to bank m (Figure 26).
4. Interrupted by a WRITE (with or without auto
precharge): A WRITE to bank m will interrupt a
WRITE on bank n when registered. The PRECHARGE
to bank n will begin after tWR is met, where tWR
begins when the WRITE to bank m is registered.
The last valid data WRITE to bank n will be data
registered one clock prior to a WRITE to bank m
(Figure 27).
Figure 26
WRITE With Auto Precharge Interrupted by a READ
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
BANK n
Internal
States
NOP
WRITE - AP
BANK n
Page Active
READ - AP
BANK m
NOP
WRITE with Burst of 4
DIN
a
DQ
NOP
Precharge
tWR - BANK n
tRP - BANK n
NOP
tRP - BANK m
READ with Burst of 4
BANK n,
COL a
ADDRESS
NOP
Interrupt Burst, Write-Back
Page Active
BANK m
NOP
BANK m,
COL d
DOUT
d+1
DOUT
d
DIN
a+1
CAS Latency = 3 (BANK m)
NOTE: 1. DQM is LOW.
Figure 27
WRITE With Auto Precharge Interrupted by a WRITE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
BANK n
Internal
States
NOP
WRITE - AP
BANK n
Page Active
NOP
NOP
WRITE with Burst of 4
NOP
Interrupt Burst, Write-Back
tWR - BANK n
BANK m
ADDRESS
DQ
Page Active
BANK n,
COL a
DIN
a
NOP
NOP
Precharge
tRP - BANK n
t WR - BANK m
Write-Back
WRITE with Burst of 4
BANK m,
COL d
DIN
a+1
DIN
a+2
NOTE: 1. DQM is LOW.
09005aef80cd8e48
256MbSDRAMx32.p65 – Rev. B; Pub. 03/04
WRITE - AP
BANK m
DIN
d
DIN
d+1
DIN
d+2
DIN
d+3
DON’T CARE
27
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PRELIMINARY
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SDRAM
TRUTH TABLE 2 – CKE
(Notes: 1-4)
CKE n-1 CKE n
L
L
L
H
H
L
H
CURRENT STATE
COMMAND n
Power-Down
X
Maintain Power-Down
Self Refresh
X
Maintain Self Refresh
Clock Suspend
X
Maintain Clock Suspend
Power-Down
COMMAND INHIBIT or NOP
Exit Power-Down
5
Self Refresh
COMMAND INHIBIT or NOP
Exit Self Refresh
6
Clock Suspend
X
Exit Clock Suspend
7
All Banks Idle
COMMAND INHIBIT or NOP
Power-Down Entry
All Banks Idle
AUTO REFRESH
Self Refresh Entry
Reading or Writing
VALID
H
ACTION n
NOTES
Clock Suspend Entry
See Truth Table 3
NOTE: 1.
2.
3.
4.
5.
CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge.
Current state is the state of the SDRAM immediately prior to clock edge n.
COMMANDn is the command registered at clock edge n, and ACTIONn is a result of COMMANDn.
All states and sequences not shown are illegal or reserved.
Exiting power-down at clock edge n will put the device in the all banks idle state in time for clock
edge n + 1 (provided that tCKS is met).
6. Exiting self refresh at clock edge n will put the device in the all banks idle state once tXSR is met.
COMMAND INHIBIT or NOP commands should be issued on any clock edges occurring during the tXSR
period. A minimum of two NOP commands must be provided during tXSR period.
7. After exiting clock suspend at clock edge n, the device will resume operation and recognize the next
command at clock edge n + 1.
09005aef80cd8e48
256MbSDRAMx32.p65 – Rev. B; Pub. 03/04
28
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PRELIMINARY
256Mb: x32
SDRAM
TRUTH TABLE 3 – CURRENT STATE BANK n, COMMAND TO BANK n
(Notes: 1-6; notes appear below and on next page)
CURRENT STATE
Any
CS# RAS# CAS# WE#
COMMAND (ACTION)
NOTES
H
X
X
X
COMMAND INHIBIT (NOP/Continue previous operation)
L
H
H
H
NO OPERATION (NOP/Continue previous operation)
L
L
H
H
ACTIVE (Select and activate row)
L
L
L
H
AUTO REFRESH
7
L
L
L
L
LOAD MODE REGISTER
7
L
L
H
L
PRECHARGE
11
L
H
L
H
READ (Select column and start READ burst)
10
L
H
L
L
WRITE (Select column and start WRITE burst)
10
L
L
H
L
PRECHARGE (Deactivate row in bank or banks)
8
Read
L
H
L
H
READ (Select column and start new READ burst)
10
(Auto
L
H
L
L
WRITE (Select column and start WRITE burst)
10
Precharge
L
L
H
L
PRECHARGE (Truncate READ burst, start PRECHARGE)
8
Disabled)
L
H
H
L
BURST TERMINATE
9
Write
L
H
L
H
READ (Select column and start READ burst)
10
(Auto
L
H
L
L
WRITE (Select column and start new WRITE burst)
10
Precharge
L
L
H
L
PRECHARGE (Truncate WRITE burst, start PRECHARGE)
8
Disabled)
L
H
H
L
BURST TERMINATE
9
Idle
Row Active
NOTE:
1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Truth Table 2) and after tXSR has
been met (if the previous state was self refresh).
2. This table is bank-specific, except where noted, i.e., the current state is for a specific bank and the
commands shown are those allowed to be issued to that bank when in that state. Exceptions are
covered in the notes below.
3. Current state definitions:
Idle:
The bank has been precharged, and tRP has been met.
Row Active:
A row in the bank has been activated, and tRCD has been met. No data bursts/
accesses and no register accesses are in progress.
Read:
A READ burst has been initiated, with auto precharge disabled, and has not yet
terminated or been terminated.
Write:
A WRITE burst has been initiated, with auto precharge disabled, and has not yet
terminated or been terminated.
4. The following states must not be interrupted by a command issued to the same bank. COMMAND
INHIBIT or NOP commands, or allowable commands to the other bank should be issued on any clock
edge occurring during these states. Allowable commands to the other bank are determined by its
current state and Truth Table 3, and according to Truth Table 4.
Precharging:
Starts with registration of a PRECHARGE command and ends when tRP is met.
Once tRP is met, the bank will be in the idle state.
Row Activating:
Starts with registration of an ACTIVE command and ends when tRCD is met. Once
tRCD is met, the bank will be in the row active state.
Read w/Auto
Precharge Enabled: Starts with registration of a READ command with auto precharge enabled and
ends when tRP has been met. Once tRP is met, the bank will be in the idle state.
09005aef80cd8e48
256MbSDRAMx32.p65 – Rev. B; Pub. 03/04
29
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
PRELIMINARY
256Mb: x32
SDRAM
NOTE (continued):
Write w/Auto
Precharge Enabled:
5.
6.
7.
8.
9.
10.
11.
Starts with registration of a WRITE command with auto precharge enabled and
ends when tRP has been met. Once tRP is met, the bank will be in the idle state.
The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP
commands must be applied on each positive clock edge during these states.
Refreshing: Starts with registration of an AUTO REFRESH command and ends when tRC is met.
Once tRC is met, the SDRAM will be in the all banks idle state.
Accessing Mode
Register:
Starts with registration of a LOAD MODE REGISTER command and ends when
tMRD has been met. Once tMRD is met, the SDRAM will be in the all banks idle
state.
Precharging All:
Starts with registration of a PRECHARGE ALL command and ends when tRP is met.
Once tRP is met, all banks will be in the idle state.
All states and sequences not shown are illegal or reserved.
Not bank-specific; requires that all banks are idle.
May or may not be bank-specific; if all banks are to be precharged, all must be in a valid state for
precharging.
Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, regardless of bank.
READs or WRITEs listed in the Command (Action) column include READs or WRITEs with auto
precharge enabled and READs or WRITEs with auto precharge disabled.
Does not affect the state of the bank and acts as a NOP to that bank.
09005aef80cd8e48
256MbSDRAMx32.p65 – Rev. B; Pub. 03/04
30
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
PRELIMINARY
256Mb: x32
SDRAM
TRUTH TABLE 4 – CURRENT STATE BANK n, COMMAND TO BANK m
(Notes: 1-6; notes appear below and on next page)
CURRENT STATE
Any
CS# RAS# CAS# WE#
COMMAND (ACTION)
NOTES
H
X
X
X
COMMAND INHIBIT (NOP/Continue previous operation)
L
H
H
H
NO OPERATION (NOP/Continue previous operation)
Idle
X
X
X
X
Any Command Otherwise Allowed to Bank m
Row
L
L
H
H
ACTIVE (Select and activate row)
Activating,
L
H
L
H
READ (Select column and start READ burst)
7
7
Active, or
L
H
L
L
WRITE (Select column and start WRITE burst)
Precharging
L
L
H
L
PRECHARGE
Read
L
L
H
H
ACTIVE (Select and activate row)
(Auto
L
H
L
H
READ (Select column and start new READ burst)
7, 10
Precharge
L
H
L
L
WRITE (Select column and start WRITE burst)
7, 11
Disabled)
L
L
H
L
PRECHARGE
Write
L
L
H
H
ACTIVE (Select and activate row)
(Auto
L
H
L
H
READ (Select column and start READ burst)
7, 12
Precharge
L
H
L
L
WRITE (Select column and start new WRITE burst)
7, 13
Disabled)
L
L
H
L
PRECHARGE
Read
L
L
H
H
ACTIVE (Select and activate row)
(With Auto
L
H
L
H
READ (Select column and start new READ burst)
7, 8, 14
Precharge)
L
H
L
L
WRITE (Select column and start WRITE burst)
7, 8, 15
L
L
H
L
PRECHARGE
Write
L
L
H
H
ACTIVE (Select and activate row)
(With Auto
L
H
L
H
READ (Select column and start READ burst)
7, 8, 16
Precharge)
L
H
L
L
WRITE (Select column and start new WRITE burst)
7, 8, 17
L
L
H
L
PRECHARGE
NOTE:
9
9
9
9
1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Truth Table 2) and after tXSR has
been met (if the previous state was self refresh).
2. This table describes alternate bank operation, except where noted; i.e., the current state is for bank n
and the commands shown are those allowed to be issued to bank m (assuming that bank m is in such a
state that the given command is allowable). Exceptions are covered in the notes below.
3. Current state definitions:
Idle: The bank has been precharged, and tRP has been met.
Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/
accesses and no register accesses are in progress.
Read: A READ burst has been initiated, with auto precharge disabled, and has not yet
terminated or been terminated.
Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet
terminated or been terminated.
Read w/Auto
Precharge Enabled: Starts with registration of a READ command with auto precharge enabled, and
ends when tRP has been met. Once tRP is met, the bank will be in the idle state.
09005aef80cd8e48
256MbSDRAMx32.p65 – Rev. B; Pub. 03/04
31
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
PRELIMINARY
256Mb: x32
SDRAM
NOTE (continued):
4. AUTO REFRESH, SELF REFRESH, and LOAD MODE REGISTER commands may only be issued when all
banks are idle.
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented
by the current state only.
6. All states and sequences not shown are illegal or reserved.
7. READs or WRITEs to bank m listed in the Command (Action) column include READs or WRITEs with
auto precharge enabled and READs or WRITEs with auto precharge disabled.
8. CONCURRENT AUTO PRECHARGE: Bank n will initiate the auto precharge command when its burst has
been interrupted by bank m’s burst.
9. Burst in bank n continues as initiated.
10. For a READ without auto precharge interrupted by a READ (with or without auto precharge), the
READ to bank m will interrupt the READ on bank n, CAS latency later (Figure 7).
11. For a READ without auto precharge interrupted by a WRITE (with or without auto precharge), the
WRITE to bank m will interrupt the READ on bank n when registered (Figures 9 and 10). DQM should
be used one clock prior to the WRITE command to prevent bus contention.
12. For a WRITE without auto precharge interrupted by a READ (with or without auto precharge), the
READ to bank m will interrupt the WRITE on bank n when registered (Figure 17), with the data-out
appearing CAS latency later. The last valid WRITE to bank n will be data-in registered one clock prior
to the READ to bank m.
13. For a WRITE without auto precharge interrupted by a WRITE (with or without auto precharge), the
WRITE to bank m will interrupt the WRITE on bank n when registered (Figure 15). The last valid WRITE
to bank n will be data-in registered one clock prior to the READ to bank m.
14. For a READ with auto precharge interrupted by a READ (with or without auto precharge), the READ to
bank m will interrupt the READ on bank n, CAS latency later. The PRECHARGE to bank n will begin
when the READ to bank m is registered (Figure 24).
15. For a READ with auto precharge interrupted by a WRITE (with or without auto precharge), the
WRITE to bank m will interrupt the READ on bank n when registered. DQM should be used two
clocks prior to the WRITE command to prevent bus contention. The PRECHARGE to bank n will
begin when the WRITE to bank m is registered (Figure 25).
16. For a WRITE with auto precharge interrupted by a READ (with or without auto precharge), the READ
to bank m will interrupt the WRITE on bank n when registered, with the data-out appearing CAS
latency later. The PRECHARGE to bank n will begin after tWR is met, where tWR begins when the
READ to bank m is registered. The last valid WRITE to bank n will be data-in registered one clock prior
to the READ to bank m (Figure 26).
17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE
to bank m will interrupt the WRITE on bank n when registered. The PRECHARGE to bank n will begin
after tWR is met, where tWR begins when the WRITE to bank m is registered. The last valid WRITE to
bank n will be data registered one clock prior to the WRITE to bank m (Figure 27).
09005aef80cd8e48
256MbSDRAMx32.p65 – Rev. B; Pub. 03/04
32
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
PRELIMINARY
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SDRAM
ABOLUTE MAXIMUM RATINGS
Voltage on VDD, VDDQ Supply
Relative to VSS .............................................. -1V to +4.6V
Voltage on Inputs, NC or I/O Pins
Relative to VSS .............................................. -1V to +4.6V
Operating Temperature, TA ............................ 0°C to +70°C
Storage Temperature (plastic) ............ -55°C to +150°C
Power Dissipation ........................................................ 1W
Operating Temperature, TA (IT) ........... -40°C to +85°C
*Stresses greater than those listed may cause
permanent damage to the device. This is a stress
rating only, and functional operation of the device
at these or any other conditions above those
indicated in the operational sections of this
specification is not implied. Exposure to absolute
maximum rating conditions for extended periods
may affect reliability.
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(Notes: 1, 6; notes appear on page 36) (VDD, VDDQ = +3.3V ±0.3V)
PARAMETER/CONDITION
SYMBOL
MIN
MAX
SUPPLY VOLTAGE
VDD, VDDQ
3
3.6
V
INPUT HIGH VOLTAGE: Logic 1; All inputs
VIH
2
VDDQ+ 0.3
V
22
INPUT LOW VOLTAGE: Logic 0; All inputs
VIL
-0.3
0.8
V
22
II
-5
5
µA
OUTPUT LEAKAGE CURRENT: DQs are disabled; 0V ≤ VOUT ≤ VDDQ
IOZ
-5
5
µA
OUTPUT LEVELS:
Output High Voltage (IOUT = -4mA)
Output Low Voltage (IOUT = 4mA)
VOH
2.4
–
V
VOL
–
0.4
V
INPUT LEAKAGE CURRENT:
Any input 0V ≤ VIN ≤ VDD
(All other pins not under test = 0V)
09005aef80cd8e48
256MbSDRAMx32.p65 – Rev. B; Pub. 03/04
33
UNITS NOTES
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©2003 Micron Technology, Inc.
PRELIMINARY
256Mb: x32
SDRAM
CAPACITANCE
(Note: 2)
PARAMETER
SYMBOL
MIN
MAX
UNITS
Input Capacitance: CLK
CI1
2.5
4.0
pF
Input Capacitance: All other input-only pins
CI2
2.5
4.0
pF
Input/Output Capacitance: DQs
CIO
4.0
6.5
pF
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 5, 6, 8, 9, 11; notes appear on page 36)
AC CHARACTERISTICS
PARAMETER
Access time from CLK
(pos. edge)
Address hold time
Address setup time
CLK high-level width
CLK low-level width
Clock cycle time
-6
CL = 3
CL = 2
CL = 1
CL = 3
CL = 2
CL = 1
CKE hold time
CKE setup time
CS#, RAS#, CAS#, WE#, DQM hold time
CS#, RAS#, CAS#, WE#, DQM setup time
Data-in hold time
Data-in setup time
Data-out high-impedance time
CL = 3
CL = 2
CL = 1
Data-out low-impedance time
Data-out hold time
ACTIVE to PRECHARGE command
ACTIVE to ACTIVE command period
AUTO REFRESH period
ACTIVE to READ or WRITE delay
Refresh period (4,096 rows)
PRECHARGE command period
ACTIVE bank a to ACTIVE bank b command
Transition time
WRITE recovery time
Exit SELF REFRESH to ACTIVE command
09005aef80cd8e48
256MbSDRAMx32.p65 – Rev. B; Pub. 03/04
SYMBOL
tAC (3)
tAC (2)
tAC (1)
t AH
t AS
tCH
tCL
tCK (3)
tCK (2)
tCK (1)
tCKH
tCKS
tCMH
tCMS
t DH
t DS
tHZ (3)
tHZ (2)
tHZ (1)
tLZ
tOH
tRAS
tRC
tRFC
tRCD
tREF
t RP
tRRD
tT
tWR
tXSR
MIN
-7
MAX
5.5
7.5
17
1
1.5
2.5
2.5
6
10
20
1
1.5
1
1.5
1
1.5
MIN
1
2
2.75
2.75
7
10
20
1
2
1
2
1
2
5.5
7.5
17
1
2
42
60
60
18
120K
6
8
17
1
2.5
42
70
70
20
64
18
12
0.3
1CLK+
6ns
12ns
70
34
MAX
6
8
17
1.2
120K
64
20
14
0.3
1CLK+
7ns
14ns
70
1.2
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
tCK
NOTES
ns
ns
27
20
23
23
23
10
10
10
25
7
24
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PRELIMINARY
256Mb: x32
SDRAM
AC FUNCTIONAL CHARACTERISTICS
(Notes: 5, 6, 7, 8, 9, 11; notes appear on page 36)
PARAMETER
READ/WRITE command to READ/WRITE command
CKE to clock disable or power-down entry mode
CKE to clock enable or power-down exit setup mode
DQM to input data delay
DQM to data mask during WRITEs
DQM to data high-impedance during READs
WRITE command to input data delay
Data-in to ACTIVE command
SYMBOL
tCCD
tCKED
t PED
t DQD
tDQM
t DQZ
t DWD
tDAL (3)
tDAL (2)
tDAL (1)
tDPL
tBDL
tCDL
tRDL
tMRD
tROH (3)
tROH (2)
tROH (1)
CL = 3
CL = 2
CL = 1
Data-in to PRECHARGE command
Last data-in to burst STOP command
Last data-in to new READ/WRITE command
Last data-in to PRECHARGE command
LOAD MODE REGISTER command to ACTIVE or REFRESH command
Data-out to high-impedance from PRECHARGE command
CL = 3
CL = 2
CL = 1
-6
1
1
1
0
0
2
0
5
4
3
2
1
1
2
2
3
2
1
-7
1
1
1
0
0
2
0
5
4
3
2
1
1
2
2
3
2
1
UNITS
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
NOTES
17
14
14
17
17
17
17
15, 21
15, 21
15, 21
16, 21
17
17
16, 21
26
17
17
17
IDD SPECIFICATIONS AND CONDITIONS
(Notes: 1, 6, 11, 13; notes appear on page 36) (VDD, VDDQ = +3.3V ±0.3V)
MAX
PARAMETER/CONDITION
SYMBOL
IDD1
Operating Current: Active Mode; Burst = 2; READ or
WRITE;
t
RC = tRC (MIN)
Standby Current: Power-Down Mode; All banks idle; CKE IDD2N
= LOW
Standby Current: Power-Down Mode; All banks idle; CKE IDD2NS
= HIGH
Standby Current: Active Mode; CKE = HIGH; CS# = HIGH; IDD3NS
All banks active after tRCD met; No accesses in progress
IDD3N
Standby Current: Active Mode; CKE = LOW; CS# = HIGH;
All banks active; No accesses in progress
IDD4
Operating Current: Burst Mode; Continuous burst; READ
or WRITE; All banks active, half DQs toggling every cycle.
tRFC = tRFC
IDD5
Auto Refresh Current
CKE = HIGH; CS# = HIGH
(MIN)
tRFC =
IDD6
-6
-7
210
190
mA
300
300
µA
30
30
mA
40
40
mA
30
30
mA
165
145
mA
3, 18, 19, 26
335
295
mA
3, 12, 18, 19,
26
3
mA
3
UNITS
NOTES
3, 18, 19, 26
3, 12, 19, 26
15.625µs
SELF REFRESH current: CKE < 0.2V
09005aef80cd8e48
256MbSDRAMx32.p65 – Rev. B; Pub. 03/04
IDD7
35
1
1
mA
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PRELIMINARY
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SDRAM
NOTES
1.
2.
3.
4.
5.
6.
7.
8.
All voltages referenced to VSS.
This parameter is sampled. VDD, VDD Q = +3.3V;
f = 1 MHz, TA = 25°C; pin under test biased at 1.4V.
AC can range from 0pF to 6pF.
IDD is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle
time and the outputs open.
Enables on-chip refresh and address counters.
The minimum specifications are used only to indicate cycle time at which proper operation over the
full temperature range (0°C ≤ T A ≤ +70°C and
-40°C ≤ TA ≤ +85°C for IT parts) is ensured.
An initial pause of 100µs is required after powerup, followed by two AUTO REFRESH commands,
before proper device operation is ensured. (VDD
and VDDQ must be powered up simultaneously. VSS
and VSSQ must be at same potential.) The two
AUTO REFRESH command wake-ups should be
repeated any time the tREF refresh requirement is
exceeded.
AC characteristics assume tT = 1ns.
In addition to meeting the transition rate specification, the clock and CKE must transit between VIH
and VIL (or between VIL and VIH) in a monotonic
manner.
12. Other input signals are allowed to transition no
more than once in any two-clock period and are
otherwise at valid VIH or VIL levels.
13. IDD specifications are tested after the device is properly initialized.
14. Timing actually specified by tCKS; clock(s) specified as a reference only at minimum cycle rate.
15. Timing actually specified by tWR plus tRP; clock(s)
specified as a reference only at minimum cycle rate.
16. Timing actually specified by tWR.
17. Required clocks are specified by JEDEC functionality and are not dependent on any timing parameter.
18. The IDD current will decrease as the CAS latency is
reduced. This is due to the fact that the maximum
cycle rate is slower as the CAS latency is reduced.
19. Address transitions average one transition every
two clocks.
20. CLK must be toggled a minimum of two times during this period.
21. Based on tCK = 143 MHz for -7, 166 MHz for -6.
22. VIH overshoot: VIH (MAX) = VDDQ + 1.2V for a pulse
width ≤ 3ns, and the pulse width cannot be greater
than one third of the cycle rate. VIL undershoot: VIL
(MIN) = -1.2V for a pulse width ≤ 3ns, and the pulse
width cannot be greater than one third of the cycle
rate.
23. The clock frequency must remain constant during
access or precharge states (READ, WRITE, including tWR, and PRECHARGE commands). CKE may
be used to reduce the data rate.
24. Auto precharge mode only.
25. JEDEC and PC100 specify three clocks.
26. tCK = 7ns for -7, 6ns for -6.
27. Check factory for availability of specially screened
devices having tWR = 10ns. tWR = 1 tCK for 100 MHz
and slower ( tCK = 10ns and higher) in manual
precharge.
Q
30pF
9. Outputs measured at 1.5V with equivalent load:
10. tHZ defines the time at which the output achieves
the open circuit condition; it is not a reference to
VOH or VOL. The last valid data element will meet
tOH before going High-Z.
11. AC timing and IDD tests have VIL = .25 and VIH = 2.75,
with timing referenced to 1.5V crossover point.
09005aef80cd8e48
256MbSDRAMx32.p65 – Rev. B; Pub. 03/04
36
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©2003 Micron Technology, Inc.
PRELIMINARY
256Mb: x32
SDRAM
INITIALIZE AND LOAD MODE REGISTER
T0
CLK
((
))
tCKS
tCK
T1
Tn + 1
((
))
((
))
tCKH
tCH
((
))
((
))
To + 1
tCL
((
))
((
))
((
))
((
))
((
))
((
))
((
))
COMMAND
((
))
((
))
DQM 0-3
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
A0-A9, A11
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
A10
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
BA0, BA1
DQ
NOP
SINGLE BANK
ALL
BANKS
High-Z
Power-up:
VDD and
CK stable
Tp + 3
tCMS tCMH
((
))
PRECHARGE
((
))
ALL BANKS
((
))
((
))
((
))
T = 100µs
(MIN)
tCMS tCMH
Tp + 2
((
))
CKE
tCMS tCMH
Tp + 1
AUTO
REFRESH
((
))
NOP
NOP
((
))
AUTO
REFRESH
((
))
NOP
NOP
((
))
LOAD MODE
REGISTER
tAS
NOP
tAH
ROW
CODE
tAS
ACTIVE
tAH
ROW
CODE
BANK
((
))
tRP
Precharge
all banks
tRFC
tRFC
AUTO REFRESH
AUTO REFRESH
tMRD
Program Mode Register 1, 2
DON’T CARE
UNDEFINED
NOTE: 1. The Mode Register may be loaded prior to the AUTO REFRESH cycles if desired.
2. Outputs are guaranteed High-Z after command is issued.
09005aef80cd8e48
256MbSDRAMx32.p65 – Rev. B; Pub. 03/04
37
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©2003 Micron Technology, Inc.
PRELIMINARY
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SDRAM
POWER-DOWN MODE1
T0
T1
tCK
CLK
T2
tCKS
tCH
CKE
tCKS
PRECHARGE
Tn + 2
tCKS
((
))
tCKH
tCMS tCMH
COMMAND
Tn + 1
((
))
((
))
tCL
NOP
((
))
((
))
NOP
NOP
ACTIVE
DQM 0-3
((
))
((
))
A0-A9, A11
((
))
((
))
ROW
((
))
((
))
ROW
((
))
((
))
BANK
ALL BANKS
A10
SINGLE BANK
tAS
BA0, BA1
tAH
BANK(S)
High-Z
((
))
DQ
Two clock cycles
Input buffers gated off while in
power-down mode
Precharge all
active banks
All banks idle, enter
power-down mode
All banks idle
Exit power-down mode
DON’T CARE
UNDEFINED
NOTE: 1. Violating refresh requirements during power-down may result in a loss of data.
09005aef80cd8e48
256MbSDRAMx32.p65 – Rev. B; Pub. 03/04
38
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©2003 Micron Technology, Inc.
PRELIMINARY
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SDRAM
CLOCK SUSPEND MODE1
T0
T1
tCK
CLK
T2
T3
T4
T5
T6
T7
T8
NOP
WRITE
T9
tCL
tCH
tCKS tCKH
CKE
tCKS
tCKH
tCMS tCMH
COMMAND
READ
NOP
NOP
NOP
NOP
NOP
tCMS tCMH
DQM0-3
tAS
A0-A9, A11
tAH
COLUMN m 2
tAS
COLUMN e
2
tAH
A10
tAS
BA0, BA1
tAH
BANK
BANK
tAC
tOH
tAC
DQ
tLZ
DOUT m
tHZ
DOUT m + 1
tDS
tDH
DOUT e
DOUT e + 1
DON’T CARE
UNDEFINED
NOTE: 1. For this example, the burst length = 2, the CAS latency = 3, and auto precharge is disabled.
2. A9 and A11 = “Don’t Care.”
09005aef80cd8e48
256MbSDRAMx32.p65 – Rev. B; Pub. 03/04
39
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
PRELIMINARY
256Mb: x32
SDRAM
AUTO REFRESH MODE
T0
CLK
T1
tCK
T2
((
))
((
))
tCH
tCKS
tCKH
tCMS
tCMH
PRECHARGE
NOP
AUTO
REFRESH
NOP
((
))
( ( NOP
))
NOP
((
))
( ( NOP
))
ACTIVE
((
))
((
))
((
))
((
))
ROW
((
))
((
))
((
))
((
))
ROW
((
))
((
))
((
))
((
))
BANK
((
))
((
))
ALL BANKS
A10
SINGLE BANK
DQ
AUTO
REFRESH
((
))
((
))
A0-A9, A11
tAS
To + 1
((
))
((
))
((
))
DQM 0-3
BA0, BA1
((
))
((
))
((
))
CKE
COMMAND
Tn + 1
tCL
tAH
BANK(S)
High-Z
tRP
tRFC
tRFC
Precharge all
active banks
09005aef80cd8e48
256MbSDRAMx32.p65 – Rev. B; Pub. 03/04
DON’T CARE
40
UNDEFINED
DON’T CARE
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
PRELIMINARY
256Mb: x32
SDRAM
SELF REFRESH MODE
T0
CLK
T1
tCK
tCL
tCH
T2
tCKS
> tRAS
CKE
COMMAND
tCKS
tCKH
tCMS
tCMH
PRECHARGE
Tn + 1
((
))
((
))
((
))
((
))
((
))
NOP
AUTO
REFRESH
((
))
((
))
((
))
((
))
((
))
((
))
((
))
A0-A9, A11
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
SINGLE BANK
tAS
BA0, BA1
DQ
AUTO
REFRESH
))
((
))
((
))
ALL BANKS
To + 2
tCKS
NOP ( (
DQM 0-3
A10
To + 1
tAH
BANK(S)
High-Z
tRP
Precharge all
active banks
tXSR
Enter self refresh mode
Exit self refresh mode
(Restart refresh time base)
CLK stable prior to exiting
self refresh mode
09005aef80cd8e48
256MbSDRAMx32.p65 – Rev. B; Pub. 03/04
41
DON’T CARE
UNDEFINED
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
PRELIMINARY
256Mb: x32
SDRAM
SINGLE READ – WITHOUT AUTO PRECHARGE1
T0
T1
T2
tCK
CLK
T3
T4
T5
NOP
ACTIVE
tCL
tCH
tCKS
tCKH
tCMS
tCMH
CKE
COMMAND
ACTIVE
NOP
READ
tCMS
PRECHARGE
tCMH
DQM /
DQML, DQMH
tAS
A0-A9, A11
COLUMN m2
ROW
tAS
ROW
tAH
ALL BANKS
ROW
A10
tAS
BA0, BA1
tAH
ROW
DISABLE AUTO PRECHARGE
tAH
BANK
SINGLE BANK
BANK
BANK
BANK
tAC
DQ
tLZ
tRCD
tOH
DOUT m
tHZ
CAS Latency
tRP
tRAS
tRC
DON’T CARE
NOTE: 1. For this example, the burst length = 1, the CAS latency = 2, and the READ burst is followed by a “manual” PRECHARGE.
2. A9 and A11 = “Don’t Care.”
09005aef80cd8e48
256MbSDRAMx32.p65 – Rev. B; Pub. 03/04
42
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
PRELIMINARY
256Mb: x32
SDRAM
READ – WITHOUT AUTO PRECHARGE1
T0
T1
tCK
CLK
T2
T3
T4
T5
NOP
NOP
T6
T7
T8
NOP
ACTIVE
tCL
tCH
tCKS
tCKH
tCMS
tCMH
CKE
COMMAND
ACTIVE
NOP
READ
tCMS
NOP
PRECHARGE
tCMH
DQM 0-3
tAS
COLUMN m 2
ROW
A0-A9, A11
tAS
ROW
tAH
ALL BANKS
ROW
A10
tAS
BA0, BA1
tAH
ROW
SINGLE BANK
DISABLE AUTO PRECHARGE
tAH
BANK
BANK
BANK
tAC
tOH
tAC
DQ
tLZ
tRCD
DOUT m
tAC
tOH
DOUT m + 1
BANK
tAC
tOH
tOH
DOUT m + 2
DOUT m + 3
tHZ
tRP
CAS Latency
tRAS
tRC
DON’T CARE
UNDEFINED
NOTE: 1. For this example, the burst length = 4, the CAS latency = 2, and the READ burst is followed by a “manual” PRECHARGE.
2. A9 and A11 = “Don’t Care.”
09005aef80cd8e48
256MbSDRAMx32.p65 – Rev. B; Pub. 03/04
43
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
PRELIMINARY
256Mb: x32
SDRAM
READ – WITH AUTO PRECHARGE1
T0
T1
tCK
CLK
tCKS
T2
T3
T4
T5
NOP
NOP
T6
T7
T8
NOP
ACTIVE
tCL
tCH
tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
READ
tCMS
NOP
NOP
tCMH
DQM 0-3
tAS
A0-A9, A11
tAH
ROW
ENABLE AUTO PRECHARGE
ROW
tAS
BA0, BA1
COLUMN m 2
ROW
tAS
A10
tAH
ROW
tAH
BANK
BANK
BANK
tAC
tOH
tAC
DQ
tLZ
tRCD
DOUT m
tAC
tAC
tOH
tOH
tOH
DOUT m + 1
DOUT m + 2
DOUT m + 3
tHZ
tRP
CAS Latency
tRAS
tRC
DON’T CARE
UNDEFINED
NOTE: 1. For this example, the burst length = 4, and the CAS latency = 2.
2. A9 and A11 = “Don’t Care.”
09005aef80cd8e48
256MbSDRAMx32.p65 – Rev. B; Pub. 03/04
44
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
PRELIMINARY
256Mb: x32
SDRAM
ALTERNATING BANK READ ACCESSES1
T0
T1
tCK
CLK
T2
T3
T4
T5
NOP
ACTIVE
T6
T7
T8
READ
NOP
ACTIVE
tCL
tCH
tCKS
tCKH
tCMS
tCMH
CKE
COMMAND
ACTIVE
NOP
READ
tCMS
NOP
tCMH
DQM 0-3
tAS
A0-A9, A11
tAH
COLUMN b 2
ROW
ENABLE AUTO PRECHARGE
ROW
ENABLE AUTO PRECHARGE
ROW
tAS
BA0, BA1
COLUMN m 2
ROW
tAS
A10
tAH
ROW
ROW
tAH
BANK 0
BANK 0
BANK 4
tAC
tOH
tAC
DQ
tLZ
tRCD - BANK 0
BANK 4
DOUT m
tAC
tOH
DOUT m + 1
BANK 0
tAC
tOH
DOUT m + 2
tAC
tOH
DOUT m + 3
tRP - BANK 0
CAS Latency - BANK 0
tAC
tOH
DOUT b
tRCD - BANK 0
tRAS - BANK 0
tRC - BANK 0
tRCD - BANK 4
tRRD
CAS Latency - BANK 4
DON’T CARE
UNDEFINED
NOTE: 1. For this example, the burst length = 4, and the CAS latency = 2.
2. A9 and A11 = “Don’t Care.”
09005aef80cd8e48
256MbSDRAMx32.p65 – Rev. B; Pub. 03/04
45
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
PRELIMINARY
256Mb: x32
SDRAM
READ – FULLL-PAGE BURST1
T0
T1
T2
tCL
CLK
T3
T4
T5
T6
((
))
((
))
tCK
tCH
tCKS
tCMH
ACTIVE
NOP
READ
tCMS
NOP
NOP
NOP
NOP
tCMH
tAS
tAH
tAH
NOP
BURST TERM
NOP
NOP
((
))
((
))
ROW
tAS
((
))
((
))
((
))
((
))
COLUMN m 2
ROW
tAS
BA0, BA1
Tn + 4
((
))
((
))
DQM 0-3
A10
Tn + 3
((
))
((
))
tCMS
A0-A9, A11
Tn + 2
tCKH
CKE
COMMAND
Tn + 1
tAH
BANK
((
))
((
))
BANK
tAC
tAC
tOH
Dout m
DQ
DOUT m+1
tLZ
tRCD
CAS Latency
tAC
tOH
tAC ( (
))
tOH
((
))
DOUT m+2
((
))
tAC
tOH
DOUT m-1
tAC
tOH
DOUT m
tOH
DOUT m+1
tHZ
256 locations within same row
Full page completed
Full-page burst does not self-terminate.
3
Can use BURST TERMINATE command.
DON’T CARE
UNDEFINED
NOTE: 1. For this example, the CAS latency = 2.
2. A9 and A11 = “Don’t Care.”
3. Page left open; no tRP.
09005aef80cd8e48
256MbSDRAMx32.p65 – Rev. B; Pub. 03/04
46
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
PRELIMINARY
256Mb: x32
SDRAM
READ – DQM OPERATION1
T0
T1
tCK
CLK
tCKS
tCKH
tCMS
tCMH
T2
T3
T4
T5
NOP
NOP
T6
T7
T8
NOP
NOP
NOP
tCL
tCH
CKE
COMMAND
ACTIVE
NOP
READ
tCMS
NOP
tCMH
DQM 0-3
tAS
A0-A9, A11
tAH
ENABLE AUTO PRECHARGE
ROW
tAS
BA0, BA1
COLUMN m 2
ROW
tAS
A10
tAH
DISABLE AUTO PRECHARGE
tAH
BANK
BANK
tAC
DQ
tOH
DOUT m
tLZ
tRCD
tAC
tHZ
tAC
tOH
DOUT m + 2
tLZ
tOH
DOUT m + 3
tHZ
CAS Latency
DON’T CARE
UNDEFINED
NOTE: 1. For this example, the CAS latency = 2.
2. A9 and A11 = “Don’t Care.”
09005aef80cd8e48
256MbSDRAMx32.p65 – Rev. B; Pub. 03/04
47
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
PRELIMINARY
256Mb: x32
SDRAM
SINGLE WRITE
T0
tCK
CLK
T1
T2
tCL
T3
T4
T5
T6
tCH
tCKS
tCKH
tCMS
tCMH
CKE
COMMAND
ACTIVE
NOP
WRITE
NOP
PRECHARGE
NOP
ACTIVE
tCMS tCMH
DQM /
DQML, DQMH
tAS
A0-A9, A11
ROW
tAH
ALL BANKS
ROW
tAS
BA0, BA1
COLUMN m 3
ROW
tAS
A10
tAH
ROW
DISABLE AUTO PRECHARGE
tAH
BANK
SINGLE BANK
BANK
tDS
BANK
BANK
tDH
DIN m
DQ
tRCD
tRAS
t WR 2
tRP
tRC
DON’T CARE
NOTE: 1. For this example, the burst length = 1, and the WRITE burst is followed by a “manual” PRECHARGE.
2. tWR is required between <DIN m> and the PRECHARGE command, regardless of frequency.
3. A9 and A11 = “Don’t Care.”
09005aef80cd8e48
256MbSDRAMx32.p65 – Rev. B; Pub. 03/04
48
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
PRELIMINARY
256Mb: x32
SDRAM
WRITE – WITHOUT AUTO PRECHARGE1
T0
tCK
CLK
T1
T2
tCL
T3
T4
T5
T6
NOP
NOP
NOP
T7
T8
NOP
ACTIVE
tCH
tCKS
tCKH
tCMS
tCMH
CKE
COMMAND
ACTIVE
NOP
WRITE
PRECHARGE
tCMS tCMH
DQM 0-3
tAS
A0-A9, A11
ROW
tAH
ALL BANKs
ROW
tAS
BA0, BA1
COLUMN m 3
ROW
tAS
A10
tAH
ROW
tAH
DISABLE AUTO PRECHARGE
SINGLE BANK
BANK
BANK
BANK
tDS
tDH
DIN m
DQ
tDS
tDH
DIN m + 1
tDS
tDH
DIN m + 2
tDS
tDH
DIN m + 3
t WR 2
tRCD
tRAS
BANK
tRP
tRC
DON T CARE
NOTE: 1.
2.
3.
4.
For this example, the burst length = 4, and the WRITE burst is followed by a “manual” PRECHARGE.
Faster frequencies require two clocks (when tWR > tCK).
A9 and A11 = “Don’t Care.”
t
WR of 1 CLK available if running 100 MHz or slower. Check factory for availability.
09005aef80cd8e48
256MbSDRAMx32.p65 – Rev. B; Pub. 03/04
49
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
PRELIMINARY
256Mb: x32
SDRAM
WRITE – WITH AUTO PRECHARGE1
T0
tCK
CLK
tCKS
tCKH
tCMS
tCMH
T1
T2
tCL
T3
T4
T5
T6
T7
T8
T9
NOP
NOP
NOP
NOP
NOP
NOP
ACTIVE
tCH
CKE
COMMAND
ACTIVE
NOP
WRITE
tCMS tCMH
DQM 0-3
tAS
A0-A9, A11
tAH
ROW
ENABLE AUTO PRECHARGE
ROW
tAS
BA0, BA1
COLUMN m 3
ROW
tAS
A10
tAH
ROW
tAH
BANK
BANK
tDS
tDH
DIN m
DQ
BANK
tDS
tDH
DIN m + 1
tDS
tDH
DIN m + 2
tDS
tDH
DIN m + 3
tWR 2
tRCD
tRAS
tRP
tRC
DON’T CARE
NOTE: 1. For this example, the burst length = 4.
2. Faster frequencies require two clocks (when tWR > tCK).
3. A9 and A11 = “Don’t Care.”
09005aef80cd8e48
256MbSDRAMx32.p65 – Rev. B; Pub. 03/04
50
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
PRELIMINARY
256Mb: x32
SDRAM
ALTERNATING BANK WRITE ACCESSES1
T0
tCK
CLK
T1
T2
tCL
T3
T4
T5
T6
T7
T8
T9
NOP
NOP
ACTIVE
tCH
tCKS
tCKH
tCMS
tCMH
CKE
COMMAND
ACTIVE
NOP
WRITE
tCMS
NOP
ACTIVE
NOP
WRITE
tCMH
DQM 0-3
tAS
A0-A9, A11
tAS
A10
COLUMN m 3
tAH
COLUMN b 3
ROW
ENABLE AUTO PRECHARGE
ROW
ENABLE AUTO PRECHARGE
ROW
tAS
BA0, BA1
tAH
ROW
ROW
ROW
tAH
BANK 0
BANK 0
tDS
tDH
DIN m
DQ
BANK 1
tDS
tDH
DIN m + 1
tDS
BANK 1
tDH
tDS
DIN m + 2
tDH
DIN m + 3
tDS
tDH
DIN b
tWR2 - BANK 0
tRCD - BANK 0
BANK 0
tDS
tDH
DIN b + 1
tRP - BANK 0
tDS
tDH
DIN b + 2
tDS
tDH
DIN b + 3
tRCD - BANK 0
tRAS - BANK 0
tRC - BANK 0
tRRD
tRCD - BANK 4
tWR - BANK 4
DON’T CARE
NOTE: 1. For this example, the burst length = 4.
2. Faster frequencies require two clocks (when tWR > tCK).
3. A9 and A11 = “Don’t Care.”
09005aef80cd8e48
256MbSDRAMx32.p65 – Rev. B; Pub. 03/04
51
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
PRELIMINARY
256Mb: x32
SDRAM
WRITE – FULL-PAGE BURST
T0
T1
T2
tCL
CLK
T3
T4
T5
((
))
((
))
tCK
tCH
tCKS
tCKH
COMMAND
tCMH
ACTIVE
NOP
WRITE
NOP
NOP
NOP
tCMS tCMH
A0-A9, A11
tAS
A10
((
))
((
))
NOP
BURST TERM
NOP
((
))
((
))
COLUMN m 1
tAH
((
))
((
))
ROW
tAS
BA0, BA1
tAH
ROW
Tn + 3
((
))
((
))
DQM 0-3
tAS
Tn + 2
((
))
((
))
CKE
tCMS
Tn + 1
tAH
BANK
((
))
((
))
BANK
tDS
tDH
DIN m
DQ
tDS
tDH
tDS
DIN m + 1
tDH
DIN m + 2
tRCD
tDS
tDH
DIN m + 3
((
))
((
))
tDS
tDH
DIN m - 1
256 locations within same row
Full-page burst does
not self-terminate. Can
use BURST TERMINATE
command to stop.2, 3
Full page completed
NOTE: 1. A9 and A11 = “Don’t Care.”
2. tWR must be satisfied prior to PRECHARGE command.
3. Page left open; no tRP.
09005aef80cd8e48
256MbSDRAMx32.p65 – Rev. B; Pub. 03/04
52
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
PRELIMINARY
256Mb: x32
SDRAM
WRITE – DQM OPERATION1
T0
T1
tCK
CLK
T2
T3
T4
T5
NOP
NOP
NOP
T6
T7
NOP
NOP
tCL
tCH
tCKS
tCKH
tCMS
tCMH
CKE
COMMAND
ACTIVE
NOP
WRITE
tCMS tCMH
DQM 0-3
tAS
A0-A9, A11
tAH
ENABLE AUTO PRECHARGE
ROW
tAS
BA0, BA1
COLUMN m 2
ROW
tAS
A10
tAH
tAH
DISABLE AUTO PRECHARGE
BANK
BANK
tDS
tDH
tDS
DIN m
DQ
tDH
DIN m + 2
tDS
tDH
DIN m + 3
tRCD
DON’T CARE
NOTE: 1. For this example, the burst length = 4.
2. A9 and A11 = “Don’t Care.”
09005aef80cd8e48
256MbSDRAMx32.p65 – Rev. B; Pub. 03/04
53
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
PRELIMINARY
256Mb: x32
SDRAM
86-PIN PLASTIC TSOP (400 MIL)
SEE DETAIL A
22.22 ±.08
.61
.50
TYP
.10 (2X)
+.07
0.20 -.03
2.80 (2X)
11.76 ±.10
10.16 ±.08
R .75 (2X)
PIN #1 ID
+.03
.15 -.02
R 1.00
(2X)
.25
GUAGE
PLANE
+.10
.10 -.05
.10
.50 ±.10
1.20 MAX
.80
TYP
DETAIL A
NOTE:
1. All dimensions in millimeters.
2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm
per side.
09005aef80cd8e48
256MbSDRAMx32.p65 – Rev. B; Pub. 03/04
54
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
PRELIMINARY
256Mb: x32
SDRAM
90-BALL FBGA (8mm x 13mm)
0.65 ±0.05
SEATING PLANE
C
0.10 C
SOLDER BALL MATERIAL: 62% Sn, 36% Pb, 2% Ag OR
96.5% Sn, 3%Ag, 0.5% Cu
SOLDER MASK DEFINED BALL PADS: Ø0.40
90X Ø0.45 ±0.05
SOLDER BALL DIAMETER
REFERS TO POST REFLOW
CONDITION. THE PREREFLOW DIAMETER IS Ø0.42
SUBSTRATE MATERIAL: PLASTIC LAMINATE
MOLD COMPOUND: EPOXY NOVOLAC
6.40
0.80 TYP
BALL A1 ID
BALL A1 ID
BALL A1
BALL A9
0.80 TYP
11.20 ±0.10
CL
13.00 ±0.10
5.60 ±0.05
6.50 ±0.05
CL
3.20 ±0.05
1.00 MAX
4.00 ±0.05
8.00 ±0.10
(Bottom View)
NOTE: 1. All dimensions in millimeters.
2. Recommended pad size for PCB is 0.33mm±0.025mm.
Preliminary: This data sheet contains initial characterization limits that are subject to change upon full
characterization of production devices.
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
E-mail: [email protected], Internet: http://www.micronsemi.com, Customer Comment Line: 800-932-4992
Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
09005aef80cd8e48
256MbSDRAMx32.p65 – Rev. B; Pub. 03/04
55
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.