AD AD7176-2BRUZ The ad7176-2 is a fast settling, highly accurate, high resolution, multiplexed î£-î analog-to-digital converter (adc) for low band-width input signals. Datasheet

24-Bit, 250 kSPS Sigma-Delta ADC
with 20 µs Settling
AD7176-2
Data Sheet
FEATURES
GENERAL DESCRIPTION
Fast and flexible output rate—5 SPS to 250 kSPS
Fast settling time—20 µs
Channel scan data rate of 50 kSPS/channel
Performance specifications
17 noise free bits at 250 kSPS
20 noise free bits at 2.5 kSPS
22 noise free bits at 5 SPS
INL ±2.5 ppm of FSR
85 dB rejection of 50 Hz and 60 Hz with 50 ms settling
User-configurable input channels
2 fully differential or 4 pseudo differential
Crosspoint multiplexer
On-chip 2.5 V reference (drift 2 ppm/°C)
Internal oscillator, external crystal, or external clock
Power supply
Single supply: 5 V AVDD1, 2 V to 5 V AVDD2 and IOVDD
Optional split supply: AVDD1 and AVSS ± 2.5 V
Current: 7.8 mA
Temperature range: −40°C to +105°C
3- or 4-wire serial digital interface (Schmitt trigger on SCLK)
CRC error checking
SPI, QSPI, MICROWIRE, and DSP compatible
The AD7176-2 is a fast settling, highly accurate, high resolution,
multiplexed Σ-Δ analog-to-digital converter (ADC) for low bandwidth input signals. Its inputs can be configured as two fully
differential or four pseudo differential inputs via the integrated
crosspoint multiplexer. An integrated precision, 2.5 V, low drift
(2 ppm/°C), band gap internal reference (with an output
reference buffer) adds functionality and reduces the external
component count.
The maximum channel scan data rate is 50 kSPS (with a settling
time of 20 µs), resulting in fully settled data of 17 noise free bits.
User-selectable output data rates range from 5 SPS to 250 kSPS.
The resolution increases at lower speeds.
The AD7176-2 offers three key digital filters. The fast settling filter
maximizes the channel scan rate. The Sinc3 filter maximizes the
resolution for single-channel, low speed applications. For 50 Hz
and 60 Hz environments, the AD7176-2 specific filter minimizes
the settling times or maximizes the rejection of the line frequency.
These enhanced filters enable simultaneous 50 Hz and 60 Hz rejection with a 27 SPS output data rate (with a settling time of 36 ms).
System offset and gain errors can be corrected on a per channel
basis. This per channel configurability extends to the type of filter
and output data rate used for each channel. All switching of the
crosspoint multiplexer is controlled by the ADC and can be configured to automatically control an external multiplexer via the
GPIO pins.
APPLICATIONS
Process control: PLC/DCS modules
Temperature and pressure measurement
Medical and scientific multichannel instrumentation
Chromatography
The specified operating temperature range is −40°C to +105°C.
The AD7176-2 is housed in a 24-lead TSSOP package.
FUNCTIONAL BLOCK DIAGRAM
AVDD1
AVDD2 REGCAPA REF– REF+ REFOUT
IOVDD REGCAPD
BUFFERED
PRECISION
REFERENCE
1.8V
LDO
1.8V
LDO
INT
REF
AIN0
CS
AIN1
DIGITAL
FILTER
Σ-Δ ADC
AIN2
SERIAL
INTERFACE
AND CONTROL
SCLK
DIN
DOUT/RDY
AIN3
I/O
CONTROL
AD7176-2
CROSSPOINT
MULTIPLEXER
AVSS
SYNC/ERROR
XTAL AND INTERNAL
CLOCK OSCILLATOR
CIRCUITRY
GPIO0 GPIO1
XTAL1 CLKIO/XTAL2
DGND
11037-001
AIN4
Figure 1.
Rev. 0
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Technical Support
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AD7176-2
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Serial Interface Reset (DOUT_RESET) .................................. 41
Applications ....................................................................................... 1
Synchronization (SYNC/ERROR) ........................................... 41
General Description ......................................................................... 1
Error Flags ................................................................................... 42
Functional Block Diagram .............................................................. 1
DATA_STAT ............................................................................... 42
Revision History ............................................................................... 3
IOSTRENGTH ........................................................................... 42
Specifications..................................................................................... 4
Grounding and Layout .................................................................. 43
Timing Characteristics ................................................................ 7
Register Summary .......................................................................... 44
Timing Diagrams.......................................................................... 7
Register Details ............................................................................... 46
Absolute Maximum Ratings ............................................................ 8
Communications Register......................................................... 46
Thermal Resistance ...................................................................... 8
Status Register ............................................................................. 47
ESD Caution .................................................................................. 8
ADC Mode Register ................................................................... 48
Pin Configuration and Function Descriptions ............................. 9
Interface Mode Register ............................................................ 49
Typical Performance Characteristics ........................................... 11
Register Check ............................................................................ 50
Noise Performance and Resolution .............................................. 15
Data Register ............................................................................... 50
Getting Started ................................................................................ 16
GPIO Configuration Register ................................................... 51
Power Supplies ............................................................................ 17
ID Register................................................................................... 52
Digital Communication............................................................. 17
Channel Map Register 0 ............................................................ 53
Configuration Overview ........................................................... 19
Channel Map Register 1 ............................................................ 54
Circuit Description ......................................................................... 23
Channel Map Register 2 ............................................................ 55
Analog Input ............................................................................... 23
Channel Map Register 3 ............................................................ 56
Driver Amplifiers ....................................................................... 23
Setup Configuration Register 0 ................................................ 57
AD7176-2 Reference ................................................................... 26
Setup Configuration Register 1 ................................................ 57
AD7176-2 Clock Source ............................................................. 27
Setup Configuration Register 2 ................................................ 58
Digital Filters ................................................................................... 28
Setup Configuration Register 3 ................................................ 58
Sinc5 + Sinc1 Filter..................................................................... 28
Filter Configuration Register 0................................................. 59
Sinc3 Filter ................................................................................... 29
Filter Configuration Register 1................................................. 60
Single Cycle Settling ................................................................... 29
Filter Configuration Register 2................................................. 61
Enhanced 50 Hz and 60 Hz Rejection Filters ......................... 31
Filter Configuration Register 3................................................. 62
Operating Modes ............................................................................ 34
Offset Register 0 ......................................................................... 63
Continuous Conversion Mode ................................................. 34
Offset Register 1 ......................................................................... 63
Continuous Read Mode ............................................................. 35
Offset Register 2 ......................................................................... 63
Single Conversion Mode ........................................................... 36
Offset Register 3 ......................................................................... 63
Standby and Power-Down Modes ............................................ 37
Gain Register 0............................................................................ 64
Calibration Modes ...................................................................... 37
Gain Register 1............................................................................ 64
Digital Interface .............................................................................. 38
Gain Register 2............................................................................ 64
Checksum Protection................................................................. 38
Gain Register 3............................................................................ 64
CRC Calculation ......................................................................... 39
Outline Dimensions ....................................................................... 65
General-Purpose I/O ................................................................. 41
Ordering Guide .......................................................................... 65
16-Bit/24-Bit Conversions ......................................................... 41
Rev. 0 | Page 2 of 68
Data Sheet
AD7176-2
REVISION HISTORY
11/12—Revision 0—Initial Version
Rev. 0 | Page 3 of 68
AD7176-2
Data Sheet
SPECIFICATIONS
AVDD1 = 4.5 V to 5.5 V, AVDD2 = 2 V to 5.5 V, IOVDD = 2 V to 5.5 V, AVSS = DGND = 0 V, REF+ = 2.5 V, REF− = AVSS,
internal master clock = 16 MHz, TA = TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter
ADC SPEED AND PERFORMANCE
Output Data Rate (ODR)
No Missing Codes 1
Resolution
Noise
Noise Free Resolution
ACCURACY
Integral Nonlinearity (INL)
Offset Error 2
Offset Drift
Offset Drift vs. Time 3
Gain Error2
Gain Drift vs. Temperature1
Gain Drift vs. Time3
REJECTION
Power Supply Rejection
Common-Mode Rejection
At DC
At 50 Hz and 60 Hz1
Normal Mode Rejection1
ANALOG INPUTS
Differential Input Voltage Range
Absolute AIN Voltage Limits1
Analog Input Current
Input Current
Input Current Drift
Crosstalk
INTERNAL REFERENCE
Output Voltage
Initial Accuracy1
Temperature Coefficient
Reference Load Current, ILOAD
Power Supply Rejection (Line
Regulation)
Load Regulation
Voltage Noise
Voltage Noise Density
Test Conditions/Comments
Min
Typ
5
24
See Table 6
See Table 6
250 kSPS, REF+ = 5 V
2.5 kSPS, REF+ = 5 V
5 SPS, REF+ = 5 V
Max
Unit
250,000
SPS
Bits
17
20
22
2.5 V reference
5 V reference
±2.5
±7
±40
±110
±450
±10
±0.5
±3
25°C
AVDD1, AVDD2 VIN = 1 V
Bits
Bits
Bits
±7
±50
±1
90
VIN = 0.1 V
20 SPS ODR (post filter)
(50 Hz ± 1 Hz and 60 Hz ± 1 Hz)
50 Hz ± 1 Hz and 60 Hz ± 1 Hz
Internal clock, 20 SPS ODR (post filter)
External clock, 20 SPS ODR (post filter)
dB
95
130
71
85
dB
dB
90
90
dB
dB
±VREF
AVSS − 0.050
External clock
Internal clock (±2.5 % clock)
1 kHz input
100 nF external capacitor on
REFOUT to AVSS
REFOUT with respect to AVSS
TA = 25°C
0°C to +105°C
−40°C to +105°C
IL
AVDD1 and AVDD2
AVDD1 + 0.05
±48
±0.75
±4
−120
+ 0.16%
±2
±3
±5
±10
+10
V
V
93
ppm/°C
ppm/°C
mA
dB
32
4.5
215
ppm/mA
µV rms
nV/√Hz
−10
Rev. 0 | Page 4 of 68
V
V
µA/V
nA/V/°C
nA/V/°C
dB
2.5
− 0.16%
∆VOUT/∆IL
eN, 0.1 Hz to 10 Hz
eN, 1 kHz
ppm of FSR
ppm of FSR
µV
nV/°C
nV/500 hours
ppm/FSR
ppm/FSR/°C
ppm/FSR/
500 hours
Data Sheet
Parameter
Turn-On Settling Time
Long-Term Stability3
Short Circuit
EXTERNAL REFERENCE
Reference Input Voltage
Absolute Reference Input
Voltage Limits1
Average Reference Input
Current
Average Reference Input
Current Drift
Normal Mode Rejection1
Common-Mode Rejection
GENERAL-PURPOSE I/O (GPIO 0,
GPIO 1)
Output High Voltage, VOH1
Output Low Voltage, VOL1
Input Mode Leakage Current1
Floating-State Output
Capacitance
Input High Voltage, VIH1
Input Low Voltage, VIL1
CLOCK
Internal Clock
Frequency
Accuracy
Duty Cycle
Output Low Voltage, VOL
Output High Voltage, VOH
Crystal
Frequency
Start-Up Time
External Clock (CLKIO)
Duty Cycle1
LOGIC INPUTS
Input High Voltage, VINH1
Input Low Voltage, VINL1
Hysteresis1
Leakage Currents
LOGIC OUTPUT (DOUT/RDY)
Output High Voltage, VOH1
Output Low Voltage, VOL1
Leakage Current
Output Capacitance
AD7176-2
Test Conditions/Comments
100 nF capacitor
500 hours
ISC
Min
Typ
60
460
25
Max
Unit
µs
ppm
mA
Reference input = (REF+) – (REF−)
1
AVSS − 0.05
2.5
AVDD1
AVDD1 + 0.05
V
V
±72
µA/V
External clock
±1.2
nA/V/°C
Internal clock
See the Rejection parameter section
of this table
±6
nA/V/°C
83
dB
With respect to AVSS
ISOURCE = 200 µA
ISINK = 800 µA
AVSS + 4
AVSS + 0.4
+10
−10
5
AVSS + 3
AVSS + 0.7
16
−2.5
+2.5
50:50
0.4
0.8 × IOVDD
14
Typical duty cycle 50:50 (max:min)
30
2 V ≤ IOVDD ≤ 2.3 V
2.3 V ≤ IOVDD ≤ 5.5 V
2 V ≤ IOVDD ≤ 2.3 V
2.3 V ≤ IOVDD ≤ 5.5 V
IOVDD > 2.7 V
IOVDD < 2.7 V
0.65 × IOVDD
0.7 × IOVDD
IOVDD ≥ 4.5 V, ISOURCE = 1 mA
2.7 V ≤ IOVDD < 4.5 V, ISOURCE = 500 μA
IOVDD < 2.7 V, ISOURCE = 200 μA
IOVDD ≥ 4.5 V, ISINK = 2 mA
2.7 V ≤ IOVDD < 4.5 V, ISINK = 1 mA
IOVDD < 2.7 V, ISINK = 400 μA
Floating state
Floating state
0.8 × IOVDD
0.8 × IOVDD
0.8 × IOVDD
16
50
16
50:50
0.08
0.04
−10
10
V
V
MHz
%
%
V
V
16.384
70
MHz
µs
MHz
%
0.35 × IOVDD
0.7
0.25
0.2
+10
V
V
V
V
V
V
µA
0.4
0.4
0.4
+10
−10
Rev. 0 | Page 5 of 68
16.384
V
V
µA
pF
V
V
V
V
V
V
µA
pF
AD7176-2
Parameter
SYSTEM CALIBRATION1
Full-Scale Calibration Limit
Zero-Scale Calibration Limit
Input Span
POWER REQUIREMENTS
Power Supply Voltage
AVDD1 − AVSS
AVDD2 – AVSS
AVSS – DGND
IOVDD − DGND
IOVDD – AVSS
POWER SUPPLY CURRENTS
Full Operating Mode
AVDD1 Current
AVDD2 Current
IOVDD Current
Standby Mode
Standby (LDO On)
Power-Down Mode
POWER DISSIPATION
Full Operating Mode
Standby Mode
Power-Down Mode
Data Sheet
Test Conditions/Comments
Min
Typ
−1.05 × FS
0.8 × FS
4.5
2
−2.75
2
For AVSS < DGND
All outputs unloaded, digital inputs
connected to IOVDD or DGND
Max
Unit
1.05 × FS
2.1 × FS
V
V
V
5.5
5.5
0
5.5
6.35
V
V
V
V
V
1.75
2.1
4.9
5.1
2.3
2.6
mA
mA
mA
mA
mA
mA
mA
External reference
Internal reference
External reference
Internal reference
External clock
Internal clock
External crystal
1.5
1.75
4.3
4.5
2
2.25
2.5
Internal reference off, total current
consumption
Internal reference on, total current
consumption
Full power-down, LDO, Internal
reference
22
µA
415
µA
0.5
10
µA
AVDD2 = 2 V, IOVDD = 2 V,
external clock and reference
AVDD2 = 5 V, IOVDD = 5 V,
external clock and reference
AVDD2 = 2 V, IOVDD = 2 V,
internal clock and reference
AVDD2 = 5 V, IOVDD = 5 V,
internal clock and reference
Internal reference off, all supplies = 5 V
Internal reference on, all supplies = 5 V
Full power-down
20.1
23.15
mW
39
44.75
mW
22.25
25.9
mW
42.5
49
mW
50
µW
mW
µW
110
2.1
2.5
Specification is not production tested but is supported by characterization data at the initial product release.
Following a system or internal zero-scale calibration, the offset error is in the order of the noise for the programmed output data rate selected. A system full-scale
calibration reduces the gain error to the order of the noise for the programmed output data rate.
3
The long-term stability specification is noncumulative.
1
2
Rev. 0 | Page 6 of 68
Data Sheet
AD7176-2
TIMING CHARACTERISTICS
IOVDD = 2 V to 5.5 V, DGND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = IOVDD, CLOAD = 20 pF, unless otherwise noted.
Table 2.
Parameter
t3
t4
READ OPERATION
t1
t2 3
t5 5
t6
t7
WRITE OPERATION
t8
t9
t10
t11
Limit at TMIN, TMAX (B Version)
25
25
Unit
ns min
ns min
Test Conditions/Comments 1, 2
SCLK high pulse width
SCLK low pulse width
0
15
40
0
12
25
2.5
20
0
10
ns min
ns max
ns max
ns min
ns max
ns max
ns min
ns max
ns min
ns min
CS falling edge to DOUT/RDY active time
IOVDD = 4.5 V to 5.5 V
IOVDD = 2 V to 3.6 V
SCLK active edge to data valid delay 4
IOVDD = 4.5 V to 5.5 V
IOVDD = 2 V to 3.6 V
Bus relinquish time after CS inactive edge
0
8
8
5
ns min
ns min
ns min
ns min
CS falling edge to SCLK active edge setup time4
Data valid to SCLK edge setup time
Data valid to SCLK edge hold time
CS rising edge to SCLK edge hold time
SCLK inactive edge to CS inactive edge
SCLK inactive edge to DOUT/RDY high/low
Sample tested during initial release to ensure compliance.
See Figure 2 and Figure 3.
3
The time required for the output to cross the VOL or VOH limits.
4
The SCLK active edge is the falling edge of SCLK.
5 RDY
returns high after a read of the data register. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while RDY
is high, although care should be taken to ensure that subsequent reads do not occur close to the next output update. If the continuous read feature is enabled, the
digital word can be read only once.
1
2
TIMING DIAGRAMS
CS (I)
t6
t1
t5
MSB
DOUT/RDY (O)
LSB
t7
t2
t3
11037-002
SCLK (I)
t4
I = INPUT, O = OUTPUT
Figure 2. Read Cycle Timing Diagram
CS (I)
t11
t8
SCLK (I)
t9
t10
MSB
LSB
I = INPUT, O = OUTPUT
Figure 3. Write Cycle Timing Diagram
Rev. 0 | Page 7 of 68
11037-003
DIN (I)
AD7176-2
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
THERMAL RESISTANCE
Table 3.
θJA is specified for a device soldered on a JEDEC test board for
surface-mount packages. The values listed in Table 4 are based
on simulated data.
Parameter
AVDD1, AVDD2 to AVSS
AVDD1 to DGND
Rating
−0.3 V to +6.5 V
−0.3 V to +6.5 V
IOVDD to DGND
IOVDD to AVSS
−0.3 V to +6.5 V
−0.3 V to +7.5 V
AVSS to DGND
Analog Input Voltage to AVSS
Reference Input Voltage to AVSS
−3.25 V to +0.3 V
−0.3 V to AVDD1 + 0.3 V
−0.3 V to AVDD1 + 0.3 V
Digital Input Voltage to DGND
Digital Output Voltage to DGND
AIN[4:0] or Digital Input Current
Operating Temperature Range
−0.3 V to IOVDD + 0.3 V
−0.3 V to IOVDD + 0.3 V
10 mA
−40°C to +105°C
Storage Temperature Range
Maximum Junction Temperature
Lead Soldering, Reflow Temperature
−65°C to +150°C
150°C
260°C
Table 4. Thermal Resistance
Package Type
24-Lead TSSOP
JEDEC Board Layer 1
JEDEC Board Layer 2
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. 0 | Page 8 of 68
θJA
Unit
156
87
°C/W
°C/W
Data Sheet
AD7176-2
AIN4 1
24
AIN3
REF– 2
23
AIN2
REF+ 3
22
AIN1
REFOUT 4
21
AIN0
REGCAPA 5
20
GPIO1
19
GPIO0
18
REGCAPD
AVDD2 8
17
DGND
XTAL1 9
16
IOVDD
CLKIO/XTAL2 10
15
SYNC/ERROR
DOUT/RDY 11
14
CS
DIN 12
13
SCLK
AVSS 6
AVDD1 7
AD7176-2
TOP VIEW
(Not to Scale)
11037-004
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 4. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
1
2
3
Mnemonic
AIN4
REF−
REF+
4
5
6
7
8
9
10
REFOUT
REGCAPA
AVSS
AVDD1
AVDD2
XTAL1
CLKIO/XTAL2
11
DOUT/RDY
12
DIN
13
SCLK
14
CS
Description
Analog Input 4. Selectable through crosspoint multiplexer.
Reference Input Negative Terminal. REF− can span from AVSS to AVDD1 − 1 V.
Reference Input Positive Terminal. An external reference can be applied between REF+ and REF−. REF+ can
span from AVDD1 to AVSS + 1 V. The part functions with a reference from 1 V to AVDD1.
Buffered Output of Internal Reference. The output is 2.5 V with respect to AVSS.
Analog LDO Regulator Output. Decouple this pin to AVSS using a 1 µF capacitor.
Negative Analog Supply. This supply ranges from 0 V to −2.75 V and is nominally set to 0 V.
Analog Supply Voltage 1. This voltage is 5 V ± 10% with respect to AVSS.
Analog Supply Voltage 2. This voltage ranges from 2 V to AVDD1 with respect to AVSS.
Input 1 for Crystal.
Clock Input or Output (Based on the CLOCKSEL Bits in the ADCMODE Register)/Input 2 for Crystal. There
are four options available:
Internal oscillator—no output.
Internal oscillator—output to CLKIO/XTAL2. Operates at IOVDD logic level.
External clock—input to CLKIO/XTAL2. Input should be at IOVDD logic level.
External crystal—connected between XTAL1 and CLKIO/XTAL2.
Serial Data Output/Data Ready Output. DOUT/RDY serves a dual purpose. It functions as a serial data
output pin to access the output shift register of the ADC. The output shift register can contain data from
any of the on-chip data or control registers. The data-word/control word information is placed on the
DOUT/RDY pin on the SCLK falling edge and is valid on the SCLK rising edge. When CS is high, the
DOUT/RDY output is tristated. When CS is low, DOUT/RDY operates as a data ready pin, going low to
indicate the completion of a conversion. If the data is not read after the conversion, the pin goes high
before the next update occurs. The DOUT/RDY falling edge can be used as an interrupt to a processor,
indicating that valid data is available.
Serial Data Input to the Input Shift Register on the ADC. Data in this shift register is transferred to the
control registers in the ADC, with the register address (RA) bits of the communications register identifying
the appropriate register. Data is clocked in on the rising edge of SCLK.
Serial Clock Input. This serial clock input is for data transfers to and from the ADC. The SCLK has a Schmitttriggered input, making the interface suitable for opto-isolated applications.
Chip Select Input. This is an active low logic input used to select the ADC. CS can be used to select the ADC
in systems with more than one device on the serial bus. CS can be hardwired low, allowing the ADC to
operate in 3-wire mode with SCLK, DIN, and DOUT used to interface with the device. When CS is high, the
DOUT/RDY output is tristated.
Rev. 0 | Page 9 of 68
AD7176-2
Pin No.
15
Mnemonic
SYNC/ERROR
16
IOVDD
17
18
DGND
REGCAPD
19
20
21
22
23
24
GPIO0
GPIO1
AIN0
AIN1
AIN2
AIN3
Data Sheet
Description
Can be switched between a logic input and a logic output in the GPIOCON register. When synchronization
input is enabled, this pin allows for synchronization of the digital filters and analog modulators when
using multiple AD7176-2 devices. When synchronization input is disabled, this pin can be used in one of
three modes:
Active low error input mode: this mode sets the ADC_ERROR bit in the STATUS register.
Active low, open-drain error output mode: the STATUS register error bits are mapped to the ERROR pin.
The ERROR pins of multiple devices can be wired together to a common pull-up resistor so that an error
on any device can be observed.
General-purpose output mode: the status of the pin is controlled by the ERR_DAT bit in the GPIOCON register.
The pin is referenced between IOVDD and DGND, as opposed to the AVDD1 and AVSS levels used by the
GPIO pins. The pin has an active pull-up in this case.
Digital I/O Supply Voltage. IOVDD voltage ranges from 2 V to 5 V. IOVDD is independent of AVDD2. For
example, IOVDD can be operated at 3 V when AVDD2 equals 5 V, or vice versa. If AVSS is set to −2.5 V, the
voltage on IOVDD must not exceed 3.6 V.
Digital Ground.
Digital LDO Regulator Output. This pin is for decoupling purposes only. Decouple this pin to DGND using a
1 µF capacitor.
General-Purpose Input/Output. The pin is referenced between AVDD1 and AVSS levels.
General-Purpose Input/Output. The pin is referenced between AVDD1 and AVSS levels.
Analog Input 0. Selectable through the crosspoint multiplexer.
Analog Input 1. Selectable through the crosspoint multiplexer.
Analog Input 2. Selectable through the crosspoint multiplexer.
Analog Input 3. Selectable through the crosspoint multiplexer.
Rev. 0 | Page 10 of 68
Data Sheet
AD7176-2
TYPICAL PERFORMANCE CHARACTERISTICS
450
8388358
400
8388357
350
OCCURENCE
ADC CODE
300
8388356
8388355
250
200
150
100
8388354
0
100
200
300
400
0
11037-005
8388353
500
SAMPLE
8388356
8388354
8388356
ADC CODE
Figure 5. Noise (AVDD1 = 5 V, AVDD2 = 5 V, IOVDD = 3.3 V,
VREF = 5 V, Output Data Rate = 5 SPS)
11037-008
50
Figure 8. Noise Distribution Histogram (AVDD1 = 5 V, AVDD2 = 5 V,
IOVDD = 3.3 V, VREF = 5 V, Output Data Rate = 5 SPS)
8388375
800
8388370
700
8388365
600
OCCURENCE
ADC CODE
8388360
8388355
8388350
500
400
300
8388345
200
8388340
0
2000
4000
6000
8000
SAMPLE
0
8388336
11037-006
8388330
8388348
8388342
Figure 6. Noise (AVDD1 = 5 V, AVDD2 = 5 V, IOVDD = 3.3 V,
VREF = 5 V, Output Data Rate = 10 kSPS)
8388360
8388354
ADC CODE
8388372
8388366
11037-009
100
8388335
Figure 9. Noise Distribution Histogram (AVDD1 = 5 V, AVDD2 = 5 V,
VREF = 5 V, IOVDD = 3.3 V, Output Data Rate = 10 kSPS)
8388420
500
8388400
450
400
8388380
OCCURENCE
8388340
8388320
300
250
200
150
8388300
100
8388280
0
5000
10,000
15,000
SAMPLE
Figure 7. Noise (AVDD1 = 5 V, AVDD2 = 5 V, IOVDD = 3.3 V,
VREF = 5 V, Output Data Rate = 250 kSPS)
0
8388282
8388324
8388302
8388366
8388344
ADC CODE
8388408
8388386
Figure 10. Noise Distribution Histogram (AVDD1 = 5 V, AVDD2 = 5 V,
VREF = 5 V, IOVDD = 3.3 V, Output Data Rate = 250 kSPS)
Rev. 0 | Page 11 of 68
11037-010
50
8388260
11037-007
ADC CODE
350
8388360
AD7176-2
Data Sheet
0
12
–20
250kSPS
10
AMPLITUDE (dB)
6
4
–100
–140
1kSPS
2
3
4
5
VCM (V)
–160
11037-012
0
1
–80
–120
10kSPS
2
0
–60
0
5k
10k
15k
20k
25k
FREQUENCY (Hz)
11037-019
RMS NOISE (µV)
–40
8
Figure 14. 1 kHz Input Tone, −0.5 dBFS Input FFT (AVDD1 = 5 V, AVDD2 = 5 V,
IOVDD = 3.3 V, VREF = 2.5 V, Output Data Rate = 50 kSPS)
Figure 11. Noise vs. Common-Mode Input Voltage
(AVDD1 = 5 V, AVDD2 = 5 V, IOVDD = 3.3 V, VREF = 2.5 V)
11.0
0
–20
10.5
10.0
AMPLITUDE (dB)
RMS NOISE (µV)
–40
9.5
9.0
–60
–80
–100
–120
–140
8.5
0
5
10
–180
11037-016
8.0
15
MASTER CLOCK FREQUENCY (MHz)
Figure 12. Noise vs. Master Clock
(AVDD1 = 5 V, AVDD2 = 5 V, IOVDD = 3.3 V, VREF = 2.5 V)
0
100
150
200
250
300
350
400
450
500
FREQUENCY (Hz)
Figure 15. 50 Hz Input Tone, −6 dBFS Input FFT (AVDD1 = 5 V, AVDD2 = 5 V,
IOVDD = 3.3 V, VREF = 2.5 V, Output Data Rate = 1 kSPS)
0
0
–20
–20
–40
–40
–60
AMPLITUDE (dB)
–80
–100
–120
–60
–80
–100
–120
–140
–140
–160
0
50
100
150
200
250
300
FREQUENCY (Hz)
350
400
450
500
–160
11037-017
–180
Figure 13. 50 Hz Input Tone, −0.5 dBFS Input FFT (AVDD1 = 5 V, AVDD2 = 5 V,
IOVDD = 3.3 V, VREF = 2.5 V, Output Data Rate = 1 kSPS)
0
5k
10k
15k
FREQUENCY (Hz)
20k
25k
11037-022
AMPLITUDE (dB)
50
11037-020
–160
Figure 16. 1 kHz Input Tone, −6 dBFS Input FFT (AVDD1 = 5 V, AVDD2 = 5 V,
IOVDD = 3.3 V, VREF = 2.5 V, Output Data Rate = 50 kSPS)
Rev. 0 | Page 12 of 68
AD7176-2
0
–20
–20
–40
–40
–60
–60
–80
–100
–80
–100
–120
–120
–140
–140
–160
0
20k
40k
60k
80k
100k
120k
FREQUENCY (Hz)
–160
10
30
20
50
40
60
70
FREQUENCY (Hz)
Figure 17. 1 kHz Input Tone, −0.5 dBFS Input FFT (AVDD1 = 5 V, AVDD2 = 5 V,
IOVDD = 3.3 V, VREF = 2.5 V, Output Data Rate = 250 kSPS)
11037-031
CMRR (dB)
0
11037-023
AMPLITUDE (dB)
Data Sheet
Figure 20. Common-Mode Rejection Ratio (10 Hz to 70 Hz)
(AVDD1 = 5 V, AVDD2 = 5 V, IOVDD = 3.3 V, 20 SPS Enhanced Filter)
1.0
0
–20
0.5
FROM POWER-DOWN
–60
ERROR (%)
AMPLITUDE (dB)
–40
–80
–100
–120
0
FROM STANDBY – REFERENCE OFF
–0.5
0
20k
40k
60k
80k
100k
120k
FREQUENCY (Hz)
–1.0
0.00001
11037-026
–160
0.0001
0.001
0.01
0.1
TIME (Seconds)
Figure 18. 1 kHz Input Tone, −6 dBFS Input FFT (AVDD1 = 5 V, AVDD2 = 5 V,
IOVDD = 3.3 V, VREF = 2.5 V, Output Data Rate = 250 kSPS)
11037-032
–140
Figure 21. Internal Reference Settling Time
(AVDD1 = 5 V, AVDD2 = 5 V, IOVDD = 3.3 V)
0.10
0
–20
0.05
CMRR (dB)
0
–60
–80
–0.05
–0.10
0
10
20
30
40
TIME (Seconds)
Figure 19. Internal Reference Settling Time (Extended)
(AVDD1 = 5 V, AVDD2 = 5 V, IOVDD = 3.3 V)
50
–120
1
10
100
1k
FREQUENCY (Hz)
10k
100k
1M
11037-033
–100
11037-030
ERROR (%)
–40
Figure 22. Common-Mode Rejection Ratio vs. Frequency
(AVDD1 = 5 V, AVDD2 = 5 V, IOVDD = 3.3 V, Output Data Rate = 250 kSPS)
Rev. 0 | Page 13 of 68
Data Sheet
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
1
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
10M
11037-034
POWER SUPPLY REJECTION (dB)
AD7176-2
Figure 23. Power Supply Rejection Ratio vs. Frequency
(AVDD1 = 5 V, AVDD2 = 5 V, IOVDD = 3.3 V)
Rev. 0 | Page 14 of 68
Data Sheet
AD7176-2
NOISE PERFORMANCE AND RESOLUTION
Table 6 shows the rms noise and the noise free (peak-to-peak)
resolution of the AD7176-2 for various output data rates and
filters. The numbers given are for the bipolar input range with
an external 5 V reference.
on a single channel. It is important to note that the peak-topeak resolution is calculated based on the peak-to-peak noise.
The peak-to-peak resolution represents the resolution for which
there is no code flicker.
These numbers are typical and are generated with a differential
input voltage of 0 V when the ADC is continuously converting
Table 6. RMS Noise and Peak-to-Peak Resolution vs. Output Data Rate 1
Output Data Rate (SPS)
250,000
62,500
10,000
1000
60
50
16.7
5
1
Sinc5 + Sinc1 Filter (Default)
Noise (µV rms)
Peak-to-Peak Resolution (Bits)
9.7
17.2
5.4
18.2
2.5
19
0.82
20.8
0.46
21.4
0.42
21.7
0.42
21.7
0.32
22.2
Selected rates only, 1000 samples.
Rev. 0 | Page 15 of 68
Noise (µV rms)
220
5.1
1.8
0.62
0.32
0.31
0.29
0.29
Sinc3 Filter
Peak-to-Peak Resolution (Bits)
12.8
18.3
19.8
21
22
22
22.4
22.4
AD7176-2
Data Sheet
GETTING STARTED
The AD7176-2 includes a precision 2.5 V low drift (2 ppm/°C)
band gap internal reference. This reference can be selected to
be used for the ADC conversions, reducing the external component count. Alternatively, the reference can be output to the
REFOUT pin to be used as a low noise biasing voltage for the
external circuitry. An example of this is using the REFOUT
signal to set the input common mode for an external driving
amplifier.
The AD7176-2 offers the user a fast settling, high resolution,
multiplexed ADC with high levels of configurability.
•
•
Two fully differential or four single-ended analog inputs.
Crosspoint multiplexer selects any analog input combination as the input signals to be converted, routing them to
the modulator positive or negative input.
Fully differential input, single-ended relative to any analog
input and pseudo differential configuration available.
Per channel configurability—up to four different setups
can be defined. A separate setup can be mapped to each of
the channels. Each setup allows the user to configure:
• Gain and offset correction
• Filter type
• Output data rate
• Reference source selection (internal/external)
The AD7176-2 includes two separate linear regulator blocks for
both the analog and digital circuitry. The analog LDO regulates
the AVDD2 supply to 2 V supplying the ADC core. The user
can tie the AVDD1 and AVDD2 supplies together for easiest
connection. If there is already a clean analog supply rail in the
system in the range of 2 V to 5 V, the user can also choose to
connect this to the AVDD2 input, allowing for lower power
dissipation.
GENERAL PURPOSE IO
0 AND 1
OUTPUT HIGH = AVDD
OUTPUT LOW = AVSS
FOR SINGLE SUPPLY
CASE OUTPUT HIGH = 5V
OUTPUT LOW = GND
GPIO 0
GPIO 1
16MHz
19
20
GPIO 0
GPIO 1
CX2
CX1
SEE ANALOG INPUT SECTION FOR FURTHER DETAILS
OPTIONAL EXTERNAL
CRYSTAL CIRCUITRY
CAPACITORS
XTAL1 9
21
AIN0
IN0
CLKI0/XTAL2 10
DOUT/RDY 11
22
IN1
DOUT/RDY
AIN1
DIN
DIN 12
IN2
23
SCLK
SCLK 13
AIN2
CS
CS 14
IN3
24
AIN3
1
AIN4
SYNC/ERROR 15
SYNC/ERROR
AD7176-2
AIN4
IN4
CLKIN
OPTIONAL
EXTERNAL
CLOCK
INPUT
IOVDD
IOVDD 16
0.1µF
DGND 17
VIN
1
2
4.7µF
VIN
3
REGCAPD 18
NC 7
0.1µF
1µF
0.1µF
ADR445BRZ
4
GND
5
VOUT 6
8
AVDD1
AVDD1 7
0.1µF
4.7µF
3
REF+
2
REF–
4
REFOUT
0.1µF
AVDD2
0.1µF
AVDD2 8
2.5V REFERENCE
OUTPUT
0.1µF
REGCAPA 5
0.1µF
AVSS
6
Figure 24. Typical Connection Diagram
Rev. 0 | Page 16 of 68
0.1µF
1µF
11037-051
•
•
Data Sheet
AD7176-2
The AD7176-2 can be used across a wide variety of applications,
providing high resolution and accuracy. A sample of these
scenarios is as follows:
•
•
•
Fast scanning of analog input channels using the internal
multiplexer.
Fast scanning of analog input channels using an external
multiplexer.
High resolution at lower speeds in either channel scanning
or ADC per channel applications.
Single ADC per channel: the fast low latency output allows
further application specific filtering in an external microcontroller, DSP, or FPGA.
POWER SUPPLIES
The AD7176-2 has three independent power supply pins:
AVDD1, AVDD2, and IOVDD.
AVDD1 powers the front-end circuitry, including the crosspoint
multiplexer. AVDD1 is referenced to AVSS and AVDD1 − AVSS
= 5 V only. This can be a single 5 V supply or a ±2.5 V split
supply. The split supply operation allows for true bipolar inputs.
When using split supplies, the absolute maximum ratings (see
the Absolute Maximum Ratings section) must be kept in mind.
The communications register controls access to the full register
map of the ADC. This register is an 8-bit write only register. On
power-up or after a reset, the digital interface defaults to a state
where it is expected a write to the communications register;
therefore, all communication begins by writing to the
communications register.
The data written to the communications register determines
which register is being accessed and if the next operation is a
read or write. The register address bits (RA[5:0]) determine the
specific register to which the read or write operation applies.
When the read or write operation to the selected register is
complete, the interface returns to its defaults state, where it
expects a write operation to the communications register.
In situations where interface synchronization is lost, a write
operation of at least 64 serial clock cycles with DIN high returns
the ADC to its default state by resetting the entire part, including
the register contents. Alternatively, if CS is being used with the
digital interface, returning CS high sets the digital interface to
its default state and aborts any current operation.
Figure 26 and Figure 27 illustrate writing to and reading from a
register by first writing the 8-bit command to the communications
register followed by the data for that register.
DIGITAL COMMUNICATION
DIN
CMD
DATA
SCLK
Figure 26. Writing to a Register
(8-Bit Command with Register Address Followed by Data of 8, 16, or 24 Bits;
Data Length Is Dependent on the Register Selected)
The AD7176-2 has a 3- or 4-wire SPI interface that is compatible
with QSPI™, MICROWIRE®, and DSPs. The interface operates
in SPI Mode 3 and can be operated with CS tied low. In SPI
Mode 3, the SCLK idles high, the falling edge of SCLK is the
drive edge, and the rising edge of SCLK is the sample edge. This
means that data is clocked out on the falling/drive edge and data
is clocked in on the rising/sample edge.
8-BIT COMMAND
8 BITS, 16 BITS,
24 BITS, OR
32 BITS OF DATA
CS
DIN
DOUT/RDY
CMD
DATA
SAMPLE EDGE
SCLK
11037-052
DRIVE EDGE
8 BITS, 16 BITS,
OR 24 BITS OF DATA
CS
AVDD2 powers the internal 1.8 V analog LDO regulator. This
regulator powers the ADC core. AVDD2 is referenced to AVSS,
and AVDD2 – AVSS can range from 5 V to 2 V.
IOVDD powers the internal 1.8 V digital LDO regulator. This
regulator powers the digital logic of the ADC. IOVDD sets the
voltage levels for the SPI interface of the ADC. IOVDD is referenced to DGND, and IOVDD − DGND can vary from 5 V to 2 V.
8-BIT COMMAND
Figure 25. SPI Mode 3 SCLK Edges
11037-054
•
Accessing the ADC Register Map
11037-053
The linear regulator for the digital IOVDD supply performs a
similar function, regulating the input voltage applied at the
IOVDD pin to 2 V for the internal digital filtering. The serial
interface signals always operate from the IOVDD supply seen at
the pin. This means that if 3.3 V is applied to the IOVDD pin,
the interface logic inputs and outputs operate at this level.
Figure 27. Reading from a Register
(8-Bit Command with Register Address Followed by Data of 8, 16, or 24 Bits;
Data Length on DOUT Is Dependent on the Register Selected)
Rev. 0 | Page 17 of 68
AD7176-2
Data Sheet
Reading the ID register is the recommended method for verifying
correct communication with the part. The ID registers is a read
only register and contains the value 0x0C9X for the AD7176-2.
The communication register and ID register details are described
in Table 7 and Table 8.
Table 7. Communications Register
Reg
0x00
Name
COMMS
Bits
[7:0]
Bit 7
WEN
Bit 6
R/W
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RA
Reset
0x00
RW
W
Table 8. ID Register
Reg
0x07
Name
ID
Bits
[15:8]
[7:0]
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
ID[15:8]
ID[7:0]
Rev. 0 | Page 18 of 68
Bit 2
Bit 1
Bit 0
Reset
0x0C9X
RW
R
Data Sheet
AD7176-2
CONFIGURATION OVERVIEW
Figure 28 provides an overview of the configuration flow,
divided into the following three blocks:
•
•
ADC and interface mode configuration (labeled A in
Figure 28)
ADC setups (labeled B in Figure 28)
Channel map configuration (labeled C in Figure 28)
A
WRITE TO ADC MODE REGISTER AND INTERFACE MODE REGISTER;
SET UP HIGH LEVEL ADC PERIPHERALS AND INTERFACE
B
SET UP CONFIGURATION;
FOUR POSSIBLE ADC SETUPS USING DEDICATED
FILTER, OFFSET, AND GAIN REGISTERS
C
SELECT THE POSITIVE AND NEGATIVE INPUT FOR EACH
ADC CHANNEL AND MAP EACH CHANNEL TO A SETUP
Figure 28. Configuration Flow
Rev. 0 | Page 19 of 68
11037-055
•
AD7176-2
Data Sheet
ADC and Interface Mode Configuration
enable bits. The reference select bits are contained in the setup
configuration registers (see the ADC Setups section for more
information).
The ADC mode register and the interface mode register (see
Block A in Figure 28) configure the core peripherals to be used
by the AD7176-2 and the mode for the digital interface.
Interface Mode Register
ADC Mode Register
The interface mode register is used to configure the digital interface
operation. This register allows the user to control data-word length,
CRC enable, data + status read and continuous read mode.
The ADC mode register is used primarily to set the conversion
mode of the ADC to either continuous or single conversion.
The user can also select the standby and power-down modes as
well as any of the calibration modes. In addition, this register
contains the clock source select bits and the internal reference
Both register details are shown in Table 9 and Table 10. For
more information, see the Digital Interface section.
Table 9. ADC Mode Register
Reg
0x01
Name
ADCMODE
Bits
[15:8]
[7:0]
Bit 7
REF_EN
RESERVED
Bit 6
RESERVED
Bit 5
SING_CYC
MODE
Bit 4
Bit 3
RESERVED
Bit 2
CLOCKSEL
Bit 1
Bit 0
DELAY
RESERVED
Reset
0x8000
RW
RW
Reset
0x0000
RW
RW
Table 10. Interface Mode Register
Reg
0x02
Name
IFMODE
Bits
[15:8]
[7:0]
Bit 7
CONTREAD
Bit 6
RESERVED
DATA_STAT
Bit 5
REG_CHECK
Bit 4
ALT_SYNC
RESERVED
Bit 3
Bit 2
Bit 1
IOSTRENGTH
RESERVED
CRC_EN
RESERVED
Rev. 0 | Page 20 of 68
Bit 0
DOUT_RESET
WL16
Data Sheet
AD7176-2
reference, an external reference connected between REF+ and
REF− pins, or AVDD1 – AVSS.
ADC Setups
The AD7176-2 has four independent setups (see Block B in
Figure 28). Each setup consists of the following four registers:
Filter Configuration Register
•
•
•
•
The filter configuration register is used to select which digital
filter is used at the output of the ADC modulator. The order of
the filter and the output data rate is selected by setting the bits
in this register. For more information, see the Digital Filters section.
Setup configuration register
Filter configuration register
Offset register
Gain register
Offset Register
For example, Setup 0 consists of Setup Configuration 0, Filter
Configuration 0, Offset 0, and Gain 0. The setup is selectable
from the channel map registers detailed in the Channel Map
Configuration section. This allows each channel to be assigned
to a separate setup; therefore, each channel is fully configurable
because each setup has its own filter, offset, and gain register.
Table 11 through Table 14 show the four registers that are
associated with Setup 0.
The offset register holds the offset calibration coefficient for the
ADC. The power-on reset value of the offset register is 0x800000.
The offset register is a 24-bit read/write register. The power-on
reset value is automatically overwritten if an internal or system
zero-scale calibration is initiated by the user or if the offset register
is written to by the user.
Gain Register
Setup Configuration Register
The gain register is a 24-bit register that holds the gain
calibration coefficient for the ADC. The gain registers are
read/write registers. These registers are configured at power-on
with factory calibrated coefficients. Therefore, every device has
different default coefficients. The default value is automatically
overwritten if a system full-scale calibration is initiated by the
user or if the gain register is written to by the user. For more
information on calibration, see the Operating Modes section.
The setup configuration registers allow the user to select the output
coding of the ADC by selecting between bipolar and unipolar. In
bipolar mode, the ADC accepts negative differential input voltages,
and the output coding is offset binary. In unipolar mode, the ADC
accepts only positive differential voltages, and the coding is straight
binary. In either case, the input voltage must be within the supply
voltages. The user can also select the reference source using this
register. There are three options available—an internal 2.5 V
Table 11. Setup Configuration 0 Register
Reg Name
Bits Bit 7
Bit 6
Bit 5
0x20 SETUPCON0 [15:8]
RESERVED
[7:0]
RESERVED
Bit 4
Bit 3
BI_UNIPOLAR0
REF_SEL0
Bit 2
Bit 1
RESERVED
RESERVED
Bit 0
Reset RW
0x1020 RW
Bit 1
Bit 0
ENHFILT0
Reset RW
0x0000 RW
Table 12. Filter Configuration 0 Register
Reg Name
0x28 FILTCON0
Bits Bit 7
Bit 6
[15:8] SINC3_MAP0
[7:0] RESERVED
Bit 5
Bit 4
RESERVED
ORDER0
Bit 3
Bit 2
ENHFILTEN0
ODR0
Table 13. Offset 0 Register
Reg Name
0x30 OFFSET0
Bits Bit 7
[23:16]
[15:8]
[7:0]
Bit 6
Bit 5
Bit 4
Bit 3
OFFSET0[23:16]
OFFSET0[15:8]
OFFSET0[7:0]
Bit 2
Bit 1
Bit 0
Reset
RW
0x800000 RW
Bit 6
Bit 5
Bit 4
Bit 2
Bit 1
Bit 0
Reset
RW
0x5XXXX0 RW
Table 14. Gain 0 Register
Reg Name
0x38 GAIN0
Bits Bit 7
[23:16]
[15:8]
[7:0]
Bit 3
GAIN0[23:16]
GAIN0[15:8]
GAIN0[7:0]
Rev. 0 | Page 21 of 68
AD7176-2
Data Sheet
Channel Map Configuration
The AD7176-2 has four independent channels (see Block C in
Figure 28). The user can select which of the four setups is used
for each channel. This allows for per channel configuration.
Channel Map Register
The channel map register is used to select which of the five
analog input pins are used as either the positive analog input or
the negative analog input for that channel. This register also
contains a channel enable/disable bit and the setup selection
bits, which are used to pick which of the four available setups
are used for this channel.
When the AD7176-2 is operating in continuous conversion
mode with more than one channel enabled, the channel
sequencer cycles through the enabled channels in sequential
order, from Channel Map 0 to Channel Map 3. If a channel is
disabled, it is skipped by the sequencer. Details of the channel
map register for Channel 0 are shown in Table 15.
Table 15. Channel Map Register
Reg Name
0x10 CHMAP0
Bits Bit 7
[15:8] CH_EN0
[7:0]
Bit 6
Bit 5
Bit 4
RESERVED
SETUP_SEL0
AINPOS0[2:0]
Bit 3
Rev. 0 | Page 22 of 68
Bit 2
Bit 1
Bit 0
RESERVED
AINPOS0[4:3]
AINNEG0
Reset RW
0x8001 RW
Data Sheet
AD7176-2
CIRCUIT DESCRIPTION
Fully Differential Inputs
ANALOG INPUT
The AD7176-2 has five analog input pins: AIN0, AIN1, AIN2,
AIN3, and AIN4. Each of these pins connects to the internal
crosspoint multiplexer. The crosspoint multiplexer enables any of
these inputs to be configured as an input pair, either pseudo
differential or fully differential. The AD7176-2 can have up to four
active channels. When more than one channel is enabled, the
channels are automatically sequenced in order. The output of
the multiplexer is connected directly to the switched-capacitor
input of the ADC. The simplified analog input circuit is shown in
Figure 29.
AVDD1
AVSS
AVDD1
Ø1
+IN
CS1
AVSS
AVDD1
Ø2
Ø2
AIN2
CS2
Pseudo Differential Inputs
DRIVER AMPLIFIERS
AVSS
AVDD1
If two fully differential input paths are connected to the AD7176-2,
using AIN0/AIN1 as one differential input pair and AIN2/AIN3
as the second differential input pair is recommended. This is
due to the relative locations of these pins to each other. All
analog inputs should be decoupled to AVSS.
The user can also choose to measure four different single-ended
analog inputs. In this case, each of the analog inputs is converted
as being the difference between the single-ended input to be
measured and a set analog input common pin. Because there is
a crosspoint multiplexer, the user can set any of the analog inputs
as the common pin. An example of such a scenario is to connect
the AIN4 pin to AVSS or to the REFOUT voltage (that is, AVSS
+ 2.5 V) and select this input when configuring the crosspoint
multiplexer. When using the AD7176-2 with pseudo differential
inputs, the INL specification is degraded.
AIN0
AIN1
Because the AIN0 to AIN4 analog inputs are connected to a
crosspoint multiplexer, any combination of signals can be used
to create an analog input pair. This allows the user to select two
fully differential inputs or four pseudo differential inputs.
–IN
To drive the analog input switch capacitor, an external amplifier
is required. Details of three recommended amplifiers for the
AD7176-2 are shown in the Driver Amplifiers section. Each of
the amplifiers can run from a single 5 V voltage rail.
Ø1
AIN3
AVSS
AIN4
AVSS
11037-056
AVDD1
Figure 29. Simplified Analog Input Circuit
The CS1 and CS2 capacitors have a magnitude in the order of a
number of picofarads each. This capacitance is the combination
of both the sampling capacitance and the parasitic capacitance.
The average input current to the AD7176-2 changes linearly with
the differential input voltage at a rate of 48 µA/V. Each of the
analog inputs must be buffered externally not only to provide
the varying input current with differential input amplitude but
also to settle the switched-capacitor input to allow for accurate
sampling.
Recommended amplifiers for this purpose are discussed in the
Driver Amplifiers section.
Rev. 0 | Page 23 of 68
AD7176-2
Data Sheet
AD8475
with a fixed common mode of 2.5 V. The output of the AD8475
amplifier is connected to an RC network. The RC network, as
shown in Figure 30, includes RIN = 10 Ω; C1, C2 = 270 pF; and
C3 = 680 pF. The RC circuit acts to provide the dynamic charge
required by the AD7176-2 switched sampling capacitors while
isolating the amplifier output from any kickback from the
dynamic switched capacitor input. The configuration of the
AD8475 in Figure 30 shows a fully differential signal source
with a gain of 0.4×.
The AD8475 features an attenuating input stage of 0.8× or 0.4×
(using integrated precision resistors), allowing inputs in the ±10 V
range with a single 5 V supply and a 3 mA current consumption
to be used. The AD8475 performs single-ended to differential
conversions, allows easy setting of the common-mode output,
and drives the AD7176-2 with a differential input.
Figure 30 shows a typical connection to the AD7176-2, where
two AD8475 amplifiers attenuate two differential inputs and
then drive the AD7176-2 inputs. The common-mode output of
the AD8475 is set by connecting the internal, buffered 2.5 V
reference of the AD7176-2 to the VOCM pin of the AD8475.
The output of the AD8475 to the AD7176-2 is fully differential
The AD8475 can also be set up to convert single-ended signals
to fully differential inputs. Ground the −IN 0.4× input and
apply the single-ended input to the +IN 0.4× input.
+5V
0.1µF
0.1µF
+5V
0.1µF
±12.5V
LOW IMPEDANCE
VOLTAGE
SOURCE
–IN 0.4x
AD8475
AVSS AVDD1 AVDD2*
RIN
21
AIN0
22
AIN1
4
REFOUT
C1
AD7176-2
C3
IN1
C2
+IN 0.4x
VOCM
8
7
6
IN0
RIN
SCLK 13
2.5V
DIN 12
0.1µF
IN2
±12.5V
LOW IMPEDANCE
VOLTAGE
SOURCE
VOCM
+IN 0.4x
DOUT/RDY 11
RIN
23
AIN2
24
AIN3
MICROCONTROLLER
HOST
CS 14
C1
C3
IN3
C2
–IN 0.4x
RIN
AD8475
REF+ REF–
3
0.1µF
5.5V TO 18V
0.1µF
ADR445
0.1µF
2
5V VREF
0.1µF
4.7µF
*AVDD2 CAN BE SUPPLIED BY VOLTAGES RANGING FROM 2V TO 5.5V.
Figure 30. AD8475 Driving Two Differential Inputs of the AD7176-2
Rev. 0 | Page 24 of 68
11037-057
+5V
Data Sheet
AD7176-2
AD8656
The AD8656 is a low noise, dual precision CMOS amplifier. The
AD8656 allows the user to connect a signal of interest directly
to a high impedance, low noise, low offset amplifier input that
can drive the AD7176-2 switched capacitor input. The AD8656
can operate from a single 5 V supply. When using an external
5 V reference such as the ADR445 in conjunction with the
AD7176-2, the AD8656 output can swing to within −1 dBFS
(which equates to a differential input of ±4.45 V) of the ADC
input range.
A simple configuration for use of the AD8656 is to connect the
amplifiers in a configuration for a gain of more than 1. Each of
the AD7176-2 analog inputs has its own amplifier. This allows
the user to connect either fully differential inputs or single-ended
inputs to the AD7176-2. The example shown in Figure 31 is
configured with two fully differential inputs connecting to the
AIN0/AIN1 pair and the AIN2/AIN3 pair.
The high impedance input to the amplifier allows the user to
band-limit the input with a suitable passive filter RC combination.
The gain of the configuration used is set by the RG and RF resistors.
To improve accuracy, use precision resistors for RG and RF.
Setting RG = RF = 1 kΩ results in a gain of 2 for the circuit. The
matching of the RG and RF resistors directly affects the gain
error of the circuit. The drift and matching of these resistors
affect the gain error drift of the circuit. A 10 Ω source resistor (RS)
is placed between the feedback resistor (RF) and the amplifier
output. This resistor acts to isolate the amplifier from any
kickback from the ADC input and does not directly affect the
gain error of the circuit.
The output of each of the amplifier pairs is connected directly
to a network of decoupling and differential capacitors prior to
being connected to the AD7176-2 analog inputs. The capacitor
network shown in Figure 31 includes C1, C2 = 270 pF and C3 =
680 pF. The capacitor network acts to provide the dynamic charge
required by the AD7176-2 switched sampling capacitors.
The circuit example in Figure 31 requires inclusion of two
precision gain resistors per amplifier (RG and RF). Choose the
value, precision, and matching of such resistors according to the
requirements of the application.
+5V
+5V
0.1µF
0.1µF
0.1µF
RS
C1
AD7176-2
C3
C2
RS
IN1
22
RG
8
AVSS AVDD1 AVDD2 1
21 AIN0
AD8656
0 TO +2.5V
INPUT RANGE
7
6
RF
IN0
AIN1
RF
SCLK 13
DIN 12
DOUT/RDY 11
RG
0 TO +2.5V
INPUT RANGE
RF
IN2
CS 14
RS
AIN2
24
AIN3
C3
C2
RS
IN3
23
C1
AD8656
0 TO +2.5V
INPUT RANGE
REF+ REF–
3
RF
RG
5.5V TO 18V
ADR4452
0.1µF
2
0.1µF
0.1µF
+5V
MICROCONTROLLER
HOST
5V VREF
0.1µF
4.7µF
1AVDD2 CAN BE SUPPLIED BY VOLTAGES RANGING FROM 2V TO 5.5V.
2USING ADR444 (4.096V REFERENCE) IN PLACE OF THE ADR445 AS SHOWN
IN THIS
EXAMPLE WOULD ALLOW THE ENTIRE CCT TO BE OPERATED FROM A SINGLE 5V SUPPLY RAIL.
Figure 31. Dual AD8656 Amplifiers Driving the AD7176-2
Rev. 0 | Page 25 of 68
11037-158
RG
0 TO +2.5V
INPUT RANGE
AD7176-2
Data Sheet
ADA4940
are recommended for use. The external reference should be
applied to the AD7176-2 reference pins as shown in Figure 32.
The output of any external reference should be decoupled to
AVSS. As shown in Figure 32, the ADR445 output is decoupled
with a 0.1 µF capacitor at its output for stability purposes. The
output is then connected to a 4.7 µF capacitor, which acts as a
reservoir for any dynamic charge required by the ADC, and
followed by a 0.1 µF decoupling capacitor at the REF+ input.
This capacitor is placed as close as possible to the REF+ and
REF− pins. The REF− pin is connected directly to the AVSS
potential. On power-up of the AD7176-2, the internal reference
is enabled by default and is output on the REFOUT pin. When
an external reference is used instead of the internal reference to
supply the AD7176-2, attention must be paid to the output of
the REFOUT pin. If the internal reference is not being used
elsewhere in the application, ensure that the REFOUT pin is not
hardwired to AVSS because this will draw a large current on
power-up. On power-up if the internal reference is not being
used, write to the ADC mode register, disabling the internal
reference. This is controlled by the REF_EN bit (Bit 15) in the
ADC mode register and is shown in Table 17.
The ADA4940-1/ADA4940-2 is an alternate option to drive
the AD7176-2. It is a low noise, low distortion fully differential
amplifier with very low power consumption (1.25 mA of quiescent
current). The AD7176-2 REFOUT pin can be used to connect
to the ADA4940-1/ADA4940-2 to set the common-mode output
to 2.5 V. This option requires the use of external resistors to set
the gain of the amplifier.
AD7176-2 REFERENCE
The AD7176-2 offers the user the option of either supplying an
external reference to the REF+ and REF− pins of the device or
allowing the use of the internal 2.5 V, low noise, low drift reference.
Select the reference source to be used by the analog input by setting
the REF_SELx bits (Bits[5:4]) in the setup configuration registers
appropriately. The structure of the Setup Configuration 0 register
is shown in Table 16. The AD7176-2 defaults on power-up to
use the internal 2.5 V reference.
External Reference
The AD7176-2 has a fully differential reference input applied
through the REF+ and REF− pins. Standard low noise, low drift
voltage references, such as the ADR445, ADR444, and ADR441,
AD7176-2
5.5V TO 18V
ADR4452
0.1µF
0.1µF
5V VREF
1
4.7µF
1
1
3
REF+
2
REF–
0.1µF
1
1
1ALL DECOUPLING IS
2ANY OF THE ADR44x
11037-159
TO AVSS.
FAMILY REFERENCES MAY BE USED.
ADR444 OR ADR441 BOTH ENABLE REUSE OF THE 5V ANALOG SUPPLY
NEEDED FOR AVDD1 TO POWER THE REFERENCE VIN.
Figure 32. External Reference ADR445 Connected to AD7176-2 Reference Pins
Table 16. Setup Configuration 0 Register
Reg Name
Bits Bit 7
Bit 6
Bit 5
0x20 SETUPCON0 [15:8]
RESERVED
[7:0]
RESERVED
Bit 4
Bit 3
BI_UNIPOLAR0
REF_SEL0
Bit 2
Bit 1
RESERVED
RESERVED
Bit 0
Reset RW
0x1020 RW
Bit 1
Bit 0
DELAY
RESERVED
Reset RW
0x8000 RW
Table 17. ADC Mode Register
Reg Name
0x01 ADCMODE
Bits Bit 7
[15:8] REF_EN
[7:0] RESERVED
Bit 6
RESERVED
Bit 5
SING_CYC
MODE
Bit 4
Bit 3
RESERVED
Rev. 0 | Page 26 of 68
Bit 2
CLOCKSEL
Data Sheet
AD7176-2
The AD7176-2 includes its own low noise, low drift voltage
reference. The internal reference has a 2.5 V output. The internal
reference is output on the REFOUT pin after the REF_EN bit in
the ADC mode register is set and is decoupled to AVSS with a
0.1 µF capacitor. The AD7176-2 internal reference is enabled by
default on power-up and is selected as the reference source for
the ADC.
The REFOUT signal is buffered prior to being output to the pin.
The signal can be used externally in the circuit as a common-mode
source for external amplifier configurations. This is shown in
Figure 30 in the Driver Amplifiers section, where the REFOUT pin
supplies the VOCM input of the AD8475 amplifier.
AD7176-2 CLOCK SOURCE
The AD7176-2 requires a master clock of 16 MHz. The AD7176-2
can source its sampling clock from one of three scenarios:
•
•
•
Internal oscillator
External crystal
External clock source
All output data rates listed in the data sheet relate to a master
clock rate of 16 MHz. Using a lower clock frequency from, for
instance, an external source will scale any listed data rate
proportionally. To achieve the specified data rates, particularly
rates for rejection of 50 Hz and 60 Hz, a 16 MHz clock should
be used. The source of the master clock is selected by setting the
CLOCKSEL bits (Bits[3:2]) in the ADC mode register as shown
in Table 17. The default operation on power-up and reset of the
AD7176-2 is to operate with the internal oscillator.
introduced by the output driver. The extent to which the
performance is affected depends on the IOVDD voltage supply.
Higher IOVDD voltages create a wider logic output swing from
the driver and affect performance to a greater extent. This is
further exaggerated if the IOSTRENGTH bit is set at higher
IOVDD levels (see Table 25 for more information).
External Crystal
If higher precision, lower jitter clock sources are required, the
AD7176-2 has the ability to use an external crystal to generate
the master clock. The crystal is connected to the XTAL1 and
XTAL2 pins. A recommended crystal for use is the FA-20H—a
16 MHz, 10 ppm, 9 pF crystal from Epson-Toyocom—which is
available in a surface-mounted package. As shown in Figure 33,
allow for two capacitors to be inserted from the traces
connecting the crystal to the XTAL1 and XTAL2 pins. These
capacitors allow for circuit tuning. Connect these capacitors to
the DGND pin. The value for these capacitors depends on the
length and capacitance of the trace connections between the
crystal and the XTAL1 and XTAL2 pins. Therefore, the values
of these capacitors differ depending on the PCB layout and the
crystal employed. As a result, empirical testing of the circuit is
required.
AD7176-2
Cx1
*
XTAL1 9
CLKIO/XTAL2 10
Cx2
*
*DECOUPLE TO DGND.
11037-160
Internal Reference
Figure 33. External Crystal Connections
Internal Oscillator
The internal oscillator runs at 16 MHz and can be used as the
ADC master clock. It is the default clock source for the AD7176-2
and is specified with an accuracy of ±2.5%.
There is an option to allow the internal clock oscillator to be
output on the AD7176-2 CLKIO/XTAL2 pin. The clock output
is driven to the IOVDD logic level. Use of this option can affect
the dc performance of the AD7176-2 due to the disturbance
External Clock
The AD7176-2 can also use an externally supplied clock. In
systems where this is desirable, the external clock is routed to
the CLKIO pin. In this configuration, the CLKIO pin accepts
the externally sourced clock and routes it to the modulator. The
logic level of this clock input is defined by the voltage applied to
the IOVDD pin.
Rev. 0 | Page 27 of 68
AD7176-2
Data Sheet
DIGITAL FILTERS
to control the final ADC output data rate. Figure 35 shows the
frequency domain response of the Sinc5 + Sinc1 filter at a 50 SPS
output data rate. The Sinc5 + Sinc1 filter has a slow roll-off over
frequency and narrow notches.
The AD7176-2 has three flexible filter options to allow for
optimization of noise, settling time, and rejection:
•
•
•
Sinc5 + Sinc1 filter
Sinc3 filter
Enhanced 50 Hz and 60 Hz rejection filters
0
–20
Figure 34. Digital Filter Block Diagram
The filter and output data rate is configured by setting the
appropriate bits in the filter configuration register for the
selected setup. See the Register Details section for more
information.
–40
–60
–80
–100
–120
0
SINC5 + SINC1 FILTER
50
100
150
FREQUENCY (Hz)
The Sinc5 + Sinc1 filter is targeted at fast switching multiplexed
applications and achieves single cycle settling at output data rates of
10 kSPS and lower. The Sinc5 block output is fixed at the maximum
rate of 250 kSPS, and the Sinc1 block output data rate can be varied
11037-059
SINC3
FILTER GAIN (dB)
SINC1
11037-058
SINC5
50Hz AND 60Hz
POST FILTER
Figure 35. Sinc5 + Sinc1 Filter Response at 50 SPS ODR
The output data rates with the accompanying settling time and
rms noise for the Sinc5 + Sinc1 filter are shown in Table 18.
Table 18. AD7176-2 Output Data Rate (ODR), Noise, Settling Time (tSETTLE), and Rejection Using the Sinc5 + Sinc1 Filter
Output Data
Rate (SPS) 1
250,000
125,000
62,500
50,000
31,250
25,000
15,625
10,000
5000
2500
1000
500
400
200
100
60
50
20
16.667
10
5
1
2
Settling
Time1
20 µs
24 µs
32 µs
36 µs
48 µs
56 µs
80 µs
100 µs
200 µs
400 µs
1.0 ms
2.0 ms
2.516 ms
5.0 ms
10.0 ms
16.68 ms
20.016 ms
50.0 ms
60.02 ms
100.02 ms
200.02 ms
Switching Rate
(Hz)1
50,000
41,667
31,250
27,778
20,833
17,857
12,500
10,000
5000
2500
1000
500.0
400
200.0
100.0
460
50
20.00
16.66
10.00
5.00
Notch Frequency
(Hz)
250,000
125,000
62,500
50,000
31,250
25,000
15,625
11,905
5435
2604
1016
504
400.00
200.64
100.16
60.00
50.00
20.01
16.67
10.00
5.00
Rejection ± 1 Hz
(dB) 2
34 dB (60 Hz)
34 dB (50 Hz)
34 dB (50 Hz and 60 Hz)
Noise
(µV rms)
9.7
7.4
5.4
5
4
3.6
2.7
2.5
1.8
1.3
0.82
0.63
0.62
0.47
0.46
0.43
0.42
0.42
0.42
0.38
0.32
Peak-to-Peak Resolution
with 5 V Reference (Bits)
17.25
17.6
18.1
18.2
18.5
18.7
19.1
19.2
19.7
20.2
20.8
21.2
21.2
21.6
21.7
21.7
21.8
21.8
21.8
22
22.1
The settling time has been rounded to the nearest microsecond. This is reflected in the output data rate and switching rate. Switching rate = 1 ÷ tSETTLE.
Master clock = 160 MHz.
Rev. 0 | Page 28 of 68
Data Sheet
AD7176-2
SINC3 FILTER
For example, an output data rate of 50 SPS can be achieved with
SINC3_MAP enabled by setting the FILTCONx[14:0] bits to a
value of 5000.
The Sinc3 filter achieves the best single-channel noise performance
at lower rates and is, therefore, most suitable for single-channel
applications. The Sinc3 filter always has a settling time equal to
tSETTLE = 3/Output Data Rate
Figure 36 shows the frequency domain filter response for the
Sinc3 filter. The Sinc3 filter has good roll-off over frequency
and has wide notches for good notch frequency rejection.
0
–10
–20
The AD7176-2 can be configured by setting the SING_CYC bit
in the ADC mode register so that only fully settled data is output,
thus effectively putting the ADC into a single cycle settling mode.
This mode achieves single cycle settling by reducing the output
data rate to be equal to the settling time of the ADC for the selected
output data rate. This bit has no effect with the Sinc5 + Sinc1 at
output data rates of 10 kSPS and lower.
Figure 37 shows a step on the analog input with this mode
disabled and the Sinc3 filter selected. It takes at least three
cycles after the step change for the output to reach the final
settled value.
–30
FILTER GAIN (dB)
SINGLE CYCLE SETTLING
–40
–50
–60
–70
ANALOG
INPUT
–80
FULLY
SETTLED
–90
ADC
OUTPUT
–100
150
FREQUENCY (Hz)
Figure 36. Sinc3 Filter Response
The output data rates with the accompanying settling time and
rms noise for the Sinc3 filter are shown in Table 19.
It is possible to finely tune the output data rate for the Sinc3 filter by
setting the SINC3_MAP bit in the filter configuration register. If
this bit is set, the mapping of the filter register changes to directly
program the decimation rate of the Sinc3 filter. All other options
are eliminated. The data rate when on a single channel can be
calculated using the following equation:
Output Data Rate =
11037-061
100
50
1/ODR
Figure 37. Step Input Without Single Cycle Settling
Figure 38 shows the same step on the analog input but with
single cycle settling enabled. It takes at least a single cycle for
the output to be fully settled. The output data rate is now
reduced to equal the settling time of the filter at the selected
output data rate.
f MOD
ANALOG
INPUT
FULLY
SETTLED
ADC
OUTPUT
tSETTLE
Figure 38. Step Input with Single Cycle Settling
32 × FILTCONx[14:0]
where:
fMOD is the modulator rate and is 8 MHz.
FILTCONx[14:0] are the contents on the filter configuration
register excluding the MSB.
Rev. 0 | Page 29 of 68
11037-062
0
11037-060
–110
–120
AD7176-2
Data Sheet
Table 19. AD7176-2 Output Data Rate (ODR), Noise, Settling Time (tSETTLE), and Rejection Using the Sinc3 Filter
Output Data
Rate (SPS) 1
250,000
125,000
62,500
50,000
31,250
25,000
15,625
10,000
5000
2500
1000
500
400
200
100
59.94
49.96
20
16.667
10
5
1
2
Settling
Time (ms)1
0.012
0.024
0.048
0.060
0.096
0.120
0.192
0.300
0.600
1.200
3.000
6.000
7.500
15.000
30.000
50.004
60.000
150.000
180.000
300.000
600.000
Switching Rate1
(Hz)
83,333
41,667
20,833
16,667
10,417
8333
5208
3333
1667
833
333.3
166.7
133.3
66.7
33.3
20.00
16.67
6.67
5.56
3.33
1.67
Notch Frequency
(Hz)
250,000
125,000
62,500
50,000
31,250
25,000
15,625
10,000
5000
2500
1000
500
400
200
100
59.94
49.96
20
16.667
10
5
Rejection ± 1 Hz
(dB) 2
100 (60 Hz)
100 (50 Hz)
100 (50 Hz and 60 Hz)
Noise
(µV rms)
220
27
5.1
4.3
3.2
2.7
2.3
1.8
1.3
0.91
0.62
0.49
0.45
0.37
0.33
0.32
0.31
0.31
0.29
0.29
0.29
Peak-to-Peak Resolution
with 5 V Reference (Bits)
12.8
15.9
18.3
18.5
18.8
19
19.4
19.8
20.2
20.5
21
21.4
21.7
22
22
22
22
22
22.4
22.4
22.4
The settling time has been rounded to the nearest microsecond. This is reflected in the output data rate and switching rate. Switching rate = 1 ÷ tSETTLE.
Master clock = 160 MHz.
Rev. 0 | Page 30 of 68
Data Sheet
AD7176-2
ENHANCED 50 HZ AND 60 HZ REJECTION FILTERS
The enhanced filters are designed to provide rejection of 50 Hz
and 60 Hz simultaneously and to allow the user to trade off
settling time and rejection. These filters can operate up to
27.27 SPS or can reject up to 90 dB of 50 Hz ± 1 Hz and 60 Hz
± 1 Hz interference. These filters are realized by post filtering
the output of the Sinc5 + Sinc1 filter. For this reason, the Sinc5
+ Sinc1 filter must be selected when using the enhanced filters.
Table 20 shows the output data rates with the accompanying
settling time, rejection, and rms noise. Figure 39 to Figure 46
show the frequency domain plots of the responses from the
enhanced filters.
Table 20. AD7176-2 Enhanced Filters Output Data Rate, Noise, Settling Time (tSETTLE), and Rejection Using the Enhanced Filters
Output Data Rate
(SPS)
27.27
25
20
16.667
1
Settling Time
(ms)
36.67
40.0
50.0
60.0
Simultaneous Rejection of
50 Hz ± 1 Hz and 60 Hz ± 1 Hz
(dB) 1
47
62
85
90
Noise
(µV rms)
0.15
0.14
0.125
0.125
Master clock = 160 MHz.
Rev. 0 | Page 31 of 68
Peak-to-Peak Resolution
(Bits)
23.26
23.36
23.53
23.53
Comments
See Figure 39 and Figure 40
See Figure 41 and Figure 42
See Figure 43 and Figure 44
See Figure 45 and Figure 46
Data Sheet
0
–10
–10
–20
–20
–30
–30
–40
–50
–60
–60
–70
–80
–80
–90
–90
–100
–100
40
300
400
500
600
0
–10
–20
–20
–30
–30
FILTER GAIN (dB)
0
–40
–50
–60
–80
–90
–90
70
FREQUENCY (Hz)
–100
11037-064
65
0
–10
–10
–20
–20
–30
–30
FILTER GAIN (dB)
0
–50
–60
–90
–90
500
FREQUENCY (Hz)
600
11037-065
–80
400
500
600
–60
–70
300
400
–50
–80
200
300
–40
–70
100
200
Figure 43. DC to 600 Hz, 20 SPS ODR, 50 ms Settling Time
0
–40
100
FREQUENCY (Hz)
Figure 40. Zoom in 40 Hz to 70 Hz, 27.27 SPS ODR, 36.67 ms Settling Time
–100
40
70
–60
–70
60
65
–50
–80
55
60
–40
–70
50
55
Figure 42. Zoom in 40 Hz to 70 Hz, 25 SPS ODR, 40 ms Settling Time
–10
45
50
FREQUENCY (Hz)
Figure 39. DC to 600 Hz, 27.27 SPS ODR, 36.67 ms Settling Time
–100
40
45
11037-067
200
Figure 41. DC to 600 Hz, 25 SPS ODR, 40 ms Settling Time
–100
40
45
50
55
60
65
70
FREQUENCY (Hz)
Figure 44. Zoom in 40 Hz to 70 Hz, 20 SPS ODR, 50 ms Settling Time
Rev. 0 | Page 32 of 68
11037-068
100
FREQUENCY (Hz)
FILTER GAIN (dB)
–50
–70
0
FILTER GAIN (dB)
–40
11037-066
FILTER GAIN (dB)
0
11037-063
FILTER GAIN (dB)
AD7176-2
AD7176-2
0
–10
–10
–20
–20
–30
–30
–40
–50
–60
–40
–50
–60
–70
–70
–80
–80
–90
–90
–100
–100
40
0
100
200
300
400
500
600
FREQUENCY (Hz)
Figure 45. DC to 600 Hz,16.667 SPS ODR, 60 ms Settling Time
45
50
55
FREQUENCY (Hz)
60
65
70
11037-070
FILTER GAIN (dB)
0
11037-069
FILTER GAIN (dB)
Data Sheet
Figure 46. Zoom in 40 Hz to 70 Hz, 16.667 SPS ODR, 60 ms Settling Time
Rev. 0 | Page 33 of 68
AD7176-2
Data Sheet
OPERATING MODES
CONTINUOUS CONVERSION MODE
Continuous conversion is the default power-up mode. The
AD7176-2 converts continuously, and the RDY bit in the status
register goes low each time a conversion is complete. If CS is low,
the DOUT/RDY line also goes low when a conversion is complete.
To read a conversion, the user writes to the communications
register, indicating that the next operation is a read of the data
register. When the data-word has been read from the data register,
DOUT/RDY goes high. The user can read this register additional
times, if required. However, the user must ensure that the data
register is not being accessed at the completion of the next conversion; otherwise the new conversion word will be lost.
When several channels are enabled, the ADC automatically
sequences through the enabled channels, performing one
conversion on each channel. When all channels have been
converted, the sequence starts again with the first channel. The
channels are converted in order from lowest enabled channel to
highest enabled channel. The data register is updated as soon as
each conversion is available. The DOUT/RDY pin pulses low
each time a conversion is available. The user can then read the
conversion while the ADC converts the next enabled channel.
If the DATA_STAT bit in the interface mode register is set to 1,
the contents of the status register, along with the conversion data,
are output each time the data register is read. The status register
indicates the channel to which the conversion corresponds.
CS
0x44
0x44
DIN
DATA
DATA
11037-071
DOUT/RDY
SCLK
Figure 47. Continuous Conversion Mode
Rev. 0 | Page 34 of 68
Data Sheet
AD7176-2
CONTINUOUS READ MODE
To enable continuous read mode, set the CONTREAD bit in the
interface mode register. When this bit is set, the only serial interface
operations possible are reads from the data register. To exit continuous read mode, issue a dummy read of the ADC data register
command (0x44) while RDY is low. Alternatively, apply a software
reset, that is, 64 SCLKs with CS = 0 and DIN = 1. This resets the
ADC and all register contents. These are the only commands
that the interface recognizes after it is placed in continuous read
mode. DIN should be held low in continuous read mode until
an instruction is to be written to the device.
In continuous read mode, it is not required to write to the
communications register before reading ADC data; just apply
the required number of SCLKs after DOUT/RDYgoes low to
indicate the end of a conversion. When the conversion is read,
DOUT/RDY returns high until the next conversion is available.
In this mode, the data can be read only once. The user must also
ensure that the data-word is read before the next conversion is
complete. If the user has not read the conversion before the
completion of the next conversion or if insufficient serial clocks
are applied to the AD7176-2 to read the word, the serial output
register is reset when the next conversion is complete, and the
new conversion is placed in the output serial register. The ADC
must be configured for continuous conversion mode to use
continuous read mode.
If multiple ADC channels are enabled, each channel is output
in turn, with the status bits being appended to the data if
DATA_STAT is set in the interface mode register. The status
register indicates the channel to which the conversion corresponds.
CS
0x02
0x0800
DIN
DATA
DATA
DATA
11037-072
DOUT/RDY
SCLK
Figure 48. Continuous Read Mode
Rev. 0 | Page 35 of 68
AD7176-2
Data Sheet
SINGLE CONVERSION MODE
In single conversion mode, the AD7176-2 performs a single
conversion and is placed in standby mode after the conversion
is complete. DOUT/RDY goes low to indicate the completion of a
conversion. When the data-word has been read from the data
register, DOUT/RDY goes high. The data register can be read
several times, if required, even when DOUT/RDY has gone high.
If several channels are enabled, the ADC automatically
sequences through the enabled channels and performs a
conversion on each channel. When a conversion is started,
DOUT/RDY goes high and remains high until a valid conversion
is available and CS is low. As soon as the conversion is available,
DOUT/RDY goes low. The ADC then selects the next channel and
begins a conversion. The user can read the present conversion
while the next conversion is being performed. As soon as the next
conversion is complete, the data register is updated; therefore,
the user has a limited period in which to read the conversion.
When the ADC has performed a single conversion on each of
the selected channels, it returns to standby mode.
If the DATA_STAT bit in the interface mode register is set to 1,
the contents of the status register, along with the conversion, are
output each time the data register is read. The two LSBs of the
status register indicate the channel to which the conversion
corresponds.
CS
0x01
0x8010
0x44
DIN
DATA
11037-073
DOUT/RDY
SCLK
Figure 49. Single Conversion Mode
Rev. 0 | Page 36 of 68
Data Sheet
AD7176-2
STANDBY AND POWER-DOWN MODES
In standby mode, most blocks are powered down. The LDOs
remain active so that registers maintain their contents. The
internal reference remains active if enabled, and the crystal
oscillator remains active if selected. To power down the
reference in standby mode, set the REF_EN bit in the ADC
mode regsiter to 0. To power down the clock in standby mode,
set the CLOCKSEL bits in the ADC mode register to 00
(internal oscillator).
In power-down mode, all blocks are powered down, including
the LDOs. All registers lose their contents, and the GPIO outputs
are placed in tristate. To prevent accidental entry to power-down
mode, the ADC must first be placed into standby mode. Exiting
power-down mode requires 64 SCLKs with CS = 0 and DIN = 1,
that is, a serial interface reset. A delay of 500 µs is recommended
before issuing a subsequent serial interface command to allow
the LDO to power up.
CALIBRATION MODES
The AD7176-2 provides three calibration modes that can be
used to eliminate the offset and gain errors on a per setup basis:
•
•
•
Internal zero-scale calibration mode
System zero-scale calibration mode
System full-scale calibration mode
Only one channel can be active during calibration. After each
conversion, the ADC conversion result is scaled using the ADC
calibration registers before being written to the data register.
The default value of the offset register is 0x800000, and the
nominal value of the gain register is 0x555555. The calibration
range of the ADC gain is from 0.4 × VREF to 1.05 × VREF. The
following equations show the calculations that are used. In
unipolar mode, the ideal relationship—that is, not taking into
account the ADC gain error and offset error—is as follows:
 0.75 × VIN

Gain
Data = 
× 2 23 − (Offset − 0x800000) ×
×2
 VREF
 0x400000
In bipolar mode, the ideal relationship—that is, not taking into
account the ADC gain error and offset error—is as follows:
 0.75 × VIN

Gain
Data = 
× 223 − (Offset − 0x800000) ×
+ 0x800000
 VREF
 0x400000
To start a calibration, write the relevant value to the MODE bits
in the ADC mode register. The DOUT/RDY pin and the RDY bit
in the status register go high when the calibration initiates. When
the calibration is complete, the contents of the corresponding
offset or gain register are updated, the RDY bit in the status
register is reset, the DOUT/RDY pin returns low (if CS is low),
and the AD7176-2 reverts to standby mode.
During an internal offset calibration, the selected positive
analog input pin is disconnected, and both modulator inputs
are connected internally to the selected negative analog input
pin. For this reason, it is necessary to ensure that the voltage on
the selected negative analog input pin does not exceed the
allowed limits and is free from excessive noise and interference.
System calibrations, however, expect the system zero-scale
(offset) and system full-scale (gain) voltages to be applied to the
ADC pins before initiating the calibration modes. As a result,
errors external to the ADC are removed.
From an operational point of view, treat a calibration like
another ADC conversion. An offset calibration, if required,
must always be performed before a full-scale calibration. Set the
system software to monitor the RDY bit in the status register or
the DOUT/RDY pin to determine the end of a calibration via a
polling sequence or an interrupt-driven routine. All calibrations
require a time equal to the settling time of the selected filter and
output data rate to be completed.
An internal offset calibration, system zero-scale calibration, and
system full-scale calibration can be performed at any output data
rate. Using lower output data rates results in better calibration
accuracy and is accurate for all output data rates. A new calibration
is required for a given channel if the reference source for that
channel is changed.
The offset error is typically ±40 µV and an offset calibration
reduces the offset error to the order of the noise. The gain error
is factory calibrated at ambient temperature. Following this
calibration, the gain error is typically ±0.001%.
The AD7176-2 provides the user with access to the on-chip
calibration registers, allowing the microprocessor to read the
calibration coefficients of the device and to write its own
calibration coefficients. A read or write of the offset and gain
registers can be performed at any time except during an internal
or self-calibration.
Rev. 0 | Page 37 of 68
AD7176-2
Data Sheet
DIGITAL INTERFACE
Figure 2 and Figure 3 show timing diagrams for interfacing to
the AD7176-2 using CS to decode the part. Figure 2 shows the
timing for a read operation from the AD7176-2, and Figure 3
shows the timing for a write operation to the AD7176-2. It is
possible to read from the data register several times even though
the DOUT/RDY line returns high after the first read operation.
However, care must be taken to ensure that the read operations are
completed before the next output update occurs. In continuous
read mode, the data register can be read only once.
The serial interface can operate in 3-wire mode by tying CS low.
In this case, the SCLK, DIN, and DOUT/RDY lines are used to
communicate with the AD7176-2. The end of the conversion
can also be monitored using the RDY bit in the status register.
The serial interface can be reset by writing 64 SCLKs with CS =
0 and DIN = 1. A reset returns the interface to the state in which it
expects a write to the communications register. This operation
resets the contents of all registers to their power-on values.
Following a reset, allow a period of 500 µs before addressing the
serial interface.
CHECKSUM PROTECTION
The AD7176-2 has a checksum mode, which can be used to
improve interface robustness. Using the checksum ensures that
only valid data is written to a register and allows data read from
a register to be validated. If an error occurs during a register
write, the CRC_ERROR bit is set in the status register. However,
to ensure that the register write was successful, the register
should be read back and checksum verified.
x8 + x2 + x + 1
During read operations, the user can select between this
polynomial and a similar XOR function. The XOR function
requires less time to process on the host microcontroller than
the polynomial-based checksum. The CRC_EN bits in the
interface mode register enable and disable the checksum and
allow the user to select between the polynomial check and the
simple XOR check.
The checksum is appended to the end of each read and write
transaction. The checksum calculation for the write transaction
is calculated using the 8-bit command word and the 8- to 24-bit
data. For a read transaction, the checksum is calculated using
the command word and the 8- to 32-bit data output. Figure 50
and Figure 51 show SPI write and read transactions, respectively.
8-BIT COMMAND
UP TO 24-BIT INPUT
8-BIT CRC
CS
DATA
CRC
CS
DIN
11037-074
The DOUT/RDY pin also functions as a data-ready signal, with
the line going low if CS is low when a new data-word is available
in the data register. The pin is reset high when a read operation
from the data register is complete. The DOUT/RDY pin also
goes high before updating the data register to indicate when not
to read from the device to ensure that a data read is not attempted
while the register is being updated. CS is used to select a device.
It can be used to decode the AD7176-2 in systems where several
components are connected to the serial bus.
For CRC checksum calculations during a write operation, the
following polynomial is always used:
SCLK
Figure 50. SPI Write Transaction with CRC
8-BIT COMMAND
UP TO 32-BIT INPUT
8-BIT CRC
CS
DIN
DOUT/
RDY
CMD
DATA
CRC
SCLK
11037-075
The programmable functions of the AD7176-2 are via the SPI
serial interface. The serial interface of the AD7176-2 consists of
four signals: CS, DIN, SCLK, and DOUT/RDY. The DIN line is
used to transfer data into the on-chip registers, and DOUT/RDY is
used to access data from the on-chip registers. SCLK is the serial
clock input for the device, and all data transfers (either on DIN or
on DOUT/RDY) occur with respect to the SCLK signal.
Figure 51. SPI Read Transaction with CRC
If checksum protection is enabled when continuous read mode
is active, there is an implied read data command of 0x44 before
every data transmission that needs to be accounted for when
calculating the checksum value. This ensures a nonzero checksum
value even if the ADC data equals 0x000000.
Rev. 0 | Page 38 of 68
Data Sheet
AD7176-2
CRC CALCULATION
Polynomial
The checksum, which is 8-bits wide, is generated using the polynomial
x8 + x2 + x + 1
To generate the checksum, the data is left shifted by eight bits to create a number ending in eight Logic 0s. The polynomial is aligned so that
its MSB is adjacent to the leftmost Logic 1 of the data. An XOR (exclusive OR) function is applied to the data to produce a new, shorter
number. The polynomial is again aligned so that its MSB is adjacent to the leftmost Logic 1 of the new result, and the procedure is repeated. This
process is repeated until the original data is reduced to a value less than the polynomial. This is the 8-bit checksum.
Example of a Polynomial CRC Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data)
An example of generating the 8-bit checksum using the polynomial based checksum is as follows:
Initial value
011001010100001100100001
x +x +x+1
8
2
01100101010000110010000100000000
left shifted eight bits
=
polynomial
100000111
100100100000110010000100000000
100000111
XOR result
polynomial
100011000110010000100000000
100000111
XOR result
polynomial
11111110010000100000000
100000111
XOR result
polynomial value
1111101110000100000000
100000111
XOR result
polynomial value
111100000000100000000
100000111
XOR result
polynomial value
11100111000100000000
100000111
XOR result
polynomial value
1100100100100000000
100000111
XOR result
polynomial value
100101010100000000
100000111
XOR result
polynomial value
101101100000000
100000111
1101011000000
100000111
101010110000
100000111
1010001000
100000111
10000110
XOR result
polynomial value
XOR result
polynomial value
XOR result
polynomial value
XOR result
polynomial value
checksum = 0x86.
Rev. 0 | Page 39 of 68
AD7176-2
Data Sheet
XOR Calculation
The checksum, which is 8-bits wide, is generated by splitting the data into bytes and then performing an XOR of the bytes.
Example of an XOR Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data)
Using the previous example,
Divide into three bytes: 0x65, 0x43, and 0x21
01100101
0x65
01000011
0x43
00100110
XOR result
00100001
0x21
00000111
CRC
Rev. 0 | Page 40 of 68
Data Sheet
AD7176-2
GENERAL-PURPOSE I/O
The AD7176-2 has two general-purpose digital input/output pins:
GPIO0 and GPIO1. These are enabled using the IP_EN0/IP_EN1
or OP_EN0/OP_EN1 bits in the GPIOCON register. When the
GPIO0 or GPIO1 pin is enabled as an input, the logic level at
the pin is contained in the DATA0 or DATA1 bit, respectively.
When the GPIO0 or GPIO1 pin is enabled as an output, the
GP_DATA0 or GP_DATA1 bits, respectively, determine the
logic level output at the pin. The logic levels for these pins are
referenced to AVDD1 and AVSS; therefore, outputs have an
amplitude of 5 V.
If an external multiplexer is used to increase the channel count,
the multiplexer logic pins can be controlled via the AD7176-2
GPIO pins. With the MUX_IO bit, the GPIOs timing is controlled
by the ADC; therefore, the channel change is synchronized with
the ADC, eliminating any need for external synchronization.
The SYNC/ERROR pin can also be used as a general-purpose
output. When ERR_EN bits in the GPIOCON register are set to
11, the SYNC/ERROR pin operates as a general-purpose output.
In this configuration, the ERR_DAT bit in the GPIOCON register
determines the logic level output at the pin. The logic level for the
pin is referenced to IOVDD and DGND, and the SYNC/ERROR
pin has an active pull-up.
16-BIT/24-BIT CONVERSIONS
By default, the AD7176-2 generates 24-bit conversions. However,
the width of the conversions can be reduced to 16 bits. Setting
Bit WL16 in the interface mode register to 1 rounds all data
conversions to 16 bits. Clearing this bit sets the width of the
data conversions to 24 bits.
SERIAL INTERFACE RESET (DOUT_RESET)
The serial interface is reset when each read operation is
complete. The instant at which the serial interface is reset is
programmable. By default, the serial interface is reset after a
period of time following the last SCLK rising edge, the SCLK
edge on which the LSB is read by the processor. By setting Bit
DOUT_RESET in the interface mode register to 1, the instant at
which the interface is reset is controlled by the CS rising edge.
In this case, the DOUT/RDY pin continues to output the LSB of
the register being read until CS is taken high. Only on the CS
rising edge is the interface reset. This configuration is useful if
the CS signal is used to frame all read operations. If CS is not
used to frame all read operations, DOUT_RESET should be set
to 0 so that the interface is reset following the last SCLK edge in
the read operation.
SYNCHRONIZATION (SYNC/ERROR)
Normal Synchronization
When the SYNC_EN bit in the GPIOCON register is set to 0,
the SYNC/ERROR pin functions as a synchronization pin. The
SYNC input allows the user to reset the modulator and the
digital filter without affecting any of the setup conditions on
the part. This allows the user to start gathering samples of the
analog input from a known point in time, that is, the rising
edge of SYNC. This pin must be low for at least one master
clock cycle to ensure that synchronization occurs.
If multiple AD7176-2 devices are operated from a common
master clock, they can be synchronized so that their data registers
are updated simultaneously. This is normally done after each
AD7176-2 has performed its own calibration or has calibration
coefficients loaded into its calibration registers. A falling edge
on the SYNC pin resets the digital filter and the analog modulator
and places the AD7176-2 into a consistent known state. While
the SYNC pin is low, the AD7176-2 is maintained in this state.
On the SYNC rising edge, the modulator and filter are taken
out of this reset state, and on the next master clock edge, the
part starts to gather input samples again.
The part is taken out of reset on the master clock falling edge
following the SYNC low-to-high transition. Therefore, when
multiple devices are being synchronized, the SYNC pin should
be taken high on the master clock rising edge to ensure that all
devices begin sampling on the master clock falling edge. If the
SYNC pin is not taken high in sufficient time, it is possible to
have a difference of one master clock cycle between the devices;
that is, the instant at which conversions are available differs
from part to part by a maximum of one master clock cycle.
The SYNC pin can also be used as a start conversion command.
In this mode, the rising edge of SYNC starts a conversion, and
the falling edge of RDY indicates when the conversion is complete.
The settling time of the filter has to be allowed for each data
register update.
Alternate Synchronization
Setting Bit ALT_SYNC in the interface mode register to 1 enables
an alternate synchronization scheme. The SYNC_EN bit in the
GPIOCON register must be set to 1 to enable this alternate scheme.
In this mode, the SYNC pin operates as a start conversion command when several channels of the AD7176-2 are enabled. When
SYNC is taken low, the ADC completes the conversion on the
current channel, selects the next channel in the sequence, and
then waits until SYNC is taken high to commence the conversion.
The RDY pin goes low when the conversion is complete on
the current channel, and the data register is updated with the
corresponding conversion. Therefore, the SYNC command
does not interfere with the sampling on the currently selected
channel but allows the user to control the instant at which the
conversion begins on the next channel in the sequence.
The mode can be used only when several channels are enabled.
It is not recommended to use this mode when a single channel
is enabled.
Rev. 0 | Page 41 of 68
AD7176-2
Data Sheet
ERROR FLAGS
The status register contains three error bits—ADC_ERROR,
CRC_ERROR, and REG_ERROR—that flag errors with the
ADC conversion, errors with the CRC check, and errors due to
changes in the registers, respectively. In addition, the ERROR
pin can indicate that an error has occurred.
ADC_ERROR
The ADC_ERROR bit in the status register flags any errors that
occur during the conversion process. The flag is set when an overvoltage or undervoltage occurs on the analog inputs. The ADC
also outputs all 0s or all 1s when an undervoltage or overvoltage
occurs. This flag is reset only when the overvoltage/undervoltage is
removed. It is not reset by a read of the data register.
CRC_ERROR
If the CRC value that accompanies a write operation does not
correspond with the information sent, the CRC_ERROR flag is
set. The flag is reset as soon as the status register is explicitly read.
REG_ERROR
This flag is used in conjunction with the REG_CHECK bit in
the interface mode register. When the REG_CHECK bit is set,
the AD7176-2 monitors the values in the on-chip registers. If a
bit changes, the REG_ERROR bit is set. Therefore, for writes to
the on-chip registers, REG_CHECK should be set to 0. When
the registers have been updated, the REF_CHK bit can be set to 1.
The AD7176-2 calculates a checksum of the on-chip registers. If
one of the register values has changed, the REG_ERROR bit is
set. If an error is flagged, the REG_CHECK bit must be set to 0
to clear the REG_ERROR bit in the status register. The register
check function does not monitor the data register, status
register, or interface mode register.
ERROR Pin
When the SYNC_EN bit in the GPIOCON register is set to 1
and Bit ALT_SYNC in the interface mode register is set to 0, the
SYNC/ERROR pin functions as an error input/output pin or a
general-purpose output pin. The ERR_EN bits in the GPIOCON
register determine the function of the pin.
With ERR_EN bits are set to 10, the pin functions as an opendrain error output pin. The three error bits in the status register
(ADC_ERROR, CRC_ERROR, and REG_ERROR) are OR’ed,
inverted, and mapped to the ERROR pin. Therefore, the
ERROR pin indicates that an error has occurred. The status
register must be read to identify the error source.
When ERR_EN bits are set to 01, the ERROR pin functions as
an error input pin. The error pin of another component can be
connected to the AD7176-2 ERROR pin so that the AD7176-2
indicates when an error occurs on either itself or the external
component. The value on the ERROR pin is inverted and OR’ed
with the errors from the ADC conversion, and the result is
indicated via the ADC_ERROR bit in the status register. The value
of the ERROR pin is reflected in the ERR_DAT bit in the status
register.
The ERROR pin is disabled when the ERR_EN bits are set to 00.
When the ERR_EN1 bits are set to 11, the ERROR pin operates
as a general-purpose output.
DATA_STAT
The contents of the status register can be appended to each conversion on the AD7176-2. This is a useful function if several
channels are enabled. Each time a conversion is output, the
contents of the status register are appended. The two LSBs of
the status register indicate to which channel the conversion
corresponds. In addition, the user can determine if any errors
are being flagged by the error bits.
IOSTRENGTH
The serial interface can operate with a power supply as low as
2 V. However, at this low voltage, the DOUT/RDY pin may not
have sufficient drive strength if there is moderate parasitic
capacitance on the board or the SCLK frequency is high. The
IOSTRENGTH bit in the interface mode register increases the
drive strength of the DOUT/RDY pin.
Rev. 0 | Page 42 of 68
Data Sheet
AD7176-2
GROUNDING AND LAYOUT
The analog inputs and reference inputs are differential and,
therefore, most of the voltages in the analog modulator are
common-mode voltages. The high common-mode rejection of
the part removes common-mode noise on these inputs. The
analog and digital supplies to the AD7176-2 are independent
and separately pinned out to minimize coupling between the
analog and digital sections of the device. The digital filter
provides rejection of broadband noise on the power supplies,
except at integer multiples of the master clock frequency.
The digital filter also removes noise from the analog and
reference inputs, provided that these noise sources do not
saturate the analog modulator. As a result, the AD7176-2 is
more immune to noise interference than a conventional high
resolution converter. However, because the resolution of the
AD7176-2 is high and the noise levels from the converter are so
low, care must be taken with regard to grounding and layout.
The printed circuit board (PCB) that houses the ADC must be
designed so that the analog and digital sections are separated
and confined to certain areas of the board. A minimum etch
technique is generally best for ground planes because it results
in the best shielding.
In any layout, the user must keep in mind the flow of currents
in the system, ensuring that the paths for all return currents are as
close as possible to the paths the currents took to reach their
destinations.
Avoid running digital lines under the device because this
couples noise onto the die and allows the analog ground plane
to run under the AD7176-2 to prevent noise coupling. The
power supply lines to the AD7176-2 must use as wide a trace as
possible to provide low impedance paths and reduce glitches on
the power supply line. Shield fast switching signals like clocks
with digital ground to prevent radiating noise to other sections
of the board and never run clock signals near the analog inputs.
Avoid crossover of digital and analog signals. Run traces on
opposite sides of the board at right angles to each other. This
reduces the effects of feedthrough on the board. A microstrip
technique is by far the best but is not always possible with a
double-sided board. In this technique, the component side of
the board is dedicated to ground planes, whereas signals are
placed on the solder side.
Good decoupling is important when using high resolution ADCs.
The AD7176-2 has three power supply pins—AVDD1, AVDD2,
and IOVDD. The AVDD1 and AVDD2 pins are referenced to
AVSS, and the IOVDD pin is referenced to DGND. AVDD1 and
AVDD2 should be decoupled with a 10 µF tantalum capacitor
in parallel with a 0.1 µF capacitor to AVSS on each pin. The
0.1 µF capacitor should be placed as close as possible to the
device on each supply, ideally right up against the device.
IOVDD should be decoupled with a 10 µF tantalum capacitor
in parallel with a 0.1 µF capacitor to DGND. All analog inputs
should be decoupled to AVSS. If an external reference is used,
the REF+ and REF− pins should be decoupled to AVSS.
The AD7176-2 also has two on-board LDO regulators—one that
regulates the AVDD2 supply and one that regulates the IOVDD
supply. For the REGCAPA pin, it is recommended that 1 µF and
0.1 µF capacitors to AVSS be used. Similarly, for the REGCAPD
pin, it is recommended that 1 µF and 0.1 µF capacitors to
DGND be used.
If using the AD7176-2 for split supply operation, a separate
plane must be used for AVSS.
Rev. 0 | Page 43 of 68
AD7176-2
Data Sheet
REGISTER SUMMARY
Table 21. AD7176-2 Register Summary
Reg
Bits
Bit 7
Bit 6
0x00 COMMS
Name
[7:0]
WEN
R/W
0x00 STATUS
[7:0]
RDY
ADC_ERROR
CRC_ERROR
0x01 ADCMODE
[15:8]
[7:0]
REF_EN
RESERVED
RESERVED
SING_CYC
MODE
[15:8]
[7:0]
CONTREAD
0x02 IFMODE
0x03 REGCHECK
Bit 5
Bit 4
RESERVED
DATA_STAT
REG_ERROR
Bit 1
Bit 0
RESERVED
CHANNEL
CLOCKSEL
DELAY
RESERVED
RESERVED
REG_CHECK
[23:16]
[15:8]
ALT_SYNC
RESERVED
IOSTRENGTH
CRC_EN
RESERVED
RESERVED
DOUT_RESET
WL16
REGISTER_CHECK[23:16]
REGISTER_CHECK[15:8]
Reset
RW
0x00
W
0x80
R
0x8000
RW
0x0000
RW
0x000000 R
REGISTER_CHECK[7:0]
[23:16]
[15:8]
DATA[23:16]
DATA[15:8]
[7:0]
0x06 GPIOCON
Bit 2
RA
[7:0]
0x04 DATA
Bit 3
0x000000 R
DATA[7:0]
[15:8]
[7:0]
RESERVED
RESERVED
MUX_IO
IP_EN0
IP_EN1
SYNC_EN
OP_EN1
ERR_EN
GP_DATA1
OP_EN0
ERR_DAT
GP_DATA0
RW
0x0C9X
R
0x07 ID
[15:8]
[7:0]
0x10 CHMAP0
[15:8]
[7:0]
CH_EN0
RESERVED
AINPOS0[2:0]
SETUP_SEL0
RESERVED
AINNEG0
AINPOS0[4:3]
0x8001
RW
0x11 CHMAP1
[15:8]
[7:0]
CH_EN1
RESERVED
AINPOS1[2:0]
SETUP_SEL1
RESERVED
AINNEG1
AINPOS1[4:3]
0x0001
RW
0x12 CHMAP2
[15:8]
[7:0]
CH_EN2
RESERVED
AINPOS2[2:0]
SETUP_SEL2
RESERVED
AINNEG2
AINPOS2[4:3]
0x0001
RW
0x13 CHMAP3
[15:8]
[7:0]
CH_EN3
RESERVED
AINPOS3[2:0]
SETUP_SEL3
RESERVED
AINNEG3
AINPOS3[4:3]
0x0001
RW
0x20 SETUPCON0
[15:8]
[7:0]
RESERVED
RESERVED
BI_UNIPOLAR0
REF_SEL0
RESERVED
RESERVED
0x1020
RW
0x21 SETUPCON1
[15:8]
[7:0]
RESERVED
RESERVED
BI_UNIPOLAR1
REF_SEL1
RESERVED
RESERVED
0x1020
RW
0x22 SETUPCON2
[15:8]
[7:0]
RESERVED
RESERVED
BI_UNIPOLAR2
REF_SEL2
RESERVED
RESERVED
0x1020
RW
0x23 SETUPCON3
[15:8]
[7:0]
RESERVED
RESERVED
BI_UNIPOLAR3
REF_SEL3
RESERVED
RESERVED
0x1020
RW
0x28 FILTCON0
[15:8]
[7:0]
SINC3_MAP0
RESERVED
RESERVED
ORDER0
ENHFILTEN0
ENHFILT0
0x0000
RW
[15:8]
[7:0]
SINC3_MAP1
RESERVED
RESERVED
ORDER1
ENHFILTEN1
ENHFILT1
0x0000
RW
[15:8]
[7:0]
SINC3_MAP2
RESERVED
RESERVED
ORDER2
ENHFILTEN2
ENHFILT2
0x0000
RW
[15:8]
[7:0]
SINC3_MAP3
RESERVED
RESERVED
ORDER3
ENHFILTEN3
ENHFILT3
0x0000
RW
0x29 FILTCON1
0x2A FILTCON2
0x2B FILTCON3
0x30 OFFSET0
[23:16]
[15:8]
[7:0]
0x31 OFFSET1
[23:16]
[15:8]
[7:0]
0x32 OFFSET2
[23:16]
[15:8]
[7:0]
0x33 OFFSET3
[23:16]
[15:8]
[7:0]
ID[15:8]
ID[7:0]
0x0800
ODR0
ODR1
ODR2
ODR3
OFFSET0[23:16]
OFFSET0[15:8]
0x800000 RW
OFFSET0[7:0]
OFFSET1[23:16]
OFFSET1[15:8]
0x800000 RW
OFFSET1[7:0]
OFFSET2[23:16]
OFFSET2[15:8]
0x800000 RW
OFFSET2[7:0]
OFFSET3[23:16]
OFFSET3[15:8]
OFFSET3[7:0]
Rev. 0 | Page 44 of 68
0x800000 RW
Data Sheet
Reg
Name
0x38 GAIN0
AD7176-2
Bits
[23:16]
[15:8]
[7:0]
0x39 GAIN1
[23:16]
[15:8]
[7:0]
0x3A GAIN2
[23:16]
[15:8]
[7:0]
0x3B GAIN3
[23:16]
[15:8]
[7:0]
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
GAIN0[23:16]
GAIN0[15:8]
Bit 2
Bit 1
Bit 0
Reset
RW
0x5XXXX0 RW
GAIN0[7:0]
GAIN1[23:16]
GAIN1[15:8]
0x5XXXX0 RW
GAIN1[7:0]
GAIN2[23:16]
GAIN2[15:8]
0x5XXXX0 RW
GAIN2[7:0]
GAIN3[23:16]
GAIN3[15:8]
GAIN3[7:0]
Rev. 0 | Page 45 of 68
0x5XXXX0 RW
AD7176-2
Data Sheet
REGISTER DETAILS
COMMUNICATIONS REGISTER
Address: 0x00, Reset: 0x00, Name: COMMS
Table 22. Bit Descriptions for COMMS
Bits
7
Bit Name
WEN
6
R/W
Settings
0
1
[5:0]
RA
000000
000001
000010
000011
000100
000110
000111
010000
010001
010010
010011
100000
100001
100010
100011
101000
101001
101010
101011
110000
110001
110010
110011
111000
111001
111010
Description
This bit must be low to begin communications with the ADC.
Reset
0x0
Access
W
This bit determines if the command is a read or write operation.
Write command
Read command
The register address bits determine which register is to be read from or
written to as part of the current communication.
Status Register
ADC Mode Register
Interface Mode Register
Register Checksum Register
Data Register
GPIO Configuration Register
ID Register
Channel Map 1 Register
Channel Map 2 Register
Channel Map 3 Register
Channel Map 4 Register
Setup Configuration 1 Register
Setup Configuration 2 Register
Setup Configuration 3 Register
Setup Configuration 4 Register
Filter Configuration 1 Register
Filter Configuration 2 Register
Filter Configuration 3 Register
Filter Configuration 4 Register
Offset 1 Register
Offset 2 Register
Offset 3 Register
Offset 4 Register
Gain 1 Register
Gain 2 Register
Gain 3 Register
0x0
W
0x00
W
Rev. 0 | Page 46 of 68
Data Sheet
AD7176-2
STATUS REGISTER
Address: 0x00, Reset: 0x80, Name: STATUS
The Status Register is an 8-bit register that contains ADC and serial interface status information. It can optionally be appended to the
Data Register by setting the DATA_STAT bit in the Interface Mode Register.
Table 23. Bit Descriptions for STATUS
Bits
7
Bit Name
RDY
Settings
0
1
6
ADC_ERROR
0
1
5
CRC_ERROR
0
1
4
REG_ERROR
0
1
[3:2]
[1:0]
RESERVED
CHANNEL
00
01
10
11
Description
The status of RDY is output to the DOUT/RDYpin whenever CS is low and a
register is not being read. This bit goes low when the ADC has written a
new result to the Data Register. In ADC calibration modes, this bit goes
low when the ADC has written the calibration result. RDY is brought high
automatically by a read of the Data Register.
New data result available
Awaiting new data result
This bit by default indicates if an ADC overrange or underrange has
occurred. The ADC result will be clamped to ±full scale if this happens.
This bit is updated when the ADC result is written and is cleared by
removing the overrange or underrange condition on the analog inputs.
No Error
Error
This bit indicates if a CRC error has taken place during a register write. For
register reads, the host microcontroller determines if a CRC error has
occurred. This bit is cleared by a read of this register.
No Error
CRC Error
This bit indicates if the content of one of the internal registers has
changed from the value calculated when the register integrity check was
activated. The check is activated by setting the REG_CHECK bit in the
Interface Mode Register. This bit is cleared by clearing the REG_CHECK bit.
No Error
Error
These bits are reserved.
These bits indicate which channel was active for the ADC conversion
whose result is currently in the Data Register. This may be different from
the channel currently being converted. The mapping is a direct map from
the Channel Map Register; therefore, Channel 0 results in 0x0 and Channel
3 results in 0x3.
Channel 0
Channel 1
Channel 2
Channel 3
Rev. 0 | Page 47 of 68
Reset
0x1
Access
R
0x0
R
0x0
R
0x0
R
0x0
0x0
R
R
AD7176-2
Data Sheet
ADC MODE REGISTER
Address: 0x01, Reset: 0x8000, Name: ADCMODE
The ADC Mode Register controls the operating mode of the ADC and the master clock selection. A write to the ADC Mode Register
resets the filter and the RDY bits and starts a new conversion or calibration.
Table 24. Bit Descriptions for ADCMODE
Bits
15
Bit Name
REF_EN
Settings
0
1
14
13
RESERVED
SING_CYC
0
1
[12:11]
[10:8]
RESERVED
DELAY
000
001
010
011
100
101
110
111
7
[6:4]
RESERVED
MODE
000
001
010
011
100
110
111
[3:2]
CLOCKSEL
00
01
10
11
[1:0]
RESERVED
Description
Enables internal reference and outputs a buffered 2.5 V to the REFOUT pin.
Disabled
Enabled
This bit is reserved and should be set to 0.
This bit can be used when only a single channel is active to set the ADC to
only output at the settled filter data rate.
Disabled
Enabled
These bits are reserved and should be set to 0.
These bits allow a programmable delay to be added after a channel switch
to allow for settling of external circuitry before the ADC starts processing
its input.
0
4 µs
16 µs
40 µs
100 µs
200 µs
500 µs
1 ms
This bit is reserved and should be set to 0.
These bits control the operating mode of the ADC. Details can be found in
the Operating Modes section.
Continuous Conversion Mode
Single Conversion Mode
Standby Mode
Power-Down Mode
Internal Offset Calibration
System Offset Calibration
System Gain Calibration
This bit is used to select the ADC clock source. Selecting internal oscillator
also enables the internal oscillator.
Internal oscillator
Internal oscillator output on XTAL2 pin
External clock input on XTAL2 pin
External crystal on XTAL1 and XTAL2 pins
These bits are reserved and should be set to 0.
Rev. 0 | Page 48 of 68
Reset
0x1
Access
RW
0x0
0x0
R
RW
0x0
0x0
R
RW
0x0
0x0
R
RW
0x0
RW
0x0
R
Data Sheet
AD7176-2
INTERFACE MODE REGISTER
Address: 0x02, Reset: 0x0000, Name: IFMODE
The Interface Mode Register configures various serial interface options.
Table 25. Bit Descriptions for IFMODE
Bits
[15:13]
12
Bit Name
RESERVED
ALT_SYNC
Settings
0
1
11
IOSTRENGTH
0
1
[10:9]
8
RESERVED
DOUT_RESET
0
1
7
CONTREAD
0
1
6
DATA_STAT
0
1
5
REG_CHECK
0
1
4
RESERVED
Description
These bits are reserved and should be set to 0.
This bit enables a different behavior of the ERROR\SYNC pin to allow the
use of ERROR\SYNC as a control for conversions when cycling channels
(see the description of the SYNC_EN bit in the GPIO Configuration Register
for details).
Disabled
Enabled
This bit controls the drive strength of the DOUT pin. This bit should be set
when reading from the serial interface at high speed with low IOVDD
supply and moderate capacitance.
Disabled (default)
Enabled
These bits are reserved and should be set to 0.
This bit prevents the DOUT/RDY pin from switching from outputting
DOUT to outputting RDY soon after the last rising edge of SCLK during a
read operation. Instead, the DOUT/RDY pin will continue to output the
LSB of the data until CS goes high. This allows for longer hold times for the
SPI master to sample the LSB of the data. When this bit is set, CS must not
be tied low.
Disabled
Enabled
This enables continuous read of the ADC data register. The ADC should be
configured in continuous conversion mode to use continuous read. For
more details, see the Operating Modes section.
Disabled
Enabled
This enables the Status Register to be appended to the Data Register
when read so that channel and status information are transmitted with
the data. This is the only way to be sure that the channel bits read from
the Status Register correspond to the data in the Data Register.
Disabled
Enabled
This bit enables a register integrity checker, which can be used to monitor
any change in the value of the user registers. To use this feature, all other
registers should be configured as desired, with this bit cleared. Then write
to this register to set the REG_CHECK bit to 1. If the contents of any of the
registers change, the REG_ERROR bit is set in the Status Register. To clear
the error, the REG_CHECK bit should be set to 0. Neither the Interface
Mode Register nor the ADC Data or Status Register is included in the
registers that are checked. If a register needs to have a new value written,
this bit should first be cleared; otherwise, an error will be flagged falsely
when the new register contents are written.
Disabled
Enabled
This bit is reserved and should be set to 0.
Rev. 0 | Page 49 of 68
Reset
0x0
0x0
Access
R
RW
0x0
RW
0x0
0x0
R
RW
0x0
RW
0x0
RW
0x0
RW
0x0
R
AD7176-2
Bits
[3:2]
Bit Name
CRC_EN
Data Sheet
Settings
00
01
10
1
0
RESERVED
WL16
0
1
Description
Enables CRC protection of register reads/writes. CRC increases the
number of bytes in a serial interface transfer by one. See the CRC
Calculation section for more details.
Disabled.
XOR checksum enabled for register read transactions. Register writes will
still use CRC with these bits set.
CRC checksum enabled for read and write transactions.
This bit is reserved and should be set to 0.
Changes the ADC Data Register to 16 bits. The ADC is not reset by a write
to the Interface Mode Register; therefore, the ADC result will not be
rounded to the correct word length immediately after writing to these
bits. The first new ADC result will be correct.
24-bit data
16-bit data
Reset
0x00
Access
RW
0x0
0x0
R
RW
REGISTER CHECK
Address: 0x03, Reset: 0x000000, Name: REGCHECK
This Register Check Register is a 24-bit checksum calculated by exclusively OR'ing the contents of the user registers. The REG_CHECK
bit in the Interface Mode Register must be set for this to operate; otherwise, the register reads 0.
Table 26. Bit Descriptions for REGCHECK
Bits
[23:0]
Bit Name
REGISTER_CHECK
Settings
Description
This register contains the 24-bit checksum of user registers when the
REG_CHECK bit is set in the Interface Mode Register.
Reset
0x000000
Access
R
DATA REGISTER
Address: 0x04, Reset: 0x000000, Name: DATA
The Data Register contains the ADC conversion result. The encoding is offset binary, or it can be changed to unipolar by the
BI_UNIPOLAR bit in the Setup Configuration Register. Reading the Data Register brings the RDY bit and pin high if they had been low.
The ADC result can be read multiple times; however, because RDY has been brought high, it is not possible to know if another ADC
result is imminent. The ADC will not write a new result into the data register if the register is currently being read.
Table 27. Bit Descriptions for DATA
Bits
[23:0]
Bit Name
DATA
Settings
Description
This register contains the ADC conversion result. If DATA_STAT is set in
the Interface Mode Register, then the Status Register is appended to this
register when read, making this a 32-bit register. If WL16 is set in the
Interface Mode Register, then this register is rounded to 16 bits.
Rev. 0 | Page 50 of 68
Reset
0x000000
Access
R
Data Sheet
AD7176-2
GPIO CONFIGURATION REGISTER
Address: 0x06, Reset: 0x0800, Name: GPIOCON
The GPIO Configuration Register controls the general-purpose I/O pins of the ADC.
Table 28. Bit Descriptions for GPIOCON
Bits
[15:13]
12
Bit Name
RESERVED
MUX_IO
11
SYNC_EN
Settings
0
1
[10:9]
ERR_EN
00
01
10
11
8
ERR_DAT
[7:6]
5
RESERVED
IP_EN1
0
1
4
IP_EN0
0
1
3
OP_EN1
0
1
2
OP_EN0
Description
These bits are reserved and should be set to 0.
This bit allows the ADC to control an external multiplexer, using GPIO0/GPIO1
in sync with the internal channel sequencing. The analog input pins used
for a channel can still be selected on a per channel basis. Therefore, it is
possible to have a 4-channel multiplexer in front of AIN0/AIN1 and another
in front of AIN2/AIN3, giving a total of eight differential channels with the
AD7175-2. However, only four channels at a time can be automatically
sequenced. A delay can be inserted after switching an external multiplexer
(see the DELAY bits in the ADC Mode Register).
This bit enables the SYNC/ERROR pin as a sync input. When set low, the
SYNC/ERROR pin holds the ADC and filter in reset until SYNC/ERROR goes
high. An alternative operation of the SYNC/ERROR pin is available when
the ALT_SYNC bit in the Interface Mode Register is set. This mode only
works when multiple channels are enabled. In this case, a low on the SYNC
/ERROR pin does not immediately reset the filter/modulator. Instead, if the
SYNC/ERROR pin is low when the channel is due to be switched, the
modulator and filter are prevented from starting a new conversion.
Bringing SYNC/ERROR high begins the next conversion. This alternative
sync mode allows SYNC/ERROR to be used while cycling through channels.
Disabled
Enabled
These bits enable the SYNC/ERROR pin as an error input/output.
Disabled
SYNC/ERROR is an error input. The (inverted) readback state is OR'ed with
other error sources and is available in the ADC_ERROR bit in the Status
Register. The SYNC/ERROR pin state can also be read from the ERR_DAT bit
in this register.
SYNC/ERROR is an open-drain error output. The Status Register error bits
are OR'ed, inverted, and mapped to the SYNC/ERROR pin. SYNC/ERROR
pins of multiple devices can be wired together to a common pull-up
resistor so that an error on any device can be observed.
SYNC/ERROR is a general-purpose output. The status of the pin is
controlled by the ERR_DAT bit in this register. This is referenced between
IOVDD and DGND, as opposed to the AVDD1 and AVSS levels used by the
general-purpose I/O pins. It has an active pull-up in this case.
This bit determines the logic level at the ERROR pin if the pin is enabled as
a general-purpose output. It reflects the readback status of the pin if the
pin is enabled as an input.
These bits are reserved and should be set to 0.
This bit turns GPIO1 into an input. Input should equal AVDD5 or AVSS.
Disabled
Enabled
This bit turns GPIO0 into an input. Input should equal AVDD5 or AVSS.
Disabled
Enabled
This bit turns GPIO1 into an output. Outputs are referenced between
AVDD1 and AVSS.
Disabled
Enabled
This bit turns GPIO0 into an output. Outputs are referenced between
AVDD1 and AVSS.
Rev. 0 | Page 51 of 68
Reset
0x0
0x0
Access
R
RW
0x1
RW
0x0
RW
0x0
RW
0x0
0x0
R
RW
0x0
RW
0x0
RW
0x0
RW
AD7176-2
Bits
Bit Name
Data Sheet
Settings
0
1
1
0
GP_DATA1
GP_DATA0
Description
Disabled
Enabled
This bit is the readback or write data for GPIO1.
This bit is the readback or write data for GPIO0.
Reset
Access
0x0
0x0
RW
RW
Reset
0x0C9X
Access
R
ID REGISTER
Address: 0x07, Reset: 0x0C9X, Name: ID
The ID register returns a 16-bit ID. For the AD7176-2, this should be 0x0C94.
Table 29. Bit Descriptions for ID
Bits
[15:0]
Bit Name
ID
Settings
0x0C9X
Description
The ID register returns a 16-bit ID code that is specific to the ADC.
AD7176-2
Rev. 0 | Page 52 of 68
Data Sheet
AD7176-2
CHANNEL MAP REGISTER 0
Address: 0x10, Reset: 0x8001, Name: CHMAP0
The Channel Map Registers are 16-bit registers that are used to select which channels are currently active, which inputs are selected for
each channel, and which setup should be used to configure the ADC for that channel.
Table 30. Bit Descriptions for CHMAP0
Bits
15
Bit Name
CH_EN0
Settings
0
1
14
[13:12]
RESERVED
SETUP_SEL0
000
001
010
011
[11:10]
[9:5]
RESERVED
AINPOS0
00000
00001
00010
00011
00100
10101
10110
[4:0]
AINNEG0
00000
00001
00010
00011
00100
10101
10110
Description
This bit enables Channel 0. If more than one channel is enabled, the ADC
will automatically sequence between them.
Disabled
Enabled (default)
This bit is reserved and should be set to 0.
These bits identify which of the four setups are used to configure the ADC
for this channel. A setup comprises a set of four registers: Setup Configuration
Register, Filter Configuration Register, Offset Register, Gain Register. All
channels can use the same setup, in which case the same 3-bit value should
be written to these bits on all active channels, or up to four channels can
be configured differently.
Setup 0
Setup 1
Setup 2
Setup 3
These bits are reserved and should be set to 0.
These bits select which of the analog inputs is connected to the positive
input of the ADC for this channel.
AIN0 (default)
AIN1
AIN2
AIN3
AIN4
REF+
REF−
These bits select which of the analog inputs is connected to the negative
input of the ADC for this channel.
AIN0
AIN1 (default)
AIN2
AIN3
AIN4
REF+
REF−
Rev. 0 | Page 53 of 68
Reset
0x1
Access
RW
0x0
0x0
R
RW
0x0
0x0
R
RW
0x1
RW
AD7176-2
Data Sheet
CHANNEL MAP REGISTER 1
Address: 0x11, Reset: 0x0001, Name: CHMAP1
The Channel Map Registers are 16-bit registers that are used to select which channels are currently active, which inputs are selected for
each channel, and which setup should be used to configure the ADC for that channel.
Table 31. Bit Descriptions for CHMAP1
Bits
15
Bit Name
CH_EN1
Settings
0
1
14
[13:12]
RESERVED
SETUP_SEL1
000
001
010
011
[11:10]
[9:5]
RESERVED
AINPOS1
00000
00001
00010
00011
00100
10101
10110
[4:0]
AINNEG1
00000
00001
00010
00011
00100
10101
10110
Description
This bit enables Channel 1. If more than one channel is enabled, the ADC
will automatically sequence between them.
Disabled (default)
Enabled
This bit is reserved and should be set to 0.
These bits identify which of the four setups are used to configure the ADC
for this channel. A setup comprises a set of four registers: Setup Configuration
Register, Filter Configuration Register, Offset Register, Gain Register. All
channels can use the same setup, in which case the same 3-bit value should
be written to these bits on all active channels, or up to four channels can
be configured differently.
Setup 0
Setup 1
Setup 2
Setup 3
These bits are reserved and should be set to 0.
These bits select which of the analog inputs is connected to the positive
input of the ADC for this channel.
AIN0 (default)
AIN1
AIN2
AIN3
AIN4
REF+
REF−
These bits select which of the analog inputs is connected to the negative
input of the ADC for this channel.
AIN0
AIN1 (default)
AIN2
AIN3
AIN4
REF+
REF−
Rev. 0 | Page 54 of 68
Reset
0x0
Access
RW
0x0
0x0
R
RW
0x0
0x0
R
RW
0x1
RW
Data Sheet
AD7176-2
CHANNEL MAP REGISTER 2
Address: 0x12, Reset: 0x0001, Name: CHMAP2
The Channel Map Registers are 16-bit registers that are used to select which channels are currently active, which inputs are selected for
each channel, and which setup should be used to configure the ADC for that channel.
Table 32. Bit Descriptions for CHMAP2
Bits
15
Bit Name
CH_EN2
Settings
0
1
14
[13:12]
RESERVED
SETUP_SEL2
000
001
010
011
[11:10]
[9:5]
RESERVED
AINPOS2
00000
00001
00010
00011
00100
10101
10110
[4:0]
AINNEG2
00000
00001
00010
00011
00100
10101
10110
Description
This bit enables Channel 2. If more than one channel is enabled, the ADC
will automatically sequence between them.
Disabled (default)
Enabled
This bit is reserved and should be set to 0.
These bits identify which of the four setups are used to configure the ADC
for this channel. A setup comprises a set of four registers: Setup Configuration
Register, Filter Configuration Register, Offset Register, Gain Register. All
channels can use the same setup, in which case the same 3-bit value should
be written to these bits on all active channels, or up to four channels can
be configured differently.
Setup 0
Setup 1
Setup 2
Setup 3
These bits are reserved and should be set to 0.
These bits select which of the analog inputs is connected to the positive
input of the ADC for this channel.
AIN0 (default)
AIN1
AIN2
AIN3
AIN4
REF+
REF−
These bits select which of the analog inputs is connected to the negative
input of the ADC for this channel.
AIN0
AIN1 (default)
AIN2
AIN3
AIN4
REF+
REF−
Rev. 0 | Page 55 of 68
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0x0
0x0
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RW
0x0
0x0
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RW
0x1
RW
AD7176-2
Data Sheet
CHANNEL MAP REGISTER 3
Address: 0x13, Reset: 0x0001, Name: CHMAP3
The Channel Map Registers are 16-bit registers that are used to select which channels are currently active, which inputs are selected for
each channel, and which setup should be used to configure the ADC for that channel.
Table 33. Bit Descriptions for CHMAP3
Bits
15
Bit Name
CH_EN3
Settings
0
1
14
[13:12]
RESERVED
SETUP_SEL3
000
001
010
011
[11:10]
[9:5]
RESERVED
AINPOS3
00000
00001
00010
00011
00100
10101
10110
[4:0]
AINNEG3
00000
00001
00010
00011
00100
10101
10110
Description
This bit enables Channel 3. If more than one channel is enabled, the ADC
will automatically sequence between them.
Disabled (default)
Enabled
This bit is reserved and should be set to 0.
These bits identify which of the four setups are used to configure the ADC
for this channel. A setup comprises a set of four registers: Setup Configuration
Register, Filter Configuration Register, Offset Register, Gain Register. All
channels can use the same setup, in which case the same 3-bit value should
be written to these bits on all active channels, or up to four channels can
be configured differently.
Setup 0
Setup 1
Setup 2
Setup 3
These bits are reserved and should be set to 0.
These bits select which of the analog inputs is connected to the positive
input of the ADC for this channel.
AIN0 (default)
AIN1
AIN2
AIN3
AIN4
REF+
REF−
These bits select which of the analog inputs is connected to the negative
input of the ADC for this channel.
AIN0
AIN1 (default)
AIN2
AIN3
AIN4
REF+
REF−
Rev. 0 | Page 56 of 68
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Data Sheet
AD7176-2
SETUP CONFIGURATION REGISTER 0
Address: 0x20, Reset: 0x1020, Name: SETUPCON0
The Setup Configuration Registers are 16-bit registers that configure the reference selection and output coding of the ADC.
Table 34. Bit Descriptions for SETUPCON0
Bits
[15:13]
12
Bit Name
RESERVED
BI_UNIPOLAR0
Settings
0
1
[11:6]
[5:4]
RESERVED
REF_SEL0
00
10
11
[3:0]
RESERVED
Description
These bits are reserved and should be set to 0.
This bit sets the output coding of the ADC for Setup 0.
Unipolar coded output
Offset binary coded output
These bits are reserved and should be set to 0.
These bits allow you to select the reference source for ADC conversion on
Setup 0.
External Reference.
Internal 2.5 V Reference. This must also be enabled in the ADC Mode Register.
AVDD1 − AVSS. This can be used to as a diagnostic to validate other
reference values.
These bits are reserved and should be set to 0.
Reset
0x0
0x1
Access
R
RW
0x00
0x2
R
RW
0x0
R
SETUP CONFIGURATION REGISTER 1
Address: 0x21, Reset: 0x1020, Name: SETUPCON1
The Setup Configuration Registers are 16-bit registers that configure the reference selection and output coding of the ADC.
Table 35. Bit Descriptions for SETUPCON1
Bits
[15:13]
12
Bit Name
RESERVED
BI_UNIPOLAR1
Settings
0
1
[11:6]
[5:4]
RESERVED
REF_SEL1
00
10
11
[3:0]
RESERVED
Description
These bits are reserved and should be set to 0.
This bit sets the output coding of the ADC for Setup 1.
Unipolar coded output
Offset binary coded output
These bits are reserved and should be set to 0.
These bits allow you to select the reference source for ADC conversion on
Setup 1.
External Reference
Internal 2.5 V Reference. This must also be enabled in the ADC Mode Register.
AVDD1 − AVSS. This can be used to as a diagnostic to validate other
reference values.
These bits are reserved and should be set to 0.
Rev. 0 | Page 57 of 68
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AD7176-2
Data Sheet
SETUP CONFIGURATION REGISTER 2
Address: 0x22, Reset: 0x1020, Name: SETUPCON2
The Setup Configuration Registers are 16-bit registers that configure the reference selection and output coding of the ADC.
Table 36. Bit Descriptions for SETUPCON2
Bits
[15:13]
12
Bit Name
RESERVED
BI_UNIPOLAR2
Settings
0
1
[11:6]
[5:4]
RESERVED
REF_SEL2
00
10
11
[3:0]
RESERVED
Description
These bits are reserved and should be set to 0.
This bit sets the output coding of the ADC for Setup 2.
Unipolar coded output
Offset binary coded output
These bits are reserved and should be set to 0.
These bits allow you to select the reference source for ADC conversion on
Setup 2.
External Reference
Internal 2.5 V Reference. This must also be enabled in the ADC Mode Register.
AVDD1 − AVSS. This can be used to as a diagnostic to validate other
reference values.
These bits are reserved and should be set to 0.
Reset
0x0
0x1
Access
R
RW
0x00
0x2
R
RW
0x0
R
SETUP CONFIGURATION REGISTER 3
Address: 0x23, Reset: 0x1020, Name: SETUPCON3
The Setup Configuration Registers are 16-bit registers that configure the reference selection and output coding of the ADC.
Table 37. Bit Descriptions for SETUPCON3
Bits
[15:13]
12
Bit Name
RESERVED
BI_UNIPOLAR3
Settings
0
1
[11:6]
[5:4]
RESERVED
REF_SEL3
00
10
11
[3:0]
RESERVED
Description
These bits are reserved and should be set to 0.
This bit sets the output coding of the ADC for Setup 3.
Unipolar coded output
Offset binary coded output
These bits are reserved and should be set to 0.
These bits allow you to select the reference source for ADC conversion on
Setup 3.
External Reference
Internal 2.5 V Reference. This must also be enabled in the ADC Mode Register.
AVDD1 − AVSS. This can be used to as a diagnostic to validate other
reference values.
These bits are reserved and should be set to 0.
Rev. 0 | Page 58 of 68
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Data Sheet
AD7176-2
FILTER CONFIGURATION REGISTER 0
Address: 0x28, Reset: 0x0000, Name: FILTCON0
The Filter Configuration Registers are 16-bit registers that configure the ADC data rate and filter options. Writing to any of these registers
resets any active ADC conversion and restarts converting at the first channel in the sequence.
Table 38. Bit Descriptions for FILTCON0
Bits
15
Bit Name
SINC3_MAP0
[14:12]
11
RESERVED
ENHFILTEN0
Settings
0
1
[10:8]
ENHFILT0
010
011
101
110
7
[6:5]
RESERVED
ORDER0
00
11
[4:0]
ODR0
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
Description
If this bit is set, the mapping of the Filter Register changes to directly
program the decimation rate of the Sinc3 filter for Setup 0. All other
options are eliminated. This allows for fine tuning of the output data rate
and filter notch for rejection of specific frequencies. The data rate when on
a single channel equals FMOD/(32 × FILTCON0[14:0]).
These bits are reserved and should be set to 0.
This bit enables various post filters for enhanced 50 Hz/60 Hz rejection for
Setup 0. The ORDER bits must be set to 00 to select the Sinc5 + Sinc1 filter
for this to work.
Disabled
Enabled
These bits select between various post filters for enhanced 50 Hz/60 Hz
rejection for Setup 0.
27 SPS, 47 dB rejection, 36.7 ms settling
25 SPS, 62 dB rejection, 40 ms settling
20 SPS, 86 dB rejection, 50 ms settling
16.67 SPS, 92 dB rejection, 60 ms settling
This bit is reserved and should be set to 0.
These bits control the order of the digital filter that processes the
modulator data for Setup 0.
Sinc5 + Sinc1 (default)
Sinc3
These bits control the output data rate of the ADC and, therefore, the
settling time and noise for Setup 0.
250,000
125,000
62,500
50,000
31,250
25,000
15,625
10,000
5000
2500
1000
500
397.5
200
100
59.94
49.96
20
16.667
10
5
Rev. 0 | Page 59 of 68
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AD7176-2
Data Sheet
FILTER CONFIGURATION REGISTER 1
Address: 0x29, Reset: 0x0000, Name: FILTCON1
The Filter Configuration Registers are 16-bit registers that configure the ADC data rate and filter options. Writing to any of these registers
resets any active ADC conversion and restarts converting at the first channel in the sequence.
Table 39. Bit Descriptions for FILTCON1
Bits
15
Bit Name
SINC3_MAP1
[14:12]
11
RESERVED
ENHFILTEN1
Settings
0
1
[10:8]
ENHFILT1
010
011
101
110
7
[6:5]
RESERVED
ORDER1
00
11
[4:0]
ODR1
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
Description
If this bit is set, the mapping of the Filter Register changes to directly
program the decimation rate of the Sinc3 filter for Setup 1. All other
options are eliminated. This allows for fine tuning of the output data rate
and filter notch for rejection of specific frequencies. The data rate when on
a single channel equals FMOD/(32 × FILTCON1[14:0]).
These bits are reserved and should be set to 0.
This bit enables various post filters for enhanced 50 Hz/60 Hz rejection for
Setup 1. The ORDER bits must be set to 00 to select the Sinc5 + Sinc1 filter
for this to work.
Disabled
Enabled
These bits select between various post filters for enhanced 50 Hz/60 Hz
rejection for Setup 1.
27 SPS, 47 dB rejection, 36.7 ms settling
25 SPS, 62 dB rejection, 40 ms settling
20 SPS, 86 dB rejection, 50 ms settling
16.67 SPS, 92 dB rejection, 60 ms settling
This bit is reserved and should be set to 0.
These bits control the order of the digital filter that processes the
modulator data for Setup 1.
Sinc5 + Sinc1 (default)
Sinc3
These bits control the output data rate of the ADC and, therefore, the
settling time and noise for Setup 1.
250,000
125,000
62,500
50,000
31,250
25,000
15,625
10,000
5000
2500
1000
500
397.5
200
100
59.94
49.96
20
16.667
10
5
Rev. 0 | Page 60 of 68
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Data Sheet
AD7176-2
FILTER CONFIGURATION REGISTER 2
Address: 0x2A, Reset: 0x0000, Name: FILTCON2
The Filter Configuration Registers are 16-bit registers that configure the ADC data rate and filter options. Writing to any of these registers
resets any active ADC conversion and restarts converting at the first channel in the sequence.
Table 40. Bit Descriptions for FILTCON2
Bits
15
Bit Name
SINC3_MAP2
[14:12]
11
RESERVED
ENHFILTEN2
Settings
0
1
[10:8]
ENHFILT2
010
011
101
110
7
[6:5]
RESERVED
ORDER2
00
11
[4:0]
ODR2
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
Description
If this bit is set, the mapping of the Filter Register changes to directly
program the decimation rate of the Sinc3 filter for Setup 2. All other
options are eliminated. This allows for fine tuning of the output data rate
and filter notch for rejection of specific frequencies. The data rate when on
a single channel equals FMOD/(32 × FILTCON2[14:0]).
These bits are reserved and should be set to 0.
This bit enables various post filters for enhanced 50 Hz/60 Hz rejection for
Setup 2. The ORDER bits must be set to 00 to select the Sinc5 + Sinc1 filter
for this to work.
Disabled
Enabled
These bits select between various post filters for enhanced 50 Hz/60 Hz
rejection for Setup 2.
27 SPS, 47dB rejection, 36.7 ms settling
25 SPS, 62 dB rejection, 40 ms settling
20 SPS, 86 dB rejection, 50 ms settling
16.67 SPS, 92 dB rejection, 60 ms settling
This bit is reserved and should be set to 0.
These bits control the order of the digital filter that processes the
modulator data for Setup 2.
Sinc5 + Sinc1 (default)
Sinc3
These bits control the output data rate of the ADC and, therefore, the
settling time and noise for Setup 2.
250,000
125,000
62,500
50,000
31,250
25,000
15,625
10,000
5000
2500
1000
500
397.5
200
100
59.94
49.96
20
16.667
10
5
Rev. 0 | Page 61 of 68
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AD7176-2
Data Sheet
FILTER CONFIGURATION REGISTER 3
Address: 0x2B, Reset: 0x0000, Name: FILTCON3
The Filter Configuration Registers are 16-bit registers that configure the ADC data rate and filter options. Writing to any of these registers
resets any active ADC conversion and restarts converting at the first channel in the sequence.
Table 41. Bit Descriptions for FILTCON3
Bits
15
Bit Name
SINC3_MAP3
[14:12]
11
RESERVED
ENHFILTEN3
Settings
0
1
[10:8]
ENHFILT3
010
011
101
110
7
[6:5]
RESERVED
ORDER3
00
11
[4:0]
ODR3
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
Description
If this bit is set, the mapping of the Filter Register changes to directly
program the decimation rate of the Sinc3 filter for Setup 3. All other
options are eliminated. This allows for fine tuning of the output data rate
and filter notch for rejection of specific frequencies. The data rate when on
a single channel equals FMOD/(32 × FILTCON3[14:0]).
These bits are reserved and should be set to 0.
This bit enables various post filters for enhanced 50 Hz/60 Hz rejection for
Setup 3. The ORDER bits must be set to 00 to select the Sinc5 + Sinc1 filter
for this to work.
Disabled
Enabled
These bits select between various post filters for enhanced 50 Hz/60 Hz
rejection for Setup 3.
27 SPS, 47 dB rejection, 36.7 ms settling
25 SPS, 62 dB rejection, 40 ms settling
20 SPS, 86 dB rejection, 50 ms settling
16.67 SPS, 92 dB rejection, 60 ms settling
This bit is reserved and should be set to 0.
These bits control the order of the digital filter that processes the
modulator data for Setup 3.
Sinc5 + Sinc1 (default)
Sinc3
These bits control the output data rate of the ADC and, therefore, the
settling time and noise for Setup 3.
250,000
125,000
62,500
50,000
31,250
25,000
15,625
10,000
5000
2500
1000
500
397.5
200
100
59.94
49.96
20
16.667
10
5
Rev. 0 | Page 62 of 68
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AD7176-2
OFFSET REGISTER 0
Address: 0x30, Reset: 0x800000, Name: OFFSET0
The Offset (Zero-Scale) Registers are 24-bit registers that can be used to compensate for any offset error in the ADC or in the system.
Table 42. Bit Descriptions for OFFSET0
Bits
[23:0]
Bit Name
OFFSET0
Settings
Description
Offset calibration coefficient for Setup 0.
Reset
0x800000
Access
RW
OFFSET REGISTER 1
Address: 0x31, Reset: 0x800000, Name: OFFSET1
The Offset (Zero-Scale) Registers are 24-bit registers that can be used to compensate for any offset error in the ADC or in the system.
Table 43. Bit Descriptions for OFFSET1
Bits
[23:0]
Bit Name
OFFSET1
Settings
Description
Offset calibration coefficient for Setup 1.
Reset
0x800000
Access
RW
OFFSET REGISTER 2
Address: 0x32, Reset: 0x800000, Name: OFFSET2
The Offset (Zero-Scale) Registers are 24-bit registers that can be used to compensate for any offset error in the ADC or in the system.
Table 44. Bit Descriptions for OFFSET2
Bits
[23:0]
Bit Name
OFFSET2
Settings
Description
Offset calibration coefficient for Setup 2.
Reset
0x800000
Access
RW
OFFSET REGISTER 3
Address: 0x33, Reset: 0x800000, Name: OFFSET3
The Offset (Zero-Scale) Registers are 24-bit registers that can be used to compensate for any offset error in the ADC or in the system.
Table 45. Bit Descriptions for OFFSET3
Bits
[23:0]
Bit Name
OFFSET3
Settings
Description
Offset calibration coefficient for Setup 3.
Rev. 0 | Page 63 of 68
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AD7176-2
Data Sheet
GAIN REGISTER 0
Address: 0x38, Reset: 0x5xxxx0, Name: GAIN0
The Gain (Full-Scale) Registers are 24-bit registers that can be used to compensate for any gain error in the ADC or in the system.
Table 46. Bit Descriptions for GAIN0
Bits
[23:0]
Bit Name
GAIN0
Settings
Description
Gain calibration coefficient for Setup 0.
Reset
0x5XXXX0
Access
RW
GAIN REGISTER 1
Address: 0x39, Reset: 0x5xxxx0, Name: GAIN1
The Gain (Full-Scale) Registers are 24-bit registers that can be used to compensate for any gain error in the ADC or in the system.
Table 47. Bit Descriptions for GAIN1
Bits
[23:0]
Bit Name
GAIN1
Settings
Description
Gain calibration coefficient for Setup 1.
Reset
0x5XXXX0
Access
RW
GAIN REGISTER 2
Address: 0x3A, Reset: 0x5xxxx0, Name: GAIN2
The Gain (Full-Scale) Registers are 24-bit registers that can be used to compensate for any gain error in the ADC or in the system.
Table 48. Bit Descriptions for GAIN2
Bits
[23:0]
Bit Name
GAIN2
Settings
Description
Gain calibration coefficient for Setup 2.
Reset
0x5XXXX0
Access
RW
GAIN REGISTER 3
Address: 0x3B, Reset: 0x5xxxx0, Name: GAIN3
The Gain (Full-Scale) Registers are 24-bit registers that can be used to compensate for any gain error in the ADC or in the system.
Table 49. Bit Descriptions for GAIN3
Bits
[23:0]
Bit Name
GAIN3
Settings
Description
Gain calibration coefficient for Setup 3.
Rev. 0 | Page 64 of 68
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0x5XXXX0
Access
RW
Data Sheet
AD7176-2
OUTLINE DIMENSIONS
7.90
7.80
7.70
24
13
4.50
4.40
4.30
6.40 BSC
1
12
PIN 1
0.65
BSC
0.15
0.05
0.30
0.19
1.20
MAX
SEATING
PLANE
0.20
0.09
8°
0°
0.75
0.60
0.45
0.10 COPLANARITY
COMPLIANT TO JEDEC STANDARDS MO-153-AD
Figure 52. 24-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-24)
Dimensions shown in millimeters
ORDERING GUIDE
Models 1
AD7176-2BRUZ
AD7176-2BRUZ-RL
EVAL-AD7176-2SDZ
EVAL-SDP-CB1Z
1
Temperature Range
–40°C to +105°C
–40°C to +105°C
Package Description
24-Lead TSSOP
24-Lead TSSOP
Evaluation Board
Evaluation Controller Board
Z = RoHS Compliant Part.
Rev. 0 | Page 65 of 68
Package Option
RU-24
RU-24
AD7176-2
Data Sheet
NOTES
Rev. 0 | Page 66 of 68
Data Sheet
AD7176-2
NOTES
Rev. 0 | Page 67 of 68
AD7176-2
Data Sheet
NOTES
©2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D11037-0-11/12(0)
Rev. 0 | Page 68 of 68