AOSMD AOZ1039DI Ezbuckâ ¢ 8 a synchronous buck regulator Datasheet

AOZ1039DI
EZBuck™ 8 A Synchronous Buck Regulator
General Description
Features
The AOZ1039DI is a high efficiency, easy to use, 8 A
synchronous buck regulator. The AOZ1039DI provides
up to 8 A of continuous output current with an output
voltage adjustable from 1.2 V to 0.8 V when the input
power rail is 12 V. For higher output voltage and/or lower
input voltage, the output current should be derated
according to thermal performance.
z 4.5 V to 18 V operating input voltage range
z Synchronous Buck: 70 mΩ internal high-side switch
and 11 mΩ internal low-side switch (at 12 V)
z Up to 95% efficiency
z Internal soft start
z Output voltage adjustable to 0.8 V
z 8 A continuous output current
The AOZ1039DI comes in a DFN5x6 is rated over a
-40 °C to +85 °C operating ambient temperature range.
z Cycle-by-cycle current limit
z Pre-bias start-up
z Short-circuit protection
z Thermal shutdown
Applications
z Point of load DC/DC converters
z LCD TV
z Set top boxes
z DVD and Blu-ray players/recorders
z Cable modems
Typical Application
VIN = 12V
C1
22µF
VIN
EN
L1
1µH
AOZ1039
R1
COMP
RC
CC
VOUT
LX
C2, C3, C4
22µF
FB
AGND
PGND
R2
Figure 1. 1.05 V 8 A Synchronous Buck Regulator, Fs = 450 kHz
Rev. 1.2 September 2011
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Page 1 of 13
AOZ1039DI
Ordering Information
Part Number
Ambient Temperature Range
Package
Environmental
AOZ1039DI
-40 °C to +85 °C
5x6 DFN-8
Green Product
AOS Green Products use reduced levels of Halogens, and are also RoHS compliant.
Please visit www.aosmd.com/web/quality/rohs_compliant.jsp for additional information.
Pin Configuration
PGND
1
VIN
2
AGND
3
FB
4
PAD
(LX)
8
NC
7
NC
6
EN
5
COMP
5x6 DFN-8
(Top View)
Pin Description
Pin Number
Pin Name
1
PGND
2
VIN
3
AGND
4
FB
5
COMP
6
EN
Enable pin. Pull EN to logic high to enable the device. Pull EN to logic low to disable the
device. If on/off control in not needed, connect EN to VIN. Do not leave EN open.
7,8
NC
Not connected.
Exposed pad
LX
Switching node. LX is the drain of the internal PFET. LX is used as the thermal pad of the
power stage.
Rev. 1.2 September 2011
Pin Function
Power ground. PGND needs to be electrically connected to AGND.
Supply voltage input. When VIN rises above the UVLO threshold and EN is logic high, the
device starts up.
Analog ground. AGND is the reference point for controller section. AGND needs to be
electrically connected to PGND.
Feedback input. The FB pin is used to set the output voltage via a resistive voltage divider
between the output and AGND.
External loop compensation pin. Connect a RC network between COMP and AGND to
compensate the control loop.
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Page 2 of 13
AOZ1039DI
Block Diagram
VIN
UVLO
& POR
EN
Internal
+5V
5V LDO
Regulator
OTP
+
ISen
Softstart
Ramp
–
Reference
& Bias
0.8V
+
+
EAmp
FB
Q1
ILimit
–
–
PWM
Comp
PWM
Control
Logic
+
Level
Shifter
+
FET
Driver
LX
Q2
COMP
Oscillator
OVP
Comp
960 mV
AGND
PGND
Absolute Maximum Ratings
Recommended Operating Conditions
Exceeding the Absolute Maximum Ratings may damage the
device.
The device is not guaranteed to operate beyond the maximum
Recommended Operating Conditions.
Parameter
Supply Voltage (VIN)
LX to AGND
LX to AGND (20 ns)
EN to AGND
FB, COMP to AGND
PGND to AGND
Rating
Parameter
20 V
-0.7 V to VIN+0.3 V
-5 V to 22 V
-0.3 V to VIN+0.3 V
-0.3 V to 6 V
-0.3 V to +0.3 V
Junction Temperature (TJ)
+150 °C
Storage Temperature (TS)
-65 °C to +150 °C
ESD Rating
(1)
2.0 kV
Supply Voltage (VIN)
Output Voltage Range
Ambient Temperature (TA)
Package Thermal Resistance
5x6 DFN-8 (ΘJA)(2)
Rating
4.5 V to 18 V
0.8 V to 1.2 V
-40 °C to +85 °C
40 °C/W
Note:
2. The value of ΘJA is measured with the device mounted on a 1-in2
FR-4 board with 2 oz. Copper, in a still air environment with
TA = 25 °C. The value in any given application depends on the
user’s specific board design.
Note:
1. Devices are inherently ESD sensitive, handling precautions are
required. Human body model rating: 1.5 kΩ in series with 100 pF.
Rev. 1.2 September 2011
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Page 3 of 13
AOZ1039DI
Electrical Characteristics
TA = 25 °C, VIN = VEN = 12 V, VOUT = 1.1 V unless otherwise specified. Specifications in BOLD indicate a temperature range
of -40 °C to +85 °C.
Symbol
VIN
Parameter
Conditions
Supply Voltage
Min.
Typ.
4.5
Max
Units
18
V
VIN rising
4.1
V
VIN falling
3.7
V
Supply Current (Quiescent)
IOUT = 0, VFB = 1.2 V,
VEN > 2 V
1.6
2.5
mA
IOFF
Shutdown Supply Current
VEN = 0 V
1
10
μA
VFB
Feedback Voltage
TA = 25 °C
0.8
0.812
V
VUVLO
IIN
Input Under-voltage Lockout
Threshold
0.788
Load Regulation
0.1
%
Line Regulation
0.02
%/V
IFB
Feedback Voltage Input Current
VEN
EN Input Threshold
VHYS
EN Input Hysteresis
Off threshold
On threshold
200
nA
0.8
V
V
2
100
EN Leakage Current
mV
1
μA
500
kHz
MODULATOR
Frequency
400
DMAX
Maximum Duty Cycle
90
TMIN
Controllable Minimum On Time
fO
450
%
150
ns
Current Sense Transconductance
8.3
A/V
Error Amplifier Transconductance
200
μA / V
9
A
150
°C
PROTECTION
ILIM
Current Limit
8.5
Over-temperature Shutdown Limit
TJ rising
TJ falling
100
°C
Over-voltage Protection
Off threshold
0.96
V
Over-voltage Protection Hysteresis
100
mV
tD
Over-voltage Protection Delay
120
μs
tSS
Soft Start Time
VOVP
4.5
6
7.5
ms
OUTPUT STAGE
High-side Switch On-resistance
VIN = 12V
70
mΩ
Low-side Switch On-resistance
VIN = 12V
11
mΩ
Rev. 1.2 September 2011
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Page 4 of 13
AOZ1039DI
Typical Performance Characteristics
Circuit of Figure 1. TA = 25 °C, VIN = VEN = 12 V, VOUT = 1.1 V unless otherwise specified.
Light Load Operation
Full Load Operation
Vin
50mV/div
Vin
500mV/div
Vo
50mV/div
Vo
50mV/div
IL
5A/div
IL
2A/div
VLX
5V/div
VLX
5V/div
2µs/div
2µs/div
Startup to Full Load
Short Circuit Protection
Vcomp
2V/div
Vin
5V/div
Vo
500mV/div
Vo
500mV/div
IL
5A/div
Iin
500mA/div
VLX
5V/div
2ms/div
20ms/div
3A to 6A Load Transient
Short Circuity Recovery
Vcomp
2V/div
Vo
200mV/div
Vo
500mV/div
IL
5A/div
Io
2A/div
VLX
5V/div
100µs/div
Rev. 1.2 September 2011
20ms/div
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Page 5 of 13
AOZ1039DI
Efficiency
Efficiency (VIN = 12V) vs. Load Current
90
85
1.1V OUTPUT
Efficiency (%)
80
75
70
65
60
55
50
0
1
2
3
4
5
6
7
8
Load Current (A)
Detailed Description
The AOZ1039DI is a current-mode step down regulator
with an integrated high-side PMOS switch and a low-side
NMOS switch. The AOZ1039DI provides up to 8 A of
continuous output current with an output voltage
adjustable from 1.2 V to 0.8 V when the input power rail
is 12 V. For higher output voltage and/or lower input
voltage, the output current should be derated according
to thermal performance. Features include enable control,
power-on reset, input under voltage lockout, output over
voltage protection, fixed internal soft-start and thermal
shut down.
Enable and Soft Start
The AOZ1039DI has internal soft start feature to limit inrush current and ensure the output voltage ramps up
smoothly to regulation voltage. A soft start process
begins when the input voltage rises to 4.1 V and voltage
on the EN pin is HIGH
The EN pin of the AOZ1039DI is active high. Connect the
EN pin to VIN if enable function is not used. Pulling EN to
ground will disable the AOZ1039DI. Do not leave it open.
The voltage on the EN pin must be above 2 V to enable
the AOZ1039DI. When voltage on EN falls below 0.8 V,
the AOZ1039DI is disabled. If an application circuit
requires the AOZ1039DI to be disabled, an open drain or
open collector circuit should be used to interface to the
EN pin.
Rev. 1.2 September 2011
Steady-State Operation
Under heavy load steady-state conditions, the converter
operates in fixed frequency and Continuous-Conduction
Mode (CCM).
The AOZ1039DI integrates an internal P-MOSFET as the
high-side switch. Inductor current is sensed by amplifying
the voltage drop across the drain to source of the high
side power MOSFET. Output voltage is divided down by
the external voltage divider at the FB pin. The difference
of the FB pin voltage and reference voltage is amplified
by the internal transconductance error amplifier. The
error voltage, which shows on the COMP pin, is
compared against the current signal, which is the sum of
inductor current signal and ramp compensation signal, at
the PWM comparator input. If the current signal is less
than the error voltage, the internal high-side switch is on.
The inductor current flows from the input through the
inductor to the output. When the current signal exceeds
the error voltage, the high-side switch is off. The inductor
current is freewheeling through the internal
low-side N-MOSFET switch to output. The internal
adaptive FET driver guarantees no turn on overlap of
both the high-side and the low-side switch.
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Page 6 of 13
AOZ1039DI
Compared with regulators using freewheeling Schottky
diodes, the AOZ1039DI uses a freewheeling NMOSFET
to realize synchronous rectification. This greatly
improves the converter efficiency and reduces power
loss in the low-side switch.
The AOZ1039DI uses a P-Channel MOSFET as the
high-side switch. This saves the bootstrap capacitor
normally seen in a circuit using an NMOS switch.
Output Voltage Programming
Output voltage can be set by feeding back the output to
the FB pin by using a resistor divider network as shown
in Figure 1. The resistor divider network includes R1 and
R2. Usually, a design is started by picking a fixed R2
value and calculating the required R1 with equation
below:
R ⎞
⎛
V O = 0.8 × ⎜ 1 + ------1-⎟
R 2⎠
⎝
AOZ1039DID uses asymmetric Rdson of the high-side
PMOS and low-side NMOS to optimize high input and
the low output application. Maximum output current
should be derated if the output voltage is equal to or
higher than 1.5 V or if VIN is a 5 V power bus, based on
thermal performance.
Protection Features
The AOZ1039DI has multiple protection features to
prevent system circuit damage under abnormal
conditions.
Over Voltage Protection (OVP)
The AOZ1039DI has two over voltage protection
functions. First, once FB voltage is over 960 mV, the
AOZ1039DI turns off both the low-side and the
high-side MOSFETs to prevent either further output
overshoot or excessive negative current.
Over Current Protection (OCP)
The sensed inductor current signal is also used for over
current protection. Since the AOZ1039DI employs peak
current mode control, the COMP pin voltage is
proportional to the peak inductor current. The COMP pin
voltage is limited to be between 0.4 V and 2.5 V
internally. The peak inductor current is automatically
limited cycle by cycle.
When the output is shorted to ground under fault
conditions, the inductor current decays very slowly during
a switching cycle because the output voltage is 0 V.
To prevent catastrophic failure, a secondary current limit
Rev. 1.2 September 2011
is designed inside the AOZ1039DI. The measured
inductor current is compared against a preset voltage
which represents the current limit. When the output
current is more than current limit, the high side switch will
be turned off. The converter will initiate a soft start once
the over-current condition is resolved.
Under Voltage Lockout (UVLO)
A power-on reset circuit monitors the input voltage. When
the input voltage exceeds 4.1 V, the converter starts
operation. When input voltage falls below 3.7 V, the
converter will be shut down.
Thermal Protection
An internal temperature sensor monitors the junction
temperature. It shuts down the internal control circuit
and high side PMOS if the junction temperature exceeds
150 ºC. The regulator will restart automatically, under the
control of soft-start circuit, when the junction temperature
decreases to 100 ºC.
Application Information
The basic AOZ1039DI application circuit is show in
Figure 1. Component selection is explained below.
Input Capacitor
The input capacitor must be connected to the VIN pin
and the PGND pin of the AOZ1039DI to maintain steady
input voltage and filter out the pulsing input current. The
voltage rating of the input capacitor must be greater than
maximum input voltage plus ripple voltage.
The input ripple voltage can be approximated by
equation below:
IO
VO ⎞ VO
⎛
-⎟ × --------ΔV IN = ----------------- × ⎜ 1 – -------f × C IN ⎝
V IN⎠ V IN
Since the input current is discontinuous in a buck
converter, the current stress on the input capacitor is
another concern when selecting the capacitor. For a buck
circuit, the RMS value of the input capacitor current can
be calculated by:
VO ⎛
VO ⎞
- ⎜ 1 – -------I CIN_RMS = I O × --------⎟
V IN ⎝
V IN⎠
if we let m equal the conversion ratio:
VO
-------- = m
V IN
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AOZ1039DI
The relationship between the input capacitor RMS
current and voltage conversion ratio is calculated and
shown in Figure 2. It can be seen that when VO is half of
VIN, CIN is under the worst current stress. The worst
current stress on CIN is at 0.5 x IO.
0.5
reduces RMS current through the inductor and switches,
which results in less conduction loss. Usually, peak to
peak ripple current on the inductor is designed to be
20 % to 40 % of output current.
When selecting the inductor, make sure it is able to
handle the peak current without saturation even at the
highest operating temperature.
0.4
The inductor takes the highest current in a buck circuit.
The conduction loss on the inductor needs to be checked
for thermal and efficiency requirements.
ICIN_RMS(m) 0.3
IO
0.2
0.1
0
0
0.5
m
1
Output Capacitor
Figure 2. ICIN vs. Voltage Conversion Ratio
For reliable operation and best performance, the input
capacitors must have a current rating higher than
ICIN_RMS at the worst operating conditions. Ceramic
capacitors are preferred as input capacitors because of
their low ESR and high current rating. Depending on the
application circuits, other low ESR tantalum capacitor
may also be used. When selecting ceramic capacitors,
X5R or X7R type dielectric ceramic capacitors should be
used for their better temperature and voltage
characteristics. Note that the ripple current rating from
capacitor manufactures is based on a certain life time.
Further de-rating may need to be considered for long
term reliability.
Inductor
The inductor is used to supply constant current to output
when it is driven by a switching voltage. For given input
and output voltage, inductance and switching frequency
together decide the inductor ripple current, which is:
VO ⎛
VO ⎞
ΔI L = ----------- × ⎜ 1 – --------⎟
f×L ⎝
V ⎠
The output capacitor is selected based on the DC output
voltage rating, output ripple voltage specification and
ripple current rating.
The selected output capacitor must have a higher rated
voltage specification than the maximum desired output
voltage including ripple. De-rating needs to be
considered for long term reliability.
Output ripple voltage specification is another important
factor for selecting the output capacitor. In a buck
converter circuit, output ripple voltage is determined by
inductor value, switching frequency, output capacitor
value and ESR. It can be calculated by the equation
below:
1
ΔV O = ΔI L × ⎛ ESR CO + -------------------------⎞
⎝
8×f×C ⎠
O
where,
CO is output capacitor value, and
ESRCO is the equivalent series resistance of the output
capacitor.
IN
When a low ESR ceramic capacitor is used as the output
capacitor, the impedance of the capacitor at the switching
frequency dominates. Output ripple is mainly caused by
capacitor value and inductor ripple current. The output
ripple voltage calculation can be simplified to:
The peak inductor current is:
ΔI
I Lpeak = I O + -------L2
High inductance gives low inductor ripple current but
requires a larger size inductor to avoid saturation. Low
ripple current reduces inductor core losses. It also
Rev. 1.2 September 2011
Surface mount inductors in different shape and styles are
available from Coilcraft, Elytone and Murata. Shielded
inductors are small and radiate less EMI noise. However,
they cost more than unshielded inductors. The choice
depends on EMI requirement, price and size.
1
ΔV O = ΔI L × ------------------------8×f×C
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O
Page 8 of 13
AOZ1039DI
If the impedance of ESR at switching frequency
dominates, the output ripple voltage is mainly decided by
capacitor ESR and inductor ripple current. The output
ripple voltage calculation can be further simplified to:
ΔV O = ΔI L × ESR CO
For lower output ripple voltage across the entire
operating temperature range, X5R or X7R dielectric type
of ceramic, or other low ESR tantalum capacitors are
recommended as output capacitors.
In a buck converter, output capacitor current is
continuous. The RMS current of output capacitor is
decided by the peak to peak inductor ripple current.
It can be calculated by:
ΔI L
I CO_RMS = ---------12
used for the AOZ1039DI. For most cases, a series
capacitor and resistor network connected to the COMP
pin sets the pole-zero and is adequate for a stable highbandwidth control loop.
In the AOZ1039DI, FB pin and COMP pin are the
inverting input and the output of internal error amplifier.
A series R and C compensation network connected to
COMP provides one pole and one zero. The pole is:
G EA
f P2 = -----------------------------------------2π × C C × G VEA
where;
GEA is the error amplifier transconductance, which is 200 x 10-8
/V,
A
GVEA is the error amplifier voltage gain, which is 500 V/V, and
CC is the compensation capacitor in Figure 1.
Usually, the ripple current rating of the output capacitor is
a smaller issue because of the low current stress. When
the buck inductor is selected to be very small and
inductor ripple current is high, the output capacitor could
be overstressed.
Loop Compensation
The AOZ1039DI employs peak current mode control for
easy of use and fast transient response. Peak current
mode control eliminates the double pole effect of the
output L&C filter. It also greatly simplifies the
compensation loop design.
With peak current mode control, the buck power stage
can be simplified to be a one-pole and one-zero system
in the frequency domain. The pole is dominant pole can
be calculated by:
1
f P1 = ----------------------------------2π × C O × R L
The zero is a ESR zero due to the output capacitor and
its ESR. It is can be calculated by:
The zero given by the external compensation network,
capacitor CC and resistor RC, is located at:
1
f Z2 = ----------------------------------2π × C C × R C
To design the compensation circuit, a target crossover
frequency fC for close loop must be selected. The system
crossover frequency is where control loop has unity gain.
The crossover is the also called the converter bandwidth.
Generally a higher bandwidth means faster response to
load transient. However, the bandwidth should not be too
high because of system stability concerns. When
designing the compensation loop, converter stability
under all line and load condition must be considered.
Usually, it is recommended to set the bandwidth to be
equal or less than 1/10 of switching frequency.
The strategy for choosing RC and CC is to set the cross
over frequency with RC and set the compensator zero
with CC. Using selected crossover frequency, fC, to
calculate RC:
VO
2π × C C
R C = f C × ---------- × ----------------------------G ×G
V
1
f Z1 = -----------------------------------------------2π × C O × ESR CO
FB
EA
CS
where;
where;
CO is the output filter capacitor,
RL is load resistor value, and
fC is the desired crossover frequency. For best performance,
fC is set to be about 1/10 of the switching frequency;
ESRCO is the equivalent series resistance of output capacitor.
VFB is 0.8V,
The compensation design shapes the converter control
loop transfer function to get desired gain and phase.
Several different types of compensation network can be
Rev. 1.2 September 2011
GEA is the error amplifier transconductance, which is
200 x 10-8 A/V, and
GCS is the current sense circuit transconductance, which is
8.3 A/V
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Page 9 of 13
AOZ1039DI
The compensation capacitor CC and resistor RC together
make a zero. This zero is put somewhere close to the
dominate pole fp1 but lower than 1/5 of the selected
crossover frequency. CC can is selected by:
1.5
C C = ----------------------------------2π × R C × f P1
The actual junction temperature can be calculated by the
power dissipation of the AOZ1039DI and the thermal
impedance from junction to ambient:
T junction = ( P total_loss – P inductor_loss ) × Θ JA
The maximum junction temperature of the AOZ1039DI is
150 ºC, which limits the maximum load current capability.
The above equation can be simplified to:
The thermal performance of the AOZ1039DI is strongly
affected by the PCB layout. Care should be taken by
during the design process to ensure that the IC will
operate under the recommended environmental
conditions.
CO × RL
C C = --------------------RC
An easy-to-use application software which helps to
design and simulate the compensation loop can be found
at www.aosmd.com.
Thermal Management and Layout
Considerations
In the AOZ1039DI buck regulator circuit, high pulsing
current flows through two circuit loops. The first loop
starts from the input capacitors, to the VIN pin, to the LX
pad, to the filter inductor, to the output capacitor and
load, and then returns to the input capacitor through
ground. Current flows in the first loop when the high side
switch is on. The second loop starts from the inductor,
to the output capacitors and load, to the low side
NMOSFET. Current flows in the second loop when the
low side NMOSFET is on.
In PCB layout, minimizing the two area of the two loops
reduces the noise of the circuit and improves efficiency.
A ground plane is strongly recommended to connect the
input capacitor, the output capacitor, and the PGND pin
of the AOZ1039DI.
In the AOZ1039DI buck regulator circuit, the major power
dissipating components are the AOZ1039DI and the
output inductor. The total power dissipation of the
converter circuit can be measured as input power minus
output power:
The AOZ1039DI is a DFN 5x6 package. Several layout
tips are listed below for the best electric and thermal
performance.
1. The exposed pad (LX) is connected to the internal
PFET and NFET drains. Connected a large copper
plane to the LX pad for thermal dissipation.
2. Do not use thermal relief connection to the VIN pin
and the PGND pin. Pour a maximized copper area to
the PGND pin and the VIN pin to help thermal
dissipation.
3. The input capacitor should be connected as close as
possible to the VIN pin and the PGND pin.
4. A ground plane is preferred. If a ground plane is not
used, separate PGND from AGND and connect
them only at one point to avoid the PGND pin noise
coupling to the AGND pin.
5. Make the current trace from LX pad to L to Co to the
PGND as short as possible.
6. Pour copper plane on all unused board area and
connect to stable DC nodes, like VIN, GND or VOUT.
7. Keep sensitive signal trace away from the LX pad.
P total_loss = V IN × I IN – V O × I O
The power dissipation of the inductor can be
approximately calculated by the output current and DCR
value of the inductor:
P inductor_loss = IO2 × R inductor × 1.1
Rev. 1.2 September 2011
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Page 10 of 13
AOZ1039DI
Package Dimensions, 5x6 DFN, 8L
D2
e
b
L
θ
L2
(ALL)
L1
E
L3
E4
E1
E3
L4
E2
D3
A1
D
c
A
Dimensions in millimeters
RECOMMENDED LAND PATTERN
4.450
0.770
0.500
2.305
0.745
3.280
0.650
0.775
0.675
Symbols Min.
A
0.85
A1
0.00
0.35
b
c
0.15
D
D2
4.20
D3
1.23
E
E1
E2
0.72
E3
0.85
E4
3.00
e
L
0.47
L1
0
L2
1.375
L3
0.20
1.30
L4
0°
θ
Nom.
0.90
−−−
0.40
0.20
5.20 BSC
4.35
1.38
5.55 BSC
6.05 BSC
0.875
0.975
3.15
1.27 BSC
0.575
--1.475
0.30
1.40
---
Max
1.00
0.05
0.45
0.25
4.50
1.53
1.03
1.10
3.30
0.68
0.10
1.575
0.40
1.50
10 °
Dimensions in inches
Symbols
A
A1
b
c
D
D
D3
E
E1
E2
E
E
e
L
L1
L2
L3
L4
θ
Min.
0.033
0.000
0.014
0.006
Nom.
0.035
−−−
0.016
0.008
0.205 BSC
0.167
0.171
0.054
0.048
0.219 BSC
0.238 BSC
0.034
0.028
0.038
0.033
0.124
0.118
0.050 BSC
0.023
0.019
0
--0.058
0.054
0.008
0.012
0.051 0.055
0°
---
Max
0.039
0.002
0.018
0.010
0.175
0.060
0.041
0.043
0.130
0.027
0.004
0.062
0.016
0.059
10 °
0.635
0.500
1.270
1.430
Notes:
1. Package body sizes exclude mold flash and gate burrs. Mold flash at the non-lead sides should be less than 6 mils each.
2. Controlling dimension is millimeter. Converted inch dimensions are not necessarily exact.
Rev. 1.2 September 2011
www.aosmd.com
Page 11 of 13
AOZ1039DI
Tape and Reel Dimensions, 5x6 DFN, 8L
Carrier Tape
P1
D1
T
P2
Y
E1
E2
E
C
L
B0
Y
K0
D0
P0
A0
Feeding Direction
UNIT: MM
Package
A0
B0
K0
D0
D1
DFN 5x6
(12mm)
6.30
±0.10
5.45
±0.10
1.30
±0.10
1.50
Min.
1.55
±0.05
Reel
E
E1
12.00 1.75
±0.30 ±0.10
E2
P0
P1
P2
T
5.50
±0.10
8.00
±0.10
4.00
±0.10
2.00
±0.10
0.30
±0.05
W1
S
G
N
M
K
V
R
H
W
UNIT: MM
Tape Size
Reel Size
12 mm
ø330
M
N
ø330.0 ø97.00
±0.50
±0.10
W
W1
H
K
S
G
R
V
13.00
±0.30
17.40
±1.00
ø13.0
+0.50/-0.20
10.60
2.0
±0.5
—
—
—
Leader/Trailer and Orientation
Trailer Tape
300mm min. or
75 empty pockets
Rev. 1.2 September 2011
Components Tape
Orientation in Pocket
www.aosmd.com
Leader Tape
500mm min. or
125 empty pockets
Page 12 of 13
AOZ1039DI
Part Marking
5x6 DFN-8
Z1039DI
FAYWLT
Part Number Code
Assembly Lot Code
Fab & Assembly Location
Year & Week Code
This datasheet contains preliminary data; supplementary data may be published at a later date.
Alpha & Omega Semiconductor reserves the right to make changes at any time without notice.
LIFE SUPPORT POLICY
ALPHA & OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL
COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body or (b) support or sustain life, and (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of
the user.
Rev. 1.2 September 2011
2. A critical component in any component of a life
support, device, or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
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Page 13 of 13