AD ADATE305 250 mhz dual integrated dcl with level setting dacs, per pin pmu, and per chip vhh Datasheet

250 MHz Dual Integrated DCL with Level
Setting DACs, Per Pin PMU, and Per Chip VHH
ADATE305
FEATURES
GENERAL DESCRIPTION
Driver
3-level driver with high-Z mode and built-in clamps
Precision trimmed output resistance
Low leakage mode (typically <10 nA)
Voltage range: up to −2.0 V to +6.0 V
1.6 ns minimum pulse width, 2 V terminated
2.1 ns minimum pulse width, 3 V terminated
Comparator
Window and differential comparator
500 MHz input equivalent bandwidth
Load
±12 mA maximum current capability
Per pin PMU
Force voltage range: up to −2.0 V to +6.0 V
5 current ranges: 32 mA, 2 mA, 200 μA, 20 μA, 2 μA
Levels
14-bit DAC for DCL levels
Typically < ±5 mV INL (calibrated)
16-bit DAC for PMU levels
Typically < ±1.5 mV INL (calibrated) linearity in FV mode
HVOUT output buffer
0 V to 13.5 V output range
100-lead, 14 mm × 14 mm, TQFP_EP package
900 mW per channel with no load
The ADATE305 is a complete, single-chip solution that performs
the pin electronic functions of the driver, the comparator, and
the active load (DCL), per pin PMU, and dc levels for ATE applications. The device also contains an HVOUT driver with a VHH
buffer capable of generating up to 13.5 V.
APPLICATIONS
The driver features three active states: data high mode, data low
mode, and term mode, as well as an inhibit state. The inhibit
state, in conjunction with the integrated dynamic clamp, facilitates the implementation of a high speed active termination.
The ADATE305 supports two output voltage ranges: −2.0 V
to +6.0 V and −1.5 V to +6.0 V by adjusting the positive and
negative supply voltages.
The ADATE305 can be used as either a dual single-ended drive/
receive channel or a single differential drive/receive channel.
Each channel of the ADATE305 features a high speed window
comparator per pin for functional testing, as well as a per pin
PMU with FV, or FI and MV, or MI functions. All necessary dc
levels for DCL functions are generated by on-chip 14-bit DACs.
The per pin PMU features an on-chip 16-bit DAC for high
accuracy and contains integrated range resistors to minimize
external component counts.
The ADATE305 uses a serial bus to program all functional blocks
and has an on-board temperature sensor for monitoring the
device temperature.
Automatic test equipment
Semiconductor test systems
Board test systems
Instrumentation and characterization equipment
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2008 Analog Devices, Inc. All rights reserved.
ADATE305
TABLE OF CONTENTS
Features .............................................................................................. 1
Absolute Maximum Ratings ......................................................... 19
Applications ....................................................................................... 1
Thermal Resistance .................................................................... 19
General Description ......................................................................... 1
Explanation of Test Levels ......................................................... 19
Revision History ............................................................................... 2
ESD Caution................................................................................ 19
Functional Block Diagram .............................................................. 3
Pin Configuration and Function Descriptions........................... 20
Specifications..................................................................................... 4
Typical Performance Characteristics ........................................... 23
Total Function ............................................................................... 4
SPI Details ....................................................................................... 34
Driver ............................................................................................. 5
Definition of SPI Word .............................................................. 35
Reflection Clamp .......................................................................... 7
Write Operation.......................................................................... 36
Normal Window Comparator .................................................... 7
Read Operation........................................................................... 37
Differential Comparator .............................................................. 9
Reset Operation .......................................................................... 38
Active Load.................................................................................. 11
Register Map ................................................................................... 39
PMU ............................................................................................. 12
Details of Registers ......................................................................... 40
External Sense (PMUS_CHx)................................................... 16
User Information ............................................................................ 42
DUTGND Input ......................................................................... 16
Details of DACs vs. Levels ......................................................... 43
Serial Peripheral Interface ......................................................... 17
Recommended PMU Mode Switching Sequences................. 46
HVOUT Driver ........................................................................... 17
Block Diagrams............................................................................... 49
Overvoltage Detector (OVD) ................................................... 18
Outline Dimensions ....................................................................... 53
16-Bit DAC Monitor MUX ....................................................... 18
Ordering Guide .......................................................................... 53
REVISION HISTORY
8/08—Revision 0: Initial Version
Rev. 0 | Page 2 of 56
ADATE305
FUNCTIONAL BLOCK DIAGRAM
CH1
*
PMU
MUX
MUX
VCLAMPH
*
MUX
MEASOUT01
CH1
OVD
VCLAMPL
DAC16_MON
PMU_FLAG
16-BIT DAC
OVD_CH0
VCLAMPL
FORCE
VCLAMPH
VH
VT
VL
SENSE
PMUS_CH0
ROUT
(TRIMMED)
DATA0P
100Ω
DRV
DUT0
DATA0N
*
RCV0P
100Ω
WINDOW
DIFF.
C
RCV0N
OTHER CHANNEL
DUT1
*
COMP_VTT0
VHH
HVOUT
50Ω
COMP_QH0P
C
VOH
C
VOL
COMP_QH0N
COMP_QL0P
COMP_QL0N
*
G
IOL
ADATE305
SDIN
RST
*
SCLK
SPI
CS
VCOM
14-BIT DAC
IOH
TEMPERATURE
SENSOR
*
TEMPSENSE
07280-001
SDOUT
*ONE PER DEVICE.
Figure 1. One of Two Channels Is Shown
Rev. 0 | Page 3 of 56
ADATE305
SPECIFICATIONS
Characterization and production tests performed using Power Supply Range 1 (see Table 36). VDD = +10.0 V, VCC = +3.3 V, VSS = −5.25 V,
VPLUS = +16.75 V, VCOMP_VTT = +3.3 V, VREF = +5.0 V, VREF_GND = 0.0 V. All default test conditions are as defined in Table 38. All specified
values are at TJ = 70°C, where TJ corresponds to the internal temperature sensor, unless otherwise noted. Temperature coefficients are
measured at TJ = 70°C ± 20°C, unless otherwise noted. Typical values are based on design, simulation analyses, and/or limited bench
evaluations. Typical values are not tested or guaranteed. Test levels are specified in the Explanation of Test Levels section.
TOTAL FUNCTION
Table 1.
Parameter
TOTAL FUNCTION
Output Leakage Current
PE Disable Range E
Min
Typ
Max
Unit
Test
Level
−20.0
5.3
+20.0
nA
P
nA
CT
+400
nA
P
+6.0
pF
V
S
D
V
V
V
V
V
V
mA
mA
mA
mA
D
D
D
D
D
D
P
P
P
P
Defines PSRR conditions
Defines PSRR conditions
Defines PSRR conditions
Defines PSRR conditions
Defines PSRR conditions
+1.3
12.7
2.7
17
23.25
17.25
10.5
−5.00
3.5
5.0
+3.0
17.0
10.0
26.0
92
119
1.7
133
158
2.2
105
135
1.9
154
183
2.5
mA
mA
W
mA
mA
W
P
P
P
P
P
P
Load power down (IOH = IOL = 0 mA)
Load power down (IOH = IOL = 0 mA)
Load power down (IOH = IOL = 0 mA)
Load active off (IOH = IOL = 12 mA)
Load active off (IOH = IOL = 12 mA)
Load active off (IOH = IOL = 12 mA)
mV/K
°C
CT
CT
PE Disable Range A, B, C, D
High-Z Mode
Output Capacitance
DUT Pin Range
POWER SUPPLIES
Total Supply Range, VPLUS to VSS
VPLUS Supply, VPLUS
Positive Supply, VDD
Negative Supply, VSS
Logic Supply, VCC
Comparator Termination, VCOMP_VTT
VPLUS Supply Current, IPLUS
VPLUS Supply Current, IPLUS
Logic Supply Current, ICC
Comparator Termination Current,
ICOMP_VTT
Positive Supply Current, IDD
Negative Supply Current, ISS
Total Power Dissipation
Positive Supply Current, IDD
Negative Supply Current, ISS
Total Power Dissipation
TEMPERATURE MONITORS
Temperature Sensor Gain
Temperature Sensor Accuracy
Without Calibration over
25°C to 100°C
VREF INPUT
Reference Input Voltage Range for
DACs (VREF Pin)
Input Bias Current
5.3
−400
5.4
4
−1.5
16.25
9.5
−5.50
3.1
3.3
−1.0
4.0
1.0
10.0
72
100
1.0
102
130
1.8
22.5
16.75
10.0
−5.25
3.3
10
6
4.95
Conditions/Comments
−1.5 V < VDUTx < +6.0 V; PMU and PE disabled via SPI; PMU
Range E, VCH = 7.0 V, VCL = −2.5 V
−1.5 V < VDUTx < +6.0 V; PMU and PE disabled via SPI; PMU
Range A, PMU Range B, PMU Range C, and PMU Range D,
VCH = +7.0 V, VCL = −2.5 V
−1.5 V < VDUTx < +6.0 V; PMU disabled and PE enabled via SPI;
RCV active, VCH = +7.0 V, VCL = −2.5 V
VTERM mode operation
HVOUT disabled
HVOUT enabled, RCV active, no load, VHH = 12 V
Quiescent (SPI is static)
Temperature voltage available on Pin 3 at all times and Pin 28
when selected (see Table 24 and Table 36)
5
5.05
V
D
Referenced to VREF_GND; not referenced to VDUTGND
0.1
100
μA
P
Tested with 5 V applied
Rev. 0 | Page 4 of 56
ADATE305
DRIVER
VH − VL ≥ 200 mV (to meet dc/ac specifications).
Table 2.
Parameter
DC SPECIFICATIONS
High-Speed Differential Logic
Input Characteristics (DATA, RCV)
Input Termination Resistance
Input Voltage Differential
Common-Mode Voltage
Input Bias Current
Pin Output Characteristics
Output High Range, VH
Output Low Range, VL
Output Term Range, VT
Functional Amplitude (VH − VL)
DC Output Current Limit
Source
DC Output Current Limit Sink
Output Resistance, ±50 mA
Min
Typ
Max
Unit
Test
Level
92
100
108
Ω
P
+2.2
1.0
2.35
+20.0
V
V
μA
PF
PF
P
+6.0
+5.9
+6.0
V
V
V
V
D
D
D
D
0.2
0.85
−20.0
−1.4
−1.5
−1.5
0.0
7.5
75
100
120
mA
P
−120
45.0
−100
47.0
−75
49.0
mA
Ω
P
P
−250
±75
±450
±1
±2.5
+250
+10
mV
μV/°C
mV
mV
P
CT
CT
P
0.6
+1
mV
PF
±1.3
+7
mV
P
Conditions/Comments
Push 6 mA into xP pins, force 1.3 V on xN pins; measure voltage
from xP to xN, calculate resistance (ΔV/ΔI) 1
Each pin tested at 2.85 V and 0.35 V, while the other high speed
pin remains open
Amplitude can be programmed to VH = VL, accuracy specs
apply when VH − VL ≥ 200 mV
Driver high, VH = 6.0 V, short DUTx pin to −2.0 V, measure current
VH, VL, VT Crosstalk
±2
mV
CT
Overall Voltage Accuracy
±10
mV
CT
VH, VL, VT DC PSRR
AC SPECIFICATIONS
Rise/Fall Times
0.2 V Programmed Swing
1.0 V Programmed Swing
2.0 V Programmed Swing
3.0 V Programmed Swing
3.0 V Programmed Swing
5.0 V Programmed Swing
Rise to Fall Matching
±15
mV/V
CT
Driver low, VL = −1.5 V, short DUTx pin to 6.0 V, measure current
Source: driver high, VH = 3.0 V, IDUTx = 1 mA and 50 mA;
sink: driver low, VL = 0.0 V, IDUTx = −1 mA and −50 mA; ΔVDUT/ΔIDUT
VH tests done with VL = −2.5 V and VT= −2.5 V;
VL tests done with VH = 7.5 V and VT = 7.5 V;
VT tests done with VL = −2.5 V and VH = +7.5 V; unless otherwise
specified
Error measured at calibration points of 0 V and 5 V
Measured at calibration points
After two-point gain/offset calibration
After two-point gain/offset calibration; measured over driver
output ranges
After two-point gain/offset calibration; range/number of DAC
bits as measured at calibration points of 0 V and 5 V
Over ±0.1 V range; measured at end points of VH, VL, and VT
functional range
VL = −1.5 V: VH = −1.4 V → 6.0 V, VT = −1.5 V → 6.0 V;
VH = 6.0 V: VL = −1.5 V → 5.9 V, VT = −1.5 V → 6.0 V;
VT = 1.5 V: VL = −1.5 V → 5.9 V, VH = −1.4 V → 6.0 V; dc crosstalk
on VL, VH, VT output level when other driver DACs are varied
Sum of INL, crosstalk, DUTGND, and tempco over ±5°C, after
gain/offset calibration
Measured at calibration points
1000
800
950
1175
1650
2350
30
ps
ps
ps
ps
ps
ps
ps
CB
CB
CB
P/CB
CB
CB
CB
Toggle DATAxx
VH = 0.2 V, VL = 0.0 V, terminated; 20% to 80%
VH = 1.0 V, VL = 0.0 V, terminated; 20% to 80%
VH = 2.0 V, VL = 0.0 V, terminated; 20% to 80%
VH = 3.0 V, VL = 0.0 V, terminated; 20% to 80%
VH = 3.0 V, VL = 0.0 V, unterminated; 10% to 90%
VH = 5.0V, VL = 0.0 V, unterminated; 10% to 90%
VH = 3.0 V, VL = 0.0 V, terminated; rise to fall within one channel
ABSOLUTE ACCURACY
VH, VL, VT Uncalibrated Accuracy
VH, VL, VT Offset Tempco
VH, VL, VT DNL
VH, VL, VT INL
−10
VH, VL, VT Resolution
DUTGND Voltage Accuracy
−7
1000
1500
Rev. 0 | Page 5 of 56
ADATE305
Unit
Test
Level
1.4
1.6
ns
ns
CB
CB
2.0 V Programmed Swing
1.6
1.8
ns
ns
CB
CB
3.0 V Programmed Swing
2.1
2.3
ns
ns
CB
CB
250
200
MHz
MHz
CB
CB
VH = 2.0 V, VH = 0.0 V, terminated, 10% amplitude degradation
VH = 3.0 V, VH = 0.0 V, terminated, 10% amplitude degradation
Toggle DATAxx
3.0
3.0
ns
ps/°C
CB
CT
115
30
30
20
ps
ps
ps
mV
CB
CB
CB
CB
5
35
ns
ns
CB
CB
VH = 3.0 V, VL = 0.0 V, terminated
VH = 3.0 V, VL = 0.0 V, terminated
VH = 3.0 V, VL = 0.0 V, terminated
Rising vs. falling
Rising vs. rising, falling vs. falling
VH = 3.0 V, VL = 0.0 V, terminated; 5% to 95% duty cycle; 1 MHz
VH = 3.0 V, VL = 0.0 V, terminated
Toggle DATAxx
VH = 3.0 V, VL = 0.0 V, terminated
VH = 3.0 V, VL = 0.0 V, terminated
Toggle RCVx
3.3
100
4.0
0.85
ns
ps
ps/°C
ns
CB
CB
CT
CB
Parameter
Minimum Pulse Width
1.0 V Programmed Swing
Maximum Toggle Rate
2.0 V Programmed Swing
3.0 V Programmed Swing
Dynamic Performance, Drive
(VH to VL and VL to VH)
Propagation Delay Time
Propagation Delay Tempco
Delay Matching
Edge to Edge
Channel to Channel
Delay Change vs. Duty Cycle
Overshoot and Undershoot
Settling Time (VH to VL)
To Within 3% of Final Value
To Within 1% of Final Value
Dynamic Performance, VT
(VH or VL to VT and VT to VH
or VL)
Propagation Delay Time
Delay Matching, Edge to Edge
Propagation Delay Tempco
Transition Time, Active to VT
and VT to Active
Dynamic Performance,
Inhibit (VH or VL to/from
Inhibit)
Propagation Delay Time
Active to Inhibit
Inhibit to Active
Transition Time
Active to Inhibit
Inhibit to Active
I/O Spike
1
Min
Typ
Max
Conditions/Comments
Toggle DATAxx
VH = 1.0 V, VL = 0.0 V, terminated; timing error ±75 ps
VH = 1.0 V, VL = 0.0 V, terminated; less than 10% amplitude
degradation
VH = 2.0 V, VL = 0.0 V, terminated; timing error ±75 ps
VH = 2.0 V, VL = 0.0 V, terminated; less than 10% amplitude
degradation
VH = 3.0 V, VL = 0.0 V, terminated; timing error ±75 ps
VH = 3.0 V, VL = 0.0 V, terminated; less than 10% amplitude
degradation
VH = 3.0 V, VT = 1.5 V, VL = 0.0 V, terminated
VH = 3.0 V, VT = 1.5 V, VL = 0.0 V, terminated; rising vs. falling
VH = 3.0 V, VT = 1.5 V, VL = 0.0 V, terminated
VH = 3.0 V, VT = 1.5 V, VL = 0.0 V, terminated; 20% to 80%
Toggle RCVx
VH = +1.0 V, VL = −1.0 V, terminated
4.5
6.9
ns
ns
CB
CB
2.6
0.75
190
ns
ns
mV
CB
CB
CB
VH =+1.0 V, VL = −1.0 V, terminated; 20% to 80%
VH = 0.0 V, VL = 0.0 V, terminated
The xP pins include DATA0P, DATA1P, RCV0P, and RCV1P; the xN pins include DATA0N, DATA1N, RCV0N, and RCV1N. For example, push 6 mA into the DATA0P pin,
force 1.3 V into DATA0N, and measure the voltage from DATA0P to DATA0N.
Rev. 0 | Page 6 of 56
ADATE305
REFLECTION CLAMP
Clamp accuracy specifications apply when VCH > VCL.
Table 3.
Min
Typ
Max
Unit
Test
Level
−1.0
−200
±50
+6.0
+200
V
mV
D
P
Resolution
0.6
0.75
mV
PF
DNL
±1
mV
CT
mV
P
mV/°C
CT
Parameter
VCH
Range
Uncalibrated Accuracy
INL
−40
Tempco
VCL
Range
Uncalibrated Accuracy
±2
+40
−0.3
−1.5
−200
±50
+5.0
+200
V
mV
D
P
Resolution
0.6
0.75
mV
PF
DNL
±1
mV
CT
mV
P
mV/°C
CT
mA
mA
mV
P
P
P
INL
−40
Tempco
DC CLAMP CURRENT LIMIT
VCH
VCL
DUTGND VOLTAGE ACCURACY
±2
+40
0.5
−120
60
−7
−85
85
±1
−60
120
+7
Conditions/Comments
Driver high-Z, sinking 1 mA; VCH error measured at the
calibration points of 0.0 V and 5.0 V
Driver high-Z, sinking 1 mA; after two-point gain/offset
calibration; range/number of DAC bits as measured at
the calibration points of 0.0 V and 5.0 V
Driver high-Z, sinking 1 mA; after two-point gain/offset
calibration
Driver high-Z, sinking 1 mA; after two-point gain/offset
calibration; measured over VCH range of −1.0 V to +6.0 V
Measured at calibration points
Driver high-Z, sourcing 1 mA; VCL error measured at the
calibration points of 0.0 V and 5.0 V
Driver high-Z, sourcing 1 mA; after two-point gain/offset
calibration; range/number of DAC bits as measured at
the calibration points of 0.0 V and 5.0 V
Driver high-Z, sourcing 1 mA; after two-point gain/offset
calibration
Driver high-Z, sourcing 1 mA; after two-point gain/offset
calibration; measured over VCL range of −1.5 V to +5 V
Measured at calibration points
Driver high-Z, VCH = 0 V, VCL = −1.5 V, VDUTx = +5 V
Driver high-Z, VCH = 6.0 V, VCL = 5.0 V, VDUTx = 0.0 V
Over ±0.1 V range; measured at the end points of VCH
and VCL functional range
NORMAL WINDOW COMPARATOR
VOH tests done with VOL = −1.5 V; VOL tests done with VOH = 6.0 V, unless otherwise specified.
Table 4.
Parameter
DC SPECIFICATIONS
Input Voltage Range
Differential Voltage Range
Comparator Input Offset Voltage Accuracy, Uncalibrated
Comparator Threshold
Resolution
Comparator Threshold DNL
Comparator Threshold INL
Comparator Input Offset
Voltage Tempco
DUTGND Voltage Accuracy
Min
−1.5
±0.1
−150
−7
Typ
Max
Unit
Test
Level
±30
+6.0
±7.5
+150
V
V
mV
D
D
P
0.6
1
mV
PF
±1
±1.3
+7
mV
mV
CT
P
μV/°C
CT
mV
P
±100
−7
±0.5
+7
Rev. 0 | Page 7 of 56
Conditions/Comments
Offset measured at the calibration
points of 0.0 V and 5.0 V
After two-point gain/offset calibration;
range/number of DAC bits as measured
at the calibration points of 0 V and 5 V
After two-point gain/offset calibration
After two-point gain/offset calibration;
measured over VOH, VOL range of
−1.5 V to +6.0 V
Measured at calibration points
Over ±0.1 V range; measured at end
points of VOH and VOL functional range
ADATE305
Parameter
Comparator Uncertainty Range
DC Hysteresis
DC PSRR
Digital Output Characteristics
Internal Pull-Up Resistance
to Comparator, COMP_VTT
Pin
VCOMP_VTT Range
Common-Mode Voltage
Min
Typ
6.0
Test
Level
CB
mV
mV/V
CB
CT
60
Ω
P
5.0
V
V
D
CT
VCOMP_VTT − 1.675
V
mV
P
CT
600
mV
ps
P
CB
0.5
±5
40
50
3.3
VCOMP_VTT − 1.88
VCOMP_VTT − 2.075
Differential Voltage
250
400
Rise/Fall Time, 20% to 80%
Unit
mV
Max
500
450
AC SPECIFICATIONS
Propagation Delay, Input to
Output
1.75
ns
CB
Propagation Delay Tempco
5
ps/°C
CT
200
ps
CB
50
ps
CB
50
ps
CB
Overdrive, 250 mV and 1.5 V
75
ps
CB
Pulse Width, Sweep 1.6 ns to
10 ns
75
ps
CB
Propagation Delay Matching
High Transition to Low
Transition
High to Low Comparator
Propagation Delay Change
(with Respect To)
Slew Rate, 800 ps, 1 ns, 1.2 ns,
and 2.2 ns (10% to 90%)
Rev. 0 | Page 8 of 56
Conditions/Comments
VDUTx = 0 V, sweep comparator
threshold to determine uncertainty
region
VDUTx = 0 V
Measured at calibration points
Pull 1 mA and 10 mA from Logic 1 leg
and measure ΔV to calculate resistance; measured ΔV/9 mA; done for
both comparator logic states
Measured with 100 Ω differential
termination
Measured with no external termination
Measured with 100 Ω differential
termination
Measured with no external termination
Measured with each comparator leg
terminated 50 Ω to GND
Input transition time = 800 ps, 10% to
90%; measured with each comparator
leg terminated 50 Ω to GND; unless
otherwise specified
VDUTx = 0 V to 1.5 V swing, Driver
VTERM mode, VT = 0.0 V; high-side
measurement: VOH = 0.75 V, VOL =
−1.5 V; low-side measurement: VOH =
6.0 V, VOL = 0.75 V
VDUTx = 0 V to 1.5 V swing, Driver
VTERM mode, VT = 0.0 V; high-side
measurement: VOH = 0.75 V, VOL =
−1.5 V; low-side measurement: VOH =
6.0 V, VOL = 0.75 V
VDUTx = 0 V to 1.5 V swing, Driver
VTERM mode, VT = 0.0 V; high-side
measurement: VOH = 0.75 V, VOL =
−1.5 V; low-side measurement: VOH =
6.0 V, VOL = 0.75 V
VDUTx = 0 V to 1.5 V swing, Driver
VTERM mode, VT = 0.0 V; high-side
measurement: VOH = 0.75 V, VOL =
−1.5 V; low-side measurement: VOH =
6.0 V, VOL = 0.75 V
For 250 mV: VDUTx = 0 V to 0.5 V swing;
for 1.5 V: VDUTx = 0 V to 1.75 V swing;
Driver VTERM mode, VT = 0.0 V; highside measurement: VOH = 0.25 V,
VOL = −1.5 V; low-side measurement:
VOH = 6.0 V, VOL = 0.25 V
VDUTx = 0 V to 1.5 V swing @ 32.0 MHz,
Driver VTERM mode, VT = 0.0 V; highside measurement: VOH = 0.5 V, VOL =
−1.5 V; low-side measurement: VOH =
6.0 V, VOL = 0.5 V
ADATE305
Parameter
Duty Cycle, 5% to 95%
Min
Typ
50
Max
Unit
ps
Test
Level
CB
Minimum Pulse Width
2.0
ns
CB
Input Equivalent Bandwidth,
Terminated
500
MHz
CB
ERT High-Z Mode, 3 V, 20%
to 80%
2.5
ns
CB
Conditions/Comments
VDUTx = 0 V to 1.5 V swing @ 1.0 MHz,
Driver VTERM mode, VT =0.0 V; highside measurement: VOH = 0.75 V, VOL =
−1.5 V; low-side measurement: VOH =
6.0 V, VOL = 0.75 V
VDUTx = 0 V to 1.5 V swing, Driver
VTERM mode, VT = 0.0 V; less than
12% amplitude degradation measured
by shmoo
VDUTx = 0 V to 1.5 V swing, Driver
VTERM mode, VT = 0.0 V; as measured
by shmoo
VDUTx = 0 V to 3.0 V swing, driver high-Z;
as measured by shmoo; input transition
time of ~2000 ps, 10% to 90%
DIFFERENTIAL COMPARATOR
VOH tests done with VOL = −1.1 V, VOL tests done with VOH = +1.1 V, unless otherwise specified.
Table 5.
Parameter
DC SPECIFICATIONS
Input Voltage Range
Operational Differential Voltage
Range
Maximum Differential Voltage Range
Comparator Input Offset Voltage
Accuracy, Uncalibrated
VOH, VOL Resolution
Min
Unit
Test
Level
+4.5
±1.1
V
V
D
D
±35
±8
+150
V
mV
D
P/CT
0.6
1
mV
PF
mV
CT
mV
P
μV/°C
mV
CT
CB
mV
mV/V
CB
P
−1.25
±0.05
−150
VOH, VOL DNL
VOH, VOL INL
Max
Typ
±1
−15
±2.0
+15
VOH, VOL Offset Voltage Tempco
Comparator Uncertainty Range
±200
18
DC Hysteresis
CMRR
0.5
0.15
DC PSRR
AC SPECIFICATIONS
±1.5
mV/V
CT
Propagation Delay, Input to Output
1.7
ns
CB
Propagation Delay Tempco
5
ps/°C
CT
100
50
ps
ps
CB
CB
1
Propagation Delay Matching
High Transition to Low Transition
High-to-Low Comparator
Rev. 0 | Page 9 of 56
Conditions/Comments
Offset measured at differential calibration points +1.0 V
and −1.0 V, with common mode = 0.0 V
After two-point gain/offset calibration; range/number of
DAC bits as measured at differential calibration points
+1.0 V and −1.0 V, with common mode = 0.0 V
After two-point gain/offset calibration; common
mode = 0.0 V
After two-point gain/offset calibration; measured over VOH,
VOL range of −1.1 V to +1.1 V, common mode = 0.0 V
Measured at calibration points
VDUTx = 0 V, sweep comparator threshold to determine
uncertainty region
VDUTx = 0 V
Offset measured at common-mode voltage points of
−1.5 V and +4.5 V, with differential voltage = 0.0 V
Measured at calibration points
Input transition time = 800 ps, 10% to 90%, measured
with each comparator leg terminated 50 Ω to GND
VDUT0 = 0 V, VDUT1 = −0.5 V to +0.5 V swing, Driver VTERM
mode, VT = 0.0 V; high-side measurement: VOH = 0.0 V,
VOL = −1.1 V; low-side measurement: VOH = 1.1 V,
VOL = 0.0 V; repeat for other DUT channel
VDUT0 = 0 V, VDUT1 = −0.5 V to +0.5 V swing, Driver VTERM
mode, VT = 0.0 V; high-side measurement: VOH = 0.0 V,
VOL = −1.1 V; low-side measurement: VOH = 1.1 V, VOL =
0.0 V; repeat for other DUT channel
VDUT0 = 0 V, VDUT1 = −0.5 V to +0.5 V swing, Driver VTERM
mode, VT = 0.0 V; high-side measurement: VOH = 0.0 V,
VOL = −1.1 V; low-side measurement: VOH = 1.1 V, VOL =
0.0 V; repeat for other DUT channel
ADATE305
Parameter
Propagation Delay Change (with
Respect To)
Min
Typ
Max
Unit
Test
Level
Slew Rate, 800 ps, 1ns, 1.2ns, and
2.2 ns (10% to 90%)
60
ps
CB
Overdrive, 250 mV and 750 mV
100
ps
CB
Pulse Width, Sweep from 1.6 ns to
10 ns
75
ps
CB
Duty Cycle, 5% to 95%
60
ps
CB
Minimum Pulse Width
2.5
ns
CB
Input Equivalent Bandwidth,
Terminated
400
MHz
CB
Rev. 0 | Page 10 of 56
Conditions/Comments
VDUT0 = 0 V, VDUT1 = −0.5 V to +0.5 V swing, Driver VTERM
mode, VT = 0.0 V; high-side measurement: VOH = 0.0 V,
VOL = −1.1 V; low-side measurement: VOH = 1.1 V, VOL =
0.0 V; repeat for other DUT channel
VDUT0 = 0 V, VDUT1 = −0.5 V to +0.5 V swing, Driver VTERM
mode, VT = 0.0 V; high-side measurement: VOH = 0.0 V,
VOL = −1.1 V; low-side measurement: VOH = 1.1 V, VOL =
0.0 V; repeat for other DUT channel
VDUT0 = 0 V, for 250 mV: VDUT1 = 0 V to 0.5 V swing; for
750 mV: VDUT1 = 0 V to 1.0 V swing, Driver VTERM mode,
VT = 0.0 V; VOH = −0.25 V; repeat for other DUT channel
with comparator threshold = +0.25 V
VDUT0 = 0 V, VDUT1 = −0.5 V to +0.5 V swing @ 32 MHz, Driver
VTERM mode, VT = 0.0 V; high-side measurement: VOH =
0.0 V, VOL = −1.1 V; low-side measurement: VOH = 1.1 V,
VOL = 0.0 V; repeat for other DUT channel
VDUT0 = 0 V, VDUT1 = −0.5 V to +0.5 V swing @ 1 MHz, Driver
VTERM mode, VT = 0.0 V; high-side measurement: VOH =
0.0 V, VOL = −1.1 V; low-side measurement: VOH = 1.1 V,
VOL = 0.0 V; repeat for other DUT channel
VDUT0 = 0 V, VDUT1 = −0.5 V to +0.5 V swing, Driver VTERM
mode, VT = 0.0 V; high-side measurement: VOH = 0.0 V,
VOL = −1.1 V; low-side measurement: VOH = 1.1 V, VOL =
0.0 V; less than 10% amplitude degradation measured by
shmoo; repeat for other DUT channel
VDUT0 = 0 V, VDUT1 = −0.5 V to +0.5 V swing, Driver VTERM
mode, VT = 0.0 V; high-side measurement: VOH = 0.0 V,
VOL = −1.1 V; low-side measurement: VOH = 1.1 V, VOL =
0.0 V; less than 22% amplitude degradation measured by
shmoo; repeat for other DUT channel
ADATE305
ACTIVE LOAD
See Table 29 for load control information.
Table 6.
Parameter
DC SPECIFICATIONS
Input Characteristics
VCOM Voltage Range
VDUT Range
VCOM Accuracy, Uncalibrated
Min
−1.25
−1.5
−200
VCOM Resolution
Typ
Max
Unit
Test
Level
±30
+5.75
+6.0
+200
V
V
mV
D
D
P
0.6
1
mV
PF
VCOM DNL
VCOM INL
−7
±1
±2
+7
mV
mV
CT
P
DUTGND Voltage Accuracy
−7
±1
+7
mV
P
12
−600.0
±100
+600.0
mA
μA
D
P
−12
±4
+12
%
P
Resolution
1.5
2
μA
PF
DNL
±3.0
μA
CT
+80
μA
P
0.25
V
P
Output Characteristics
IOL
Maximum Source Current
Uncalibrated Offset
Uncalibrated Gain
INL
−80
±20
90% Commutation Voltage
IOH
Maximum Sink Current
Uncalibrated Offset
12
−600.0
±100
+600.0
mA
μA
D
P
−12
±4
+12
%
P
Resolution
1.5
2
μA
PF
DNL
±3.0
μA
CT
+80
μA
P
0.25
V
P
μA/°C
CT
Uncalibrated Gain
INL
−80
±20
90% Commutation Voltage
Output Current Tempco
±1.5
Rev. 0 | Page 11 of 56
Conditions/Comments
Load active on, RCV active, unless otherwise noted
IOH = IOL = 6 mA, VCOM error measured at the calibration
points of 0.0 V and 5.0 V
IOH = IOL = 6 mA, after two-point gain/offset calibration;
range/number of DAC bits as measured at the calibration
points of 0.0 V and 5.0 V
IOH = IOL = 6 mA, after two-point gain/offset calibration
IOH = IOL = 6 mA, after two-point gain/offset calibration;
measured over VCOM range of −1.25 V to +5.75 V
Over ±0.1 V range; measured at end points of VCOM functional
range
IOH = 0 mA, VCOM = 1.5 V, VDUTx = 0.0 V, IOL offset calculated
from the calibration points of 1 mA and 11 mA
IOH = 0 mA, VCOM = 1.5 V, VDUTx = 0.0 V, IOL gain calculated from
the calibration points of 1 mA and 11 mA
IOH = 0 mA, VCOM = 1.5 V, VDUTx = 0.0 V, after two-point gain/
offset calibration; range/number of DAC bits as measured at the
calibration points of 1 mA and 11 mA
IOH = 0 mA, VCOM = 1.5 V, VDUTx = 0.0 V, after two-point
gain/offset calibration
IOH = 0 mA, VCOM = 1.5 V, VDUTx = 0.0 V, after two-point gain/
offset calibration; measured over IOL range of 0 mA to 12 mA
IOH = IOL = 12 mA, VCOM = 2.0 V, measure IOL reference at
VDUTx = −1.0 V, measure IOL current at VDUTx = 1.75 V, ensure > 90%
of reference current
IOL = 0 mA, VCOM = 1.5 V, VDUTx = 3.0 V, IOH offset calculated
from the calibration points of 1 mA and 11 mA
IOL = 0 mA, VCOM = 1.5 V, VDUTx = 3.0 V, IOH gain calculated from
the calibration points of 1 mA and 11 mA
IOL = 0 mA, VCOM = 1.5 V, VDUTx = 3.0 V, after two-point
gain/offset calibration; range/number of DAC bits as measured
at the calibration points of 1 mA and 11 mA
IOL = 0 mA, VCOM = 1.5 V, VDUTx = 3.0 V, after two-point
gain/offset calibration
IOL = 0 mA, VCOM = 1.5 V, VDUTx = 3.0 V, after two-point gain/
offset calibration; measured over IOH range of 0 mA to 12 mA
IOH = IOL =12 mA, VCOM = 2.0 V, measure IOH reference at
VDUTx = 5.0 V, measure IOH current at VDUTx = 2.25 V, ensure >
90% of reference current
Measured at calibration points
ADATE305
Unit
Test
Level
7.3
ns
CB
Propagation Delay, Load Active
Off to Load Active On;
50%, 90%
10.3
ns
CB
Propagation Delay Matching
3.0
ns
CB
Load Spike
190
mV
CB
Settling Time to 90%
1.9
ns
CB
Parameter
AC SPECIFICATIONS
Dynamic Performance
Propagation Delay, Load Active
On to Load Active Off;
50%, 90%
Min
Typ
Max
Conditions/Comments
Load active on, unless otherwise noted
Toggle RCV, DUTx terminated 50 Ω to GND, IOH = IOL = 12 mA,
VH = VL = 0 V, VCOM = +1.25 V for IOL and VCOM = −1.25 V for
IOH; measured from 50% point of RCVxP − RCVxN to 90% point
of final output, repeat for drive low and high
Toggle RCV, DUTx terminated 50 Ω to GND, IOH = IOL = 12 mA,
VH = VL = 0 V, VCOM = +1.25 V for IOL and VCOM = −1.25 V for
IOH; measured from 50% point of RCVxP − RCVxN to 90% point
of final output, repeat for drive low and high
Toggle RCV, DUTx terminated 50 Ω to GND, IOH = IOL = 12 mA,
VH = VL = 0 V, VCOM = +1.25 V for IOL and VCOM = −1.25 V for
IOH; active on vs. active off, repeat for drive low and high
Toggle RCV, DUTx terminated 50 Ω to GND, IOH = IOL = 0 mA,
VH = VL = 0 V, VCOM = +1.25 V for IOL and VCOM = −1.25 V for
IOH; repeat for drive low and high
Toggle RCV, DUTx terminated 50 Ω to GND, IOH = IOL = 12 mA,
VH = VL = 0 V, VCOM = +1.25 V for IOL and VCOM = −1.25 V for
IOH; measured at 90% of final value
PMU
FV = force voltage, MV = measure voltage, FI = force current, MI = measure current, FN = force nothing.
Table 7.
Parameter
FORCE VOL TAGE (FV)
Current Range A
Current Range B
Current Range C
Current Range D
Current Range E
Force Input Voltage Range at
Output for All Ranges
Force Voltage Uncalibrated
Accuracy for Range C
Force Voltage Uncalibrated
Accuracy for All Ranges
Force Voltage Offset Tempco
for All Ranges
Force Voltage Gain Tempco
for All Ranges
Forced Voltage INL
Min
Max
Unit
Test
Level
+6.0
mA
mA
μA
μA
μA
V
D
D
D
D
D
D
+100
mV
P
±25
mV
CT
±25
μV/°C
CT
PMU enabled, FV, Range C, PE disabled, error measured at
calibration points of 0.0 V and 5.0 V
PMU enabled, FV, PE disabled, error measured at calibration
points of 0.0 V and 5.0 V; repeat for each PMU current range
Measured at calibration points for each PMU current range
±10
ppm/°C
CT
Measured at calibration points for each PMU current range
mV
P
PMU enabled, FV, Range C, PE disabled, after two-point gain/offset
calibration; measured over output range of −1.5 V to +6.0 V
PMU enabled, FV, PE disabled, force −1.5 V, measure voltage
while PMU sinking zero and full-scale current; measure ∆V;
force 6.0 V, measure voltage while PMU sourcing zero and fullscale current; measure ∆V; repeat for each PMU current range
mV
mV
CT
CT
Typ
±32
±2
±200
±20
±2
−1.5
−100
−7
±25
±2
+7
Force Voltage Compliance vs.
Current Load
Range A
Range B to Range E
±4
±1
Rev. 0 | Page 12 of 56
Conditions/Comments
ADATE305
Parameter
Current Limit, Source, and Sink
Range A
Range B to Range E
DUTGND Voltage Accuracy
Min
Typ
Max
Unit
Test
Level
108
140
180
%FS
P
120
145
180
%FS
P
−7
±1
+7
mV
P
+6.0
V
D
μA
CT
μA
P
MEASURE CURRENT (MI)
Measure Current, Pin DUTx
Voltage Range for All Ranges
Measure Current Uncalibrated
Accuracy
Range A
Range B
−1.5
±500
−400
±3.0
+400
Conditions/Comments
PMU enabled, FV, PE disabled; sink: force 2.5 V, short DUTx
to 6.0 V; source: force 2.5 V, short DUTx to −1.0 V; Range A FS =
32 mA, 108% FS = 35 mA, 180% FS = 58 mA
PMU enabled, FV, PE disabled; sink: force 2.5 V, short DUTx to
6.0 V; source: force 2.5 V, short DUTx to −1.0 V; repeat for each
PMU current range; example: Range B FS = 2 mA, 120 % FS =
2.4 mA, 180% FS = 3.6 mA
Over ±0.1 V range; measured at end points of FV functional
range
VDUTx externally forced to 0.0V, unless otherwise specified, ideal
MEASOUT transfer functions: VMEASOUT01 [V] = (IMEASOUT01 × 5/FSR) +
2.5 + VDUTGND I(VMEASOUT01) [A] = (VMEASOUT01 − VDUTGND − 2.5) × FSR/5
PMU enabled, FIMI, Range A, PE disabled, error at calibration
points −25 mA and +25 mA, error = (I(VMEASOUT01) − IDUTx)
PMU enabled, FIMI, Range B, PE disabled, error at calibration
points −1.6 mA and +1.6 mA, error = (I(VMEASOUT01) − IDUTx)
PMU enabled, FIMI, PE disabled, error at calibration points of
±80% FS, error = (I(VMEASOUT01)1 − IDUTx)
PMU enabled, FIMI, PE disabled, error at calibration points of
±80% FS, error = (I(VMEASOUT01) − IDUTx)
PMU enabled, FIMI, PE disabled, error at calibration points of
±80% FS, error = (I(VMEASOUT01) − IDUTx)
Range C
± 2.00
μA
CT
Range D
±0.30
μA
CT
Range E
±0.08
μA
CT
±2
±25
±5
±1
μA/°C
nA/°C
nA/°C
nA/°C
CT
CT
CT
CT
Measured at calibration points
Measured at calibration points
Measured at calibration points
Measured at calibration points
±2.5
%
CT
%
P
±4
%
CT
PMU enabled, FIMI, PE disabled, gain error from calibration
points ±80% FS
PMU enabled, FIMI, Range B, PE disabled, gain error from
calibration points ±1.6 mA
PMU enabled, FIMI, PE disabled, gain error from calibration
points ±80% FS
Measured at calibration points
±300
±50
ppm/°C
ppm/°C
CT
CT
±0.05
%FSR
CT
%FSR
P
%FSR
CT
%FSR/V
P
mV
CT
Measure Current Offset Tempco
Range A
Range B
Range C
Range D and Range E
Measure Current Gain Error,
Nominal Gain = 1
Range A
Range B
−20
Range C to Range E
Measure Current Gain Tempco
Range A
Range B to Range E
Measure Current INL
Range A
Range B
−0.02
Range B to Range E
FVMI DUT Pin Voltage Rejection
DUTGND Voltage Accuracy
±2
+20
+0.02
±0.01
−0.01
+0.01
±2.5
Rev. 0 | Page 13 of 56
PMU enabled, FIMI, Range A, PE disabled, after two-point
gain/offset calibration, measured over FSR output of −32 mA
to +32 mA
PMU enabled, FIM,I Range B, PE disabled, after two-point gain/
offset calibration measured over FSR output of −2 mA to +2 mA
PMU enabled, FIMI, PE disabled, after two-point gain/offset
calibration; measured over FSR output
PMU enabled, FVMI, Range B, PE disabled, force −1 V and +5 V
into load of 1 mA; measure ∆I reported at MEASOUT01
Over ±0.1 V range; measured at end points of MI functional range
ADATE305
Parameter
FORCE CURRENT (FI)
Force Current, DUTx Pin Voltage
Range for All Ranges
Force Current Uncalibrated
Accuracy
Range A
Min
Typ
−1.5
Max
Unit
Test
Level
+6.0
V
D
−5.0
±0.5
+5.0
mA
P
Range B
−400
±40
+400
μA
P
Range C
−40
±4
+40
μA
P
Range D
−4
±0.4
+4
μA
P
Range E
−400
±75
+400
nA
P
−20
±1
±80
±4
±4
+20
μA/°C
nA/°C
nA/°C
%
CT
CT
CT
P
ppm/°C
ppm/°C
CT
CT
Force Current Offset Tempco
Range A
Range B
Range C to Range E
Forced Current Gain Error,
Nominal Gain = 1
Forced Current Gain Tempco
Range A
Range B to Range E
Force Current INL
Range A
−500
±75
−0.3
±0.05
+0.3
%FSR
P
−0.2
±0.015
+0.2
%FSR
P
−0.6
−1.0
±0.06
±0.1
+0.6
+1.0
%FSR
%FSR
P
P
−1.5
−25
±2.0
+6.0
+25
V
mV
D
P
−2
±10
±0.01
+2
μV/°C
%
CT
P
Measure Voltage Gain Tempco
Measure Voltage INL
−7
25
±1
+7
ppm/°C
mV
CT
P
Rejection of Measure V vs. IDUTx
−1.5
±0.1
+1.5
mV
P
25
+6.0
4
200
V
mA
Ω
D
D
P
+1
μA
P
Range B to Range E
Force Current Compliance vs.
Voltage Load
Range A to Range D
Range E
MEASURE VOLTAGE
Measure Voltage Range
Measure Voltage Uncalibrated
Accuracy
Measure Voltage Offset Tempco
Measure Voltage Gain Error
MEASOUT01 DC CHARACTERISTICS
MEASOUT01 Voltage Range
DC Output Current
MEASOUT01 Pin Output
Impedance
Output Leakage Current when
Tristated
−1.5
−1
Rev. 0 | Page 14 of 56
Conditions/Comments
VDUTx externally forced to 0.0V, unless otherwise specified, ideal
force current transfer function: IFORCE = (PMUDAC − 2.5) × (FSR/5)
PMU enabled, FIMI, Range A, PE disabled, error at calibration
points of −25 mA and +25 mA
PMU enabled, FIMI, Range B, PE disabled, error at calibration
points of −1.6 mA and 1.6 mA
PMU enabled, FIMI, Range C, PE disabled, error at calibration
points of ±80% FS
PMU enabled, FIMI, Range D, PE disabled, error at calibration
points of ±80% FS
PMU enabled, FIMI, Range E, PE disabled, error at calibration
points of ±80% FS
Measured at calibration points
Measured at calibration points
Measured at calibration points
PMU enabled, FIMI, PE disabled, gain error from calibration
points of ±80% FS
Measured at calibration points
PMU enabled, FIMI, Range A, PE disabled, after two-point
gain/offset calibration; measured over FSR output of −32 mA
to +32 mA
PMU enabled, FIMI, PE disabled, after two-point gain/offset
calibration; measured over FSR output
PMU enabled, FIMV, PE disabled; force positive full-scale
current driving −1.5 V and +6.0 V, measure ∆I @ DUTx pin;
force negative full-scale current driving −1.5 V and +6.0 V,
measure ∆I @ DUTx pin
PMU enabled, FVMV, Range B, PE disabled, error at calibration
points 0 V and 5 V, error = (VMEASOUT01 − VDUTx)
Measured at calibration points
PMU enabled, FVMV, Range B, PE disabled, gain error from
calibration points 0 V and 5 V
Measured at calibration points
PMU enabled, FVMV, Range B, PE disabled, after two-point
gain/offset calibration; measured over output range of −1.5 V
to +6.0 V
PMU enabled, FVMV, Range D, PE disabled, force 0 V into load
of −10 μA and +10 μA; measure ∆V reported at MEASOUT01
PMU enabled, FVMV, PE disabled; source resistance: PMU force
6.0 V and load with 0 mA and 4 mA; sink resistance: PMU force
−1.5 V and load with 0 mA and −4 mA; resistance = ∆V/∆I at
MEASOUT01 pin
Tested at −1.5 V and +6.0 V
ADATE305
Max
+25
Unit
mA
Test
Level
P
+10
+4.0
6.0
+300
V
V
mV
D
D
P
−300
−10
+300
mV
P
Uncalibrated Accuracy
−250
±100
+250
mV
P
INL
−70
±5
+70
mV
P
±1
mV
CT
15
μs
S
20
μs
S
124
μs
S
1015
μs
S
3455
μs
S
Parameter
Output Short-Circuit Current
Min
−25
VOLTAGE CLAMPS
Low Clamp Range (VCL)
High Clamp Range (VCH)
Positive Clamp Voltage Droop
−1.5
0.0
−300
Negative Clamp Voltage Droop
DUTGND Voltage Accuracy
Typ
SETTLING/SWITCHING TIMES
Voltage Force Settling Time to
0.1% of Final Value:
Range A, 200 pF and
2000 pF Load
Range B, 200 pF and
2000 pF Load
Range C, 200 pF and
2000 pF Load
Range D, 200 pF and
2000 pF Load
Range E, 200 pF and
2000 pF Load
Voltage Force Settling Time to
1.0% of Final Value:
Range A, 200 pF and
2000 pF Load
Range B, 200 pF and
2000 pF Load
Range C, 200 pF and
2000 pF Load
Range D, 200 pF Load
Range D, 2000 pF Load
Range E, 200 pF Load
Range E, 2000 pF Load
Voltage Force Settling Time to
1.0% of Final Value:
Range A, 200 pF and
2000 pF Load
Range B, 200 pF Load
Range B, 2000 pF Load
Range C, 200 pF Load
Range C, 2000 pF Load
Range D, 200 pF Load
Range D, 2000 pF Load
Range E, 200 pF Load
Range E, 2000 pF Load
Conditions/Comments
PMU enabled, FVMV, PE disabled; source: PMU force +6.0 V,
short MEASOUT01 to −1.5 V; sink: PMU force −1.5 V, short
MEASOUT01 to +6.0 V
PMU enabled, FIMI, Range A, PE disabled, PMU clamps
enabled, VCH = 5 V,VCL = −1 V, PMU force 2 mA and 32 mA
into open; ∆V seen at DUTx pin
PMU enabled, FIMI, Range A, PE disabled, PMU clamps
enabled, VCH = 5 V,VCL = −1 V, PMU force −2 mA and −32 mA
into open; ∆V seen at DUTx pin
PMU enabled, FIMI, Range B, PE disabled, PMU clamps enabled,
PMU force ±1 mA into open; VCH errors at calibration points 0 V
and 5 V; VCL errors at the calibration points 0 V and 4 V
PMU enabled, FIMI, Range B, PE disabled, PMU clamps enabled,
PMU force ±1 mA into open; after two-point gain/offset
calibration; measured over PMU clamp range
Over ±0.1 V range; measured at end points of PMU clamp
functional range
SCAP = 330 pF, FFCAP = 220 pF
PMU enabled, FV, PE disabled, program PMUDAC steps of
500 mV and 5.0 V; simulation of worst case, 2000 pF load,
PMUDAC step of 5.0 V
PMU enabled, FV, PE disabled, start with PMUDAC
programmed to 0.0 V, program PMUDAC to 500 mV
14
μs
CB
14
μs
CB
14
μs
CB
45
45
45
225
μs
μs
μs
μs
CB
CB
CB
CB
PMU enabled, FV, PE disabled, start with PMUDAC
programmed to 0.0 V, program PMUDAC to 5.0 V
4.0
μs
CB
4.2
4.2
5.8
19
50
210
360
610
μs
μs
μs
μs
μs
μs
μs
μs
CB
CB
CB
CB
CB
CB
CB
CB
Rev. 0 | Page 15 of 56
ADATE305
Parameter
Current Force Settling Time to
0.1% of Final Value
Range A, 200 pF in Parallel
with 120 Ω
Range B, 200 pF in Parallel
with 1.5 kΩ
Range C, 200 pF in Parallel
with 15.0 kΩ
Range D, 200 pF in Parallel
with 150 kΩ
Range E, 200 pF in Parallel
with 1.5 MΩ
Current Force Settling Time to
1.0% of Final Value:
Range A, 200 pF in Parallel
with 120 Ω
Range B, 200 pF in Parallel
with 1.5 kΩ
Range C, 200 pF in Parallel
with 15.0 kΩ
Range D, 200 pF in Parallel
with 150 kΩ
Range E, 200 pF in Parallel
with 1.5 MΩ
INTERACTION AND CROSSTALK
Measure Voltage Channel-toChannel Crosstalk
Min
Measure Current Channel-toChannel Crosstalk
Unit
Test
Level
8.2
μs
S
9.4
μs
S
30
μs
S
281
μs
S
2668
μs
S
Typ
Max
Conditions/Comments
PMU enabled, FI, PE disabled, start with PMUDAC
programmed to 0 current, program PMUDAC to FS current
PMU enabled, FI, PE disabled, start with PMUDAC
programmed to 0 current, program PMUDAC to FS current
4.2
μs
CB
4.3
μs
CB
8.1
μs
CB
205
μs
CB
505
μs
CB
±0.125
%FSR
CT
±0.01
%FSR
CT
PMU enabled, FIMV, PE disabled, Range B, forcing 0 mA into
0 V load; other channel: Range A, forcing a step of 0 mA to 25 mA
into 0 V load; report ∆V of MEASOUT01 pin under test;
0.125% × 8.0 V = 10 mV
PMU enabled, FVMI, PE disabled, Range E, forcing 0 V into
0 mA current load; other channel: Range E, forcing a step of 0 V
to 5 V into 0 mA current load; report ∆V of MEASOUT01 pin
under test; 0.01% × 5.0 V = 0.5 mV
EXTERNAL SENSE (PMUS_CHX)
Table 8.
Parameter
EXTERNAL SENSE (PMUS_CHX)
Voltage Range
Input Leakage Current
Min
Max
Unit
Test
Level
Conditions/Comments
+6.0
+20
V
nA
D
P
Tested at −1.5 V and +6.0 V
Typ
Max
Unit
Test
Level
Conditions/Comments
1
+0.1
100
V
μA
D
P
Tested at −100 mV and +100 mV
Typ
−1.5
−20
DUTGND INPUT
Table 9.
Parameter
DUTGND INPUT
Input Voltage Range, Referenced to GND
Input Bias Current
Min
−0.1
Rev. 0 | Page 16 of 56
ADATE305
SERIAL PERIPHERAL INTERFACE
Table 10.
Parameter
SERIAL PERIPHERAL INTERFACE
Serial Input Logic High
Serial Input Logic Low
Input Bias Current
SCLK Clock Rate
SCLK Pulse Width
SCLK Crosstalk on DUTx Pin
Serial Output Logic High
Serial Output Logic Low
Update Time
Min
1.8
0
−10
Typ
1
50
9
8
VCC − 0.4
Max
Unit
Test
Level
VCC
0.7
+10
V
V
μA
MHz
ns
mV
V
PF
PF
P
PF
CT
CB
PF
V
μs
PF
D
VCC
0
0.8
10
Conditions/Comments
Tested at 0.0 V and 3.3 V
PE disabled, PMU FV enabled and forcing 0 V
Sourcing 2 mA
Sinking 2 mA
Maximum delay time required for the part to enter a stable state after
a serial bus command is loaded
HVOUT DRIVER
Table 11.
Max
Unit
Test
Level
VPLUS − 3.25
V
D
V
P
5.9
V
P
±100
+500
mV
P
1
1.21
1.5
mV/°C
mV
CT
PF
±15
+30
mV
P
mV
CT
10
Ω
P
60
100
mA
P
−100
−60
mA
P
200
ns
CB
26
ns
CB
±125
mV
CB
Parameter
VHH BUFFER
Voltage Range
Min
Output High
13.5
Typ
5.9
Output Low
Accuracy Uncalibrated
−500
Offset Tempco
Resolution
INL
−30
DUTGND Voltage Accuracy
±1
Output Resistance
1
DC Output Current Limit
Source
DC Output Current Limit Sink
Rise Time (From VL or VH to
VHH)
Fall Time (From VHH to VL or
VH)
Preshoot, Overshoot, and
Undershoot
Rev. 0 | Page 17 of 56
Conditions/Comments
VHH = (VT + 1 V) × 2 + DUTGND
VPLUS = 16.75 V nominal; in this condition, VHVOUT max = 13.5
V
VHH mode enabled, RCV active, VHH level = full scale,
sourcing 15 mA
VHH mode enabled, RCV active, VHH level = zero scale,
sinking 15 mA
VHH mode enabled, RCV active, VHVOUT error measured at
the calibration points of 7 V and 12 V
Measured at calibration points
VHH mode enabled, RCV active, after two-point gain/offset
calibration; range/number of DAC bits as measured at the
calibration points of 7 V and 12 V
VHH mode enabled, RCV active, after two-point gain/offset
calibration; measured over VHH range of 5.9 V to 13.5 V
Over ±0.1 V range; measured at end points of VHH
functional range
VHH mode enabled, RCV active, source: VHH = 10.0 V,
IHVOUT= 0 mA and 15 mA; sink: VHH = 6.5 V, IHVOUT = 0 mA and
−15 mA; ∆V/∆I
VHH mode enabled, RCV active, VHH = 10.0 V, short HVOUT
pin to 5.9 V, measure current
VHH mode enabled, RCV active, VHH = 6.5 V, short HVOUT
pin to 14.1 V, measure current
VHH mode enabled, toggle RCV, VHH = 13.5 V, VL = VH =
3.0 V; 20% to 80%, for DATA = high and DATA = low
VHH mode enabled, toggle RCV, VHH = 13.5 V, VL = VH =
3.0 V; 20% to 80%, for DATA = high and DATA = low
VHH mode enabled, toggle RCV, VHH = 13.5 V, VL = VH =
3.0 V; for DATA = high and DATA = low
ADATE305
Parameter
VL/VH BUFFER
Voltage Range
Accuracy Uncalibrated
Min
Typ
Max
Unit
Test
Level
−0.1
−500
±100
+6.0
+500
V
mV
D
P
1
0.61
0.75
mV/°C
mV
CT
PF
±4
+20
mV
P
mV
CT
50
Ω
P
Offset Tempco
Resolution
INL
−20
DUTGND Voltage Accuracy
±2
Output Resistance
46
48
DC Output Current Limit
Source
DC Output Current Limit Sink
60
100
mA
P
−100
−60
mA
P
Rise Time (VL to VH)
10.0
ns
CB
Fall Time (VH to VL)
11.3
ns
CB
Preshoot, Overshoot, and
Undershoot
±54
mV
CB
Max
Unit
Test
Level
+7.0
+200
V
mV
D
P
mV
CB
Conditions/Comments
VHH mode enabled, RCV inactive, error measured at the
calibration points 0 V and 5 V
Measured at calibration points
VHH mode enabled, RCV inactive, after two-point
gain/offset calibration; range/number of DAC bits as
measured at the calibration points 0 V and 5 V
VHH mode enabled, RCV inactive, after two-point
gain/offset calibration; measured over range of −0.1 V to
+6.0 V
Over ±0.1 V range; measured at end points of VH and VL,
functional range
VHH mode enabled, RCV inactive, source: VH = 3.0 V, IHVOUT
= 1 mA and 50 mA; sink: VL = 2.0 V, IHVOUT = −1 mA and −50
mA; ∆V/∆I
VHH mode enabled, RCV inactive, VH = 6.0 V, short HVOUT
pin to −0.1 V, DATA high, measure current
VHH mode enabled, RCV inactive, VL = −0.1 V, short HVOUT
pin to 6.0 V, DATA low, measure current
VHH mode enabled, RCV inactive, VL = 0.0 V, VH = 3.0 V,
toggle DATA; 20% to 80%
VHH mode enabled, RCV inactive, VL = 0.0 V, VH = 3.0 V,
toggle DATA; 20% to 80%
VHH mode enabled, RCV inactive, VL = 0.0 V, VH = 3.0 V,
toggle DATA
OVERVOLTAGE DETECTOR (OVD)
Table 12.
Parameter
DC CHARACTERISTICS
Programmable Voltage Range
Accuracy Uncalibrated
Min
Typ
−3.0
−200
Hysteresis
LOGIC OUTPUT CHARACTERISTICS
Off State Leakage
112
Conditions/Comments
OVD offset errors measured at programmed levels of +7.0 V
and −3.0 V
10
1000
nA
P
Disable OVD alarm, apply 3.3 V to OVD pin, measure
leakage current
Activate alarm, force 100 μA into OVD pin, measure active
alarm voltage
For OVD high: DUTx = 0 V to 6 V swing, OVD high = 3.0 V,
OVD low = −3.0 V; for OVD low: DUTx = 0 V to 6 V swing,
OVD high = 7.0 V, OVD low = 3.0 V
Max On Voltage @ 100 μA
0.2
0.7
V
P
Propagation Delay
1.6
μs
CB
Max
Unit
Test
Level
Conditions/Comments
+7.5
V
kΩ
D
CT
PMUDAC = 0.0 V, FV, I = 0, 200 μA; ∆V/∆I
16-BIT DAC MONITOR MUX
Table 13.
Parameter
DC CHARACTERISTICS
Programmable Voltage Range
Output Resistance
Min
Typ
−2.5
16
Rev. 0 | Page 18 of 56
ADATE305
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 14.
Parameter
Supply Voltages
Positive Supply Voltage (VDD to GND)
Positive VCC Supply Voltage (VCC to GND)
Negative Supply Voltage (VSS to GND)
Supply Voltage Difference (VDD to VSS)
Reference Ground (DUTGND to GND)
AGND to DGND
VPLUS Supply Voltage (VPLUS to GND)
Input Voltages
Input Common-Mode Voltage
Short-Circuit Voltage1
High Speed Input Voltage2
High Speed Differential Input Voltage3
VREF
DUTx I/O Pin Current
DCL Maximum Short-Circuit Current4
Temperature
Operating Temperature, Junction
Storage Temperature Range
For liquid cooled applications, θJC = 1.1°C/W.
Rating
−0.5 V to +11.0 V
−0.5 V to +4.0 V
−6.25 V to +0.5 V
−1.0 V to +16.5 V
−0.5 V to +0.5 V
−0.5 V to +0.5 V
−0.5 V to +17.5 V
VSS to VDD
−3.0 V to +8.0 V
0.0 V to VCC
0.0 V to VCC
−0.5 V to +5.5 V
±140 mA
125°C
−65°C to +150°C
1
RL = 0 Ω, VDUT continuous short-circuit condition, (VH, VL, VT, high-Z, VCOM,
clamp modes).
2
DATAxP, DATAxN, RCVxP, RCVxN, under source R = 0 Ω.
3
DATAxP to DATAxN, RCVxP, RCVxN.
4
RL = 0 Ω, VDUTx = –3 V to +8 V; DCL current limit. Continuous short-circuit
condition. ADATE305 must current limit and survive continuous short circuit.
Table 15. Thermal Resistance
Airflow
Natural Convection
1 meter per second
2 meters per second
θJA
33
30
28.5
EXPLANATION OF TEST LEVELS
D
Definition
S
Design verification simulation
P
100% production tested
PF
Functionally checked during production test
CT
Characterized on tester
CB
Characterized on bench
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. 0 | Page 19 of 56
Unit
°C/W
°C/W
°C/W
ADATE305
NC
NC
PMUS_CH0
VSS
VDD
VSSO_0 (DRIVE)
DUT0
VDDO_0 (DRIVE)
AGND
AGND
VSS
VDD
AGND
VDD
VSS
AGND
AGND
VDDO_1 (DRIVE)
DUT1
VSSO_1 (DRIVE)
VDD
VSS
PMUS_CH1
NC
NC
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
75
NC
74
NC
3
73
HVOUT
VDD/VDD_TMPSNS
4
72
VPLUS
SCAP1
5
71
SCAP0
FFCAP_1B
6
70
FFCAP_0B
VDD
7
69
VDD
OVD_CH1
8
68
OVD_CH0
DATA1N
9
67
DATA0N
DATA1P 10
66
DATA0P
FFCAP_1A 11
65
FFCAP_0A
ADATE305
64
VSS
TOP VIEW
(Not to Scale)
63 RCV0N
NC
1
NC
2
TEMPSENSE
PIN 1
VSS 12
RCV1N 13
62
RCV0P
AGND 15
61
AGND
COMP_QL1P 16
60
COMP_QL0P
COMP_QL1N 17
59 COMP_QL0N
RCV1P 14
COMP_VTT1 18
58
COMP_VTT0
COMP_QH1P 19
57
COMP_QH0P
COMP_QH1N 20
56
COMP_QH0N
AGND 21
55
AGND
AGND 22
54
AGND
AGND 23
53
AGND
NC 24
52
NC
NC 25
51
NC
NC
NC
VREF_GND
VREF
AGND
AGND
AGND
RST
VSS
VCC
VDD
SDIN
SCLK
SDOUT
DGND
VDD
VSS
DAC16_MON
CS
AGND
AGND
DUTGND
MEASOUT01/TEMP SENSE
NC
NC
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
07280-002
NOTES
1. NC = NO CONNECT.
2. EXPOSED PAD IS CONNEC TED TO VSS.
Figure 2. Pin Configuration
Table 16. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
Mnemonic
NC
NC
TEMPSENSE
VDD/VDD_TMPSNS
SCAP1
FFCAP_1B
VDD
OVD_CH1
DATA1N
DATA1P
FFCAP_1A
VSS
Description
No Connect. No physical connection to die.
No Connect. No physical connection to die.
Temperature Sense Output.
Temperature Sense Supply +10.0 V.
PMU Stability Capacitor Connection Channel 1 (330 pF).
PMU Feed Forward Capacitor Connection B Channel 1 (220 pF).
Supply +10.0 V.
Overvoltage Detection Flag Output Channel 1.
Driver Data Input (Negative) Channel 1.
Driver Data Input (Positive) Channel 1.
PMU Feedforward Capacitor Connection A Channel 1 (220 pF).
Supply −5.75 V.
Rev. 0 | Page 20 of 56
ADATE305
Pin No.
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Mnemonic
RCV1N
RCV1P
AGND
COMP_QL1P
COMP_QL1N
COMP_VTT1
COMP_QH1P
COMP_QH1N
AGND
AGND
AGND
NC
NC
NC
NC
MEASOUT01/TEMP SENSE
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
DUTGND
AGND
AGND
CS
DAC16_MON
VSS
VDD
DGND
SDOUT
SCLK
SDIN
VDD
VCC
VSS
RST
AGND
AGND
AGND
VREF
VREF_GND
NC
NC
NC
NC
AGND
AGND
AGND
Comp_QH0N
Comp_QH0P
Comp_VTT0
Comp_QL0N
Comp_QL0P
AGND
RCV0P
Description
Receive Data Input (Negative) Channel 1.
Receive Data Input (Positive) Channel 1.
Analog Ground.
Low-Side Comparator Output (Positive) Channel 1.
Low-Side Comparator Output (Negative) Channel 1.
Comparator Supply Channel 1.
High-Side Comparator Output (Positive) Channel 1.
High-Side Comparator Output (Negative) Channel 1.
Analog Ground.
Analog Ground.
Analog Ground.
No Connect. No physical connection to die.
No Connect. No physical connection to die.
No Connect. No physical connection to die.
No Connect. No physical connection to die.
Shared Muxed Output. Muxed output shared by PMU MEASOUT Channel 0, PMU
MEASOUT Channel 1, and the temperature sense and temperature sense GND
reference.
Device Under Test Ground Reference.
Analog Ground.
Analog Ground.
Serial Peripheral Interface (SPI®) Chip Select.
16-Bit DAC Monitor Mux Output.
Supply −5.75 V.
Supply +10.0 V.
Digital Ground.
Serial Programmable Interface (SPI) Data Output.
Serial Programmable Interface (SPI) Clock.
Serial Programmable Interface (SPI) Data Input.
Supply +10.0 V.
Supply +3.3 V.
Supply −5.75 V.
Serial Peripheral Interface (SPI) Reset.
Analog Ground.
Analog Ground.
Analog Ground.
+5 V DAC Reference Voltage.
DAC Ground Reference.
No Connect. No physical connection to die.
No Connect. No physical connection to die.
No Connect. No physical connection to die.
No Connect. No physical connection to die.
Analog Ground.
Analog Ground.
Analog Ground.
High-Side Comparator Output (Negative) Channel 0.
High-Side Comparator Output (Positive) Channel 0.
Comparator Supply Channel 0.
Low-Side Comparator Output (Negative) Channel 0.
Low-Side Comparator Output (Positive) Channel 0.
Analog Ground.
Receive Data Input (Positive) Channel 0.
Rev. 0 | Page 21 of 56
ADATE305
Pin No.
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
EP
Mnemonic
RCV0N
VSS
FFCAP_0A
DATA0P
DATA0N
OVD_CH0
VDD
FFCAP_0B
SCAP0
VPLUS
HVOUT
NC
NC
NC
NC
PMUS_CH0
VSS
VDD
VSSO_0 (DRIVE)
DUT0
VDDO_0 (DRIVE)
AGND
AGND
VSS
VDD
AGND
VDD
VSS
AGND
AGND
VDDO_1 (DRIVE)
DUT1
VSSO_1 (DRIVE)
VDD
VSS
PMUS_CH1
NC
NC
Description
Receive Data Input (Negative) Channel 0.
Supply −5.75 V.
PMU Feedforward Capacitor Connection A Channel 0 (220 pF).
Driver Data Input (Positive) Channel 0.
Driver Data Input (Negative) Channel 0.
Overvoltage Detection Flag Output Channel 0.
Supply +10.0 V.
PMU Feedforward Capacitor Connection B Channel 0 (220 pF).
PMU Stability Capacitor Connection Channel 0 (330 pF).
Supply +16.75 V.
High Voltage Driver Output.
No Connect. No physical connection to die.
No Connect. No physical connection to die.
No Connect. No physical connection to die.
No Connect. No physical connection to die.
PMU External Sense Path Channel 0.
Supply −5.75 V.
Supply +10.0 V.
Driver Output Supply −5.75 V Channel 0.
Device Under Test Channel 0.
Driver Output Supply +10.0 V Channel 0.
Analog Ground.
Analog Ground.
Supply −5.75 V.
Supply +10.0 V.
Analog Ground.
Supply +10.0 V.
Supply −5.75 V.
Analog Ground.
Analog Ground.
Driver Output Supply +10.0 V Channel 1.
Device Under Test Channel 1.
Driver Output Supply −5.75 V Channel 1.
Supply +10.0 V.
Supply −5.75 V.
PMU External Sense Path Channel 1.
No Connect. No physical connection to die.
No Connect. No physical connection to die.
Exposed Pad. The exposed pad is connected to VSS.
Rev. 0 | Page 22 of 56
ADATE305
TYPICAL PERFORMANCE CHARACTERISTICS
0.30
1.6
0.5V
0.25
3V
1.4
1.2
0.20
VOLTAGE (V)
VOLTAGE (V)
1.0
0.15
0.2V
0.10
2V
0.8
0.6
1V
0.4
0.05
0.2
0
2
4
6
8
10
12
14
16
18
TIME (ns)
–0.2
Figure 3. Driver Small Signal Response; VH = 0.2 V, 0.5 V;
VL = 0.0 V; 50 Ω Termination
1.0
1.5
2.0
2.5
TIME (ns)
3.0
3.5
4.0
4.5
1.8
3V
1.4
1.6
3V
1.4
1.2
1.2
1.0
2V
VOLTAGE (V)
0.8
0.6
1V
0.4
1.0
2V
0.8
0.6
1V
0.4
0.2
0.2
0
0
2
4
6
8
10
TIME (ns)
12
14
16
18
–0.2
07280-024
0
0
2
3
4
5
6
7
8
07280-021
VOLTAGE (V)
0.5
Figure 6. 50 MHz Driver Response; VH = 1.0 V, 2.0 V, 3.0 V;
VL = 0.0 V, 50 Ω Termination
1.6
–0.2
0
07280-022
0
07280-023
–0.05
0
9 10 11 12 13 14 15 16 17 18 19
TIME (ns)
Figure 7. 100 MHz Driver Response; VH = 1.0 V, 2.0 V, 3.0 V;
VL = 0.0 V; 50 Ω Termination
Figure 4. Driver Large Signal Response; VH = 1.0 V, 2.0 V, 3.0 V;
VL = 0.0 V; 50 Ω Termination
1.6
6
5V
3V
1.4
5
1.2
VOLTAGE (V)
2V
3V
3
2
1V
1
0
0.8
0.6
1V
0.2
0
2
4
6
8
10
TIME (ns)
12
14
16
18
0
Figure 5. Driver Large Signal Response; VH = 1.0 V, 3.0 V, 5.0 V;
VL = 0 .0 V; 500 Ω Termination
0
1
2
3
4
5
6
TIME (ns)
7
8
9
Figure 8. Response at 200 MH; VH = 1.0 V, 2.0 V, 3.0 V;
VL = 0.0 V; 50 Ω Termination
Rev. 0 | Page 23 of 56
10
07280-032
–1
1.0
0.4
07280-031
VOLTAGE (V)
4
ADATE305
0.6
1.6
1.4
0.5
3V
0.4
1.0
VOLTAGE (V)
VOLTAGE (V)
1.2
2V
0.8
0.6
1V
0.3
0.2
0.4
0.5V
0
0
07280-026
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
TIME (ns)
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19
TIME (ns)
07280-028
0.1
0.2
Figure 12. Driver Active (VH and VL) to and from VTERM Transition;
VH = 1.0 V, VT = 0.5 V, VL = 0.0 V
Figure 9. 300 MHz Driver Response; VH = 0.5 V, 1.0 V, 2.0 V, 3.0 V;
VL = 0.0 V; 50 Ω Termination
1.2
0.9
3V
0.8
1.0
0.7
2V
0.8
0.5
VOLTAGE (V)
VOLTAGE (V)
0.6
1V
0.4
0.6
0.4
0.3
0.5V
0.2
0.2
0
0.5
1.0
1.5
2.0
2.5
3.0
TIME (ns)
3.5
4.0
4.5
0
07280-027
0
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19
TIME (ns)
Figure 10. 400 MHz Driver Response; VH = 0.5 V, 1.0 V, 2.0 V, 3.0 V;
VL = 0.0 V; 50 Ω Termination
07280-029
0.1
Figure 13. Driver Active (VH and VL) to and from VTERM Transition;
VH = 2.0 V, VT = 1.0 V, VL = 0.0 V
1.2
1.6
1.4
1.0
1.2
1.0
VOLTAGE (V)
VOLTAGE (V)
0.8
0.6
0.4
0.8
0.6
0.4
0.2
0.2
200
250
300
350
400
450
FREQUENCY (MHz)
500
550
600
–0.2
07280-084
0
0
2
4
6
8
10
TIME (ns)
Figure 11. Driver Toggle Rate, VH = 2.0 V, VL = 0.0 V, 50 Ω Termination
Rev. 0 | Page 24 of 56
12
14
16
18
20
07280-030
0
Figure 14. Driver Active (VH and VL) to and from VTERM Transition;
VH = 3.0 V, VT = 1.5 V, VL = 0.0 V
ADATE305
20
40
2V NEG
0
0.2V NEG
TRAILING EDGE ERROR (ps)
TRAILING EDGE ERROR (ps)
20
0.2V POS
–20
–40
–60
0
2V POS
–20
–40
–60
1
2
3
4
PULSEWIDTH (ns)
5
6
7
8 9 10
–100
Figure 15. Driver Minimum Pulse Width; VH = 0.2 V, VL = 0.0 V
1
2
3
4
PULSEWIDTH (ns)
5
6
7
8 9 10
07280-034
–80
07280-036
–80
Figure 18. Driver Minimum Pulse Width; VH = 2.0 V, VL = 0.0 V
20
40
0
TRAILING EDGE ERROR (ps)
TRAILING EDGE ERROR (ps)
20
0.5V NEG
0.5V POS
–20
–40
3V POS
3V NEG
0
–20
–40
–60
1
2
3
4
PULSEWIDTH (ns)
5
6
7
8 9 10
–100
07280-037
–60
1
2
3
4
PULSE WIDTH (ns)
5
6
7
8 9 10
07280-035
–80
Figure 19. Driver Minimum Pulse Width; VH = 3.0 V, VL = 0.0 V
Figure 16. Driver Minimum Pulse Width; VH = 0.5 V, VL = 0.0 V
1.5
10
1V NEG
1.0
LINEARITY ERROR (mV)
–10
1V POS
–20
–30
–40
0
–0.5
–1.0
1
2
3
4
PULSEWIDTH (ns)
5
6
7
8 9 10
–2.0
–2
–1
0
1
2
3
4
5
DRIVER OUTPUT VOLTAGE (V)
Figure 20. Driver VH Linearity Error
Figure 17. Driver Minimum Pulse Width; VH = 1.0 V, VL = 0.0 V
Rev. 0 | Page 25 of 56
6
7
07280-051
–60
0.5
–1.5
–50
07280-033
TRAILING EDGE ERROR (ps)
0
ADATE305
100
1.5
90
DRIVER OUTPUT CURRENT (mA)
LINEARITY ERROR (mV)
1.0
0.5
0
–0.5
–1.0
80
70
60
50
40
30
20
10
0
1
2
3
4
DRIVER OUTPUT VOLTAGE (V)
5
07280-052
–1
–10
–2
6
–1
0
1
2
VDUTx (V)
3
4
5
6
07280-055
0
–1.5
–2
Figure 24. Driver Output Current Limit; Driver Programmed to −2.0 V;
VDUTx Swept from −2.0 V to +6.0 V
Figure 21. Driver VL Linearity Error
0
1.5
–10
DRIVER OUTPUT CURRENT (mA)
0.5
0
–0.5
–1.0
–1.5
–30
–40
–50
–60
–70
–80
–90
–1
0
1
2
3
4
DRIVER OUTPUT VOLTAGE (V)
5
6
–100
–2
07280-053
–2.0
–2
–20
Figure 22. Driver VT Linearity Error
–1
0
1
2
VDUTx (V)
3
4
5
6
07280-056
LINEARITY ERROR (mV)
1.0
Figure 25. Driver Output Current Limit; Driver Programmed to 6.0 V;
VDUTx Swept from −2.0 V to +6.0 V
48.5
–722
LINEARITY ERROR (mV)
47.5
47.0
46.5
–724
–725
–726
–727
–728
46.0
–60
–40
–20
0
20
DRIVER OUTPUT CURRENT (mA)
40
60
–730
–1
0
1
2
3
4
VL PROGRAMMED VOLTAGE (V)
Figure 26. HVOUT VL Linearity Error
Figure 23. Driver Output Resistance vs. Output Current
Rev. 0 | Page 26 of 56
5
6
07280-057
–729
007280-054
DRIVER OUTPUT RESISTANCE (Ω)
–723
48.0
ADATE305
1.0
6
RISE INPUT
4
0.8
RISE SHMOO
0
VOLTAGE (V)
LINEARITY ERROR (mV)
2
–2
–4
0.6
0.4
–6
–8
FALL SHMOO
0.2
FALL INPUT
5
6
7
8
9
10
11
12
VL PROGRAMMED VOLTAGE (V)
13
14
0
07280-058
–12
0
0.6
1.8
2.4
3.0
TIME (ns)
Figure 30. Comparator Shmoo, 1.0 V Input, 1.0 ns (10% to 90%) Input,
50 Ω Terminated
Figure 27. HVOUT VHH Linearity Error
1.6
80
RISE INPUT
70
60
1.2
50
VOLTAGE (V)
HVOUT DRIVER CURRENT (mA)
1.2
07280-049
–10
40
30
RISE SHMOO
0.8
20
FALL SHMOO
0.4
10
FALL INPUT
0
1
2
3
VHVOUT (V)
4
5
6
0
07280-059
–10
–1
Figure 28. HVOUT VH Current Limit; VH = −0.1 V;
VHVOUT Swept from −0.1 V to +6.0 V
0
0.6
2.4
3.0
Figure 31. Comparator Shmoo, 1.5 V Input, 1.5 ns (10% to 90%) Input,
50 Ω Terminated
80
1.6
RISE INPUT
60
40
1.2
VOLTAGE (V)
20
0
–20
–40
RISE SHMOO
0.8
FALL SHMOO
0.4
FALL INPUT
–80
5
6
7
8
9
10
11
VHVOUT (V)
12
13
14
Figure 29. HVOUT VHH Current Limit; VHH = 10.0 V;
VHVOUT Swept from −5.9 V to +14.1 V
15
0
0
0.6
1.2
1.8
TIME (ns)
2.4
3.0
07280-047
–60
07280-060
HVOUT DRIVER CURRENT (mA)
1.2
1.8
TIME (ns)
07280-048
0
Figure 32. Comparator Shmoo, 1.5 V Input, 1.2 ns (10% to 90%) Input,
50 Ω Terminated
Rev. 0 | Page 27 of 56
ADATE305
100
1.6
VOLTAGE (V)
1.2
RISE SHMOO
0.8
0.4
FALL SHMOO
FALL INPUT
0
0.6
1.2
1.8
TIME (ns)
2.4
3.0
50
25
RISING
0
FALLING
–25
–50
0.5
07280-046
0
TOTAL
75
Figure 33. Comparator Shmoo, 1.5 V Input, 1.0 ns (10% to 90%) Input,
50 Ω Terminated
1.0
1.5
2.0
INPUT SLEW RATE (10%-90%) (ns)
07280-050
PROPAGATION DELAY VARIATION (ps)
RISE INPUT
2.5
Figure 36. Comparator Slew Rate Dispersion, Input Swing = 1.5 V,
Comparator Threshold = 0.75 V
1.6
1.6
RISE INPUT
COMP_QH0P
1.4
COMP_QH0N
1.2
RISE SHMOO
VOLTAGE (V)
0.8
0.4
0.6
1.2
1.8
2.4
3.0
0
0
5
10
15
20
25
30
35
40
45
50
TIME (ns)
Figure 34. Comparator Shmoo, 1.5 V Input, 0.625 ns (10% to 90%) Input,
50 Ω Terminated
07280-025
0.6
0.2
07280-045
0
FALL INPUT
TIME (ns)
Figure 37. Comparator Output Waveform, COMP_QH0P, COMP_QH0N
0.8
10
0.6
0
0.4
LINEARITY ERROR (mV)
–10
–20
–30
1V POS
–40
–50
1V NEG
–60
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
–70
–1.2
–80
1
2
3
4
PULSEWIDTH (ns)
5
6
7
8 9 10
–1.4
–2
07280-038
TRAILING EDGE ERROR (ps)
0.8
0.4
FALL SHMOO
0
1.0
–1
0
1
2
3
4
5
PROGRAMMED THRESHOLD VOLTAGE (V)
Figure 38. Comparator Threshold Linearity
Figure 35. Comparator Minimum Pulse Width, 1.0 V
Rev. 0 | Page 28 of 56
6
07280-061
VOLTAGE (V)
1.2
0.8
2.0
0.6
1.8
0.4
LINEARITY ERROR (mV)
2.2
1.4
1.2
1.0
0.8
0.2
0
–0.2
–0.4
0.6
–0.6
0.4
–0.8
–1
0
1
2
3
INPUT COMMON-MODE VOLTAGE (V)
4
5
–1
–2
IDUTx (nA)
6
0
–5
5
6
2.8
2.6
2.4
2.2
0
1
2
3
4
5
6
VDUTx (V)
2.0
–2
07280-063
–1
Figure 40. Active Load Commutation Response; VCOM = 2.0 V;
IOH = IOL = 12 mA
4
2.5
2
2.0
IDUTx (nA)
3.0
0
–2
–6
0
–0.5
–2
07280-064
12
2
VDUTx (V)
3
4
1.0
0.5
10
1
1.5
–4
4
6
8
ACTIVE LOAD CURRENT (mA)
0
Figure 43. DUTx Pin Leakage in Low Leakage Mode
6
2
–1
07280-067
LOAD CURRENT (mA)
5
3.0
5
–10
LINEARITY ERROR (µA)
4
3.2
10
0
1
2
3
VCOM VOLTAGE (V)
3.4
15
–8
0
Figure 42. Active Load VCOM Linearity
Figure 39. Differential Comparator CMRR
–15
–2
–1
Figure 41. Active Load Current Linearity
–1
0
1
2
VDUTx (V)
3
4
Figure 44. DUTx Pin Leakage in High-Z Mode
Rev. 0 | Page 29 of 56
5
6
07280-066
0.2
–2
07280-065
1.6
07280-062
DIFFERENTIAL COMPARATOR OFFSET (mV)
ADATE305
ADATE305
40
0.008
20
0.006
LINEARITY ERROR (µA)
LINEARITY ERROR (µA)
0
–20
–40
–60
–80
0.004
0.002
0
–0.002
–100
–30
–20
–10
0
10
20
PMU OUTPUT CURRENT (mA)
30
–0.006
–0.020 –0.015 –0.010 –0.005
0
0.005 0.010
PMU OUTPUT CURRENT (mA)
07280-068
–140
–40
40
0.015
0.020
07280-071
–0.004
–120
Figure 48. PMU Force Current Range D Linearity
Figure 45. PMU Force Current Range A Linearity
0.0005
0.8
0.0004
0.0003
0.4
LINEARITY ERROR (µA)
LINEARITY ERROR (µA)
0.6
0.2
0
–0.2
–0.4
0.0002
0.0001
0
–0.0001
–0.0002
–0.0003
–0.0004
–0.6
–1.5
–1.0
–0.5
0
0.5
1.0
PMU OUTPUT CURRENT (mA)
1.5
2.0
–0.0006
–0.0020 –0.0015 –0.0010 –0.0050 0
0.0050 0.0010 0.0015 0.0020
PMU OUTPUT CURRENT (mA)
Figure 49. PMU Force Current Range E Linearity
Figure 46. PMU Force Current Range B Linearity
5
0.08
4
PMU VOLTAGE ERROR (mV)
0.04
0.02
0
–0.02
–0.04
3
2
1
0
–1
–2
–0.15
–0.10 –0.05
0
0.05
0.10
PMU OUTPUT CURRENT (mA)
0.15
Figure 47. PMU Force Current Range C Linearity
0.20
–4
–40
–30
–20
–10
0
10
IDUTx (mA)
20
30
40
07280-073
–3
07280-070
LINEARITY ERROR (µA)
0.06
–0.06
–0.20
07280-072
–0.0005
07280-069
–0.8
–2.0
Figure 50. PMU Force Voltage Range A Output Voltage Error at 6.0 V vs.
Output Current
Rev. 0 | Page 30 of 56
ADATE305
5
10
0
3
PMU CURRENT ERROR (µA)
2
1
0
–1
–2
–10
0
10
IDUTx (mA)
20
30
40
–40
–60
–2
0.6
10
0.4
0
0.2
0
–0.2
–0.4
1
2
VDUTx (V)
3
4
5
6
–10
–20
–30
–40
–0.5
0
0.5
IDUTx (mA)
1.0
1.5
2.0
–60
–2
–1
0
1
2
VDUTx (V)
3
4
5
6
07280-078
–1.0
07280-075
–1.5
Figure 52. PMU FV Range B Output Voltage Error at 6.0 V vs. Output Current
Figure 55. PMU FI Range A Output Current Error at +32 mA vs. Output
Voltage; Output Voltage Is Pulled Externally
0.5
0.4
0.4
PMU CURRENT ERROR (µA)
0.6
0.2
0
–0.2
–0.4
–0.6
0.3
0.2
0.1
0
–0.1
–1.5
–1.0
–0.5
0
0.5
IDUTx (mA)
1.0
1.5
2.0
–0.2
–2
07280-076
–0.8
–2.0
0
–50
–0.6
–0.8
–2.0
–1
Figure 54. PMU FI Range A Output Current Error at −32 mA vs. Output
Voltage; Output Voltage Is Pulled Externally
PMU CURRENT ERROR (µA)
PMU VOLTAGE ERROR (mV)
–30
07280-077
–20
07280-074
–30
Figure 51. PMU FV Range A Output Voltage Error at −1.5 V vs. Output Current
PMU VOLTAGE ERROR (mV)
–20
–50
–3
–4
–40
–10
Figure 53. PMU FV Range B Output Voltage Error at −1.5 V vs. Output Current
–1
0
1
2
VDUTx (V)
3
4
5
6
07280-079
PMU VOLTAGE ERROR (mV)
4
Figure 56. PMU FI Range B Output Current Error at −2 mA vs. Output Voltage;
Output Voltage Is Pulled Externally
Rev. 0 | Page 31 of 56
0.7
0.45
0.6
0.40
0.5
0.35
PMU VOLTAGE ERROR (mV)
0.4
0.3
0.2
0.1
0
0.30
0.25
0.20
0.15
0.10
0.05
–0.1
–1
0
1
2
3
4
5
6
VDUTx (V)
0
–2
07280-080
–0.2
–2
Figure 57. PMU FI Range B Output Current Error at +2 mA vs. Output Voltage;
Output Voltage Is Pulled Externally
–1
0
1
2
VDUTx (V)
3
4
5
07280-083
PMU CURRENT ERROR (µA)
ADATE305
Figure 60. PMU Measure Current CMRR, Externally Pulling 1 mA, FVMI; Error
of MI vs. External 1 mA
0.0010
89mV/DIV
0.0005
0
–0.0010
–2
–1
0
1
2
VDUTx (V)
3
4
5
6
Figure 58. PMU FI Range E Output Current Error at −2 μA vs. Output Voltage;
Output Voltage Is Pulled Externally
960ps/DIV
07280-039
–0.0005
07280-081
PMU CURRENT ERROR (µA)
0.0015
Figure 61. Eye Diagram, 200 Mbps, PRBS31; VH = 1.0 V, VL = 0.0 V
0.0016
0.0012
0.0010
89mV/DIV
PMU CURRENT ERROR (µA)
0.0014
0.0008
0.0006
0.0004
0.0002
–1
0
1
2
VDUTx (V)
3
4
5
6
Figure 59. PMU FI Range E Output Current Error at +2 μA vs. Output Voltage;
Output Voltage Is Pulled Externally
Rev. 0 | Page 32 of 56
400ps/DIV
07280-040
–0.0002
–2
07280-082
0
Figure 62. Eye Diagram, 400 Mbps, PRBS31; VH = 1.0 V, VL = 0.0 V
250ps/DIV
07280-043
07280-044
200ps/DIV
07280-042
Figure 65. Eye Diagram, 400 Mbps, PRBS31; VH = 2.0 V, VL = 0.0 V
130mV/DIV
400ps/DIV
Figure 63. Eye Diagram, 600 Mbps, PRBS31; VH = 1.0 V, VL = 0.0 V
100mV/DIV
250ps/DIV
07280-041
130mV/DIV
100mV/DIV
ADATE305
Figure 66. Eye Diagram, 600 Mbps, PRBS31; VH = 2.0 V, VL = 0.0 V
Figure 64. Eye Diagram, 800 Mbps, PRBS31; VH = 1.0 V, VL = 0.0 V
Rev. 0 | Page 33 of 56
ADATE305
SPI DETAILS
tCH
SCLK
tCL
tCSSA
tCSHA
tCSHD
tCSSD
CS
tCSW
tDH
tDS
SDOUT
DATA[15]
DATA[14]
DO_15 LAST
DO_14 LAST
CH[1]
R/W
DO_13 LAST
DO_12 LAST
ADDR[1]
DO_2LAST
ADDR[0]
DO_1LAST
07280-003
SDIN
DO_0LAST
tDO
Figure 67. SPI Timing Diagram
Table 17. Serial Peripheral Interface Timing Requirements
Symbol
tCH
tCL
tCSHA
tCSSA
tCSHD
tCSSD
tDH
tDS
tDO
tCSW
tCSTP
1
Parameter
SCLK minimum high
SCLK minimum low
CS assert hold
CS assert setup
CS deassert hold
CS deassert setup
SDIN hold
SDIN setup
SDOUT Data Out
CS minimum between assertions 1
CS minimum directly after a read request
Minimum delay after CS is deasserted before SCLK can be
stopped (not shown in Figure 67); this allows any internal
operations to complete
An extra cycle is needed after a read request to prime the read data into the SPI shift register.
Rev. 0 | Page 34 of 56
Min
9.0
9.0
3.0
3.0
3.0
3.0
3.0
3.0
Max
15.0
2
3
16
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCLK cycles
SCLK cycles
SCLK cycles
ADATE305
DEFINITION OF SPI WORD
Table 18. Channel Selection
The SPI can accept variable length words, depending on the
operation. At most, the word length equals 24 bits: 16 bits of
data, two channel selects, one R/W selector, and a 5-bit address.
Channel 1
0
Channel 0
0
0
1
1
1
0
1
Depending on the operation, the data can be smaller or, in the
case of a read operation, nonexistent.
Channel Selected
NOP (no channel selected, no register
changes)
Channel 0 selected
Channel 1 selected
Channel 0 and Channel 1 selected
Table 19. R/W Definition
R/W
0
Description
Current register specified by address shifts out of
SDOUT on next shift operation
Current data is written to the register specified by
address and channel select
1
Example 1: 16-Bit Write
DATA[15:0]
CH[1:0]
R/W
07280-004
Write 16 bits of data to a register or DAC; ignore unused MSBs. For example, Bit 15 and Bit 14 are ignored, and Bit 13 through Bit 0 are
applied to the 14-bit DAC.
ADDR[4:0]
Figure 68. 16-Bit Write
Example 2: 14-Bit Write
DATA[13:0]
CH[1:0]
R/W
ADDR[4:0]
07280-005
Write 14 bits of data to the DAC.
Figure 69. 14-Bit Write
Example 3a: 2-Bit Write
DATA[1:0]
CH[1:0]
R/W
ADDR[4:0]
07280-006
Write two bits of data to the 2-bit register.
Figure 70. 2-Bit Write
Example 3b: 2-Bit Write
DATA[15:0]
CH[1:0]
R/W
07280-007
Write two bits of data to the 2-bit register. Bit 15 through Bit 2 are ignored and Bit 1 through Bit 0 are applied to the register.
ADDR[4:0]
Figure 71. 2-Bit Write
Example 4: Read Request
DATA[15:0]
CH[1:0]
R/W = 0
ADDR[4:0]
CH[1:0]
R/W
ADDR[4:0]
Figure 72. Read Request
Rev. 0 | Page 35 of 56
07280-008
Read request and follow with a second instruction (could be NOP) to clock out the data.
ADATE305
WRITE OPERATION
CS
INPUT
SCLK
INPUT
SDIN
INPUT
DATA[2] DATA[1] DATA[0]
DATA[15] DATA[14] DATA[13]
0
1
2
13
14
15
CH[1]
CH[0]
R/W
16
17
18
SDOUT
OUTPUT
ADDR[4]
19
ADDR[3]
20
ADDR[2]
21
ADDR[1]
22
X
ADDR[0]
23
24
25
X
07280-009
NOTES
1. R/W = 1.
2. X = DON’T CARE.
Figure 73. 16-Bit SPI Write
CS
INPUT
SCLK
INPUT
SDIN
INPUT
DATA[1] DATA[0]
0
SDOUT
OUTPUT
1
CH[1]
CH[0]
R/W
2
3
4
ADDR[4] ADDR[3] ADDR[2] ADDR[1] ADDR[0]
5
6
7
8
X
9
10
11
X
07280-010
NOTES
1. R/W = 1.
2. X = DON’T CARE.
Figure 74. 2-Bit SPI Write
Rev. 0 | Page 36 of 56
ADATE305
back the previous specified data. The NOP address can be used
for this read if there is no need to write/read another register. To
maintain the clarity of the operation, it is strongly recommended
that the NOP address be used for all reads.
READ OPERATION
The read operation is a two-stage operation. First, a word is
shifted in, specifying which register to read. CS is deasserted
for three clock cycles, and then a second word is shifted in to
obtain the readback data. This second word can be either
another operation or an NOP address. If another operation is
shifted in, it needs to shift in at least eight bits of data to read
Any register read that is fewer than 16 bits has zeroes filled in
the top bits to make it a 16-bit word.
CS
INPUT
SCLK
INPUT
SDIN
INPUT
READ INSTRUCTION
SDOUT
OUTPUT
X
NOP
READ DATA
X
07280-011
X
X
NOTES
1. X = DON’T CARE.
Figure 75. SPI Read Overview
CS
INPUT
SCLK
INPUT
SDIN
INPUT
DATA[15:0], VALUE IS A DON’T CARE
0
1
2
13
14
CH[1]
CH[0]
R/W
16
17
18
15
SDOUT
OUTPUT
X
ADDR[4] ADDR[3] ADDR[2] ADDR[1] ADDR[0]
19
20
21
22
23
24
25
07280-012
X
NOTES
1. X = DON’T CARE.
Figure 76. SPI Read—Details of Read Request
CS
INPUT
SCLK
INPUT
SDIN
INPUT
DATA[15:0], VALUE IS A DON’T CARE
0
SDOUT
OUTPUT
RDATA[15]
1
2
RDATA[14]
13
RDATA[2]
CH[1]
14
15
RDATA[1]
RDATA[0]
16
CH[0]
17
ADDR[4:0] = 0x00 (NOP)
R/W = 1
18
19
21
22
23
24
25
X
07280-013
NOTES
1. RDATA IS THE REGISTER VALUE BEING READ.
2. X = DON’T CARE.
20
X
Figure 77. SPI Read—Details of Read Out
Rev. 0 | Page 37 of 56
ADATE305
RESET OPERATION
The ADATE305 contains an asynchronous reset feature. The
ADATE305 can be reset to the default values shown in Table 20
by utilizing the RST pin. To initiate the reset operation, deassert
the RST pin for a minimum of 100 ns and deassert the CS pin
for a minimum of two SCLK cycles.
100ns
MINIMUM
RST
SCLK
MINIMUM OF TWO SCLK EDGES AFTER ASSERTING RST BEFORE RESUMING NORMAL OPERATION.
Figure 78. Reset Operation
Rev. 0 | Page 38 of 56
07280-014
CS
ADATE305
REGISTER MAP
The ADDR[4:0] bits determine the destination register of the data being written to the ADATE305.
Table 20. Register Selection
DATA[15:0]
N/A 1
DATA[13:0]
DATA[13:0]
DATA[13:0]
DATA[13:0]
DATA[13:0]
DATA[13:0]
DATA[13:0]
DATA[13:0]
DATA[13:0]
DATA[13:0]
DATA[13:0]
DATA[15:0]
DATA[2:0]
DATA[2:0]
DATA[9:0]
DATA[2:0]
DATA[0]
DATA[1:0]
DATA[1:0]
DATA[2:0]
N/A
1
CH[1:0]
N/A
CH[1:0]
CH[1:0]
CH[1:0]
CH[1:0]
CH[1:0]
CH[1:0]
CH[1:0]
CH[1:0]
CH[1:0]
CH[1]
CH[0]
CH[1:0]
CH[1:0]
CH[1:0]
CH[1:0]
CH[1:0]
CH[1:0]
CH[1:0]
CH[1:0]
CH[1:0]
N/A
R/W
N/A
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
N/A
ADDR[4:0]
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14 to 0x1F
Register Selected
NOP
VH DAC level
VL DAC level
VT/VCOM DAC level
VOL DAC level
VOH DAC level
VCH DAC level
VCL DAC level
V(IOH ) DAC level
V(IOL ) DAC level
OVD high level
OVD low level
PMUDAC level
PE/PMU enable
Channel state
PMU state
PMU measure enable
Differential comparator enable
16-bit DAC monitor
OVD_CHx alarm mask
OVD_CHx alarm state
Reserved
N/A means not applicable.
Rev. 0 | Page 39 of 56
Reset State
N/A
4096d
4096d
4096d
4096d
4096d
4096d
4096d
4096d
4096d
4096d
4096d
16384d
000b
000b
0d
000b
0b
00b
01b
N/A
N/A
ADATE305
DETAILS OF REGISTERS
Table 21. PE/PMU Enable (ADDR[4:0] = 0x0C)
Bit
DATA[2]
Name
PMU enable
DATA[1]
Force VT
DATA[0]
PE disable
Description
0 = disable PMU force output and clamps, place PMU in MV mode
1 = enable PMU force output
When set to 0, the PMU state bits are ignored, except for PMU sense path (Data[7])
0 = normal driver operation
1 = force driver to VT
See Table 29 for complete functionality of this bit
0 = enable driver functions
1 = disable driver (low leakage)
See Table 29 for complete functionality of this bit
Table 22. Channel State (ADDR[4:0] = 0x0D)
Bit
DATA[2]
Name
HV mode select
DATA[1]
Load enable
DATA[0]
Driver high-Z or VT
Description
0 = HV driver in low impedance.
1 = enable HV driver.
This bit affects Channel 0 only. Ensure that the Channel 0 bit in SPI write is active.
Channel 1 bit in SPI write is don’t care.
0 = disable load.
1 = enable load.
See Table 29 for complete functionality of this bit.
0 = enable Driver high-Z function.
1 = enable Driver VTERM function.
See Table 29 for complete functionality of this bit.
Table 23. PMU State (ADDR[4:0] = 0x0E) 1, 2
Bit
DATA[9:8]
Name
PMU input selection
DATA[7]
PMU sense path
DATA[6]
DATA[5]
Reserved
PMU clamp enable
DATA[4]
PMU measure voltage or current
DATA[3]
PMU force voltage or current
DATA[2:0]
PMU range
1
2
Description
00 = VDUTGND (calibrated for 0.0 V voltage reference)
01 = 2.5 V + VDUTGND (calibrated for 0.0 A current reference)
1X = PMUDAC
0 = internal sense
1 = external sense
0 = disable clamps
1 = enable clamps
0 = measure voltage mode
1 = measure current mode
0 = force voltage mode
1 = force current mode
0XX = 2 μA range
100 = 20 μA range
101 = 200 μA range
110 = 2 mA range
111 = 32 mA range
Note that when ADDR[4:0] = 0x0C, the PMU enable bit (DATA[2]) = 0, PMU force outputs and clamps are disabled, and the PMU is placed into measure voltage mode.
PMU State DATA[9:8] and DATA[6:0] are ignored, and only the DATA[7] PMU sense path is valid.
X = don’t care.
Rev. 0 | Page 40 of 56
ADATE305
Table 24. PMU Measure Enable (ADDR[4:0] = 0x0F) 1
Bit
DATA[2:1]
Name
MEASOUT01 select
DATA[0]
MEASOUT01 output enable
1
Description
00 = PMU MEASOUT Channel 0
01 = PMU MEASOUT Channel 1
10 = Temp sensor ground reference
11 = Temp sensor
0 = MEASOUT01 is tristated
1 = MEASOUT01 is enabled
This register is written to or read from when either of the CH[1:0] bits is 1.
Table 25. Differential Comparator Enable (ADDR[4:0] = 0x10) 1
Bit
DATA[0]
1
Name
Differential Comparator Enable
Description
0 = differential comparator is disabled; the Channel 0 normal window
comparator (NWC) outputs are located on Channel 0
1 = differential comparator is enabled; the differential comparator outputs
are located on Channel 0
This register is written to or read from when either of the CH[1:0] bits is 1.
Table 26. DAC16_MON (16-Bit DAC Monitor) (ADDR[4:0] = 0x11) 1
Bit
DATA[1]
Name
16-Bit DAC mux enable
DATA[0]
16-Bit DAC mux select
1
Description
0 = 16-bit DAC mux is tristated
1 = 16-bit DAC mux is enabled
0 = 16-bit DAC Channel 0
1 = 16-bit DAC Channel 1
This register is written to or read from when either of the CH[1:0] bits is 1.
Table 27. OVD_CHx Alarm Mask (ADDR[4:0] = 0x12)
Bit
DATA[1]
Name
PMU mask
DATA[0]
OVD mask
Description
0 = disable PMU alarm flag
1 = enable PMU alarm flag
0 = disable OVD alarm flag
1 = enable OVD alarm flag
Table 28. OVD_CHx Alarm State (ADDR[4:0] = 0x13) 1
Bit
DATA[2]
Name
PMU clamp flag
DATA[1]
OVD high flag
DATA[0]
OVD low flag
1
Description
0 = PMU is not clamped
1 = PMU is clamped
0 = DUT voltage < OVD high voltage
1 = DUT voltage > OVD high voltage
0 = DUT voltage > OVD low voltage
1 = DUT voltage < OVD low voltage
This register is a read-only register.
Rev. 0 | Page 41 of 56
ADATE305
USER INFORMATION
Table 29. Driver and Load Truth Table 1
PE Disable
DATA[0]
ADDR[4:0] = 0x0C
1
Registers
Force VT
Load Enable
DATA[1]
DATA[1]
ADDR[4:0] = 0x0C ADDR[4:0] = 0x0D
X
X
Driver High-Z/VT
DATA[0]
ADDR[4:0] = 0x0D
X
DATAx
X
RCVx
X
Driver State
High-Z without clamps
Load State
Power-down
0
0
1
0
X
0
X
0
X
0
X
0
VT
VL
Power-down
Power-down
0
0
0
0
0
0
0
0
0
1
1
0
High-Z with clamps
VH
Power-down
Power-down
0
0
0
0
0
0
0
1
1
0
1
0
High-Z with clamps
VL
Power-down
Power-down
0
0
0
0
0
0
1
1
0
1
1
0
VT
VH
Power-down
Power-down
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
VT
VL
High-Z with clamps
VH
High-Z with clamps
VL
High-Z with clamps
VH
High-Z with clamps
Power-down
Active off
Active on
Active off
Active on
Active on
Active on
Active on
Active on
1
Signals
X = don’t care.
Table 30. HVOUT Truth Table 1
HVOUT Mode Select
DATA[2]
ADDR[4:0] =0x0D
1
1
1
0
1
Channel 0
RCV
1
0
0
X
Channel 0
DATA
X
0
1
X
HVOUT Driver Output
VHH mode; VHH = (VT + 1 V) × 2 + DUTGND (Channel 0 VT DAC)
VL (Channel 0 VL DAC)
VH (Channel 0 VH DAC)
Disabled (HVOUT pin set to 0 V low impedance)
X = don’t care.
Table 31. Comparator Truth Table
Differential
Comparator Enable
DATA[0]
ADDR[4:0] = 0x10
0
1
COMP_QH0
Normal window mode
Logic high: VOH0 < VDUT0
Logic low: VOH0 > VDUT0
Differential comparator mode
Logic high: VOH0 < VDUT0 − VDUT1
Logic low: VOH0 > VDUT0 − VDUT1
COMP_QL0
Normal window mode
Logic high: VOL0 < VDUT0
Logic low: VOL0 > VDUT0
Differential comparator mode
Logic high: VOL0 < VDUT0 − VDUT1
Logic low: VOL0 > VDUT0 − VDUT1
Rev. 0 | Page 42 of 56
COMP_QH1
Normal window mode
Logic high: VOH1 < VDUT1
Logic low: VOH1 > VDUT1
Normal window mode
Logic high: VOH1 < VDUT1
Logic low: VOH1 > VDUT1
COMP_QL1
Normal window mode
Logic high: VOL1 < VDUT1
Logic low: VOL1 > VDUT1
Normal window mode
Logic high: VOL1 < VDUT1
Logic low: VOL1 > VDUT1
ADATE305
•
DETAILS OF DACS vs. LEVELS
There are ten 14-bit DACs per channel. These DACs provide
levels for the driver, comparator, load currents, VHH buffer, OVD,
and clamp levels. There are three versions of output levels as
follows:
•
−2.5 V to +7.5 V and tracks DUTGND. Controls the VH,
VL, VT/VCOM/VHH, VOH, VOL, VCH, and VCL levels.
•
−3.0 V to +7.0 V and tracks DUTGND. Controls the
OVD levels.
−2.5 V to +7.5 V and does not track DUTGND. Controls
the IOH and IOL levels.
There is one 16-bit DAC per channel. This DAC provides the
levels for the PMU. The output level is as follows:
•
−2.5 V to +7.5 V and tracks DUTGND; controls the
PMU levels.
Table 32. Level Transfer Functions
DAC Transfer Function
VOUT = 2.0 × (VREF − VREF_GND) × (Code/(214)) – 0.5 × (VREF − VREF_GND) + VDUTGND
Code = [VOUT − VDUTGND + 0.5 × (VREF − VREF_GND)] × [(214)/(2.0 × (VREF − VREF_GND))]
VOUT = 4.0 × (VREF − VREF_GND) × (Code/(214)) − 1.0 × (VREF − VREF_GND) + 2.0 + VDUTGND
Code = [VOUT − VDUTGND − 2.0 + 1.0 × (VREF − VREF_GND)] × [(214)/(4.0 × (VREF − VREF_GND))]
VOUT = 2.0 × (VREF − VREF_GND) × (Code/(214)) − 0.6 × (VREF − VREF_GND) + VDUTGND
Code = [VOUT − VDUTGND + 0.6 × (VREF − VREF_GND)] × [(214)/(2.0 × (VREF − VREF_GND))]
IOUT = [2.0 × (VREF − VREF_GND) × (Code/(214)) − 0.5 × (VREF − VREF_GND)] × (0.012/5.0)
Code = [(IOUT × (5.0/0.012)) + 0.5 × (VREF − VREF_GND)] × [(214)/(2.0 × (VREF − VREF_GND))]
VOUT = 2.0 × (VREF − VREF_GND) × (Code/(216)) – 0.5 × (VREF − VREF_GND) + VDUTGND
Code = [VOUT − VDUTGND + 0.5 × (VREF − VREF_GND)] × [(216)/(2.0 × (VREF − VREF_GND))]
IOUT = [2.0 × (VREF − VREF_GND) × (Code/(216)) – 0.5 × (VREF − VREF_GND) − 2.5] × (0.050/5.0)
Code = [(IOUT × (5.0/0.050)) + 2.5 + 0.5 × (VREF − VREF_GND)] × [(216)/(2.0 × (VREF − VREF_GND))]
IOUT = [2.0 × (VREF − VREF_GND) × (Code/(216)) – 0.5 × (VREF − VREF_GND) − 2.5] × (0.004/5.0)
Code = [(IOUT × (5.0/0.004)) + 2.5 + 0.5 × (VREF − VREF_GND)] × [(216)/(2.0 × (VREF − VREF_GND))]
IOUT = [2.0 × (VREF − VREF_GND) × (Code/(216)) – 0.5 × (VREF − VREF_GND) − 2.5] × (0.0004/5.0)
Code = [(IOUT × (5.0/0.0004)) + 2.5 + 0.5 × (VREF − VREF_GND)] × [(216)/(2.0 × (VREF − VREF_GND))]
IOUT = [2.0 × (VREF − VREF_GND) × (Code/(216)) – 0.5 × (VREF − VREF_GND) − 2.5] × (0.00004/5.0)
Code = [(IOUT × (5.0/0.00004)) + 2.5 + 0.5 × (VREF − VREF_GND)] × [(216)/(2.0 × (VREF − VREF_GND))]
IOUT = [2.0 × (VREF − VREF_GND) × (Code/(216)) – 0.5 × (VREF − VREF_GND) − 2.5] × (0.000004/5.0)
Code = [(IOUT × (5.0/0.000004)) + 2.5 + 0.5 × (VREF − VREF_GND)] × [(216)/(2.0 × (VREF − VREF_GND))]
1
Programmable Range 1
(All 0s to All 1s)
−2.5 V to +7.5 V
−3.0 V to +17.0 V
Levels
VH, VL, VT/VCOM,
VOL, VOH, VCH, VCL
VHH
−3.0 V to +7.0 V
OVD
−6 mA to +18 mA
IOH, IOL
−2.5 V to +7.5 V
PMUDAC
−50 mA to +50 mA
PMUDAC
(PMU FI Range A)
PMUDAC
(PMU FI Range B)
PMUDAC
(PMU FI Range C)
PMUDAC
(PMU FI Range D)
PMUDAC
(PMU FI Range E)
−4 mA to +4 mA
−400 μA to +400 μA
−40 μA to +40 μA
−4 μA to +4 μA
Programmable range includes a margin outside of the specified part performance, allowing for offset/gain calibration.
Table 33. Load Transfer Functions
Load Level
IOL
IOH
1
Transfer Function 1
V(IOL)/5 V × 12 mA
V(IOH)/5 V × 12 mA
V(IOH), V(IOL) DAC levels are not referenced to DUTGND.
Table 34. PMU Transfer Functions
PMU Mode
Force Voltage
Measure Voltage
Force Current
Measure Current
1
Transfer Functions
VOUT = PMUDAC
VMEASOUT01 = VDUTx (internal sense) or VMEASOUT01 = VPMUS_CHx (external sense)
IOUT = [PMUDAC − (VREF/2)]/(R 1 × 5)
VMEASOUT01 = (VREF/2) + VDUTGND + (IDUTx × 5 × R1)
R = 15.5 Ω for Range A; 250 Ω for Range B; 2.5 kΩ for Range C; 25 kΩ for Range D; 250 kΩ for Range E.
Rev. 0 | Page 43 of 56
ADATE305
Table 35. PMU User Required Capacitors
Table 36. Temperature Sensor
Capacitor
220 pF
220 pF
330 pF
330 pF
Temperature
0K
300 K
xK
Location
Across Pin 70 (FFCAP_0B) and Pin 65 (FFCAP_0A)
Across Pin 6 (FFCAP_1B) and Pin 11 (FFCAP_1A)
Between GND and Pin 71 (SCAP0)
Between GND and Pin 5 (SCAP1)
Output
0V
3V
(x K) × 10 mV/K
Table 37. Power Supply Ranges
Parameter
Nominal VDD
Nominal VSS
Driver
VH range
VL range
VT range
Functional Amplitude
Reflection Clamp
VCH Range
VCL Range
Comparator Input Voltage Range
Active Load VCOM Range
PMU
Force Voltage Range
Measure Voltage Range
Force Current Voltage Range
Measure Current Voltage Range
Low Clamp Range
High Clamp Range
Range 1
+10.0 V
−5.25 V
Range 2
+10.0 V
−5.75 V
−1.4 V to +6.0 V
−1.5 V to +5.9 V
−1.5 V to +6.0 V
7.5 V
−1.9 V to +6.0 V
−2.0 V to +5.9 V
−2.0 V to +6.0 V
8.0 V
−1.0 V to +6.0 V
−1.5 V to +5.0 V
−1.5 V to +6.0 V
−1.25 V to +5.75 V
−1.5 V to +6.0 V
−2.0 V to +5.0 V
−2.0 V to +6.0 V
−1.75 V to +5.75 V
−1.5 V to +6.0 V
−1.5 V to +6.0 V
−1.5 V to +6.0 V
−1.5 V to +6.0 V
−1.5 V to +4.0 V
0.0 V to +6.0 V
−2.0 V to +6.0 V
−2.0 V to +6.0 V
−2.0 V to +6.0 V
−2.0 V to +6.0 V
−2.0 V to +4.0 V
0.0 V to +6.0 V
Rev. 0 | Page 44 of 56
ADATE305
Table 38. Default Test Conditions (Range 1)
Name
VH DAC Level
VL DAC Level
VT/VCOM DAC Level
VOL DAC Level
VOH DAC Level
VCH DAC Level
VCL DAC Level
IOH DAC Level
IOL DAC Level
OVD Low DAC Level
OVD High DAC Level
PMUDAC DAC Level
PE/PMU Enable
Channel State
PMU State
PMU Measure Enable
Differential Comparator Enable
16-Bit DAC Monitor
OVD_CHx Alarm Mask
Data Input
Receive Input
DUTx Pin
Comparator Output
Default Test Condition
+2.0 V
+0.0 V
+1.0 V
−1.0 V
+6.0 V
+7.5 V
−2.5 V
0.0 A
0.0 A
−2.5 V
+6.5 V
0.0 V
0x0000: PMU disabled, VT not forced through driver, PE enabled
0x0000: HV mode disabled, load disabled, VTERM inactive
0x0000: Input of DUTGND, internal sense, clamps disabled, FVMV, Range E
0x0000: MEASOUT01 pin tristated
0x0000: Normal window comparator mode
0x0000: DAC16_MON tristated
0x0000: disable alarm functions
Logic low
Logic low
Unterminated
Unterminated
Rev. 0 | Page 45 of 56
ADATE305
RECOMMENDED PMU MODE SWITCHING
SEQUENCES
To minimize any possible aberrations and voltage spikes on the
DUT output, specific mode switching sequences are
recommended for the following transitions:
•
•
•
PMU disable to PMU enable.
PMU force voltage mode to PMU force current mode.
PMU force current mode to PMU force voltage mode.
PMU Disable to PMU Enable
Note that in Table 39 through Table 49, X indicates the don’t care bit.
Step 1. Table 39 lists the state of the registers in PMU disabled mode.
Table 39.
Register
PE/PMU Enable Register, ADDR[4:0] = 0x0C
PMU State Register, ADDR[4:0] = 0x0E
Bits
DATA[2]
DATA[9:8]
DATA[7]
DATA[6]
DATA[5]
DATA[4]
DATA[3]
DATA[2:0]
Setting
0
XX
X
X
X
X
X
XXX
Step 2. Write to Register ADDR[4:0] = 0x0E (see Table 40).
Table 40.
Register
PMU State Register, ADDR[4:0] = 0x0E
Bits
DATA[9:8]
DATA[7]
DATA[6]
DATA[5]
DATA[4]
DATA[3]
Setting
1X or 00
X
X
X
X
0
Comments
Set desired input selection
DATA[2:0]
XXX
This bit must be set to force voltage mode to reduce
aberrations
Set desired range
Setting
1
Comments
PMU is now enabled in force voltage mode
Step 3. Write to Register ADDR[4:0] = 0x0C (see Table 41).
Table 41.
Register
PE/PMU Enable Register, ADDR[4:0] = 0x0C
Bits
DATA[2]
PMU Force Voltage Mode to PMU Force Current Mode
Step 1. Table 42 lists the state of registers in force voltage mode.
Table 42.
Register
PE/PMU Enable Register, ADDR[4:0] = 0x0C
PMU State Register, ADDR[4:0] = 0x0E
Bits
DATA[2]
DATA[9:8]
DATA[7]
DATA[6]
DATA[5]
DATA[4]
DATA[3]
DATA[2:0]
Setting
1
XX
X
X
X
X
0
XXX
Rev. 0 | Page 46 of 56
ADATE305
Step 2. Write to Register ADDR[4:0] = 0x0E (see Table 43).
Table 43.
Register
PMU State Register, ADDR[4:0] = 0x0E
Bits
DATA[9:8]
DATA[7]
DATA[6]
DATA[5]
DATA[4]
DATA[3]
DATA[2:0]
Setting
01
X
X
X
X
1
0XX
Comments
Set 2.5 V + DUTGND input selection
Setting
X
Comments
Update the VIN 16-Bit DAC register to the
desired value
Setting
1X
X
X
X
X
1
XXX
Comments
Set VIN input selection
Set to force current mode
2 μA range has the minimum offset current
Step 3. Write to Register ADDR[4:0] = 0x0B (see Table 44).
Table 44.
Register
VIN 16-Bit DAC, ADDR[4:0] = 0x0B
Bits
DATA[15:0]
Step 4. Write to Register ADDR[4:0] = 0x0E (see Table 45).
Table 45.
Register
PMU State Register, ADDR[4:0] = 0x0E
Bits
DATA[9:8]
DATA[7]
DATA[6]
DATA[5]
DATA[4]
DATA[3]
DATA[2:0]
Set to the desired current range
Transition from PMU Force Current Mode to PMU Force Voltage Mode
Step 1. Table 46 lists the state of the registers in force current mode.
Table 46.
Register
PE/PMU Enable Register, ADDR[4:0] = 0x0C
PMU State Register, ADDR[4:0] = 0x0E
Bits
DATA[2]
DATA[9:8]
DATA[7]
DATA[6]
DATA[5]
DATA[4]
DATA[3]
DATA[2:0]
Setting
1
XX
X
X
X
X
1
XXX
Step 2. Write to Register ADDR[4:0] = 0x0E (see Table 47).
Table 47.
Register
PMU State Register, ADDR[4:0] = 0x0E
Bits
DATA[9:8]
DATA[7]
DATA[6]
DATA[5]
DATA[4]
DATA[3]
DATA[2:0]
Setting
00
X
X
X
X
0
XXX
Rev. 0 | Page 47 of 56
Comments
Set DUTGND input selection
Set to force voltage mode
Set to the desired current range
ADATE305
Step 3. Write to Register ADDR[4:0] = 0x0B (see Table 48).
Table 48.
Register
VIN 16-Bit DAC, ADDR[4:0] = 0x0B
Bits
DATA[15:0]
Setting
X
Comments
Update the VIN 16-Bit DAC register to the desired value
Setting
1X
X
X
X
X
0
XXX
Comments
Set VIN input selection
Step 4. Write to Register ADDR[4:0] = 0x0E (see Table 49).
Table 49.
Register
PMU State Register, ADDR[4:0] = 0x0E
Bits
DATA[9:8]
DATA[7]
DATA[6]
DATA[5]
DATA[4]
DATA[3]
DATA[2:0]
Force voltage mode
Rev. 0 | Page 48 of 56
ADATE305
BLOCK DIAGRAMS
VCL
VCH
PE DISABLE DATA[0] (ADDR[4:0] = 0x0C)
FORCES SWITCH OPEN WHEN 1
VH
ROUT = 47Ω
(TRIMMED)
DRIVER
VL
DUT
DATA
VT
DRIVER HIGH-Z/VT DATA[0]
(ADDR[4:0] = 0x0D)
VT BUFFER WHEN 1
HIGH-Z BUFFER WHEN 0
V(IOH)
RCV
VCOM
FORCE VT DATA[1] (ADDR[4:0] = 0x0C)
OVERRIDES THE RCV PIN AND FORCES
VTERM MODE ON THE DRIVER AND LOAD
POWER-DOWN MODE
LOAD ENABLE DATA[1] (ADDR[4:0] = 0x0D)
FORCES SWITCHES OPEN AND POWERS
DOWN LOAD WHEN 0
Figure 79. Driver and Load Block Diagram
~5Ω
VHH = (VT + 1V) × 2 + DUTGND
HVOUT
VH
VL
DATA
48Ω
HV MODE SELECT DATA[2]
(ADDR [4:0] = 0x0D) DISABLES
HV DRIVER AND FORCES
0V ON HVOUT WHEN 0
Figure 80. HVOUT Driver Output Stage
Rev. 0 | Page 49 of 56
07280-016
RCV (SHOWN IN
RCV = 0 STATE)
07280-015
V(IOL)
ADATE305
DUT0
VOL0
VOH0
DUT1
–
VOH
NWC
+
+
VOL
NWC
–
–
VOH
DMC
+
DU T0 –
DUT0–
DU T1
DUT1
DIFFERENTIAL
BUFFER
VOL0
2:1 COMP_QH0
MUX
DIFFERENTIAL
COMPARATOR ENABLE
DATA[0] (ADDR[4:0] = 0x10)
2:1 COMP_QL0
MUX
+
VOL
DMC
–
07280-017
VOH0
NOTES
1. DIFFERENTIAL COMPARATOR ONLY ON CHANNEL 0.
Figure 81. Comparator Block Diagram
COMPARATOR
OUTPUT (AB)
VTT = 3.3V
RECEIVER
OUT HIGH = 1.55V
50Ω
OUT CM = 1.42V
OUT LOW = 1.30V
50Ω
GND
Figure 82. Comparator Output Scheme
Rev. 0 | Page 50 of 56
07280-018
100Ω
ADATE305
PMU MEASURE V/I DATA[4]
(ADDR[4:0] = 0x0E)
PMU SENSE PATH DATA[7]
(ADDR[4:0] = 0x0E)
EXTERNAL DUT
SENSE PIN
MEASURE V
MEASURE I
MEASOUT01 SELECT DATA[2:1]
(ADDR[4:0] = 0x0F)
MUX
MUX
PMU FORCE V/I DATA[3]
(ADDR[4:0] = 0x0E)
MEASURE
OUT
CH[1] PMU V/I
TEMP SENSE
GND REF
TEMP SENSE
IN-AMP G = 5
10kΩ
2.5 + DUTGND
REF
MUX
MUX
MEASOUT01 OUTPUT
ENABLE DATA[0]
(ADDR[4:0] = 0x0F)
ONE PER DEVICE
225kΩ
2µA
PMU INPUT SELECTION DATA[9:8]
(ADDR[4:0] = 0x0E)
20µA
22.5kΩ
200µA
2.25kΩ
250Ω DUTx
15.5Ω
2mA
MV
VIN
2.5V + DUTGND
DUTGND
FFCAP_xA
MUX
PMU CLAMP ENABLE DATA[5]
(ADDR[4:0] = 0x0E)
330pF
SCAPx
(EXTERNAL)
32mA BUFFER
FFCAP_xB
CRA = 220pF
VCH
VCL
32mA
NOTES
1. SWITCHES CONNECTED WITH DOTTED LINES REPRESENT PMU RANGE DATA[2:0] (ADDR[4:0] = 0x0E); WHEN PMU ENABLE D ATA[2] = 0 (ADDR[4:0] = 0x0C), ALL
SWITCHES OPEN AND PMU POWERS DOWN.
2. THE EXTERNAL SENSE PATH MUST CLOSE THE LOOP TO ENABLE THE CLAMPS TO OPERATE CORRECTLY.
3. 32mA RANGE HAS ITS OWN OUTPUT BUFFER.
4. 32mA BUFFER TRISTATES WHEN NOT IN USE.
Figure 83. PMU Block Diagram
Rev. 0 | Page 51 of 56
07280-019
MEASURE V
(AT OUTPUT OF
SENSE MUX)
ADATE305
(ADDR[4:0] = 0x12) DATA[0]
OVD MASK ENABLES OVD
FLAGS TO ALARM OVD_CHx PIN
6.5V 1
OVD HIGH LEVEL
DAC (ADDR[4:0] = 0x0A, CH[1])
OVD_CHx
SHORT-CIRCUIT
CURRENT = 100µA
DUT
ADATE305
–2.5V 1
OVD LOW LEVEL
DAC (ADDR[4:0] = 0x0A, CH[0])
PMU
V/I CLAMP
FLAG
(ADDR[4:0] = 0x12) DATA[1]
PMU MASK ENABLES PMU V/I
FLAG TO ALARM OVD_CHx PIN
(ADDR[4:0] = 0x13) 2 DATA[2] DATA[1] DATA[0]
LEVEL CAN BE SET PER CHIP. THE OVD DACs PROVIDE A VOLTAGE RANGE OF –3V TO +7V. THE RECOMMENDED
HIGH/LOW SETTINGS ARE +6.5V/–2.5V. (THESE VALUES NEED TO BE PROGRAMMED BY THE USER UPON STARTUP/RESET.)
2THIS IS A READ ONLY REGISTER THAT ALLOWS THE USER TO DETERMINE THE CAUSE OF THE ACTIVE OVD FLAG.
Figure 84. OVD Block Diagram
Rev. 0 | Page 52 of 56
07280-020
1THE OVD HIGH/LOW LEVEL DAC IS SHARED BY EACH CHANNEL; THEREFORE, ONLY ONE OVD HIGH/LOW VOLTAGE
ADATE305
OUTLINE DIMENSIONS
0.75
0.60
0.45
16.00 BSC SQ
1.20
MAX
14.00 BSC SQ
76
100
1
75
PIN 1
8.00
BSC SQ
EXPOSED
PAD
0.15
0.05
SEATING
PLANE
0.20
0.09
7°
3.5°
0°
0.08 MAX
COPLANARITY
TOP VIEW
(PINS DOWN)
25
26
VIEW A
51
50
0.50 BSC
LEAD PITCH
0.27
0.22
0.17
VIEW A
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-AED-HU
072408-A
0° MIN
1.05
1.00
0.95
Figure 85. 100-Lead, Thin Quad Flatpack, Exposed Pad [TQFP_EP]
(SV-100-7)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADATE305BSVZ 1
1
Temperature Range
−40°C to +85°C
Package Description
100-Lead, Thin Quad Flatpack, Exposed Pad [TQFP_EP]
Z = RoHS Compliant Part.
Rev. 0 | Page 53 of 56
Package Option
SV-100-7
ADATE305
NOTES
Rev. 0 | Page 54 of 56
ADATE305
NOTES
Rev. 0 | Page 55 of 56
ADATE305
NOTES
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07280-0-8/08(0)
Rev. 0 | Page 56 of 56