Microchip MCP6074-E 110 ua, high precision op amp Datasheet

MCP6071/2/4
110 µA, High Precision Op Amps
Description
Features
•
•
•
•
•
•
•
•
Low Offset Voltage: ±150 µV (maximum)
Low Quiescent Current: 110 µA (typical)
Rail-to-Rail Input and Output
Wide Supply Voltage Range: 1.8V to 6.0V
Gain Bandwidth Product: 1.2 MHz (typical)
Unity Gain Stable
Extended Temperature Range: -40°C to +125°C
No Phase Reversal
Applications
•
•
•
•
•
•
•
The Microchip Technology Inc. MCP6071/2/4 family of
operational amplifiers (op amps) has low input offset
voltage (±150 µV, maximum) and rail-to-rail input and
output operation. This family is unity gain stable and
has a gain bandwidth product of 1.2 MHz (typical).
These devices operate with a single supply voltage as
low as 1.8V, while drawing low quiescent current per
amplifier (110 µA, typical). These features make the
family of op amps well suited for single-supply, high
precision, battery-powered applications.
The MCP6071/2/4 family is offered in single
(MCP6071), dual (MCP6072), and quad (MCP6074)
configurations.
Automotive
Portable Instrumentation
Sensor Conditioning
Battery Powered Systems
Medical Instrumentation
Test Equipment
Analog Filters
The MCP6071/2/4 is designed with Microchip’s
advanced CMOS process. All devices are available in
the extended temperature range, with a power supply
range of 1.8V to 6.0V.
Package Types
•
•
•
•
•
MCP6072
SOIC
MCP6071
SOIC
Design Aids
SPICE Macro Models
FilterLab® Software
MAPS (Microchip Advanced Part Selector)
Analog Demonstration and Evaluation Boards
Application Notes
Typical Application
7 VDD
VINA– 2
7 VOUTB
6 VOUT
5 NC
VINA+ 3
6 VINB–
5 VINB+
VIN– 2
VIN+ 3
VSS 4
VIN+ 3
MCP6071
C
Gyrator
EP
9
MCP6072
2x3 TDFN
8 NC
VOUTA 1
7 VDD
VINA– 2
6 VOUT VINA+ 3
VSS 4
5 NC
MCP6071
SOT-23-5
VOUT 1
VSS 2
R
L = R L RC
VOUT
VSS 4
MCP6071
2x3 TDFN
VIN– 2
Z IN = RL + jωL
8 VDD
8 NC
NC 1
RL
ZIN
VOUTA 1
NC 1
VIN+ 3
VSS 4
8 VDD
EP
9
7 VOUTB
6 VINB–
5 VINB+
MCP6074
SOIC, TSSOP
5 VDD
VOUTA 1
4 VIN–
VINA+ 3
VINA– 2
14 VOUTD
13 VIND–
VDD 4
12 VIND+
11 VSS
VINB+ 5
10 VINC+
VINB– 6
9 VINC–
VOUTB 7
8 VOUTC
* Includes Exposed Thermal Pad (EP); see Table 3-1.
© 2010 Microchip Technology Inc.
DS22142B-page 1
MCP6071/2/4
NOTES:
DS22142B-page 2
© 2010 Microchip Technology Inc.
MCP6071/2/4
1.0
ELECTRICAL CHARACTERISTICS
1.1
Absolute Maximum Ratings †
Current at Output and Supply Pins ............................±30 mA
† Notice: Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at those or any other conditions
above those indicated in the operational listings of this
specification is not implied. Exposure to maximum
rating conditions for extended periods may affect
device reliability.
Storage Temperature ....................................-65°C to +150°C
†† See 4.1.2 “Input Voltage Limits”
VDD – VSS ........................................................................7.0V
Current at Input Pins .....................................................±2 mA
Analog Inputs (VIN+, VIN-)†† .......... VSS – 1.0V to VDD + 1.0V
All Other Inputs and Outputs ......... VSS – 0.3V to VDD + 0.3V
Difference Input Voltage ...................................... |VDD – VSS|
Output Short-Circuit Current .................................continuous
Maximum Junction Temperature (TJ) .......................... +150°C
ESD protection on all pins (HBM; MM) ................ ≥ 4 kV; 400V
1.2
Specifications
TABLE 1-1:
DC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, VDD = +1.8V to +6.0V, VSS= GND, TA= +25°C, VCM = VDD/2,
VOUT ≈ VDD/2, VL = VDD/2 and RL = 10 kΩ to VL. (Refer to Figure 1-1).
Parameters
Sym
Min
Typ
Max
Units
Conditions
VOS
-150
—
+150
µV
ΔVOS/ΔTA
—
±1.5
—
µV/°C TA= -40°C to +85°C,
VDD = 3.0V, VCM = VDD/3
ΔVOS/ΔTA
—
±4.0
—
µV/°C TA= +85°C to +125°C,
VDD = 3.0V, VCM = VDD/3
PSRR
70
87
—
dB
pA
Input Offset
Input Offset Voltage
Input Offset Drift with Temperature
Power Supply Rejection Ratio
VDD = 3.0V,
VCM = VDD/3
VCM = VSS
Input Bias Current and Impedance
Input Bias Current
Input Offset Current
IB
—
±1.0
100
IB
—
60
—
pA
TA = +85°C
IB
—
1100
5000
pA
TA = +125°C
IOS
—
±1.0
—
pA
13
Common Mode Input Impedance
ZCM
—
10 ||6
—
Ω||pF
Differential Input Impedance
ZDIFF
—
1013||6
—
Ω||pF
VCMR
VSS−0.15
—
VDD+0.15
V
VDD = 1.8V (Note 1)
VCMR
VSS−0.3
—
VDD+0.3
V
VDD = 6.0V (Note 1)
CMRR
72
89
—
dB
VCM = -0.15V to 1.95V,
VDD = 1.8V
74
91
—
dB
VCM = -0.3V to 6.3V,
VDD = 6.0V
72
87
—
dB
VCM = 3.0V to 6.3V,
VDD = 6.0V
74
89
—
dB
VCM = -0.3V to 3.0V,
VDD = 6.0V
Common Mode
Common Mode Input Voltage Range
Common Mode Rejection Ratio
Note 1:
Figure 2-13 shows how VCMR changed across temperature.
© 2010 Microchip Technology Inc.
DS22142B-page 3
MCP6071/2/4
TABLE 1-1:
DC ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: Unless otherwise indicated, VDD = +1.8V to +6.0V, VSS= GND, TA= +25°C, VCM = VDD/2,
VOUT ≈ VDD/2, VL = VDD/2 and RL = 10 kΩ to VL. (Refer to Figure 1-1).
Parameters
Sym
Min
Typ
Max
Units
Conditions
AOL
95
115
—
dB
0.2V < VOUT <(VDD-0.2V)
VCM = VSS
VOL, VOH
VSS+15
—
VDD–15
mV
0.5V input overdrive
Open-Loop Gain
DC Open-Loop Gain
(Large Signal)
Output
Maximum Output Voltage Swing
Output Short-Circuit Current
—
±7
—
mA
VDD = 1.8V
—
±28
—
mA
VDD = 6.0V
VDD
1.8
—
6.0
V
IQ
50
110
170
µA
ISC
Power Supply
Supply Voltage
Quiescent Current per Amplifier
Note 1:
IO = 0, VDD = 6.0V
VCM = 0.9VDD
Figure 2-13 shows how VCMR changed across temperature.
TABLE 1-2:
AC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +1.8 to +6.0V, VSS = GND, VCM = VDD/2,
VOUT ≈ VDD/2, VL = VDD/2, RL = 10 kΩ to VL and CL = 60 pF. (Refer to Figure 1-1).
Parameters
Sym
Min
Typ
Max
Units
Conditions
AC Response
Gain Bandwidth Product
GBWP
—
1.2
—
MHz
Phase Margin
PM
—
57
—
°
Slew Rate
SR
—
0.5
—
V/µs
Input Noise Voltage
Eni
—
4.3
—
µVp-p
f = 0.1 Hz to 10 Hz
Input Noise Voltage Density
eni
—
19
—
nV/√Hz
f = 10 kHz
Input Noise Current Density
ini
—
0.6
—
fA/√Hz
f = 1 kHz
G = +1 V/V
Noise
TABLE 1-3:
TEMPERATURE SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, VDD = +1.8V to +6.0V and VSS = GND.
Parameters
Sym
Min
Typ
Max
Units
Operating Temperature Range
TA
-40
—
+125
°C
Storage Temperature Range
TA
-65
—
+150
°C
Thermal Resistance, 5L-SOT-23
θJA
—
220.7
—
°C/W
Thermal Resistance, 8L-2x3 TDFN
θJA
—
52.5
—
°C/W
Thermal Resistance, 8L-SOIC
θJA
—
149.5
—
°C/W
Thermal Resistance, 14L-SOIC
θJA
—
95.3
—
°C/W
Thermal Resistance, 14L-TSSOP
θJA
—
100
—
°C/W
Conditions
Temperature Ranges
Note 1
Thermal Package Resistances
Note 1: The internal junction temperature (TJ) must not exceed the absolute maximum specification of +150°C.
DS22142B-page 4
© 2010 Microchip Technology Inc.
MCP6071/2/4
1.3
Test Circuits
The circuit used for most DC and AC tests is shown in
Figure 1-1. This circuit can independently set VCM and
VOUT; see Equation 1-1. Note that VCM is not the
circuit’s common mode voltage ((VP + VM)/2), and that
VOST includes VOS plus the effects (on the input offset
error, VOST) of temperature, CMRR, PSRR and AOL.
CF
6.8 pF
RG
100 kΩ
RF
100 kΩ
VP
EQUATION 1-1:
VDD
VIN+
G DM = R F ⁄ R G
V CM = ( VP + VDD ⁄ 2 ) ⁄ 2
CB1
100 nF
MCP607X
V OST = V IN– – V IN+
V OUT = ( V DD ⁄ 2 ) + ( V P – V M ) + V OST ( 1 + G DM )
Where:
GDM = Differential Mode Gain
(V/V)
VCM = Op Amp’s Common Mode
Input Voltage
(V)
VOST = Op Amp’s Total Input Offset
Voltage
(mV)
VDD/2
CB2
1 µF
VIN–
VM
RG
100 kΩ
RL
10 kΩ
RF
100 kΩ
CF
6.8 pF
VOUT
CL
60 pF
VL
FIGURE 1-1:
AC and DC Test Circuit for
Most Specifications.
© 2010 Microchip Technology Inc.
DS22142B-page 5
MCP6071/2/4
NOTES:
DS22142B-page 6
© 2010 Microchip Technology Inc.
MCP6071/2/4
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Input Offset Drift with Temperature (µV/°C)
Input Offset Drift with Temperature (µV/°C)
FIGURE 2-3:
Input Offset Voltage Drift
with VDD = 3.0V and TA ≥ +85°C.
© 2010 Microchip Technology Inc.
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
3.4
3.1
2.8
2.5
2.3
2.1
1.9
1.7
1.5
1.3
1.1
TA = -40°C
TA = +25°C
TA = +85°C
TA = +125°C
0.9
20
16
12
8
4
0
-4
-8
-12
-16
-20
0%
Representative Part
0.7
6%
3%
VDD = 1.8V
0.5
12%
9%
1000
800
600
400
200
0
-200
-400
-600
-800
-1000
0.3
18%
15%
FIGURE 2-5:
Input Offset Voltage vs.
Common Mode Input Voltage with VDD = 3.0V.
-0.5
1244 Samples
VDD = 3.0V
VCM = VDD/3
TA = +85°C to +125°C
24%
21%
1.5
Common Mode Input Voltage (V)
Input Offset Voltage (µV)
27%
2.2
-0.5
20
16
12
8
4
0
-4
-8
-12
-16
-20
0%
1.9
3%
1.6
6%
TA = -40°C
TA = +25°C
TA = +85°C
TA = +125°C
1.3
9%
Representative Part
1.0
12%
VDD = 3.0V
0.7
15%
1000
800
600
400
200
0
-200
-400
-600
-800
-1000
0.1
18%
Input Offset Voltage (µV)
21%
1244 Samples
VDD = 3.0V
VCM = VDD/3
TA = -40°C to +85°C
1.0
FIGURE 2-4:
Input Offset Voltage vs.
Common Mode Input Voltage with VDD = 6.0V.
27%
24%
Common Mode Input Voltage (V)
0.4
Input Offset Voltage with
FIGURE 2-2:
Input Offset Voltage Drift
with VDD = 3.0V and TA ≤ +85°C.
Percentage of Occurences
-0.5
150
120
90
60
30
0
-30
Input Offset Voltage (µV)
FIGURE 2-1:
VDD = 3.0V.
Percentage of Occurences
-60
-90
-120
0%
0.5
2%
Representative Part
TA = -40°C
TA = +25°C
TA = +85°C
TA = +125°C
0.1
4%
0.0
6%
VDD = 6.0V
-0.2
8%
1000
800
600
400
200
0
-200
-400
-600
-800
-1000
-0.1
10%
1244 Samples
VDD = 3.0V
VCM = VDD /3
-0.3
12%
Input Offset Voltage (µV)
14%
-150
Percentage of Occurences
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +6.0V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
VL = VDD/2, RL = 10 kΩ to VL and CL = 60 pF.
Common Mode Input Voltage (V)
FIGURE 2-6:
Input Offset Voltage vs.
Common Mode Input Voltage with VDD = 1.8V.
DS22142B-page 7
MCP6071/2/4
5
Output Voltage (V)
TA = -40°C
TA = +25°C
TA = +85°C
TA = +125°C
PSRR-
100
CMRR, PSRR (dB)
Representative Part
6.5
Representative Part
90
CMRR
80
70
PSRR+
60
50
40
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
30
FIGURE 2-8:
Input Offset Voltage vs.
Power Supply Voltage.
20
10
10
PSRR, CMRR (dB)
100
0.1
1.E-1
1
1.E+0
FIGURE 2-9:
vs. Frequency.
DS22142B-page 8
10
1.E+1 100
1.E+2 1k
1.E+3 10k
1.E+4100k
1.E+5
Frequency (Hz)
Input Noise Voltage Density
100
100
FIGURE 2-11:
Frequency.
1,000
Input Noise Voltage Density
(nV/ √Hz)
6.0
FIGURE 2-10:
Input Noise Voltage Density
vs. Common Mode Input Voltage.
Input Offset Voltage vs.
Power Supply Voltage (V)
10
5.5
Common Mode Input Voltage (V)
110
1000
800
600
400
200
0
-200
-400
-600
-800
-1000
1.5
Input Offset Voltage (µV)
FIGURE 2-7:
Output Voltage.
5.0
0
4.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-350
10
4.0
VDD = 1.8V
3.5
-250
15
3.0
VDD = 3.0V
-150
20
2.5
-50
25
2.0
VDD = 6.0V
1.5
50
30
1.0
150
f = 10 kHz
VDD = 6.0V
35
-0.5
250
40
0.5
Representative Part
0.0
350
Input Noise Voltage Density
(nV/√Hz)
Input Offset Voltage (µV)
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +6.0V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
VL = VDD/2, RL = 10 kΩ to VL and CL = 60 pF.
110
105
100
95
90
85
80
75
70
65
60
1k
10k
1000
10000
Frequency (Hz)
100k
100000
1M
1000000
CMRR, PSRR vs.
CMRR (VDD = 6.0V, VCM = -0.3V to 6.3V)
PSRR (VDD = 1.8V to 6.0V, VCM = VSS )
-50
-25
FIGURE 2-12:
Temperature.
0
25
50
75
Ambient Temperature (°C)
100
125
CMRR, PSRR vs. Ambient
© 2010 Microchip Technology Inc.
MCP6071/2/4
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
-0.05
-0.10
-0.15
-0.20
-0.25
-0.30
-0.35
150
140
Quiescent Current
(µA/Amplifier)
VCMR_H - VDD @ VDD = 6.0V
@ VDD = 3.0V
@ VDD = 1.8V
VCMR_L - VSS @ VDD = 1.8V
VOL - VSS @ VDD = 3.0V
VOL - VSS @ VDD = 6.0V
120
110
100
90
80
60
-50
125
120
100
80
60
40
120
100
TA = +85°C
1
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Common Mode Input Votlage (V)
FIGURE 2-15:
Input Bias Current vs.
Common Mode Input Voltage.
© 2010 Microchip Technology Inc.
Open-Loop Gain (dB)
VDD = 6.0V
TA = +125°C
7.0
6.5
FIGURE 2-17:
Quiescent Current vs.
Power Supply Voltage with VCM = 0.9VDD.
10000
1000
6.0
4.5
4.0
3.5
Power Supply Voltage (V)
0
Open-Loop Gain
100
80
-30
Open-Loop Phase
-60
60
-90
40
-120
20
0
-150
VDD = 6.0V
-180
-20
Open-Loop Phase (°)
FIGURE 2-14:
Input Bias, Offset Currents
vs. Ambient Temperature.
3.0
125
2.5
0.0
45
65
85
105
Ambient Temperature (°C)
2.0
20
0
Input Offset Current
1
25
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
5.5
10
125
VDD = 6.0V
VCM = 0.9VDD
5.0
Input Bias Current
100
180
160
140
Quiescent Current
(µA/Amplifier)
Input Bias and Offset
Currents (pA)
1000
0
25
50
75
100
Ambient Temperature (°C)
FIGURE 2-16:
Quiescent Current vs
Ambient Temperature with VCM = 0.9VDD.
10000
VDD = 6.0V
VCM = VDD
-25
1.5
0
25
50
75
100
Ambient Temperature (°C)
1.0
-25
FIGURE 2-13:
Common Mode Input
Voltage Range Limit vs. Ambient Temperature.
Input Bias Current (pA)
VDD = 1.8V
VCM = 0.9VDD
70
-50
10
VDD = 6.0V
VCM = 0.9VDD
130
0.5
Common Mode Input Voltage
Range Limit (V)
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +6.0V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
VL = VDD/2, RL = 10 kΩ to VL and CL = 60 pF.
-210
1.E-01
1.E+02 1.E+03
1.E+04 100k
1.E+05 1.E+06
0.1 1.E+00
1 1.E+01
10 100
1k 10k
1M 1.E+07
10M
Frequency
Frequency (Hz)
(Hz)
FIGURE 2-18:
Frequency.
Open-Loop Gain, Phase vs.
DS22142B-page 9
MCP6071/2/4
RL = 10 kΩ
VSS + 0.2V < VOUT < VDD - 0.2V
5.5
DC-Open-Loop Gain (dB)
0.6
0.4
0.2
6.0
VDD = 6.0V
Phase Margin
0
FIGURE 2-22:
Gain Bandwidth Product,
Phase Margin vs. Common Mode Input Voltage.
1.8
VDD = 6.0V
VDD = 1.8V
Large Signal AOL
0.05
0.10
0.15
0.20
0.25
180
1.6
Gain Bandwidth Product
140
1.2
120
1.0
100
0.8
80
0.6
60
0.4
VDD = 6.0V
Phase Margin
0.2
-50
-25
0
25
50
75 100
Ambient Temperature (°C)
120
110
100
Input Referred
80
100
1k
10k
100k
1M
1.00E+02
1.00E+03
1.00E+04
1.00E+05
1.00E+06
Frequency (Hz)
FIGURE 2-21:
Channel-to-Channel
Separation vs. Frequency ( MCP6072/4 only).
0
125
FIGURE 2-23:
Gain Bandwidth Product,
Phase Margin vs. Ambient Temperature.
Gain Bandwidth Product
(MHz)
130
40
20
1.8
140
160
1.4
0.0
150
DS22142B-page 10
60
40
20
Common Mode Input Voltage (V)
FIGURE 2-20:
DC Open-Loop Gain vs.
Output Voltage Headroom.
Channel to Channel
Separation (dB)
100
80
Phase Margin (°)
2.5 3.0 3.5 4.0 4.5 5.0
Power Supply Voltage (V)
Output Voltage Headroom
V DD - VOH or VOL - VSS (V)
90
1.0
0.8
0.0
FIGURE 2-19:
DC Open-Loop Gain vs.
Power Supply Voltage.
150
145
140
135
130
125
120
115
110
105
100
0.00
Gain Bandwidth Product
180
1.6
160
Gain Bandwidth Product
1.4
140
1.2
120
1.0
100
0.8
80
0.6
60
0.4
VDD = 1.8V
0.2
Phase Margin
0.0
-50
-25
0
25
50
75 100
Ambient Temperature (°C)
40
Phase Margin (°)
2.0
180
160
140
120
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
1.5
1.8
1.6
1.4
1.2
Phase Margin (°)
Gain Bandwidth Product
(MHz)
150
145
140
135
130
125
120
115
110
105
100
Gain Bandwidth Product
(MHz)
DC-Open-Loop Gain (dB)
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +6.0V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
VL = VDD/2, RL = 10 kΩ to VL and CL = 60 pF.
20
0
125
FIGURE 2-24:
Gain Bandwidth Product,
Phase Margin vs. Ambient Temperature.
© 2010 Microchip Technology Inc.
MCP6071/2/4
16.0
35
Output Voltage Headroom
VDD - VOH or VOL - VSS (mV)
40
TA = -40°C
TA = +25°C
TA = +85°C
TA = +125°C
30
25
20
15
10
5
14.0
10.0
8.0
6.0
2.0
0.0
-50
VDD = 6.0V
VDD = 1.8V
1
0.1
1k
1000
10k
10000
100k
100000
1M
1000000
(VDD - VOH)/IOUT
VDD = 1.8V
(VOL - VSS )/(-IOUT)
(VDD - VOH )/IOUT
(VOL - VSS )/(-IOUT)
VDD = 6.0V
0.1
1
Output Current (mA)
© 2010 Microchip Technology Inc.
125
Rising Edge, VDD = 6.0V
Rising Edge, VDD = 1.8V
-25
FIGURE 2-29:
Temperature.
10
FIGURE 2-27:
Ratio of Output Voltage
Headroom to Output Current vs. Output Current.
0
25
50
75
100
Ambient Temperature (°C)
Falling Edge, VDD = 6.0V
Falling Edge, VDD = 1.8V
Output Voltage (50 mV/div)
Ratio of Output Headroom to
Current (mV/mA)
60
55
50
45
40
35
30
25
20
15
10
5
0
Output Voltage Swing vs.
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
-50
Frequency (Hz)
FIGURE 2-26:
Frequency.
-25
FIGURE 2-28:
Output Voltage Headroom
vs. Ambient Temperature.
Slew Rate (V/µs)
Output Voltage Swing (V P-P)
10
VOL - VSS
4.0
Power Supply Voltage (V)
FIGURE 2-25:
Ouput Short Circuit Current
vs. Power Supply Voltage.
VDD - VOH
12.0
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0.0
Output Short Circuit Current
(mA)
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +6.0V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
VL = VDD/2, RL = 10 kΩ to VL and CL = 60 pF.
0
25
50
75
Ambient Temperature (°C)
100
125
Slew Rate vs. Ambient
VDD = 6.0V
G = +1 V/V
Time (2 µs/div)
FIGURE 2-30:
Pulse Response.
Small Signal Non-Inverting
DS22142B-page 11
MCP6071/2/4
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +6.0V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
VL = VDD/2, RL = 10 kΩ to VL and CL = 60 pF.
VDD = 6.0V
G = -1 V/V
6.0
VIN
4.0
3.0
2.0
1.0
VDD = 6.0V
G = +2 V/V
0.0
-1.0
Time (2 µs/div)
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
Small Signal Inverting Pulse
Time (0.1 ms/div)
FIGURE 2-34:
The MCP6071/2/4 Shows
No Phase Reversal.
1000
VDD = 6.0V
G = +1 V/V
Closed Loop Output
Impedance (Ω)
FIGURE 2-31:
Response.
Output Voltage (V)
VOUT
5.0
Output Voltage (V)
Output Voltage (50 mV/div)
7.0
100
1
10
10
Time (0.02 ms/div)
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
Large Signal Non-Inverting
DS22142B-page 12
1000
1k
10000
10k
Frequency (Hz)
100000
100k
1000000
1M
1.E-03
1m
1.E-04
100
µ
VDD = 6.0V
G = -1 V/V
1.E-05
10µ
1.E-06
1µ
1.E-07
100n
1.E-08
10n
1.E-09
1n
1.E-10
100p
TA = -40°C
TA = +25°C
TA = +85°C
TA = +125°C
1.E-11
10p
1.E-12
1p
Time (0.02 ms/div)
FIGURE 2-33:
Response.
100
100
FIGURE 2-35:
Closed Loop Output
Impedance vs. Frequency.
-IIN (A)
Output Voltage (V)
FIGURE 2-32:
Pulse Response.
GN:
101 V/V
11 V/V
1 V/V
10
Large Signal Inverting Pulse
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0
VIN (V)
FIGURE 2-36:
Measured Input Current vs.
Input Voltage (below VSS).
© 2010 Microchip Technology Inc.
MCP6071/2/4
3.0
PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
PIN FUNCTION TABLE
MCP6071
SOIC
MCP6072
SOT-23-5 2x3 TDFN
SOIC
2x3 TDFN
MCP6074
SOIC,
TSSOP
Symbol
Description
6
1
6
1
1
1
VOUT, VOUTA
Analog Output (op amp A)
2
4
2
2
2
2
VIN–, VINA–
Inverting Input (op amp A)
3
3
3
3
3
3
VIN+, VINA+
Non-inverting Input (op amp A)
7
5
7
8
8
4
VDD
—
—
—
5
5
5
VINB+
Non-inverting Input (op amp B)
—
—
—
6
6
6
VINB–
Inverting Input (op amp B)
—
—
—
7
7
7
VOUTB
Analog Output (op amp B)
—
—
—
—
—
8
VOUTC
Analog Output (op amp C)
—
—
—
—
—
9
VINC–
Inverting Input (op amp C)
—
—
—
—
—
10
VINC+
Non-inverting Input (op amp C)
Positive Power Supply
Negative Power Supply
4
2
4
4
4
11
VSS
—
—
—
—
—
12
VIND+
Non-inverting Input (op amp D)
—
—
—
—
—
13
VIND–
Inverting Input (op amp D)
—
—
—
—
—
14
VOUTD
Analog Output (op amp D)
1, 5, 8
—
1, 5, 8
—
—
—
NC
No Internal Connection
—
—
9
—
9
—
EP
Exposed Thermal Pad (EP); must
be connected to VSS.
3.1
Analog Outputs
The output pins are low-impedance voltage sources.
3.2
Analog Inputs
The non-inverting and inverting inputs are highimpedance CMOS inputs with low bias currents.
3.3
Power Supply Pins
The positive power supply (VDD) is 1.8V to 6.0V higher
than the negative power supply (VSS). For normal
operation, the other pins are at voltages between VSS
and VDD.
Typically, these parts are used in a single (positive)
supply configuration. In this case, VSS is connected to
ground and VDD is connected to the supply. VDD will
need bypass capacitors.
3.4
Exposed Thermal Pad (EP)
There is an internal electrical connection between the
Exposed Thermal Pad (EP) and the VSS pin; they must
be connected to the same potential on the Printed
Circuit Board (PCB).
© 2010 Microchip Technology Inc.
DS22142B-page 13
MCP6071/2/4
NOTES:
DS22142B-page 14
© 2010 Microchip Technology Inc.
MCP6071/2/4
4.0
APPLICATION INFORMATION
The MCP6071/2/4 family of op amps is manufactured
using Microchip’s state-of-the-art CMOS process and
is specifically designed for low-power, high precision
applications.
4.1
VDD
D1
U1
D2
V1
MCP607X
Rail-to-Rail Input
VOUT
V2
4.1.1
PHASE REVERSAL
The MCP6071/2/4 op amps are designed to prevent
phase reversal when the input pins exceed the supply
voltages. Figure 2-34 shows the input voltage
exceeding the supply voltage without any phase
reversal.
4.1.2
INPUT VOLTAGE LIMITS
In order to prevent damage and/or improper operation
of these amplifiers, the circuit must limit the voltages at
the input pins (see Section 1.1, Absolute Maximum
Ratings †).
The ESD protection on the inputs can be depicted as
shown in Figure 4-1. This structure was chosen to
protect the input transistors and to minimize input bias
current (IB).
FIGURE 4-2:
Inputs.
Protecting the Analog
A significant amount of current can flow out of the
inputs when the Common Mode voltage (VCM) is below
ground (VSS). See Figure 2-36.
4.1.3
INPUT CURRENT LIMITS
In order to prevent damage and/or improper operation
of these amplifiers, the circuit must limit the voltages at
the input pins (see Section 1.1, Absolute Maximum
Ratings †).
Figure 4-3 shows one approach to protecting these
inputs. The resistors R1 and R2 limit the possible currents in or out of the input pins (and the ESD diodes, D1
and D2). The diode currents will go through either VDD
or VSS.
VDD Bond
Pad
VIN+ Bond
Pad
VDD
Input
Stage
Bond V –
IN
Pad
D1
D2
U1
V1
R1
MCP607X
VOUT
V2
Bond
VSS
Pad
FIGURE 4-1:
Structures.
R2
VSS – min (V1,V2)
2 mA
max(V1,V2) – VDD
min(R1,R2) >
2 mA
min(R1,R2) >
Simplified Analog Input ESD
The input ESD diodes clamp the inputs when they try
to go more than one diode drop below VSS. They also
clamp any voltages that go well above VDD; their breakdown voltage is high enough to allow normal operation,
but not low enough to protect against slow over-voltage
(beyond VDD) events. Very fast ESD events (that meet
the spec) are limited so that damage does not occur.
In some applications, it may be necessary to prevent
excessive voltages from reaching the op amp inputs.
Figure 4-2 shows one approach to protecting these
inputs.
FIGURE 4-3:
Inputs.
4.1.4
Protecting the Analog
NORMAL OPERATION
The input stage of the MCP6071/2/4 op amps use two
differential input stages in parallel. One operates at a
low common mode input voltage (VCM), while the other
operates at a high VCM. With this topology, the device
operates with a VCM up to 300 mV above VDD and
300 mV below VSS. (See Figure 2-13). The input offset
voltage is measured at VCM = VSS – 0.3V and
VDD + 0.3V to ensure proper operation.
The transition between the input stages occurs when
VCM is near VDD – 1.1V (See Figures 2-4, 2-5 and
Figure 2-6). For the best distortion performance and
gain linearity, with non-inverting gains, avoid this region
of operation.
© 2010 Microchip Technology Inc.
DS22142B-page 15
MCP6071/2/4
4.2
Rail-to-Rail Output
The output voltage range of the MCP6071/2/4 op amps
is VSS + 15 mV (minimum) and VDD – 15 mV
(maximum) when RL = 10 kΩ is connected to VDD/2
and VDD = 6.0V. Refer to Figures 2-27 and 2-28 for
more information.
4.3
4.4
Capacitive Loads
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
reduced. This produces gain peaking in the frequency
response, with overshoot and ringing in the step
response. While a unity-gain buffer (G = +1) is the most
sensitive to capacitive loads, all gains show the same
general behavior.
When driving large capacitive loads with these op
amps (e.g., > 100 pF when G = +1), a small series
resistor at the output (RISO in Figure 4-4) improves the
feedback loop’s phase margin (stability) by making the
output load resistive at higher frequencies. The
bandwidth will be generally lower than the bandwidth
with no capacitance load.
–
Supply Bypass
With this family of operational amplifiers, the power
supply pin (VDD for single-supply) should have a local
bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm
for good high frequency performance. It can use a bulk
capacitor (i.e., 1 µF or larger) within 100 mm to provide
large, slow currents. This bulk capacitor can be shared
with other analog parts.
4.5
Unused Op Amps
An unused op amp in a quad package (MCP6074)
should be configured as shown in Figure 4-6. These
circuits prevent the output from toggling and causing
crosstalk. Circuit A sets the op amp at its minimum
noise gain. The resistor divider produces any desired
reference voltage within the output voltage range of the
op amp; the op amp buffers that reference voltage.
Circuit B uses the minimum number of components
and operates as a comparator, but it may draw more
current.
RISO
MCP607X
+
VIN
After selecting RISO for your circuit, double-check the
resulting frequency response peaking and step
response overshoot. Modify RISO’s value until the
response is reasonable. Bench evaluation and
simulations with the MCP6071/2/4 SPICE macro
model are very helpful.
VOUT
CL
¼ MCP6074 (A)
¼ MCP6074 (B)
VDD
FIGURE 4-4:
Output Resistor, RISO
Stabilizes Large Capacitive Loads.
Figure 4-5 gives recommended RISO values for
different capacitive loads and gains. The x-axis is the
normalized load capacitance (CL/GN), where GN is the
circuit's noise gain. For non-inverting gains, GN and the
Signal Gain are equal. For inverting gains, GN is
1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V).
R1
VDD
VDD
R2
VREF
R2
VREF = VDD × -------------------R1 + R2
FIGURE 4-6:
Unused Op Amps.
1000
Recommended R
ISO
(Ω)
VDD = 6.0 V
RL = 10 kΩ
100
10
GN:
1 V/V
2 V/V
≥ 5 V/V
1
10p
100p 1.E-09
1n
10n
0.1µ
1µ
1.E-11
1.E-10
1.E-08
1.E-07
1.E-06
Normalized Load Capacitance; CL/GN (F)
FIGURE 4-5:
Recommended RISO Values
for Capacitive Loads.
DS22142B-page 16
© 2010 Microchip Technology Inc.
MCP6071/2/4
4.6
PCB Surface Leakage
In applications where low input bias current is critical,
Printed Circuit Board (PCB) surface leakage effects
need to be considered. Surface leakage is caused by
humidity, dust or other contamination on the board.
Under low humidity conditions, a typical resistance
between nearby traces is 1012Ω. A 5V difference would
cause 5 pA of current to flow; which is greater than the
MCP6071/2/4 family’s bias current at +25°C (±1.0 pA,
typical).
The easiest way to reduce surface leakage is to use a
guard ring around sensitive pins (or traces). The guard
ring is biased at the same voltage as the sensitive pin.
An example of this type of layout is shown in
Figure 4-7.
Guard Ring
FIGURE 4-7:
for Inverting Gain.
1.
2.
VIN– VIN+
VSS
Example Guard Ring Layout
Non-inverting Gain and Unity-Gain Buffer:
a.Connect the non-inverting pin (VIN+) to the
input with a wire that does not touch the
PCB surface.
b.Connect the guard ring to the inverting input
pin (VIN–). This biases the guard ring to the
common mode input voltage.
Inverting Gain and Transimpedance Gain
Amplifiers (convert current to voltage, such as
photo detectors):
a.Connect the guard ring to the non-inverting
input pin (VIN+). This biases the guard ring
to the same reference voltage as the op
amp (e.g., VDD/2 or ground).
b.Connect the inverting pin (VIN–) to the input
with a wire that does not touch the PCB
surface.
© 2010 Microchip Technology Inc.
DS22142B-page 17
MCP6071/2/4
4.7
Application Circuits
4.7.1
4.7.2
GYRATOR
The MCP6071/2/4 op amps can be used in gyrator
applications. The gyrator is an electric circuit which can
make a capacitive circuit behave inductively.
Figure 4-8 shows an example of a gyrator simulating
inductance, with an approximately equivalent circuit
below. The two ZIN have similar values in typical
applications. The primary application for a gyrator is to
reduce the size and cost of a system by removing the
need for bulky, heavy and expensive inductors. For
example, RLC bandpass filter characteristics can be
realized with capacitors, resistors and operational
amplifiers without using inductors. Moreover, gyrators
will typically have higher accuracy than real inductors,
due to the lower cost of precision capacitors than
inductors.
INSTRUMENTATION AMPLIFIER
The MCP6071/2/4 op amps are well suited for
conditioning sensor signals in battery-powered
applications. Figure 4-9 shows a two op amp
instrumentation amplifier, using the MCP6072, that
works well for applications requiring rejection of
common mode noise at higher gains. The reference
voltage (VREF) is supplied by a low impedance source.
In single supply applications, VREF is typically VDD/2.
RG
VREF R1
R2
R2
R1
VOUT
V2
½
MCP6072
½
MCP6072
V1
.
RL
ZIN
MCP6071
C
VOUT
Gyrator
Z IN = R L + jωL
L = RL RC
4.7.3
RL
Equivalent Circuit
L
FIGURE 4-8:
FIGURE 4-9:
Two Op Amp
Instrumentation Amplifier.
To obtain the best CMRR possible, and not limit the
performance by the resistor tolerances, set a high gain
with the RG resistor.
R
ZIN
R1 2R 1
VOUT = ( V1 – V 2 ) ⎛ 1 + ------ + ---------⎞ + VREF
⎝
R2 RG ⎠
PRECISION COMPARATOR
Use high gain before a comparator to improve the
latter’s input offset performance. Figure 4-10 shows a
gain of 11 V/V placed before a comparator. The
reference voltage VREF can be any value between the
supply rails.
Gyrator.
VIN
MCP6071
1 MΩ
100 kΩ
FIGURE 4-10:
Comparator.
DS22142B-page 18
MCP6541
VOUT
VREF
Precision, Non-inverting
© 2010 Microchip Technology Inc.
MCP6071/2/4
5.0
DESIGN AIDS
Microchip provides the basic design tools needed for
the MCP6071/2/4 family of op amps.
5.1
SPICE Macro Model
The latest SPICE macro model for the MCP6071/2/4
op amps is available on the Microchip web site at
www.microchip.com. The model was written and tested
in official Orcad (Cadence) owned PSPICE. For the
other simulators, it may require translation.
The model covers a wide aspect of the op amp's
electrical specifications. Not only does the model cover
voltage, current, and resistance of the op amp, but it
also covers the temperature and noise effects on the
behavior of the op amp. The model has not been
verified outside of the specification range listed in the
op amp data sheet. The model behaviors under these
conditions can not be guaranteed that it will match the
actual op amp performance.
Moreover, the model is intended to be an initial design
tool. Bench testing is a very important part of any
design and cannot be replaced with simulations. Also,
simulation results using this macro model need to be
validated by comparing them to the data sheet
specifications and characteristic curves.
5.2
FilterLab® Software
Microchip’s FilterLab® software is an innovative
software tool that simplifies analog active filter (using
op amps) design. Available at no cost from the
Microchip web site at www.microchip.com/filterlab, the
FilterLab design tool provides full schematic diagrams
of the filter circuit with component values. It also
outputs the filter circuit in SPICE format, which can be
used with the macro model to simulate actual filter
performance.
5.3
MAPS (Microchip Advanced Part
Selector)
MAPS is a software tool that helps semiconductor
professionals efficiently identify Microchip devices that
fit a particular design requirement. Available at no cost
from the Microchip website at www.microchip.com/
maps, the MAPS is an overall selection tool for
Microchip’s product portfolio that includes Analog,
Memory, MCUs and DSCs. Using this tool you can
define a filter to sort features for a parametric search of
devices and export side-by-side technical comparison
reports. Helpful links are also provided for Data Sheets,
purchase, and sampling of Microchip parts.
© 2010 Microchip Technology Inc.
5.4
Analog Demonstration and
Evaluation Boards
Microchip offers a broad spectrum of Analog
Demonstration and Evaluation Boards that are
designed to help you achieve faster time to market. For
a complete listing of these boards and their
corresponding user’s guides and technical information,
visit the Microchip web site at www.microchip.com/
analogtools.
Some boards that are especially useful are:
•
•
•
•
•
•
•
MCP6XXX Amplifier Evaluation Board 1
MCP6XXX Amplifier Evaluation Board 2
MCP6XXX Amplifier Evaluation Board 3
MCP6XXX Amplifier Evaluation Board 4
Active Filter Demo Board Kit
5/6-Pin SOT-23 Evaluation Board, P/N VSUPEV2
8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board,
P/N SOIC8EV
• 14-Pin SOIC/TSSOP/DIP Evaluation Board, P/N
SOIC14EV
5.5
Application Notes
The following Microchip Analog Design Note and
Application Notes are available on the Microchip web
site at www.microchip. com/appnotes and are
recommended as supplemental reference resources.
• ADN003: “Select the Right Operational Amplifier
for your Filtering Circuits”, DS21821
• AN722: “Operational Amplifier Topologies and DC
Specifications”, DS00722
• AN723: “Operational Amplifier AC Specifications
and Applications”, DS00723
• AN884: “Driving Capacitive Loads With Op
Amps”, DS00884
• AN990: “Analog Sensor Conditioning Circuits –
An Overview”, DS00990
• AN1177: “Op Amp Precision Design: DC Errors”,
DS01177
• AN1228: “Op Amp Precision Design: Random
Noise”, DS01228
• AN1332: “Current Sensing Circuit Concepts and
Fundamentals”, DS01332
These application notes and others are listed in the
design guide:
• “Signal Chain Design Guide”, DS21825
DS22142B-page 19
MCP6071/2/4
NOTES:
DS22142B-page 20
© 2010 Microchip Technology Inc.
MCP6071/2/4
6.0
PACKAGING INFORMATION
6.1
Package Marking Information
5-Lead SOT-23 (MCP6071)
YH25
XXNN
8-Lead SOIC (150 mil) (MCP6071, MCP6072)
8-Lead 2x3 TDFN (MCP6071, MCP6072)
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
Example:
MCP6071E
e3 1044
SN^^
256
XXXXXXXX
XXXXYYWW
NNN
XXX
YWW
NN
Example:
Example:
AHE
044
25
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
© 2010 Microchip Technology Inc.
DS22142B-page 21
MCP6071/2/4
Package Marking Information (Continuation)
14-Lead SOIC (150 mil) (MCP6074)
Example:
MCP6074
E/SL e3
1044256
XXXXXXXXXXX
XXXXXXXXXXX
YYWWNNN
14-Lead TSSOP (MCP6074)
XXXXXXXX
YYWW
NNN
DS22142B-page 22
Example:
MCP6074E
1044
256
© 2010 Microchip Technology Inc.
MCP6071/2/4
.# #$ # /
## +22--- 2
! -
/ 0 # 1 /
% # # ! #
b
N
E
E1
3
2
1
e
e1
D
A2
A
c
φ
A1
L
L1
3#
4#
5$8 %1
4
44""
5
5
7
(
!1#
6$# ! 4
56
()*
!1#
6, 9 #
! !1 /
/
# !%%
6, <!#
! !1 /
6, 4 #
<!#
)*
:
;
:
(
:
(
"
:
"
:
;
:
.#4 #
4
:
=
.# #
4
(
:
;
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!/
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8
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)*+ ) # & #, $ --#$## ! - * )
© 2010 Microchip Technology Inc.
DS22142B-page 23
MCP6071/2/4
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS22142B-page 24
© 2010 Microchip Technology Inc.
MCP6071/2/4
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
© 2010 Microchip Technology Inc.
DS22142B-page 25
MCP6071/2/4
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS22142B-page 26
© 2010 Microchip Technology Inc.
MCP6071/2/4
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
© 2010 Microchip Technology Inc.
DS22142B-page 27
MCP6071/2/4
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS22142B-page 28
© 2010 Microchip Technology Inc.
MCP6071/2/4
! " #$%&''()*+, !
.# #$ # /
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© 2010 Microchip Technology Inc.
! -
/ 0 # 1 /
% # # ! #
DS22142B-page 29
MCP6071/2/4
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DS22142B-page 30
© 2010 Microchip Technology Inc.
MCP6071/2/4
.# #$ # /
## +22--- 2
© 2010 Microchip Technology Inc.
! -
/ 0 # 1 /
% # # ! #
DS22142B-page 31
MCP6071/2/4
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS22142B-page 32
© 2010 Microchip Technology Inc.
MCP6071/2/4
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
© 2010 Microchip Technology Inc.
DS22142B-page 33
MCP6071/2/4
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS22142B-page 34
© 2010 Microchip Technology Inc.
MCP6071/2/4
APPENDIX A:
REVISION HISTORY
Revision B (December 2010)
The following is the list of modifications:
1.
2.
3.
4.
5.
6.
7.
Added new SOT-23-5 package type for
MCP6071 device.
Corrected Figures 2-13, 2-22, 2-23, 2-24, 2-28,
2-29 and 2-34 in Section 2.0 “Typical
Performance Curves”.
Modified Table 3-1 to show the pin column for
MCP6071, SOT-23-5 package.
Updated Section 4.1.2 “Input Voltage Limits”.
Added Section 4.1.3 “Input Current Limits”.
Added new document item in Section 5.5
“Application Notes”.
Updated the Product Identification System
page.
Revision A (March 2009)
• Original Release of this Document.
© 2010 Microchip Technology Inc.
DS22142B-page 35
MCP6071/2/4
NOTES:
DS22142B-page 36
© 2010 Microchip Technology Inc.
MCP6071/2/4
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
-X
/XX
Device
Temperature
Range
Package
Device:
Examples:
a)
b)
c)
MCP6071:
MCP6071T:
MCP6072:
MCP6072T:
MCP6074:
MCP6074T:
Single Op Amp
Single Op Amp (Tape and Reel)
(SOIC, SOT-23 and 2x3 TDFN)
Dual Op Amp
Dual Op Amp (Tape and Reel)
(SOIC and 2x3 TDFN)
Quad Op Amp
Quad Op Amp (Tape and Reel)
(SOIC and TSSOP)
d)
a)
b)
c)
Temperature Range:
E
= -40°C to +125°C
Package:
MNY *
OT =
SL =
SN =
ST =
= Plastic Dual Flat, No Lead, (2x3 TDFN ) 8-leadd
Plastic Small Outline Transistor (SOT-23), 5-lead
Plastic SOIC (150 mil Body), 14-lead
Plastic SOIC, (150 mil Body), 8-lead
Plastic TSSOP (4.4mm Body), 14-lead
* Y = Nickel palladium gold manufacturing designator. Only
available on the TDFN package.
© 2010 Microchip Technology Inc.
MCP6071T-E/OT:
Tape and Reel,
5LD SOT-23 pkg
MCP6071-E/SN:
8LD SOIC pkg
MCP6071T-E/SN: Tape and Reel,
8LD SOIC pkg
MCP6071T-E/MNY: Tape and Reel,
8LD 2x3 TDFN pkg
MCP6072-E/SN:
MCP6072T-E/SN:
8LD SOIC pkg
Tape and Reel,
8LD SOIC pkg
MCP6072T-E/MNY: Tape and Reel
8LD 2x3 TDFN pkg
a)
b)
MCP6074-E/SL:
MCP6074T-E/SL:
c)
d)
MCP6074-E/ST:
MCP6074T-E/ST:
14LD SOIC pkg
Tape and Reel,
14LD SOIC pkg
14LD TSSOP pkg
Tape and Reel,
14LD TSSOP pkg
DS22142B-page 37
MCP6071/2/4
NOTES:
DS22142B-page 38
© 2010 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
PIC32 logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,
TSHARC, UniWinDriver, WiperLock and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2010, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-60932-732-3
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
© 2010 Microchip Technology Inc.
DS22142B-page 39
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://support.microchip.com
Web Address:
www.microchip.com
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Japan - Yokohama
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Cleveland
Independence, OH
Tel: 216-447-0464
Fax: 216-447-0643
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Farmington Hills, MI
Tel: 248-538-2250
Fax: 248-538-2260
Kokomo
Kokomo, IN
Tel: 765-864-8360
Fax: 765-864-8387
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
Santa Clara
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
China - Beijing
Tel: 86-10-8528-2100
Fax: 86-10-8528-2104
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
China - Chongqing
Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
China - Hong Kong SAR
Tel: 852-2401-1200
Fax: 852-2401-3431
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Taiwan - Hsin Chu
Tel: 886-3-6578-300
Fax: 886-3-6578-370
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
Taiwan - Kaohsiung
Tel: 886-7-213-7830
Fax: 886-7-330-9305
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
08/04/10
DS22142B-page 40
© 2010 Microchip Technology Inc.