MP4088 Non-Isolated, High PFC, TRIAC Dimmable LED Driver for 230VAC, Up to 10W LEDs The Future of Analog IC Technology DESCRIPTION FEATURES The MP4088 is a highly integrated, TRIAC dimmable LED driver with an integrated 500V MOSFET that regulates precise LED currents in non-isolated lighting applications and requires only a single winding inductor. The MP4088 features MPS’ proprietary hybrid operation mode, which is designed to achieve optimal dimming performance. The MP4088 is designed specifically for high-line input (230VAC) and TRIAC dimmable LED lighting applications, especially for low-cost and small form-factor applications. • • • • • • • • • • • The accurate output LED current is achieved by an internal averaging current feedback loop. An internal high-voltage regulator makes the MP4088 start up quickly without a perceptible delay. The power de-rating at high temperatures makes the system flicker-free when the ambient temperature is high. • Full protections features include VCC undervoltage lockout (UVLO), over-voltage protection (OVP), and short-circuit protection (SCP). All of these features make the MP4088 an ideal solution for simple, offline, and non-isolated TRIAC dimmable LED lighting applications. The MP4088 is available in TSOT23-5, SOIC87A, and SOIC-8 EP packages. MP4088 Rev. 1.0 11/23/2015 • • • • Excellent TRIAC Dimming Performance Lowest BOM Cost Constant Current LED Driver Integrated 500V MOSFET Internal HV Fast Start-Up Single Winding Inductor High Power Factor (>0.7) Good LED Current Accuracy Supports Buck and Buck-Boost Topology LED Current Foldback at High Temperature Thermal Shutdown (Auto-Restart with Hysteresis) VCC Under-Voltage Lockout with Hysteresis (UVLO) Programmable Over-Voltage Protection (OVP) Output Short-Circuit Protection (SCP) Auto-Restart Function Available in TSOT23-5, SOIC8-7A, and SOIC-8 EP Packages APPLICATIONS • • • 230VAC, Up to 10W LED Lighting Residential and Commercial Lighting TRIAC Dimmable LED Lighting, A19, GU10, PAR Lamps All MPS parts are lead-free, halogen-free, and adhere to the RoHS directive. For MPS green status, please visit the MPS website under Quality Assurance. “MPS” and “The Future of Analog IC Technology” are registered trademarks of Monolithic Power Systems, Inc. www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2015 MPS. All Rights Reserved. 1 MP4088 – NON N-ISOLATED, TRIAC DIMMABLE PFC LED DR RIVER FOR 230VAC TYPICAL APPLICATION (B BUCK) MP4088 L2 HV VCC C4 TRIAC Dimmer OVF C5 C1 FR1 CS R4 198 to 265VAC R3 R2 MP4068 C2 LED+ GND L1 C3 R1 D1 LED- BUCK-BOOST) TYPICAL APPLICATION (B MP4088 L2 HV VCC C4 OVF TRIAC Dimmer MP4068 C5 CS C1 FR1 GND C2 R4 D1 R1 R2 LED- 198 to 265VAC L1 C3 R3 LED+ MP4088 Rev. 1.0 11/23/2015 www.MonolithicPower.com n. Patent Protected. Unauthorized Photocopy and Duplication Pro ohibited. MPS Proprietary Information © 2015 MPS. All Rights Reserved. 2 MP4088 – NON N-ISOLATED, TRIAC DIMMABLE PFC LED DR RIVER FOR 230VAC ORDERING INFORMATION Part Number Package Top Mark king MP4088GJ* TSOT23-5 See Bellow MP4088GS** MP4088GN*** SOIC8-7A SOIC-8 EP See Bellow See Bellow * For Tap pe & Reel, add suffix –Z (e.g. MP4088GN–Z) ** For Tap pe & Reel, add suffix –Z (e.g. MP4088GS–Z) *** For Tape & Reel, add suffix –Z (e.g. MP4088GN–Z) TO OP MARKING (MP4088GJ) ARN: Product code o of MP4088GJ Y: Year code TO OP MARKING (MP4088GS) MP4088: Product cod de of MP4088GS LLLLLLLL: Lot numb ber MPS: MPS prefix Y: Year code WW: Week code TO OP MARKING (MP4088GN) MP4088: Product cod de of MP4088GN LLLLLLLL: Lot numb ber MPS: MPS prefix Y: Year code WW: Week code MP4088 Rev. 1.0 11/23/2015 www.MonolithicPower.com n. Patent Protected. Unauthorized Photocopy and Duplication Pro ohibited. MPS Proprietary Information © 2015 MPS. All Rights Reserved. 3 MP4088 – NON N-ISOLATED, TRIAC DIMMABLE PFC LED DR RIVER FOR 230VAC P PACKAGE REFERENCE TOP VIEW VCC 1 OVF 2 GND 3 TOP VIEW TOP VIEW 5 HV V VCC 1 8 HV G GND 2 4 CS VCC 1 8 NC OVF 2 7 HV GND 3 6 NC 4 5 NC OVF 3 6 GND CS CS 4 5 GND EXPOSED PAD SIDE ON BACKS CONNECT TO GND TSOT23-5 SOIC8-7A SOIC-8 S EP ABSOLUTE MAXIMUM RAT TINGS (1) Thermal Resistance HV to CS...................................... -0 0.3V to 500V VCC, CS to GND .......................... -0 0.3V to 6.5V OVF to GND ................................. -0 0.7V to 6.5V Source current on OVF ..............................4mA (2) Continuous power dissipation (TA = +25°C) TSOT23-5 ................................................ 1.25W SOIC8-7A ……............................................ 1.6W SOIC-8 EP .................................................2.6W Lead temperature .................................... 260°C C to +150°C Storage temperature ................ -60°C ESD capability human body mode ............ 2.0kV CDM ESD capability TSOT23-5 ................................................. 1.5kV SOIC8-7A/SOIC-8 EP.................................. 2kV TSOT23-5 .............................. 100 ..... 55 ... °C/W SOIC8-7A................................ 76 ...... 35 ... °C/W SOIC-8 EP .............................. 48 ...... 10 ... °C/W Recommended Operating Cond ditions (3) (4) θJA θJC NOTES: mage the device. 1) Exceeding these ratings may dam 2) The maximum allowable power dissipation is a function of the maximum junction temperature TJ (MAX), the junction-toa the ambient temperature ambient thermal resistance θJA, and TA. The maximum allowable conttinuous power dissipation at any ambient temperature is calc culated by PD (MAX) = (TJ (MAX)-TA)/θJA. Exceeding the maximum m allowable power dissipation produces an excessiv ve die temperature, causing the regulator to go into thermal shutdown. Internal thermal e device from permanent shutdown circuitry protects the damage. 3) The device is not guaranteed to function outside of its operating conditions. P 4) Measured on JESD51-7, 4-layer PCB. Operating VCC range ....................... 4.5V to 5V MP4088 Rev. 1.0 11/23/2015 www.MonolithicPower.com n. Patent Protected. Unauthorized Photocopy and Duplication Pro ohibited. MPS Proprietary Information © 2015 MPS. All Rights Reserved. 4 MP4088 – NON N-ISOLATED, TRIAC DIMMABLE PFC LED DR RIVER FOR 230VAC ELECTRICAL CHARACTER RISTICS Typical values are VCC = 5V, TJ = 25°C, unless otherwise noted. Minimum and maximum values arre VCC = 5V, TJ = -40°C to +125°C, unless oth herwise noted, guaranteed by characterization. Parameter Symbol Condition Min Ty yp Max Units VCC = 0V, VHV = 100V 3.8 5 6.1 mA 14 4 22 μA 4.3 35 4.7 V Start-Up Current Source (HV) Internal regulator supply current IREGULATOR Leakage current from HV IHV LKG VCC = 5V, VHV = 400V Supply Voltage Management (VCC) VCC upper threshold for internal regulator turn-off VCCOFF VCC rising edge VCC normal level VCCNOR Normal operation VCC lower threshold for internal VCCON VCC falling edge regulator turn-on VCC hysteresis between regulator V VCCOFF-ON on/off VCC lower threshold for IC V VCCSTOP VCC falling edge shutdown VCC hysteresis between regulator VC CCOFF-STOP off/IC shutdown VCC lower threshold where VCCPRO VCC falling edge protection phase ends VCC = 4.3V, Internal IC consumption ICC fsw = 33kHz, duty = 84% Internal IC consumption, latch-off ICC_LATCH VCC = 5V phase Internal MOSFET (HV to CS) Breakdown voltage VBR On-state resistance RDS(ON) IHV = 80µA 4 4.2 25 V 3.8 4..1 4.45 V 0.12 0.2 21 0.3 V 3.0 3..4 3.8 V 0.5 0.9 95 1.4 V 1.90 2.3 35 2.80 V 35 50 400 μA 18 32 μA 500 V IHV = 10mA, TJ = 25°C 8..5 12 Ω VCC = VCCSTOP + 50mV, IHV = 10mA, TJ = 25°C 8..5 12 Ω 0.4 46 0.52 V Current Sampling Management (CS)) Peak current limit at normal operation Leading edge blanking VCS_LIMIT 0.40 tLEB 20 00 ns Feedback threshold to turn on MOSFET Minimum off-time limitation at normal operation VREF 0.186 0.195 0.204 V tOFF_MIN 7.1 9..3 11.8 μs Maximum on-time limitation tON_MAX 3.3 4..5 6 μs σ 0.42 0.4 48 0.58 Ratio of tON_MAX/tOFF_MIN MP4088 Rev. 1.0 11/23/2015 www.MonolithicPower.com n. Patent Protected. Unauthorized Photocopy and Duplication Pro ohibited. MPS Proprietary Information © 2015 MPS. All Rights Reserved. 5 MP4088 – NON N-ISOLATED, TRIAC DIMMABLE PFC LED DR RIVER FOR 230VAC ELECTRICAL CHARACTER RISTICS (continued) Typical values are VCC = 5V, TJ = 25°C, unless otherwise noted. Minimum and maximum values arre at VCC = 5V, TJ = -40°C to +125°C, unless otherwise o noted, guaranteed by characterization. Parameter S Symbol Condition Min Ty yp Max Units 1.85 2.0 2.15 V tOVP 21 32 μs TSTART 14 45 °C TSD 16 60 °C THYS 50 0 °C Protection Input (OVF) Threshold to trigger OVP VOVP Time constraint on OVP comparator Thermal Protection Power de-rating threshold (5) Thermal shutdown threshold Thermal shutdown recovery (5) hysteresis (5) NOTE: 5) Guaranteed by characterization. MP4088 Rev. 1.0 11/23/2015 www.MonolithicPower.com n. Patent Protected. Unauthorized Photocopy and Duplication Pro ohibited. MPS Proprietary Information © 2015 MPS. All Rights Reserved. 6 MP4088 – NON N-ISOLATED, TRIAC DIMMABLE PFC LED DR RIVER FOR 230VAC TYPICAL CHARACTERISTICS MP4088 Rev. 1.0 11/23/2015 www.MonolithicPower.com n. Patent Protected. Unauthorized Photocopy and Duplication Pro ohibited. MPS Proprietary Information © 2015 MPS. All Rights Reserved. 7 MP4088 – NON N-ISOLATED, TRIAC DIMMABLE PFC LED DR RIVER FOR 230VAC TYPICAL PERFORMANCE CHARACTERISTICS Performance waveforms are teste ed on the evaluation board of the Design Exa ample section. VIN = 230VAC, VOUT = 50V, ILED = 16 60mA, TA = 25°C, unless otherwise noted. MP4088 Rev. 1.0 11/23/2015 www.MonolithicPower.com n. Patent Protected. Unauthorized Photocopy and Duplication Pro ohibited. MPS Proprietary Information © 2015 MPS. All Rights Reserved. 8 MP4088 – NON N-ISOLATED, TRIAC DIMMABLE PFC LED DR RIVER FOR 230VAC TYPICAL PERFORMANCE CHARACTERISTICS (continued) Performance waveforms are teste ed on the evaluation board of the Design Exa ample section. VIN = 230VAC, VOUT = 50V, ILED = 16 60mA, TA = 25°C, unless otherwise noted. MP4088 Rev. 1.0 11/23/2015 www.MonolithicPower.com n. Patent Protected. Unauthorized Photocopy and Duplication Pro ohibited. MPS Proprietary Information © 2015 MPS. All Rights Reserved. 9 MP4088 – NON N-ISOLATED, TRIAC DIMMABLE PFC LED DR RIVER FOR 230VAC TYPICAL PERFORMANCE CHARACTERISTICS (continued) Performance waveforms are teste ed on the evaluation board of the Design Exa ample section. VIN = 230VAC, VOUT = 50V, ILED = 16 60mA, TA = 25°C, unless otherwise noted. MP4088 Rev. 1.0 11/23/2015 www.MonolithicPower.com n. Patent Protected. Unauthorized Photocopy and Duplication Pro ohibited. MPS Proprietary Information © 2015 MPS. All Rights Reserved. 10 MP4088 – NON N-ISOLATED, TRIAC DIMMABLE PFC LED DR RIVER FOR 230VAC PIN FUNCTIONS Pin # TSOT23-5 SOIC8-7A SOIC-8 EP N Name Description 1 1 1 V VCC Power supply. VCC is the supply powerr for all of the control circuits. Connect VCC to an external bulk ca apacitor. 3 2, 5, 6 3 G GND C. Ground. GND is the virtual ground of the IC 2 3 2 OVF Output voltage feedback. The over-voltag ge condition is detected on OVF. When the voltage on OVF exceed ds VOVP after a blanking time, OVP is triggered, and the chip shuts down. 4 4 4 CS 5 8 7 HV -- -- 5, 6, 8 NC Current sense of the internal power MOSFET. Connect a resistor from CS to GND to sense the curren nt through the inductor. When the voltage on CS exceeds VCS_LIMIT, the internal MOSFET is turned off. If the start-up time exceeds the maximum on-time, the internal MOSFET is turned off, even tho ough the voltage on CS has not reached VCS LIMIT. High-voltage input of the internal powerr MOSFET. HV is also the input of the internal high-voltage currentt source. Not connected. Exxposed The exposed pad should be connected to the GND plane for optimal thermal performance. Pad MP4088 Rev. 1.0 11/23/2015 www.MonolithicPower.com n. Patent Protected. Unauthorized Photocopy and Duplication Pro ohibited. MPS Proprietary Information © 2015 MPS. All Rights Reserved. 11 MP4088 – NON N-ISOLATED, TRIAC DIMMABLE PFC LED DR RIVER FOR 230VAC BLOCK DIAGRAM VCC P Power agement Mana Start -Up Unit HV TRIAC and PF Management OVF Protecti on Unit Therma al Protecti on GND Minimum equency Fre C ontrol Driving Signal Unit Average Current Control and Dimming Peak Current Limit CS Fiigure 1: Functional Block Diagram MP4088 Rev. 1.0 11/23/2015 www.MonolithicPower.com n. Patent Protected. Unauthorized Photocopy and Duplication Pro ohibited. MPS Proprietary Information © 2015 MPS. All Rights Reserved. 12 MP4088 – NON N-ISOLATED, TRIAC DIMMABLE PFC LED DR RIVER FOR 230VAC OPERATION The MP4088 is a highly integrrated, costeffective, TRIAC dimmable LED driver. The MP4088 requires only a minimal number of external components, making it a competitive IC in high-line (230VAC) input and non-isolated applications, especially for small form-factor de achieves applications. Hybrid operation mod both good dimming performance and accurate output current. The power factor excceeds 0.7 in most applications to eliminate e harmonic pollution on the AC line. The integ grated highvoltage regulator enables fast starrt-up without any perceptible delay. The powe er de-rating function at high temperatures prottects the IC from thermal damage. Hybrid Operation Mode mming, the To achieve smooth TRIAC dim MP4088 implements proprieta ary hybrid operation mode, in which the IC selff-adjusts the internal switching mode between CCM and C cycle. The DCM during different times of the AC hybrid operation mode actively maintains the latching current and holding current of the good power leading edge TRIAC to enable a g factor. The hybrid operation mode also achieves a small dimming duty condition. The IC works in n time when CCM during the entire dimming on the dimmer is set to a small dimm ming duty. A higher and smoother input current ccan achieve excellent dimming performance. Power Supply The IC is self-supplied by the internal highvoltage regulator, which is drawn fro om HV. The IC begins switching, and the intternal highvoltage regulator turns off once the e voltage on VCC reaches VCCOFF. When the voltage on VCC falls below VCCON, the intternal highvoltage regulator turns on again to o charge the external VCC capacitor. VCC is rregulated at VCCNOR for normal operation. In TRIAC dimming applications, the internal high-voltage regulator only workss when the dimmer is on. To maintain a sufficcient driving capacity, a capacitor of 10μF o or larger is recommended for VCC. If a ssingle VCC ower supply capacitor cannot provide enough po for the chip, an external chargin ng circuit is recommended (see Figure 2). MP4088 Rev. 1.0 11/23/2015 CCSTOP, the IC stops When VCC drops below VC working, and the internal high-voltage regulator recharges the VCC capacito or. Figure 2: VCC Charrging Circuit When a fault conditions occ curs, such as OVP or OTP, the MP4088 stops s working, and an internal current source (ICC_LATCH) discharges the VCC capacitor. After VCC drops below VCCPRO, the internal high-voltage V capacitor. The regulator recharges the VCC restart time can be calculate ed with Equation (1): tRESTART = CVCC × VCCNOR − VCCPRO VCCOFF − VCCPRO + CVCC × ICC_LATCH IREGULATOR (1) Figure 3 shows the typical waveform with VCC under-voltage lockout. Figure 3: VCC Under-Volta age Lockout (UVLO) Constant Current Operatio on The MP4088 is a highly in ntegrated driver. The internal feedback logic resp ponds to the internal sample and hold circuit to t achieve constant output-current regulation. The voltage of the internal sampling capacitor (VFB) is compared to the internal reference (VREF). When the sampling capacitor voltage (VFB) falls below the reference voltage, indicating an insuffficient output current, the integrated MOSFET is s turned on. The on period is determined by the peak current limit. After the on period elapses, the integrated MOSFET turns off (see Figu ure 4). www.MonolithicPower.com n. Patent Protected. Unauthorized Photocopy and Duplication Pro ohibited. MPS Proprietary Information © 2015 MPS. All Rights Reserved. 13 MP4088 – NON N-ISOLATED, TRIAC DIMMABLE PFC LED DR RIVER FOR 230VAC MOS Diode IPK IL IO VO V FB VRE F Figure 4: VFB vs. IOUT The inductor’s average curren nt can be regulated by monitoring the intern nal sampling capacitor voltage. The inductor averrage current can be calculated with Equation (2): IL _ AVG = VREF RS (2) The peak inductor current can be e calculated with Equation (3): IPK = VCS _ LIMIT RS (3) Where RS is the sense resistor connected from CS to GND. Minimum Operating Frequency Limit The MP4088 incorporates a minimu um operating frequency (22kHz) to eliminate au udible noise. When the operating frequency iss less than 22kHz, the internal peak curren nt regulator decreases the peak current value to keep the operating frequency constant at abo out 22kHz. Minimum Off-Time Limit The MP4088 implements a minim mum off-time limit. During normal operation, the m minimum offtime limit is 9.3μs. In the start-up period, the minimum off-time limit is shortene ed gradually from 3.5 times to 1.2 times the norm mal minimum off-time (see Figure 5). Each minim mum off-time limit lasts for 32 switching cycles. T This process ensures a soft-start function of the IC to safely start up the part. Driver ≥ t MIN_OFF ×3.5 ≥tMIN _OFF ×2 ≥t MIN_OFF ×1.2 Thermal Protection To protect the IC and the system s from thermal damage, the MP4088 reduces the reference to decrease the output curre ent. This limits the temperature rising speed of the IC when the junction temperature exc ceeds 145°C. The output current drops to aro ound 20% when the IC temperature rises to 160°C. Once the junction temperature exc ceeds 160°C, the MP4088 shuts down the sw witching cycle. Once the junction temperature drops d below 110°C, the power supply resume es operation. During thermal shutdown, VCC is discharged to VCCPRO, and then it is recha arged by the internal high-voltage regulator. OVP) Over-Voltage Protection (O If VOVF is higher than VOVP when the MOSFET ops working and a turns off, the MP4088 sto restart cycle begins. Whe en OVP occurs, the chip works in hiccup mode. m The MP4088 monitors the OVF voltage e continuously, and VCC discharges and recharrges repeatedly. The MP4088 resumes operatio on once the fault is removed. SCP) Short-Circuit Protection (S When an LED short circuit occurs, o the switching off-time is extended. Due e to the minimum operating frequency limit, the IC reduces the atically and achieves switching frequency automa a closed loop control. The output power at this condition is limited at a safe range. The MP4088 resumes normal operation once the short circuit is released. LEB) Leading Edge Blanking (L Internal leading edge blanking (LEB) is witching pulse from employed to prevent a sw terminating prematurely due to parasitic capacitance discharging when w the MOSFET turns on. During the blanking time, the path c input is from CS to the current comparator blocked. Figure 6 shows s the leading-edge blanking time. VCS ≥tMIN _OFF t LEB V LIMIT 32 Switching Cycles 32 Switching Cycles 32 Switching Cycles Figure 5: tOFF_MIN at Start-U Up t Figure 6: Leading Edge e Blanking (LEB) MP4088 Rev. 1.0 11/23/2015 www.MonolithicPower.com n. Patent Protected. Unauthorized Photocopy and Duplication Pro ohibited. MPS Proprietary Information © 2015 MPS. All Rights Reserved. 14 MP4088 – NON N-ISOLATED, TRIAC DIMMABLE PFC LED DR RIVER FOR 230VAC APPLICATION INFORMATIION Selecting the Inductor The MP4088 has a minimum off-tim me limit. The inductor current ripple at CCM is de etermined by the inductor value and the minim mum off-time limit. The current ripple is limited to 80% to achieve a tradeoff between the p power factor and the dimming performance. The e inductance value can be calculated with Equatio on (4): L= VOUT × t OFF _ MIN Figure 7: Feedback Resistor Connection 0.8 × IPEAK The upper feedback resis stor (R3) should be larger than 100kΩ to avoid a an efficiency reduction in the applicatio on. A 1% tolerance type is recommended to o achieve accurate protection. (4) If the inductance value is too larg ge, then the switching frequency is low and d the EMI performance is good. However, the TRIAC dimming performance is poor in this condition. If the inductance value is too small, the TRIAC dimming performance is good, but the system may work in an open-loop condition, making the e, a tradeoff current consistency poor. Therefore must be made. Freewheeling Diode um reverseThe diode should have a maximu voltage rating greater than the maxximum input voltage. The current rating of th he diode is determined by the output current, w which should be larger than 1.5 to 2 times the outp put current. Slow diodes cause excessive and d unwanted leading edge current spikes during g start-up. A long reverse-recovery time of the ffreewheeling diode can affect efficiency and circu uit operation as well. An ultrafast diode (trr < 75n ns), such as WUGC10JH or ES1G, is recommended. Dummy Load The dummy load is used to o consume the power transferred to the output capacitor c when OVP occurs. The IC works in hiccup h mode without any power consumption. Normally, a dummy load less than 1mA is recommended. This does not deteriorate the n guarantee normal system efficiency but can over-voltage protection. Surge Place an appropriate RCD snubber beside the diode rectifier bridge for f optimal surge performance. For mostt applications, a 1µF/400V electrolytic capa acitor with a 1000V diode is recommended. The resistor can be as large as 1MΩ to reduce power loss during normal operation. Over-Voltage Protection (OVP) Po oint Set A feedback resistor is used to dete ect an overvoltage condition. Figure 7 sshows the connection of the feedback resistor. over-voltage The MP4088 employs an o protection (OVP). When OVP is triggered, the maximum output voltage can be callculated with Equation (5): VOUT _ OVP = VOVP ⋅ R2 + R3 − VD R2 (5) Where VD is the freewheeling dio ode forward voltage drop. MP4088 Rev. 1.0 11/23/2015 www.MonolithicPower.com n. Patent Protected. Unauthorized Photocopy and Duplication Pro ohibited. MPS Proprietary Information © 2015 MPS. All Rights Reserved. 15 MP4088 – NON N-ISOLATED, TRIAC DIMMABLE PFC LED DR RIVER FOR 230VAC PCB Layout Guidelines Efficient PCB layout is critical for stable od thermal operation, good EMI, and goo performance, especially in very small LED applications. For best results, refer to Figure 8 and follow the guidelines below: he MP4088, 1. Keep the loop formed between th the inductor, the freewheeling dio ode, and the possible for output capacitor as small as p better EMI. 2. Place the AC input far awayy from the switching nodes to minimize the noise coupling that may bypass the input filter. ose to VCC 3. Place the VCC capacitor as clo and GND as possible. Design Example Table 1 is a design exa ample following the application guidelines base ed on the following specifications: Table 1: Design Example VIN VOUT IOUT 198V VAC to 265VAC 55V 100mA Figure 9 shows the detailed d application schematic. This circuit is used for the typical performance and circuit waveforms. For more e refer to the related device applications, please evaluation board datasheets s. 4. Place the feedback resistor as close to OVF e feedback as possible to minimize the sampling loop and minimize the noise coupling route. C, remember 5. If using SOIC-8 EP package IC to connect the exposed pad to GN ND plane. Top Layer Bottom Layer Layout Figure 8: Recommended PCB L MP4088 Rev. 1.0 11/23/2015 www.MonolithicPower.com n. Patent Protected. Unauthorized Photocopy and Duplication Pro ohibited. MPS Proprietary Information © 2015 MPS. All Rights Reserved. 16 MP4088 – NON N-ISOLATED, TRIAC DIMMABLE PFC LED DR RIVER FOR 230VAC TYPICAL APPLICATION CIIRCUITS Figure 9 shows a typical application example of a 55V, 100mA, non-isolated, buck-b boost topology LED driver with the MP4088. Figure 9: T Typical Buck-Boost Converter Application MP4088 Rev. 1.0 11/23/2015 www.MonolithicPower.com n. Patent Protected. Unauthorized Photocopy and Duplication Pro ohibited. MPS Proprietary Information © 2015 MPS. All Rights Reserved. 17 MP4088 – NON N-ISOLATED, TRIAC DIMMABLE PFC LED DR RIVER FOR 230VAC PACKAGE INFORMATION TSOT23-5 0.60 TYP 2.80 3.00 5 4 1.20 TYP 1.50 1.70 1 0.95 BSC 2.60 3.00 2.60 TYP 3 TOP VIEW RECOMMENDED LAND D PATTERN 0.70 0.90 1.00 MAX 0.09 0.20 SEATING PLANE 0.30 0.50 0.95 BSC 0.00 0.10 SEE DETAIL "A" FRONT VIEW SIDE VIEW NOTE: GAUGE PLANE 0.25 BSC 0o-8o 0.30 0.50 DETAIL “A” MP4088 Rev. 1.0 11/23/2015 1) ALL DIMENSIONS ARE IN MILLIMET ERS. UDE MOLD FLASH , 2) PACKAGE LENGTH DOES NOT INCLU PROTRUSION OR GATE BURR. 3) PACKAGE WIDTH DOES NOT INCLUD DE INTERLEAD FLASH OR PROTRUSION. 4) LEAD COPLANARITY(BOTTOM OF LE EADS AFTER FORMING) SHALL BE 0.10 MILLIMETERS MAX. 5) DRAWING CONFORMS TO JEDEC MO O-193, VARIATION AA. 6) DRAWING IS NOT TO SCALE. www.MonolithicPower.com n. Patent Protected. Unauthorized Photocopy and Duplication Pro ohibited. MPS Proprietary Information © 2015 MPS. All Rights Reserved. 18 MP4088 – NON N-ISOLATED, TRIAC DIMMABLE PFC LED DR RIVER FOR 230VAC PACKAGE INFORMATION (continued) SOIC8-7A 0.189(4.80) 0.197(5.00) 8 0 0.050(1.27) 0.024(0.61) 5 0.063(1.60) 0.150(3.80) 0.157(4.00) PIN 1 ID 1 0.228(5.80) 0.244(6.20) 0.213(5.40) 4 TOP VIEW RECOMMENDED LAND PA ATTERN 0.053(1.35) 0 0 0.069(1.75) S SEATING PLANE 0.004 4(0.10) 0.010 0(0.25) 0.013(0.3 33) 0.020(0.5 51) 0.050(1.27) BSC 0.0075(0.19) 0.0098(0.25) SEE DETAIL "A" SIDE VIEW FRONT VIEW 0.010(0.25) x 45o 0.020(0.50) GAUGE PLANE 0.010(0.25) BSC 0o-8o 0.016(0.41) 0.050(1.27) DETAIL "A" MP4088 Rev. 1.0 11/23/2015 NOTE: 1) CONTROL DIMENSION IS IN INCHES S. DIMENSION IN BRACKET IS IN MILLIMETERS. LUDE MOLD FLASH , 2) PACKAGE LENGTH DOES NOT INCL PROTRUSIONS OR GATE BURRS. 3) PACKAGE WIDTH DOES NOT INCLU UDE INTERLEAD FLASH OR PROTRUSIONS. L AFTER FORMING) 4) LEAD COPLANARITY(BOTTOM OF LEADS SHALL BE 0.004" INCHES MAX. 5) JEDEC REFERENCE IS MS-012. 6) DRAWING IS NOT TO SCALE. www.MonolithicPower.com n. Patent Protected. Unauthorized Photocopy and Duplication Pro ohibited. MPS Proprietary Information © 2015 MPS. All Rights Reserved. 19 MP4088 – NON N-ISOLATED, TRIAC DIMMABLE PFC LED DR RIVER FOR 230VAC PACKAGE INFORMATION (continued) SOIC-8 EP 0.189(4.80) 0.197(5.00) 8 0.124(3.15) 0.136(3.45) 5 0.15 50(3.80) 0.15 57(4.00) PIN 1 ID 1 0.228(5.80) 0.244(6.20) 0.089(2.26) 0.101(2.56) 4 TOP VIEW BOTTOM VIEW SEE DETAIL "A" 0.013(0.33) 0.020(0.51) 0 0.051(1.30) 0 0.067(1.70) S SEATING PLANE 0.000 0(0.00) 0.006 6(0.15) 0.0075(0.19) 0.0098(0.25) SIDE VIEW 0.050(1.27) BSC FRONT VIEW 0.010(0.25 5) x 45o 0.020(0.50 0) GAUGE PLANE 0.010(0.25) BSC 0.050(1.27) 0.020(0.51) 0o-8o 0.047(1.20) 0.016(0.41) 0.050(1.27) DETAIL "A" 0.089(2.2 26) 0.236(6.00) NOTE: 0.124(3.15) RECOMMENDED LAND PATTERN 1) CONTROL DIMENSION IS IN INCHES. DIMENSION D IN BRACKET IS IN MILLIMETERS. 2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH , PROTRUSIONS OR GATE BURRS. E INTERLEAD FLASH 3) PACKAGE WIDTH DOES NOT INCLUDE OR PROTRUSIONS. 4) LEAD COPLANARITY(BOTTOM OF LEA ADS AFTER FORMING) SHALL BE 0.004" INCHES MAX. 012, VARIATION BA. 5) DRAWING CONFORMS TO JEDEC MS-0 6) DRAWING IS NOT TO SCALE. NOTICE: The information in this document is subject to change without notice. Users should warrantt and guarantee that third nfringed upon when integrating MPS products into any application. a MPS will not party Intellectual Property rights are not in assume any legal responsibility for any said applications. MP4088 Rev. 1.0 11/23/2015 www.MonolithicPower.com n. Patent Protected. Unauthorized Photocopy and Duplication Pro ohibited. MPS Proprietary Information © 2015 MPS. All Rights Reserved. 20