54LS74/DM54LS74A/DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs General Description This device contains two independent positive-edge-triggered D flip-flops with complementary outputs. The information on the D input is accepted by the flip-flops on the positive going edge of the clock pulse. The triggering occurs at a voltage level and is not directly related to the transition time of the rising edge of the clock. The data on the D input may be changed while the clock is low or high without affecting the outputs as long as the data setup and hold times are not violated. A low logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the other inputs. Features Y Alternate military/aerospace device (54LS74) is available. Contact a National Semiconductor Sales Office/ Distributor for specifications. Connection Diagram Dual-In-Line Package TL/F/6373 – 1 Order Number 54LS74DMQB, 54LS74FMQB, 54LS74LMQB, DM54LS74AJ, DM54LS74AW, DM74LS74AM or DM74LS74AN See NS Package Number E20A, J14A, M14A, N14A or W14B Function Table Inputs Outputs PR CLR CLK D Q Q L H L H H H H L L H H H X X X X X X H L X H L H* H L Q0 L H H* L H Q0 u u L H e High Logic Level X e Either Low or High Logic Level L e Low Logic Level u e Positive-going Transition * e This configuration is nonstable; that is, it will not persist when either the preset and/or clear inputs return to their inactive (high) level. Q0 e The output logic level of Q before the indicated input conditions were established. C1995 National Semiconductor Corporation TL/F/6373 RRD-B30M105/Printed in U. S. A. 54LS74/DM54LS74A/DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs June 1989 Absolute Maximum Ratings (Note) Note: The ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the ‘‘Electrical Characteristics’’ table are not guaranteed at the absolute maximum ratings. The ‘‘Recommended Operating Conditions’’ table will define the conditions for actual device operation. If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage 7V Input Voltage 7V Operating Free Air Temperature Range b 55§ C to a 125§ C DM54LS and 54LS DM74LS 0§ C to a 70§ C Storage Temperature Range b 65§ C to a 150§ C Recommended Operating Conditions Symbol VCC Supply Voltage VIH High Level Input Voltage VIL Low Level Input Voltage IOH High Level Output Current IOL Low Level Output Current fCLK Clock Frequency (Note 2) fCLK tW tW DM54LS74A Parameter DM74LS74A Nom Max Min Nom Max 4.5 5 5.5 4.75 5 5.25 2 2 V 0.7 0.8 V b 0.4 mA 4 25 Clock Frequency (Note 3) 0 20 Pulse Width (Note 2) 18 Pulse Width (Note 3) V b 0.4 0 Clock High Units Min 8 mA 0 25 MHz 0 20 MHz 18 Preset Low 15 15 Clear Low 15 15 Clock High 25 25 Preset Low 20 20 Clear Low 20 20 ns ns tSU Setup Time (Notes 1 and 2) 20u 20u ns tSU Setup Time (Notes 1 and 3) 25u 25u ns tH Hold Time (Note 1 and 4) 0u TA Free Air Operating Temperature b 55 Note 1: The symbol ( 0u 125 u) indicates the rising edge of the clock pulse is used for reference. Note 2: CL e 15 pF, RL e 2 kX, TA e 25§ C, and VCC e 5V. Note 3: CL e 50 pF, RL e 2 kX, TA e 25§ C, and VCC e 5V. Note 4: TA e 25§ C and VCC e 5V. 2 0 ns 70 §C Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Min Typ (Note 1) DM54 2.5 3.4 DM74 2.7 3.4 Conditions Max Units b 1.5 V VI Input Clamp Voltage VCC e Min, II e b18 mA VOH High Level Output Voltage VCC e Min, IOH e Max VIL e Max, VIH e Min Low Level Output Voltage VCC e Min, IOL e Max VIL e Max, VIH e Min DM54 0.25 DM74 0.35 0.5 IOL e 4 mA, VCC e Min DM74 0.25 0.4 VCC e Max VI e 7V Data VOL II IIH Input Current @ Max Input Voltage High Level Input Current VCC e Max VI e 2.7V V 0.4 0.1 Clock 0.1 Preset 0.2 Clear 0.2 Data 20 Clock 20 Clear 40 Preset IIL Low Level Input Current VCC e Max VI e 0.4V ICC Short Circuit Output Current VCC e Max (Note 2) Supply Current VCC e Max (Note 3) mA mA 40 Data b 0.4 Clock b 0.4 Preset b 0.8 Clear IOS V mA b 0.8 DM54 b 20 b 100 DM74 b 20 b 100 4 8 mA mA Note 1: All typicals are at VCC e 5V, TA e 25§ C. Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second. For devices, with feedback from the outputs, where shorting the outputs to ground may cause the outputs to change logic state an equivalent test may be performed where VO e 2.25V and 2.125V for DM54 and DM74 series, respectively, with the minimum and maximum limits reduced by one half from their stated values. This is very useful when using automatic test equipment. Note 3: With all outputs open, ICC is measured with CLOCK grounded after setting the Q and Q outputs high in turn. Switching Characteristics at VCC e 5V and TA e 25§ C (See Section 1 for Test Waveforms and Output Load) Symbol Parameter RL e 2 kX From (Input) To (Output) CL e 15 pF Min Max 25 CL e 50 pF Min Units Max fMAX Maximum Clock Frequency tPLH Propagation Delay Time Low to High Level Output Clock to Q or Q 25 35 ns tPHL Propagation Delay Time High to Low Level Output Clock to Q or Q 30 35 ns tPLH Propagation Delay Time Low to High Level Output Preset to Q 25 35 ns tPHL Propagation Delay Time High to Low Level Output Preset to Q 30 35 ns tPLH Propagation Delay Time Low to High Level Output Clear to Q 25 35 ns tPHL Propagation Delay Time High to Low Level Output Clear to Q 30 35 ns 3 20 MHz Physical Dimensions inches (millimeters) Ceramic Leadless Chip Carrier Package (E) Order Number 54LS74LMQB NS Package Number E20A 14-Lead Ceramic Dual-In-Line Package (J) Order Number 54LS74DMQB or DM54LS74AJ NS Package Number J14A 4 Physical Dimensions inches (millimeters) (Continued) 14-Lead Small Outline Molded Package (M) Order Number DM74LS74AM NS Package Number M14A 14-Lead Molded Dual-In-Line Package (N) Order Number DM74LS74AN NS Package Number N14A 5 54LS74/DM54LS74A/DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs Physical Dimensions inches (millimeters) (Continued) 14-Lead Ceramic Flat Package (W) Order Number 54LS74FMQB or DM54LS74AW NS Package Number W14B LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. 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