Product Folder Sample & Buy Support & Community Tools & Software Technical Documents ISO7330C, ISO7330FC, ISO7331C, ISO7331FC SLLSEK9B – JANUARY 2015 – REVISED APRIL 2015 ISO733x Robust EMC, Low Power, Triple-Channel Digital Isolators 1 Features 3 Description • • • • ISO733x provide galvanic isolation up to 3000 VRMS for 1 minute per UL and 4242 VPK per VDE. These devices have three isolated channels comprised of logic input and output buffers separated by a silicon dioxide (SiO2) insulation barrier. ISO7330 has all three channels in the same direction while ISO7331 has two channels in forward and one channel in reverse direction. In case of input power or signal loss, default output is 'low' for devices with suffix 'F' and 'high' for devices without suffix 'F'. Used in conjunction with isolated power supplies, these devices prevent noise currents on a data bus or other circuits from entering the local ground and interfering with or damaging sensitive circuitry. ISO733x has integrated noise filter for harsh industrial environment where short noise pulses may be present at the device input pins. ISO733x has TTL input thresholds and operates from 3 V to 5.5 V supply levels. Through innovative chip design and layout techniques, electromagnetic compatibility of ISO733x has been significantly enhanced to enable systemlevel ESD, EFT, Surge and Emissions compliance. 1 • • • • • • • • • Signaling Rate: 25 Mbps Integrated Noise Filter on the Inputs Default Output 'High' and 'Low' Options Low Power Consumption: Typical ICC per Channel at 1 Mbps: – ISO7330: 1 mA (5 V Supplies), 0.8 mA (3.3 V Supplies) – ISO7331: 1.4 mA (5 V Supplies), 1 mA (3.3 V Supplies) Low Propagation Delay: 32 ns Typical (5V Supplies) Operates from 3.3 V and 5 V Supplies 3.3 V and 5 V Level Translation Wide Temperature Range: –40°C to 125°C 70 KV/μs Transient Immunity, Typical (5V Supplies) Robust Electromagnetic Compatibility (EMC) – System-level ESD, EFT, and Surge Immunity – Low Emissions Wide Body SOIC-16 Package Isolation Barrier Life: > 25 Years Safety and Regulatory Approvals: – 4242 VPK Isolation per DIN V VDE V 0884-10 and DIN EN 61010-1 – 3000 VRMS Isolation for 1 minute per UL 1577 – CSA Component Acceptance Notice 5A, IEC 60950-1 and IEC 61010-1 End Equipment Standards – CQC Certification per GB4943.1-2011 Device Information(1) PART NUMBER ISO7330FC ISO7331C Opto-Coupler Replacement in: – Industrial FieldBus – ProfiBus – ModBus – DeviceNet™ Data Buses – Servo Control Interface – Motor Control – Power Supplies – Battery Packs BODY SIZE (NOM) SOIC (16) 10,3mm x 7,5mm ISO7331FC (1) For all available packages, see the orderable addendum at the end of the datasheet. Simplified Schematic VCCO VCCI Isolation Capacitor 2 Applications • PACKAGE ISO7330C INx OUTx ENx GNDI GNDO (1) VCCI and GNDI are supply and ground connections respectively for the input channels. (2) VCCO and GNDO are supply and ground connections respectively for the output. 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. ISO7330C, ISO7330FC, ISO7331C, ISO7331FC SLLSEK9B – JANUARY 2015 – REVISED APRIL 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 4 4 4 4 5 6 7 7 8 Absolute Maximum Ratings ..................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Electrical Characteristics........................................... Switching Characteristics .......................................... Switching Characteristics .......................................... Typical Characteristics .............................................. Parameter Measurement Information ................ 10 Detailed Description ............................................ 12 8.1 Overview ................................................................. 12 8.2 Functional Block Diagram ....................................... 12 8.3 Feature Description................................................. 13 8.4 Device Functional Modes........................................ 16 9 Applications and Implementation ...................... 17 9.1 Application Information............................................ 17 9.2 Typical Application ................................................. 17 10 Power Supply Recommendations ..................... 19 11 Layout................................................................... 20 11.1 PCB Material ......................................................... 20 11.2 Layout Guidelines ................................................. 20 11.3 Layout Example .................................................... 20 12 Device and Documentation Support ................. 21 12.1 12.2 12.3 12.4 Related Links ........................................................ Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 21 21 21 21 13 Mechanical, Packaging, and Orderable Information ........................................................... 21 4 Revision History Changes from Revision A (April 2015) to Revision B Page • Changed "(VDE V 0884-10):2006-12" To "and DIN EN 61010-1" in the 4242 VPK in the Features ..................................... 1 • Changed From: VCCI To: VCC in Figure 12 ........................................................................................................................... 10 • Deleted IEC from the section title: Package Insulation Specifications ................................................................................ 13 • Changed the CTI Test Conditions in Package Insulation Specifications ............................................................................ 13 • Changed VISO Test Condition in the Insulation Characteristics table .................................................................................. 14 • Deleted the VISO Specification 3600 in the Insulation Characteristics table ........................................................................ 14 Changes from Original (January 2015) to Revision A Page • Changed the device From: Product Preview To: Production data ........................................................................................ 1 • Changed Features From: ISO7330: TBD mA To: 1 mA......................................................................................................... 1 • Changed Features From: ISO731: TBD mA (3.3 V Supplies) To: 0.8 mA............................................................................. 1 • Changed Features From: ISO731: TBD mA (5 V Supplies) To: 1.4 mA................................................................................ 1 • Changed Features From: 65 KV/μs Transient Immunity To: 70 KV/μs Transient Immunity .................................................. 1 • Changed the Safety and Regulatory Approvals Features ...................................................................................................... 1 • Changed the Simplified Schematic and added Notes 1 and 2............................................................................................... 1 2 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ISO7330C ISO7330FC ISO7331C ISO7331FC ISO7330C, ISO7330FC, ISO7331C, ISO7331FC www.ti.com SLLSEK9B – JANUARY 2015 – REVISED APRIL 2015 5 Pin Configuration and Functions ISO7330 DW (SOIC) Package (Top View) ISO7331 DW (SOIC) Package (Top View) VCC1 1 16 VCC2 GND1 2 15 GND2 INA INB 3 14 OUTA 4 13 OUTB INC 5 12 OUTC NC 6 11 NC NC 7 10 EN GND1 9 8 GND2 VCC1 1 16 GND1 2 15 GND2 VCC2 INA INB 3 14 OUTA 4 13 OUTB OUTC 5 12 INC NC 6 11 NC EN1 7 10 EN2 GND1 8 9 GND2 Pin Functions PIN NAME ISO7330 ISO7331 I/O DESCRIPTION VCC1 1 1 – Power supply, VCC1 VCC2 16 16 – Power supply, VCC2 GND1 2, 8 2, 8 – Ground connection for VCC1 GND2 9, 15 9, 15 – Ground connection for VCC2 INA 3 3 I Input, channel A INB 4 4 I Input, channel B INC 5 12 I Input, channel C NC 6, 7, 11 6, 11 – No Connect. These pins have no internal connection. OUTA 14 14 O Output, channel A OUTB 13 13 O Output, channel B OUTC 12 5 O Output, channel C EN 10 – I Output enable. OUTA, OUTB, and OUTC are enabled when EN is high or disconnected and disabled when EN is low. EN1 – 7 I Output enable 1. OUTC is enabled when EN1 is high or disconnected and disabled when EN1 is low. EN2 – 10 I Output enable 2. OUTA and OUTB are enabled when EN2 is high or disconnected and disabled when EN2 is low. Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ISO7330C ISO7330FC ISO7331C ISO7331FC 3 ISO7330C, ISO7330FC, ISO7331C, ISO7331FC SLLSEK9B – JANUARY 2015 – REVISED APRIL 2015 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings (1) Supply voltage (2) Voltage (2) MIN MAX VCC1 , VCC2 –0.5 6 INx, OUTx, ENx –0.5 VCC+0.5 (3) Output current, IO Junction temperature, TJ Storage temperature, Tstg (1) –65 UNIT V V ±15 mA 150 °C 150 °C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal and are peak voltage values. Maximum voltage must not exceed 6 V. (2) (3) 6.2 ESD Ratings Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 VESD (1) (2) (1) Charged device model (CDM), per JEDEC specification JESD22-C101 (2) VALUE UNIT ±4000 V ±1500 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions MIN VCC1, VCC2 Supply voltage IOH High-level output current IOL Low-level output current VIH High-level input voltage VIL Low-level input voltage tui Input pulse duration 1 / tui TJ (1) 3 5.5 4 2 5.5 0 0.8 40 -40 V mA V V ns 0 Ambient temperature UNIT mA Junction temperature TA MAX –4 Signaling rate (1) TYP 25 25 Mbps 136 °C 125 °C To maintain the recommended operating conditions for TJ, see the Thermal Information table. 6.4 Thermal Information DW PACKAGE THERMAL METRIC (1) (16) PINS RθJA Junction-to-ambient thermal resistance 78.3 RθJCtop Junction-to-case (top) thermal resistance 40.9 RθJB Junction-to-board thermal resistance 42.9 ψJT Junction-to-top characterization parameter 15.3 ψJB Junction-to-board characterization parameter 42.4 RθJCbot Junction-to-case (bottom) thermal resistance N/A PD (ISO7330) Maximum Power Dissipation by ISO7330 PD1 (ISO7330) Maximum Power Dissipation by Side-1 of ISO7330 PD2 (ISO7330) Maximum Power Dissipation by Side-2 of ISO7330 PD (ISO7331) Maximum Power Dissipation by ISO7331 PD1 (ISO7331) Maximum Power Dissipation by Side-1 of ISO7331 PD2 (ISO7331) Maximum Power Dissipation by Side-2 of ISO7331 (1) 4 VCC1 = VCC2 = 5.5V, TJ = 150°C, CL = 15pF, Input a 12.5 MHz 50% duty cycle square wave VCC1 = VCC2 = 5.5V, TJ = 150°C, CL = 15pF, Input a 12.5 MHz 50% duty cycle square wave UNIT °C/W 70 20 mW 50 84 35 mW 49 For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ISO7330C ISO7330FC ISO7331C ISO7331FC ISO7330C, ISO7330FC, ISO7331C, ISO7331FC www.ti.com SLLSEK9B – JANUARY 2015 – REVISED APRIL 2015 6.5 Electrical Characteristics VCC1 and VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted) PARAMETER MIN TYP IOH = –4 mA; see Figure 11 TEST CONDITIONS VCCO (1)– 0.5 4.7 IOH = –20 μA; see Figure 11 VCCO (1) – 0.1 5 VOH High-level output voltage VOL Low-level output voltage VI(HYS) Input threshold voltage hysteresis IIH High-level input current IN = VCC IIL Low-level input current IN = 0 V CMTI Common-mode transient immunity VI = VCC or 0 V; see Figure 14. MAX V IOL = 4 mA; see Figure 11 0.2 0.4 IOL = 20 μA; see Figure 11 0 0.1 480 V mV 10 μA μA –10 25 UNIT 70 kV/μs SUPPLY CURRENT (All inputs switching with square wave clock signal for dynamic ICC measurement) ISO7330 ICC1 ICC2 ICC1 ICC2 Disable VI = VCC or 0 V, EN = 0 V 0.5 1.1 0.4 0.9 DC to 1 Mbps DC Input: VI = VCC or 0 V, AC Input: CL = 15pF 0.5 1.1 2.6 4.2 1.1 1.9 Supply current for VCC1 and VCC2 ICC1 10 Mbps ICC2 ICC1 ICC2 CL = 15pF 4.3 6 2.1 3.3 7 9.3 25 Mbps CL = 15pF Disable VI = VCC or 0 V, EN1 = EN2 = 0 V 0.7 1.6 0.7 1.3 DC to 1 Mbps DC Input: VI = VCC or 0 V, AC Input: CL = 15pF 1.8 3 2.4 3.6 10 Mbps CL = 15pF 2.8 4.1 3.8 5.1 4.3 6.2 5.8 7.8 mA ISO7331 ICC1 ICC2 ICC1 ICC2 ICC1 Supply current for VCC1 and VCC2 ICC2 ICC1 25 Mbps ICC2 (1) CL = 15pF mA VCCO is supply voltage, VCC1 or VCC2, for the output channel being measured. Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ISO7330C ISO7330FC ISO7331C ISO7331FC 5 ISO7330C, ISO7330FC, ISO7331C, ISO7331FC SLLSEK9B – JANUARY 2015 – REVISED APRIL 2015 www.ti.com 6.6 Electrical Characteristics VCC1 and VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted) PARAMETER MIN TYP IOH = –4 mA; see Figure 11 TEST CONDITIONS VCCO (1)– 0.5 3 IOH = –20 μA; see Figure 11 VCCO (1)– 0.1 3.3 VOH High-level output voltage VOL Low-level output voltage VI(HYS) Input threshold voltage hysteresis IIH High-level input current IN = VCC IIL Low-level input curre IN = 0 V CMTI Common-mode transient immunity VI = VCC or 0 V; see Figure 14 MAX V IOL = 4 mA; see Figure 11 0.2 0.4 IOL = 20 μA; see Figure 11 0 0.1 425 V mV 10 μA μA -10 25 UNIT 50 kV/μs SUPPLY CURRENT(All inputs switching with square wave clock signal for dynamic ICC measurement) ISO7330 ICC1 ICC2 ICC1 ICC2 Disable VI = VCC or 0 V, EN = 0 V 0.3 0.6 0.3 0.6 DC to 1 Mbps DC Input: VI = VCC or 0 V, AC Input: CL = 15pF 0.3 0.6 2 3.1 0.7 1.1 3.1 4.3 Supply current for VCC1 and VCC2 ICC1 10 Mbps ICC2 ICC1 ICC2 CL = 15pF 1.2 2 4.8 6.3 25 Mbps CL = 15pF Disable VI = VCC or 0 V, EN = 0 V 0.5 0.9 0.5 0.8 DC Input: VI = VCC or 0 V, AC Input: CL = 15pF 1.3 2.1 1.7 2.6 1.9 2.7 2.6 3.5 2.9 4.2 3.9 5.2 mA ISO7331 ICC1 ICC2 ICC1 ICC2 ICC1 DC to 1 Mbps Supply current for VCC1 and VCC2 10 Mbps ICC2 ICC1 25 Mbps ICC2 (1) 6 CL = 15pF CL = 15pF mA VCCO is supply voltage, VCC1 or VCC2, for the output channel being measured. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ISO7330C ISO7330FC ISO7331C ISO7331FC ISO7330C, ISO7330FC, ISO7331C, ISO7331FC www.ti.com SLLSEK9B – JANUARY 2015 – REVISED APRIL 2015 6.7 Switching Characteristics VCC1 and VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted) PARAMETER tPLH, tPHL Propagation delay time PWD (1) Pulse width distortion |tPHL – tPLH| tsk(o) (2) tsk(pp) (3) TEST CONDITIONS MIN TYP MAX 20 32 58 ns 4 ns See Figure 11 Channel-to-channel output skew time Same direction channels 2.5 Opposite direction channels 17 Part-to-part skew time 23 tr Output signal rise time tf Output signal fall time tPHZ Disable propagation delay, high-to-high impedance output 7 12 tPLZ Disable propagation delay, low-to-high impedance output 7 12 7 12 11000 23000 (4) 11000 23000 (4) 7 12 See Figure 11 tPZH Enable propagation delay, high impedance-to-high output ISO733xC tPZL Enable propagation delay, high impedance-to-low output ISO733xC tfs Fail-safe output delay time from input power loss (1) (2) (3) (4) 3 ISO733xFC ISO733xFC See Figure 13 ns ns ns 2 See Figure 12 UNIT ns ns μs 7 Also known as pulse skew. tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads. tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads. The enable signal rate should be ≤ 43 Kbps 6.8 Switching Characteristics VCC1 and VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted) PARAMETER tPLH, tPHL Propagation delay time PWD (1) Pulse width distortion |tPHL – tPLH| TEST CONDITIONS MIN TYP MAX 22 36 66 ns 2.5 ns See Figure 11 Same direction channels tsk(o) (2) tsk(pp) (3) Channel-to-channel output skew time 3 Opposite direction channels 16 Part-to-part skew time 27 tr Output signal rise time tf Output signal fall time tPHZ Disable propagation delay, high-to-high impedance output 9 18 tPLZ Disable propagation delay, low-to-high impedance output 9 18 9 18 13000 24000 (4) 13000 24000 (4) 9 18 tPZH Enable propagation delay, high impedance-to-high output ISO733xC tPZL Enable propagation delay, high impedance-to-low output ISO733xC tfs Fail-safe output delay time from input power loss (1) (2) (3) (4) 3 See Figure 11 ISO733xFC ISO733xFC See Figure 13 ns ns ns 2 See Figure 12 UNIT ns 7 ns μs Also known as pulse skew. tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads. tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads. The enable signal rate should be ≤ 41 Kbps Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ISO7330C ISO7330FC ISO7331C ISO7331FC 7 ISO7330C, ISO7330FC, ISO7331C, ISO7331FC SLLSEK9B – JANUARY 2015 – REVISED APRIL 2015 www.ti.com 6.9 Typical Characteristics 8 5 ICC1 at 3.3 V ICC1 at 5 V ICC2 at 3.3 V ICC2 at 5 V 6 ICC1 at 3.3 V ICC1 at 5 V ICC2 at 3.3 V ICC2 at 5 V 4 Supply Current (mA) Supply Current (mA) 7 4.5 5 4 3 2 3.5 3 2.5 2 1.5 1 1 0.5 0 0 0 5 10 TA = 25°C 15 20 Data Rate (Mbps) 25 30 0 CL = 15 pF 10 TA = 25°C Figure 1. ISO7330 Supply Current vs Data Rate (with 15 pF Load) 15 20 Data Rate (Mbps) 25 30 D002 CL = No Load Figure 2. ISO7330 Supply Current vs Data Rate (with No Load) 7 5 ICC1 at 3.3 V ICC1 at 5 V ICC2 at 3.3 V ICC2 at 5 V 5 ICC1 at 3.3 V ICC1 at 5 V ICC2 at 3.3 V ICC2 at 5 V 4.5 4 Supply Current (mA) 6 Supply Current (mA) 5 D001 4 3 2 3.5 3 2.5 2 1.5 1 1 0.5 0 0 0 5 10 TA = 25°C 15 20 Data Rate (Mbps) 25 30 0 CL = 15 pF 15 20 Data Rate (Mbps) 25 30 D004 CL = No Load Figure 4. ISO7331 Supply Current vs Data Rate (with No Load) 0.9 6 VCC at 3.3 V VCC at 5 V VCC at 3.3 V VCC at 5 V 0.8 Low-Level Output Voltage (V) High-Level Output Voltage (V) 10 TA = 25°C Figure 3. ISO7331 Supply Current vs Data Rate (with 15 pF Load) 5 5 D003 4 3 2 1 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0 -15 -10 -5 High-Level Output Current (mA) 0 TA = 25°C 5 10 Low-Level Output Current (mA) 15 D006 TA = 25°C Figure 5. High-Level Output Voltage vs High-level Output Current 8 0 D005 Submit Documentation Feedback Figure 6. Low-Level Output Voltage vs Low-Level Output Current Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ISO7330C ISO7330FC ISO7331C ISO7331FC ISO7330C, ISO7330FC, ISO7331C, ISO7331FC www.ti.com SLLSEK9B – JANUARY 2015 – REVISED APRIL 2015 Typical Characteristics (continued) 2.48 45 VCC Rising VCC Falling 2.46 2.44 2.42 2.40 2.38 41 39 37 35 33 31 29 27 2.36 -50 0 50 100 Free-Air Temperature (qC) 25 -40 150 -10 20 50 80 Free-Air Temperature (qC) D007 Figure 7. Power Supply Undervoltage Threshold vs Free-Air Temperature 110 135 D008 Figure 8. Propagation Delay Time vs Free-Air Temperature 250 29 tGS at 3.3 V tGS at 5 V 27 Peak-to-Peak Output Jitter (ps) Input Glitch Suppression Time (ns) tPHL at 3.3 V tPHL at 5 V tPLH at 3.3 V tPLH at 5 V 43 Propagation Delay Time (ns) Power Supply Under-Voltage Threshold (V) 2.50 25 23 21 19 17 15 -40 Output Jitter at 3.3 V Output Jitter at 5 V 200 150 100 50 0 -10 20 50 80 Free-Air Temperature (qC) 110 135 0 5 D009 10 15 Data Rate (Mbps) 20 25 D010 TA = 25°C Figure 9. Input Glitch Suppression Time vs Free-Air Temperature Copyright © 2015, Texas Instruments Incorporated Figure 10. Output Jitter vs Data Rate Submit Documentation Feedback Product Folder Links: ISO7330C ISO7330FC ISO7331C ISO7331FC 9 ISO7330C, ISO7330FC, ISO7331C, ISO7331FC SLLSEK9B – JANUARY 2015 – REVISED APRIL 2015 www.ti.com Isolation Barrier 7 Parameter Measurement Information IN Input Generator Note A 50 W VI VCCI VI OUT 50% 50% 0V tPLH VO CL Note B tPHL 90% 10% 50% VO VOH 50% VOL tr tf A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50 Ω. At the input, a 50-Ω resistor is required to terminate the Input Generator signal. It is not needed in actual application. B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. Figure 11. Switching Characteristic Test Circuit and Voltage Waveforms VCCO VCC ISOLATION BARRIER 0V R L = 1 k W ± 1% IN Input Generator OUT EN VO 0V tPLZ tPZL VO CL VCC/2 VCC/2 VI VCCO 0.5 V 50% VOL Note B VI 50 W 3V ISOLATION BARRIER Note A IN Input Generator Note A VI VCC OUT VO VCC/2 VI VCC/2 0V EN 50 W CL Note B tPZH R L = 1 k W ± 1% VO VOH 50% 0.5 V tPHZ A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 10 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50 Ω. B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. 0V Figure 12. Enable/Disable Propagation Delay Time Test Circuit and Waveform 10 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ISO7330C ISO7330FC ISO7331C ISO7331FC ISO7330C, ISO7330FC, ISO7331C, ISO7331FC www.ti.com SLLSEK9B – JANUARY 2015 – REVISED APRIL 2015 Parameter Measurement Information (continued) VI IN = 0 V (Devices without suffix F) IN = VCCI (Devices with suffix F) A. VCCI ISOLATION BARRIER VCCI IN 2.7 V VI OUT 0V t fs VO fs high VO CL Note A VOH 50% fs low V OL CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. Figure 13. Fail-Safe Output Delay-Time Test Circuit and Voltage Waveforms S1 IN C = 0.1 μ F ±1% Isolation Barrier VCCI GNDI VCCO C = 0.1 μ F ±1% Pass-fail criteria – output must remain stable. OUT + CL Note A GNDO VOH or VOL – + VCM – A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. Figure 14. Common-Mode Transient Immunity Test Circuit Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ISO7330C ISO7330FC ISO7331C ISO7331FC 11 ISO7330C, ISO7330FC, ISO7331C, ISO7331FC SLLSEK9B – JANUARY 2015 – REVISED APRIL 2015 www.ti.com 8 Detailed Description 8.1 Overview The isolator in Figure 15 is based on a capacitive isolation barrier technique. The I/O channel of the device consists of two internal data channels, a high-frequency (HF) channel with a bandwidth from 100 kbps up to 25 Mbps, and a low-frequency (LF) channel covering the range from 100 kbps down to DC. In principle, a single-ended input signal entering the HF channel is split into a differential signal via the inverter gate at the input. The following capacitor-resistor networks differentiate the signal into transient pulses, which then are converted into CMOS levels by a comparator. The transient pulses at the input of the comparator can be either above or below the common mode voltage VREF depending on whether the input bit transitioned from 0 to 1 or 1 to 0. The comparator threshold is adjusted based on the expected bit transition. A decision logic (DCL) at the output of the HF channel comparator measures the durations between signal transients. If the duration between two consecutive transients exceeds a certain time limit, (as in the case of a low-frequency signal), the DCL forces the output-multiplexer to switch from the high-frequency to the low-frequency channel. 8.2 Functional Block Diagram Isolation Barrier OSC Low ± Frequency Channel (DC...100 kbps) PWM VREF LPF 0 Polarity and Threshold Selection IN OUT 1 S High ± Frequency Channel (100 kbps ...25 Mbps ) DCL VREF Polarity and Threshold Selection Figure 15. Conceptual Block Diagram of a Digital Capacitive Isolator Because low-frequency input signals require the internal capacitors to assume prohibitively large values, these signals are pulse-width modulated (PWM) with the carrier frequency of an internal oscillator, thus creating a sufficiently high frequency, capable of passing the capacitive barrier. As the input is modulated, a low-pass filter (LPF) is needed to remove the high-frequency carrier from the actual data before passing it on to the output multiplexer. 12 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ISO7330C ISO7330FC ISO7331C ISO7331FC ISO7330C, ISO7330FC, ISO7331C, ISO7331FC www.ti.com SLLSEK9B – JANUARY 2015 – REVISED APRIL 2015 8.3 Feature Description PRODUCT CHANNEL DIRECTION ISO7330C 3 Forward, 0 Reverse ISO7330FC ISO7331C MAX DATA RATE DEFAULT OUTPUT High 3000 VRMS / 4242 VPK (1) Low 25 Mbps High 2 Forward, 1 Reverse ISO7331FC (1) RATED ISOLATION Low See the Regulatory Information section for detailed Isolation Ratings 8.3.1 High Voltage Feature Description 8.3.1.1 Package Insulation Specifications over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT L(I01) Minimum air gap (clearance) Shortest terminal-to-terminal distance through air 8 mm L(I02) Minimum external tracking (creepage) Shortest terminal-to-terminal distance across the package surface 8 mm CTI Tracking resistance (comparative tracking index) DIN EN 60112 (VDE 0303-11); IEC 60112 DTI Minimum internal gap (internal clearance) Distance through the insulation >400 V 13 VIO = 500 V, TA = 25°C µm 12 Ω 11 Ω >10 RIO Isolation resistance, input to output (1) CIO Isolation capacitance, input to output (1) VIO = 0.4 sin (2πft), f = 1 MHz 2 pF CI Input capacitance (2) VI = VCC/2 + 0.4 sin (2πft), f = 1 MHz, VCC = 5 V 2 pF (1) (2) VIO = 500 V, 100°C ≤ TA ≤ max >10 All pins on each side of the barrier tied together creating a two-terminal device. Measured from input pin to ground. NOTE Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications. Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ISO7330C ISO7330FC ISO7331C ISO7331FC 13 ISO7330C, ISO7330FC, ISO7331C, ISO7331FC SLLSEK9B – JANUARY 2015 – REVISED APRIL 2015 www.ti.com 8.3.1.2 Insulation Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER (1) SPECIFICATION UNIT VIOWM Maximum isolation working voltage TEST CONDITIONS 1000 VRMS VIORM Maximum repetitive peak voltage per DIN V VDE V 0884-10 1414 VPK Input-to-output test voltage per DIN V VDE V 0884-10 VPR After Input/Output safety test subgroup 2/3, VPR = VIORM x 1.2, t = 10 s, Partial discharge < 5 pC 1697 Method a, After environmental tests subgroup 1, VPR = VIORM x 1.6, t = 10 s, Partial Discharge < 5 pC 2262 Method b1, VPR = VIORM x 1.875, t = 1 s (100% Production test) Partial discharge < 5 pC 2651 VPK VIOTM Maximum transient overvoltage per DIN V VDE V 0884-10 VTEST = VIOTM t = 60 sec (qualification) t= 1 sec (100% production) 4242 VPK VIOSM Maximum surge isolation voltage per DIN V VDE V 0884-10 Test method per IEC 60065, 1.2/50 µs waveform, VTEST = 1.3 x VIOSM = 7800 VPK (qualification) 6000 VPK VISO Withstand isolation voltage per UL 1577 VTEST = VISO = 3000 VRMS, t = 60 sec (qualification) VTEST = 1.2 x VISO = 3600 VRMS, t = 1 sec (100% production) 3000 VRMS RS Insulation resistance VIO = 500 V at TS >109 Ω Pollution degree (1) 2 Climatic Classification 40/125/21 Table 1. IEC 60664-1 Ratings Table PARAMETER TEST CONDITIONS Basic isolation group SPECIFICATION Material group Installation classification II Rated mains voltage ≤ 300 VRMS I–IV Rated mains voltage ≤ 600 VRMS I–III Rated mains voltage ≤ 1000 VRMS I–II 8.3.1.3 Regulatory Information VDE CSA UL CQC Certified according to DIN V VDE V 0884-10 (VDE V 088410):2006-12 and DIN EN 61010-1 (VDE 0411-1):2011-07 Approved under CSA Component Acceptance Notice 5A, IEC 60950-1, and IEC 61010-1 Basic Insulation Maximum Transient Overvoltage, 4242 VPK ; Maximum Surge Isolation Voltage, 6000 VPK; Maximum Repetitive Peak Isolation Voltage', 1414 VPK 800 VRMS Basic Insulation and 400 VRMS Reinforced Insulation working voltage per CSA 609501-07+A1+A2 and IEC 60950-1 Single protection, 3000 VRMS 2nd Ed.+A1+A2; 300 VRMS Basic Insulation working voltage per CSA 610101-12 and IEC 61010-1 3rd Ed. Certificate number: 40016131 Master contract number: 220991 File number: E181974 (1) 14 Recognized under UL 1577 Component Recognition Program Certified according to GB4943.12011 (1) Reinforced Insulation, Altitude ≤ 5000 m, Tropical Climate, 250 VRMS maximum working voltage Certificate number: CQC15001121716 Production tested ≥ 3600 VRMS for 1 second in accordance with UL 1577. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ISO7330C ISO7330FC ISO7331C ISO7331FC ISO7330C, ISO7330FC, ISO7331C, ISO7331FC www.ti.com SLLSEK9B – JANUARY 2015 – REVISED APRIL 2015 8.3.1.4 Safety Limiting Values Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry. A failure of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat the die and damage the isolation barrier, potentially leading to secondary system failures. PARAMETER TEST CONDITIONS IS Safety input, output, or supply current TS Maximum case temperature MIN TYP MAX RθJA = 78.3 °C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C 290 RθJA = 78.3 °C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C 443 150 UNIT mA °C The safety-limiting constraint is the absolute-maximum junction temperature specified in the Absolut Maximun Ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information table is that of a device installed on a High-K Test Board for Leaded Surface-Mount Packages. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance. 500 Safety Limiting Current (mA) VCC1 = VCC2 = 3.6 V VCC1 = VCC2 = 5.5 V 400 300 200 100 0 0 50 100 150 Case Temperature (qC) 200 Figure 16. θJC Thermal Derating Curve per DIN V VDE V 0884-10 Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ISO7330C ISO7330FC ISO7331C ISO7331FC 15 ISO7330C, ISO7330FC, ISO7331C, ISO7331FC SLLSEK9B – JANUARY 2015 – REVISED APRIL 2015 www.ti.com 8.4 Device Functional Modes Table 2. Function Table (1) VCCI VCCO PU (1) (2) (3) PU INPUT (INx) OUTPUT ENABLE (ENx) H H or Open OUTPUT (OUTx) ISO733xC ISO733xFC H H L H or Open L L X L Z Z Open H or Open H (2) L (3) H or Open (2) L (3) PD PU X H X PU X L Z Z X PD X X Undetermined Undetermined VCCI = Input-side VCC; VCCO = Output-side VCC; PU = Powered up (VCC ≥ 3 V); PD = Powered down (VCC ≤ 2.1 V); X = Irrelevant; H = High level; L = Low level; Open = Not connected In fail-safe condition, output defaults to high level In fail-safe condition, output defaults to low level 8.4.1 Device I/O Schematics Input (Devices Without Suffix F) VCCI VCCI Input (Devices With Suffix F) VCCI VCCI VCCI VCCI VCCI 5 mA 500 W 500 W INx INx 5 mA Output Enable VCCO VCCO VCCO VCCO VCCO 5 mA 500 W 40 W OUTx ENx Figure 17. Device I/O Schematics 16 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ISO7330C ISO7330FC ISO7331C ISO7331FC ISO7330C, ISO7330FC, ISO7331C, ISO7331FC www.ti.com SLLSEK9B – JANUARY 2015 – REVISED APRIL 2015 9 Applications and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information ISO733x utilize single-ended TTL-logic switching technology. Its supply voltage range is from 3 V to 5.5 V for both supplies, VCC1 and VCC2. When designing with digital isolators, it is important to keep in mind that due to the single-ended design structure, digital isolators do not conform to any specific interface standard and are only intended for isolating single-ended CMOS or TTL digital signal lines. The isolator is typically placed between the data controller (that is, μC or UART), and a data converter or a line transceiver, regardless of the interface type or standard. 9.2 Typical Application ISO7331C combined with Texas Instruments' mixed signal micro-controller, RS-485 transceiver, transformer driver, and voltage regulator can create an isolated RS-485 system as shown in Figure 18. VIN 3.3V 0.1F 2 Vcc D2 3 1:2.2 MBR0520L 1 SN6501 GND D1 3 1 10F OUT 5VISO 5 TPS76350 10F 0.1F 4,5 IN EN GND 10F 2 MBR0520L ISO-BARRIER 0.1F 0.1F 0.1F DVcc 6 P3.0 XOUT XIN 11 15 MSP430 UCA0TXD F2132 UCA0RXD 16 DVss 4 16 1 2 5 0.1F 3 4 5 VCC1 VCC2 INA OUTA ISO7331 INB OUTC 7 EN1 GND1 2,8 OUTB INC VCC 14 13 12 EN2 10 GND2 2 3 4 1 10 MELF RE DE B D SN65HVD 3082E A R GND 10 MELF SM712 9,15 4.7nF/ 2kV Figure 18. Typical ISO7331 Application Circuit Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ISO7330C ISO7330FC ISO7331C ISO7331FC 17 ISO7330C, ISO7330FC, ISO7331C, ISO7331FC SLLSEK9B – JANUARY 2015 – REVISED APRIL 2015 www.ti.com Typical Application (continued) 9.2.1 Design Requirements 9.2.1.1 Typical Supply Current Equations ISO7330: ISO7331: At VCC1 = VCC2 = 5 V At VCC1 = VCC2 = 5 V • • • ICC1 = 0.46544 + (0.006455 x f) ICC2 = 2.28021 + (0.08242 x f) + (0.006237 x f x CL) • ICC1 = 1.661 + (0.07916 x f) + (0.00169 x f x CL) ICC2 = 2.04 + (0.0778 x f) + (0.00422 x f x CL) At VCC1 = VCC2 = 3.3 V At VCC1 = VCC2 = 3.3 V • • • ICC1 = 0.29211 + (0.03588 x f) ICC2 = 1.8414 + (0.02886 x f) + (0.00548 x f x CL) • ICC1 = 1.2402 + (0.03127 x f) + (0.001954 x f x CL) ICC2 = 1.53839 + (0.02933 x f) + (0.0037285 x f x CL) ICC1 and ICC2 are typical supply currents measured in mA, f is data rate measured in Mbps, CL is the capacitive load measured in pF. 9.2.2 Detailed Design Procedure 9.2.2.1 Electromagnetic Compatibility (EMC) Considerations Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge (ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances are regulated by international standards such as IEC 61000-4-x and CISPR 22. Although system-level performance and reliability depends, to a large extent, on the application board design and layout, the ISO733x incorporate many chip-level design improvements for overall system robustness. Some of these improvements include: • Robust ESD protection cells for input and output signal pins and inter-chip bond pads. • Low-resistance connectivity of ESD cells to supply and ground pins. • Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events. • Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance path. • PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic SCRs. • Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation. 18 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ISO7330C ISO7330FC ISO7331C ISO7331FC ISO7330C, ISO7330FC, ISO7331C, ISO7331FC www.ti.com SLLSEK9B – JANUARY 2015 – REVISED APRIL 2015 Typical Application (continued) 9.2.3 Application Performance Curves Typical eye diagrams of ISO733x below indicate low jitter and wide open eye at the maximum data rate of 25 Mbps. Figure 20. Eye Diagram at 25 Mbps, 3.3 V and 25°C Figure 19. Eye Diagram at 25 Mbps, 5 V and 25°C 9.2.4 Systems Examples Unlike Optocouplers, which need external components to improve performance, provide bias, or limit current, ISO733x only needs two external bypass capacitors to operate. 2 mm max from VCC1 ISO7330 0.1 µF VCC1 VCC1 VCC2 1 16 2 15 INA 3 14 OUTA INB 4 13 OUTB INC 5 12 OUTC 6 11 NC NC 16 2 15 INA 3 14 OUTA INB 4 13 OUTB OUTC 5 12 INC 6 11 7 10 8 9 GND1 NC EN 9 8 GND2 NC NC 10 GND1 0.1 µF VCC2 1 GND2 7 ISO7331 0.1 µF 0.1 µF GND1 2 mm max from VCC2 2 mm max from VCC1 2 mm max from VCC2 EN2 EN1 GND2 GND1 GND2 Figure 21. Typical ISO7330 Circuit Hook-up Figure 22. Typical ISO7331 Circuit Hook-up 10 Power Supply Recommendations To ensure reliable operation at all data rates and supply voltages, a 0.1 µF bypass capacitor is recommended at input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to the supply pins as possible. If only a single primary-side power supply is available in an application, isolated power can be generated for the secondary-side with the help of a transformer driver such as Texas Instruments' SN6501. For such applications, detailed power supply design and transformer selection recommendations are available in SN6501 datasheet (SLLSEA0) . Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ISO7330C ISO7330FC ISO7331C ISO7331FC 19 ISO7330C, ISO7330FC, ISO7331C, ISO7331FC SLLSEK9B – JANUARY 2015 – REVISED APRIL 2015 www.ti.com 11 Layout 11.1 PCB Material For digital circuit boards operating below 150 Mbps, (or rise and fall times higher than 1 ns), and trace lengths of up to 10 inches, use standard FR-4 epoxy-glass as PCB material. FR-4 (Flame Retardant 4) meets the requirements of Underwriters Laboratories UL94-V0, and is preferred over cheaper alternatives due to its lower dielectric losses at high frequencies, less moisture absorption, greater strength and stiffness, and its selfextinguishing flammability-characteristics. 11.2 Layout Guidelines A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 23). Layer stacking should be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency signal layer. • Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits of the data link. • Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for transmission line interconnects and provides an excellent low-inductance path for the return current flow. • Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of approximately 100pF/in2. • Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links usually have margin to tolerate discontinuities such as vias. If an additional supply voltage plane or signal layer is needed, add a second power / ground plane system to the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the power and ground plane of each power system can be placed closer together, thus increasing the high-frequency bypass capacitance significantly. For detailed layout recommendations, see Application Note SLLA284, Digital Isolator Design Guide. 11.3 Layout Example High-speed traces 10 mils Ground plane 40 mils Keep this space free from planes, traces , pads, and vias FR-4 0r ~ 4.5 Power plane 10 mils Low-speed traces Figure 23. Recommended Layer Stack 20 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ISO7330C ISO7330FC ISO7331C ISO7331FC ISO7330C, ISO7330FC, ISO7331C, ISO7331FC www.ti.com SLLSEK9B – JANUARY 2015 – REVISED APRIL 2015 12 Device and Documentation Support 12.1 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 3. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY ISO7330C Click here Click here Click here Click here Click here ISO7330FC Click here Click here Click here Click here Click here ISO7331C Click here Click here Click here Click here Click here ISO7331FC Click here Click here Click here Click here Click here 12.2 Trademarks DeviceNet is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 12.3 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.4 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. SLLA353, Isolation Glossary 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ISO7330C ISO7330FC ISO7331C ISO7331FC 21 PACKAGE OPTION ADDENDUM www.ti.com 30-Apr-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) ISO7330CDW ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ISO7330C ISO7330CDWR ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ISO7330C ISO7330FCDW ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ISO7330FC ISO7330FCDWR ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ISO7330FC ISO7331CDW ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ISO7331C ISO7331CDWR ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ISO7331C ISO7331FCDW ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ISO7331FC ISO7331FCDWR ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ISO7331FC (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com (4) 30-Apr-2015 There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 30-Apr-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ISO7330CDWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1 ISO7330FCDWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1 ISO7331CDWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1 ISO7331FCDWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 30-Apr-2015 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ISO7330CDWR SOIC DW 16 2000 367.0 367.0 38.0 ISO7330FCDWR SOIC DW 16 2000 367.0 367.0 38.0 ISO7331CDWR SOIC DW 16 2000 367.0 367.0 38.0 ISO7331FCDWR SOIC DW 16 2000 367.0 367.0 38.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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