Fujitsu MB89PV140CF-102-ES 8-bit proprietary microcontroller Datasheet

FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-12522-2E
8-bit Proprietary Microcontroller
CMOS
F2MC-8L MB89140 Series
MB89145/146 and MB89P147/PV140
■ DESCRIPTION
The MB89140 series is a line of single-chip microcontrollers that use the F2MC*-8L CPU core which can operate
at low voltage but at high speed. The MB89140 series contains a variety of peripheral functions, such as timers,
a serial interface, an A/D converter, and an external interrupt. The MB89140 series is applicable to a wide range
of applications from welfare products to industrial equipment, including portable devices.
*: F2MC stands for FUJITSU Flexible Microcontroller.
■ FEATURES
• Minimum execution time: 0.5 µs/8-MHz oscillation
• F2MC-8L family CPU core
Instruction set optimized for controllers
Multiplication and division instructions
16-bit arithmetic operations
Test and branch instructions
Bit manipulation instructions, etc.
(Continued)
■ PACKAGE
64-pin Plastic SH-DIP
64-pin Plastic QFP
64-pin Ceramic MDIP
(DIP-64P-M01)
(FPT-64P-M06)
(MDP-64C-P02)
64-pin Ceramic MQFP
(MQP-64C-P01)
MB89140 Series
(Continued)
• Low-voltage operation (when an A/D converter is not used)
• Low current consumption (compatible with dual-clock system)
• High-voltage ports on chip
• Five types of timers
8-bit PWM timer (also usable as a reload timer)
12-bit MPG timer (also usable as a PPG output, PWM output, and reload timer)
8/16-bit timer (also usable as two 8-bit timers)
21-bit time-base timer
• One serial interface
Swichable transfer direction allows communication with various equipment.
• 10-bit A/D converter: 12 channels
Successive approximation type
• External interrupt: 2 channels
Two channels are independent and capable of wake-up from low-power consumption modes. (Rising edge,
falling edge/both edges selectability)
–0.3 V to +7.0 V can be applied to INT1 (N-ch open-drain)
• Low-power consumption modes
Stop mode (Oscillation stops to minimize the current consumption.)
Sleep mode (The CPU stops to reduce the current consumption to approx. 1/3 of normal.)
Subclock mode
Watch mode
• Reset output and power-on reset selectability
2
MB89140 Series
■ PRODUCT LINEUP
Part number
MB89145
MB89146
MB89P147
MB89PV140
Parameter
Classification
Mass production products
(mask ROM products)
ROM size
16 K × 8 bits
(internal mask
ROM)
24 K × 8 bits
(internal mask
ROM)
RAM size
512 × 8 bits
768 × 8 bits
CPU functions
Number of instructions:
Instruction bit length:
Instruction length:
Data bit length:
Minimum execution time:
Interrupt processing time:
Note:
Ports
High-voltage output port
(P-ch open-drain):
Buzzer output
(P-ch open-drain, high-voltage):
Output ports (CMOS):
Input ports (CMOS):
I/O ports (CMOS):
I/O ports (N-ch open-drain):
Total:
Clock timer
8-bit PWM timer
(timer 1)
12-bit MPG
(timer 4)
8/16-bit timer
counter
(timer 2, 3)
One-time PROM/
EPROM product
Piggyback/
evaluation product
(for evaluation and
development)
32 K × 8 bits
(internal PROM)
32 K × 8 bits
(external ROM)
1 K × 8 bits
136
8 bits
1 to 3 bytes
1, 8, 16 bits
0.5 µs/8 MHz to 8.0 µs/8 MHz, 61 µs/32.768 kHz
4.5 µs/8 MHz to 72.0 µs/8 MHz, 562.5 µs/32.768 kHz
The above times change according to the gear function.
8 (P60 to P67, for heavy current) 16 (P40 to P47, P50 to
P57 for low current)
1 (heavy current)
4 (P20 to P23)
2 (P70 and P71, function as X0A and XIA pins when
dual-clock system is used.)
23 (P00 to P07, P10 to P17, P30, and P32 to P37)
1 (P31)
55
21 bits × 1 (in main clock mode), 15 bits × 1 (at 32.768 kHz)
8-bit timer operation
(toggled output capable, operating clock: 1, 2, 8, 16 system clock cycles)
8-bit resolution PWM operation
(conversion cycle: 128 µs to 2.0 ms at 8.0-MHz oscillation, and highest gear speed)
12-bit resolution PWM operation (maximum conversion cycle of 2048.4 µs to 16.4 ms at
8.0 MHz-oscillation, and highest gear speed)
12-bit resolution reload timer operation (toggled output capable)
12-bit resolution PPG operation (minimum resolution of 0.5 µs at 8.0-MHz oscillation, and
highest gear speed)
8/16-bit timer operation (operating clock, internal clock, external trigger)
8/16-bit event counter operation (Rising edge/falling edge/both edges selectability)
(Continued)
3
MB89140 Series
(Continued)
Part number
MB89145
Parameter
8-bit serial I/O
MB89146
MB89P147
MB89PV140
8 bits
LSB first/MSB first selectability
One clock selectable from four transfer clocks
(one external shift clock, three internal shift clocks: 4, 8, 16 system clock cycles)
10-bit resolution × 12 channels
A/D conversion mode (conversion time of 16.5 µs/8 MHz, and highest gear speed)
Sense mode (conversion time of 9.0 µs/8 MHz, and highest gear speed)
External activation capable
10-bit A/D
converter
External interrupt
2 independent channels (edge selection, interrupt vector, source flag)
Rising edge/falling edge/both edges selectability
Built-in analog noise canceller
Used also for wake-up from stop/sleep mode. (Edge detection is also permitted in stop mode.)
Standby mode
Sleep mode, stop mode, watch mode, and subclock mode
Process
CMOS
Operating
voltage*
2.7 V to 6.0 V
EPROM for use
MBM27C256A-20TV
MBM27C256A-20CZ
* : Varies with conditions such as the operating frequency. (See section “■ Electrical Characteristics.”)
■ PACKAGE AND CORRESPONDING PRODUCTS
MB89145
MB89146
MB89P147
Package
×
DIP-64P-M01
×
DIP-64C-A06
×
×
FPT-64P-M06
MDP-64C-P02
×
MQP-64C-P01
×
: Available
MB89PV140
× : Not available
Note: For more information about each package, see section “■ Package Dimensions.”
4
MB89140 Series
■ DIFFERENCES AMONG PRODUCTS
1. Memory Size
Before evaluating using the piggyback product, verify its differences from the product that will actually be used.
Take particular care on the following points:
• On the MB89P147, the program area starts from address 8007H but on the MB89PV140 starts from 8000H.
(On the MB89P147, addresses 8000H to 8006H comprise the option setting area, option settings can be read
by reading these addresses. On the MB89PV140, addresses 8000H to 8006H could also be used as a program
ROM. However, do not use these addresses in order to maintain compatibility of the MB89P147.)
• The stack area, etc., is set at the upper limit of the RAM.
2. Current Consumption
• In the case of the MB89PV140, add the current consumed by the EPROM which is connected to the top socket.
• When operated at low speed, the product with an OTPROM (one-time PROM) or an EPROM will consume
more current than the product with a mask ROM.
However, the current consumption in sleep/stop modes is the same. (For more information, see section
“■ Electrical Characteristics.”)
3. Mask Options
Functions that can be selected as options and how to designate these options vary by the product. Before using
options check section “■ Mask Options.”
Take particular care on the following points:
• Options are fixed on the MB89PV140.
• On the MB89P147, MB89145, and MB89146, the pull-down resistor option can either be selected for all affected
pins, or for no pin; it is not possible to specify the pull-down resistor option for individual pins.
4. Subclock Oscillation Feedback Resistor
A built-in oscillation feedback resistor is provided for the subclock oscillator pin on the MB89PV140, but it is not
provided for the MB89145, MB89146, MB89P147. Therefor these products should be connected to an external
oscillation feedback resistor.
5
MB89140 Series
■ PIN ASSIGNMENT
(Top view)
BZ
P67
P66
P65
P64
P63
P62
P61
P60
VFDP
P57
P56
P55
P54
P53
P52
P51
P50
P47
P46
P45
P44
P43
P42
P41
P40
P23/WDG
RST
MODA
X0
X1
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
A15/VPP
A12
A7
A6
A5
A4
A3
A2
A1
A0
O1
O2
O3
VSS
65
66
67
68
69
70
71
72
73
74
75
76
77
78
92
91
90
89
88
87
86
85
84
83
82
81
80
79
VCC
A14
A13
A8
A9
A11
OE
A10
CE
O8
O7
O6
O5
O4
Each pin inside the dashed line
is for the MB89PV140 only.
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VCC
AVCC
AVSS
P00/AN0
P01/AN1
P02/AN2
P03/AN3
P04/AN4
P05/AN5
P06/AN6
P07/AN7
P10/AN8
P11/AN9
P12/ANA
P13/ANB
P14
P15
P16
P17/ADST
P30/INT0/TRG
P31/INT1
P32/SCK
P33/SO
P34/SI
P35/EC
P36/PWO1
P37/DTT1
P20
P21/PWO0
P22
P70/X0A*
P71/X1A*
(DIP-64P-M01)
(MDP-64C-P02)
*: When dual-clock system is selected.
6
MB89140 Series
64
63
62
61
60
59
58
57
56
55
54
53
52
P62
P63
P64
P65
P66
P67
BZ
VCC
AVCC
AVSS
P00/AN0
P01/AN1
P02/AN2
(Top view)
84
83
82
81
80
79
78
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
85
86
87
88
89
90
91
92
93
77
76
75
74
73
72
71
70
69
94
95
96
65
66
67
68
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Each pin inside the dashed line
is for the MB89PV140 only.
P03/AN3
P04/AN4
P05/AN5
P06/AN6
P07/AN7
P10/AN8
P11/AN9
P12/ANA
P13/ANB
P14
P15
P16
P17/ADST
P30/INT0/TRG
P31/INT1
P32/SCK
P33/SO
P34/SI
P35/EC
P23/WDG
RST
MODA
X0
X1
VSS
P71/X1A*
P70/X0A*
P22
P21/PWO0
P20
P37/DTTI
P36/PWO1
20
21
22
23
24
25
26
27
28
29
30
31
32
P61
P60
VFDP
P57
P56
P55
P54
P53
P52
P51
P50
P47
P46
P45
P44
P43
P42
P41
P40
(FPT-64P-M06)
(MQP-64C-P01)
*: When dual-clock system is selected.
• Pin assignment on package top (MB89PV140 only)
Pin no.
Pin name
Pin no.
Pin name
Pin no.
Pin name
Pin no.
Pin name
65
N.C.
73
A2
81
N.C.
89
OE
66
A15/VPP
74
A1
82
O4
90
N.C.
67
A12
75
A0
83
O5
91
A11
68
A7
76
N.C.
84
O6
92
A9
69
A6
77
O1
85
O7
93
A8
70
A5
78
O2
86
O8
94
A13
71
A4
79
O3
87
CE
95
A14
72
A3
80
VSS
88
A10
96
VCC
N.C.: Internally connected. Do not use.
7
MB89140 Series
■ PIN DESCRIPTION
Pin no.
QFP*3
MQFP*4
30
23
X0
31
24
X1
29
22
28
21
54 to 61
Circuit
type
Function
A
Main clock crystal oscillator pins
MODA
C
Operating mode selection pin
Connect directly to VSS in normal operation. This pin
functions as the VPP pin in EPROM products.
RST
D
Reset I/O pin
This pin is an N-ch open-drain output type with a pull-up
resistor, and a hysteresis input type.
“L” is output from this pin by an internal reset source
when the option is set. The internal circuit is initialized
by the input of “L”.
This pin is with a noise canceller.
47 to 54
P07/AN7 to
P00/AN0
G
General-purpose I/O ports
The input is a hysteresis input type and with a built-in
noise canceller. Although these ports also serve as an
analog input, analog input does not pass through the
hysteresis input noise canceller.
46
39
P17/ADST
J
General-purpose I/O port
The input is a hysteresis input type and with a built-in
noise canceller. Also serves as an A/D converter
external activation.
47 to 49
40 to 42
P16 to P14
J
General-purpose I/O ports
The input is a hysteresis input type and with a built-in
noise canceller.
50 to 53
43 to 46
P13/ANB to
P10/AN8
G
General-purpose I/O ports
The input is a hysteresis input type and with a built-in
noise canceller. Although these ports also serves as an
analog input, analog input does not pass through the
hysteresis input noise canceller.
34,
33
27,
26
P70/X0A,
P71/X1A
B/K
General-purpose I/O ports with a built-in noise
canceller
(single-clock operation)
Function as subclock crystal oscillator pins. (dual-clock
operation)
35
28
P22
E
General-purpose output port
27
20
P23/WDG
E
General-purpose output port
Also serves as a watchdog output.
36
29
P21/PWO0
E
General-purpose output port
Also serves as the PWM output for the 8-bit PWM timer.
37
30
P20
E
General-purpose output port
*1:
*2:
*3:
*4:
8
Pin name
SDIP*1
MDIP*2
DIP-64P-M01
MDP-64C-P02
FPT-64P-M06
MQP-64C-P01
(Continued)
MB89140 Series
Pin no.
Circuit
type
Function
P37/DTTI
J
General-purpose I/O port
The input is a hysteresis input type and with a built-in
noise canceller. When overcurrent is detected, the 12bit MPG output can be inactivated by the external edge
input.
32
P36/PWO1
J
General-purpose I/O port
The input is a hysteresis input type and with a built-in
noise canceller. Also serves as a 12-bit MPG output.
40
33
P35/EC
J
General-purpose I/O port
The input is a hysteresis input type and with a built-in
noise canceller. Also serves as the external clock input
for the 8/16-bit timer/counter.
41
34
P34/SI
J
General-purpose I/O port
The input is a hysteresis input type and with a built-in
noise canceller. Also serves as the serial data input for
the 8-bit serial interface.
42
35
P33/SO
J
General-purpose I/O port
The input is a hysteresis input type and with a built-in
noise canceller. Also serves as the serial data output
for the 8-bit serial interface.
43
36
P32/SCK
J
General-purpose I/O port
The input is a hysteresis input type and with a built-in
noise canceller. Also serves as the serial transfer clock
for the 8-bit serial interface.
44
37
P31/INT1
F
General-purpose I/O port
The output is an N-ch open-drain type. The input is a
hysteresis input type and with a built-in noise canceller.
Also serves as an external interrupt. The interrupt
input is also a hysteresis input type and with a built-in
noise canceller.
45
38
P30/INT0/TRG
J
General-purpose I/O port
The input is a hysteresis input type and with a built-in
noise canceller. Also serve as an external interrupt or
as an MPG trigger input. The interrupt input is also a
hysteresis input type and with a built-in noise canceller.
1
58
BZ
I
Buzzer output-only pin
P-ch high-voltage open-drain output port
19 to 26,
11 to 18
12 to 19,
4 to 11
P47 to P40,
P57 to P50
H
Low-current P-ch high-voltage open-drain output ports
Products with and without a built-in pull-down resistor
between these pins and the VFDP pin are provided.
*1
*1:
*2:
*3:
*4:
SDIP
MDIP*2
QFP*3
MQFP*4
38
31
39
DIP-64P-M01
MDP-64C-P02
FPT-64P-M06
MQP-64C-P01
Pin name
(Continued)
9
MB89140 Series
(Continued)
Pin no.
SDIP*1
MDIP*2
2 to 9
*1:
*2:
*3:
*4:
10
QFP*3
MQFP*4
59 to 64
1, 2
Pin name
Circuit
type
Function
P67 to P60
H
Heavy-current P-ch high-voltage open-drain output
port
Products with and without a built-in pull-down resistor
between these pins and the VFDP pin are provided.
10
3
VFDP
—
Voltage supply pin for connection to a pull-down
resistor for ports 4, 5, and 6. In products without a
built-in pull-down resistor and in the MB89PV140, this
pin should be left open.
64
57
VCC
—
Power supply pin
32
25
VSS
—
Power supply (GND) pin
63
56
AVCC
—
A/D converter power supply pin
Use this pin at the same voltage as VCC.
62
55
AVSS
—
A/D converter power supply (GND) pin
Use this pin at the same voltage as VSS.
DIP-64P-M01
MDP-64C-P02
FPT-64P-M06
MQP-64C-P01
MB89140 Series
• External EPROM pins (MB89PV140 only)
Pin no.
*3
*1:
*2:
*3:
*4:
Pin name
I/O
Function
SDIP
MDIP*4
QFP*1
MQFP*2
65
66
A15/VPP
O
“H” level output pin
66
67
68
69
70
71
72
73
74
67
68
69
70
71
72
73
74
75
A12
A7
A6
A5
A4
A3
A2
A1
A0
O
Address output pins
75
76
77
77
78
79
O1
O2
O3
I
Data input pins
78
80
VSS
O
Power supply (GND) pin
79
80
81
82
83
82
83
84
85
86
O4
O5
O6
O7
O8
I
Data input pins
84
87
CE
O
ROM chip enable pin
Outputs “H” during standby.
85
88
A10
O
Address output pin
86
89
OE
O
ROM output enable pin
Outputs “L” at all times.
87
88
89
91
92
93
A11
A9
A8
O
Address output pins
90
94
A13
91
95
A14
92
96
VCC
O
EPROM power supply pin
—
65
76
81
90
N.C.
—
Internally connected pins
Be sure to leave them open.
DIP-64P-M01
MDP-64C-P02
FPT-64P-M06
MQP-64C-P01
11
MB89140 Series
■ I/O CIRCUIT TYPE
Type
A
Circuit
Remarks
• Crystal or ceramic oscillation type (main clock)
• At an oscillation feedback resistor of approximately
1 MΩ/5.0 V
X1
X0
Standby control signal
B
• Crystal or ceramic oscillation type (subclock)
• At an oscillation feedback resistor of approximately
4.5 MΩ/5.0 V
(The built-in feedback resistor is not provided except
on the MB89PV140-102.)
X1A
X0A
Standby control signal
C
D
R
P-ch
• At an output pull-up resistor (P-ch) of approximately
50 kΩ/5.0 V
• CMOS hysteresis input
(with noise canceller)
N-ch
Hysteresis input (with noise canceller)
E
• CMOS output
P-ch
N-ch
F
N-ch
• N-ch open-drain output
• CMOS hysteresis input
(with noise canceller)
Hysteresis input (with noise canceller)
(Continued)
12
MB89140 Series
(Continued)
Type
Circuit
Remarks
G
• CMOS output
• CMOS hysteresis input
(with noise canceller, except analog input)
P-ch
N-ch
Port
Hysteresis input (with noise canceller)
Analog input
H
• P-ch high-voltage open-drain output
• Products with and without a built-in pull-down resistor
are provided (except the MB89PV140).
P-ch
VFDP
I
• P-ch high-voltage open-drain output
P-ch
J
• CMOS output
• CMOS hysteresis input
(with noise canceller)
• Pull-up resistor optional
P-ch
N-ch
Port
Hysteresis input (with noise canceller)
K
Port
• CMOS hysteresis input
(with noise canceller)
Hysteresis input (with noise canceller)
13
MB89140 Series
■ HANDLING DEVICES
1. Preventing Latchup
Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins
other than medium- to high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum
Ratings” in section “■ Electrical Characteristics” is applied between VCC and VSS. (However, up to 7.0 V can be
applied to P31/INT pin, regardless of VCC)
When latchup occurs, power supply current increases rapidly and might thermally damage elements. When
using, take great care not to exceed the absolute maximum ratings.
2. Treatment of Unused Input Pins
Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down
resistor.
3. Treatment of N.C. Pins
Be sure to leave (internally connected) N.C. pins open.
4. Power Supply Voltage Fluctuations
Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage
could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is therefore
important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P
value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the transient
fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched.
5. Precautions when Using an External Clock
Even when an external clock is used, oscillation stabilization time is required for power-on reset (optional) and
wake-up from stop mode.
14
MB89140 Series
■ PROGRAMMING TO THE EPROM ON THE MB89P147
The MB89P147 is an OTPROM version of the MB89140 series.
1. Features
• 32-Kbyte PROM on chip
• Options can be set using the EPROM programmer.
• Equivalency to the MBM27C256A in EPROM mode (when programmed with the EPROM programmer)
2. Memory Space
Memory space in each mode such as 32-Kbyte PROM, option area is diagrammed below.
Address
Single chip
EPROM mode
(Corresponding addresses on the EPROM programmer)
0000H
I/O
0080H
RAM
0480H
Not available
8000H
0000H
Not available
Option area
8007H
0007H
PROM
32 KB
FFFFH
EPROM
32 KB
7FFFH
3. Programming to the EPROM
In EPROM mode, the MB89P147 functions equivalent to the MBM27C256A. This allows the PROM to be
programmed with a general-purpose EPROM programmer (the electronic signature mode cannot be used) by
using the dedicated socket adapter.
When the operating ROM area for a single chip is 32 Kbytes (8007H to FFFFH) the PROM can be programmed
as follows:
• Programming procedure
(1) Set the EPROM programmer to the MBM27C256A.
(2) Load program data into the EPROM programmer at 0007H to 7FFFH (note that addresses 8007H to FFFFH
while operating as a single chip assign to 0007H to 7FFFH in EPROM mode).
Load option data into addresses 0000H to 0006H of the EPROM programmer. (For information about each
corresponding option, see “5. Setting OTPROM Options.” in section “■ Programming to the EPROM with
Piggyback/evaluation Device” )
(3) Program to 0000H to 7FFFH with the EPROM programmer.
15
MB89140 Series
4. Recommended Screening Conditions
High-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked
OTPROM microcomputer program.
Program, verify
Aging
+150°C, 48 Hrs.
Data verification
Assembly
5. Programming Yield
All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature.
For this reason, a programming yield of 100% cannot be assured at all times.
6. EPROM Programmer Socket Adapter
Package
Compatible socket adapter
DIP-64P-M01
ROM-64SD-28DP-8L4
FPT-64P-M06
ROM-64QF-28DP-8L4
Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-3802-5760
16
MB89140 Series
■ PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE
1. EPROM for Use
MBM27C256A-20TV, MBM27C256A-20CZ
2. Programming Socket Adapter
To program to the PROM using an EPROM programmer, use the socket adapter (manufacturer: Sun Hayato
Co., Ltd.) listed below.
Package
Adapter socket part number
LCC-32 (Rectangle)
ROM-32LC-28DP-YG
LCC-32 (Square)
ROM-32LC-28DP-S
Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-3802-5760
3. Memory Space
Memory space in each mode, such as 32-Kbyte PROM, option area is diagrammed below.
Address
Single chip
Corresponding addresses on the EPROM programmer
0000H
I/O
0080H
RAM
0480H
Not available
8000H
0000H
Not available
Option area
8007H
0007H
PROM
32 KB
FFFFH
EPROM
32 KB
7FFFH
4. Programming to the EPROM
(1) Set the EPROM programmer to the MBM27C256A.
(2) Load program data into the EPROM programmer at 0007H to 7FFFH.
(3) Program to 0000H to 7FFFH with the EPROM programmer.
17
MB89140 Series
5. Setting OTPROM Options
The programming procedure is the same as that for the PROM. Options can be set by programming values at
the addresses shown on the memory map. The relationship between bits and options is shown on the following
bit map:
• OTPROM option bit map
Bit 7
Bit 6
Bit 5
8002H
(0002H)
Bit 2
Bit 1
Bit 0
Readable and
writable
Reset pin
output
1: Yes
0: No
Power-on
reset
1: Yes
0: No
Reserved
Reserved
(Write 1 bit (Write 1 bit
to this bit.) to this bit.)
P16
Pull-up
1: No
0: Yes
P15
Pull-up
1: No
0: Yes
P14
Pull-up
1: No
0: Yes
Vacancy
Vacancy
Vacancy
Vacancy
Readable and
writable
Readable and
writable
Readable and
writable
Readable and
writable
P37
Pull-up
1: No
0: Yes
P36
Pull-up
1: No
0: Yes
P35
Pull-up
1: No
0: Yes
P34
Pull-up
1: No
0: Yes
P33
Pull-up
1: No
0: Yes
P32
Pull-up
1: No
0: Yes
Vacancy
Vacancy
Readable and
writable
Readable and
writable
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Readable and
writable
Readable and
writable
Readable and
writable
Readable and
writable
Readable and
writable
Readable and
writable
Readable and
writable
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Readable and
writable
Readable and
writable
Readable and
writable
Readable and
writable
Readable and
writable
Readable and
writable
Readable and
writable
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Readable and
writable
Readable and
writable
Readable and
writable
Readable and
writable
Readable and
writable
Readable and
writable
Readable and
writable
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Readable and
writable
Readable and
writable
Readable and
writable
Readable and
writable
Readable and
writable
Readable and
writable
Readable and
writable
Vacancy
Vacancy
Readable and
writable
P17
Pull-up
1: No
0: Yes
(0000H) Readable and
writable
(0001H)
Bit 3
Single/dualclock system
1: Dual clock
0: Single clock
Vacancy
8000H
8001H
Bit 4
8003H
(0003H) Readable and
writable
Vacancy
8004H
(0004H) Readable and
writable
Vacancy
8005H
(0005H) Readable and
writable
Vacancy
8006H
(0006H) Readable and
writable
Notes: • Set each bit to 1 to erase.
• Do not write 0 to the vacant bit.
The read value of the vacant bit is 1, unless 0 is written to it.
• The parenthesized addresses are the corresponding addresses on the EPROM programmer.
18
MB89140 Series
■ BLOCK DIAGRAM
X0
X1
Main clock oscillator
Clock controller
Buzzer
Subclock oscillator
(32.768 kHz)
High-voltage port 6
CMOS input port
CMOS output port
Port 2
P23/WDG
P22
P21/PWO0
P20
Internal bus
Port 7
P70, P71
X0A
X1A
Time-base timer
BZ
High-voltage port 5
High-voltage port 4
8
P60 to P67
8
P50 to P57
8
P40 to P47
8-bit PWM timer
VFDP
Mode control
MODA
P32/SCK
P33/SO
P34/SI
8-bit serial interface
AVCC
P17/ADST
4
P14 to P16
4
P13/ANB to
P10/AN8
8
P07/AN7 to
P00/AN0
Port 0 and port 1
12-bit MPG
CMOS I/O port
RAM
F2MC-8L
CPU
8/16-bit
timer/counter
External
interrupt
Port 3
10-bit A/D converter
AVSS
P30/TRG/INT0
P37/DTTI
P36/PWO1
P35/EC
P31/INT1
(N-ch open-drain)
CMOS I/O port
Reset circuit
RST
ROM
Other pins
VCC, VSS
19
MB89140 Series
■ CPU CORE
1. Memory Space
The microcontrollers of the MB89140 series offer a memory space of 64 Kbytes for storing all of I/O, data, and
program areas. The I/O area is located at the lowest address. The data area is provided immediately above the
I/O area. The data area can be divided into register, stack, and direct areas according to the application. The
program area is located at exactly the opposite end, that is, near the highest address. Provide the tables of
interrupt reset vectors and vector call instructions toward the highest address within the program area. The
memory space of the MB89140 series is structured as illustrated below.
Memory Space
MB89PV140
0000H
MB89145
0000H
I/O
0080H
I/O
0080H
RAM
0100H
I/O
RAM
Register
I/O
0080H
RAM
0100H
Register
0200H
MB89P147
0000H
0080H
0100H
0200H
MB89146
0000H
RAM
0100H
Register
0200H
Register
0200H
0280H
0380H
0480H
0480H
Not available
Not available
Not available
Not available
8000H
8000H
*
*
8006H
8006H
A000H
C000H
External ROM
32 KB
FFFFH
ROM
16 KB
FFFFH
PROM
32 KB
ROM
24 KB
FFFFH
FFFFH
*: Since addresses 8000H to 8005H for the MB89P147 comprise an option area, do not use this area for the MB89PV140.
20
MB89140 Series
2. Registers
The F2MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers
in the memory. The following dedicated registers are provided:
Program counter (PC):
A 16-bit register for indicating instruction storage positions
Accumulator (A):
A 16-bit temporary register for storing arithmetic operations, etc. When the
instruction is an 8-bit data processing instruction, the lower byte is used.
Temporary accumulator (T):
A 16-bit register which performs arithmetic operations with the accumulator
When the instruction is an 8-bit data processing instruction, the lower byte is used.
Index register (IX):
A 16-bit register for index modification
Extra pointer (EP):
A 16-bit pointer for indicating a memory address
Stack pointer (SP):
A 16-bit register for indicating a stack area
Program status (PS):
A 16-bit register for storing a register pointer, a condition code
16 bits
Initial value
: Program counter
PC
FFFDH
A
: Accumulator
Undefined
T
: Temporary accumulator
Undefined
IX
: Index register
Undefined
EP
: Extra pointer
Undefined
SP
: Stack pointer
Undefined
PS
: Program status
I-flag = 0, IL1, 0 = 11
Other bits are undefined.
The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for
use as a condition code register (CCR). (See the diagram below.)
Structure of the Program Status Register
15
PS
14
13
12
RP
11
10
9
8
Vacancy Vacancy Vacancy
RP
7
6
H
I
5
4
IL1, 0
3
2
1
0
N
Z
V
C
CCR
21
MB89140 Series
The RP indicates the address of the register bank currently in use. The relationship between the pointer contents
and the actual address is based on the conversion rule illustrated below.
Rule for Conversion of Actual Addresses of the General-purpose Register Area
Lower OP codes
RP
“0” “0” “0” “0” “0” “0” “0” “1” R4 R3 R2 R1 R0 b2
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
b1
b0
↓
↓
Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and
bits for control of CPU operations at the time of an interrupt.
H-flag: Set when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared
otherwise. This flag is for decimal adjustment instructions.
I-flag:
Interrupt is allowed when this flag is set to 1. Interrupt is prohibited when the flag is set to 0. Set to 0
when reset.
IL1, 0:
Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is
higher than the value indicated by this bit.
IL1
IL0
Interrupt level
0
0
0
1
1
0
2
1
1
3
1
High-low
High
Low = no interrupt
N-flag: Set if the MSB is set to 1 as the result of an arithmetic operation. Cleared when the bit is set to 0.
Z-flag:
Set when an arithmetic operation results in 0. Cleared otherwise.
V-flag:
Set if the complement on 2 overflows as a result of an arithmetic operation. Reset if the overflow does
not occur.
C-flag: Set when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared otherwise.
Set to the shift-out value in the case of a shift instruction.
22
MB89140 Series
The following general-purpose registers are provided:
General-purpose registers: An 8-bit register for storing data
The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains
eight registers and up to a total of 32 banks can be used in the MB89140 series. The bank currently in use is
indicated by the register bank pointer (RP).
Register Bank Configuration
This address = 0100H + 8 × (RP)
R0
R1
R2
R3
R4
R5
R6
R7
32 banks
Memory area
23
MB89140 Series
■ I/O MAP
Address
Read/write
Register name
Register description
00H
(R/W)
PDR0
Port 0 data register
01H
(W)
DDR0
Port 0 data direction register
02H
(R/W)
PDR1
Port 1 data register
03H
(W)
DDR1
Port 1 data direction register
04H
(R/W)
PDR2
Port 2 data register
05H
Vacancy
06H
Vacancy
07H
(R/W)
SYCC
System clock control register
08H
(R/W)
STBC
Standby control register
09H
(R/W)
WDTC
Watchdog timer control register
0AH
(R/W)
TBCR
Time-base timer control register
0BH
(R/W)
WPCR
Watch prescaler control register
0CH
(R/W)
PDR3
Port 3 data register
0DH
(W)
DDR3
Port 3 data direction register
0EH
(R/W)
BUZR
Buzzer register
0FH
(R/W)
EIC
10H
(R/W)
PDR4
Port 4 data register
11H
(R/W)
PDR5
Port 5 data register
12H
(R/W)
PDR6
Port 6 data register
13H
(R)
PDR7
Port 7 data register
External interrupt control register
14H
Vacancy
15H
Vacancy
16H
(W)
COMR
8-bit PWM timer compare register
17H
(R/W)
CNTR
8-bit PWM timer control register
18H
(R/W)
T3CR
Timer 3 control register
19H
(R/W)
T2CR
Timer 2 control register
1AH
(R/W)
T3DR
Timer 3 data register
1BH
(R/W)
T2DR
Timer 2 data register
1CH
(R/W)
SMR
Serial mode register
1DH
(R/W)
SDR
Serial data register
1EH
(R/W)
ADC1
A/D converter control register 1
1FH
(R/W)
ADC2
A/D converter control register 2
(Continued)
24
MB89140 Series
(Continued)
Address
Read/write
Register name
Register description
20H
(R/W)
ADDH
A/D converter data register (H)
21H
(R/W)
ADDL
A/D converter data register (L)
22H
(W)
PCR0
Port input control register 0
23H
(W)
PCR1
Port input control register 1
24H
(R/W)
MCNT
MPG control register
25H
(R/W)
INTSTR
26H
(W)
CMCLBR (H)
MPG compare clear buffer register H
27H
(W)
CMCLBR (L)
MPG compare clear buffer register L
28H
(W)
OUTCBR (H)
MPG output buffer register H
29H
(W)
OUTCBR (L)
MPG output buffer register L
MPG interrupt status register
2AH
Vacancy
2BH
Vacancy
2CH
Vacancy
2DH
Vacancy
2EH
Vacancy
2FH
Vacancy
30H to 77H
Vacancy
78H
Vacancy
79H
Vacancy
7AH
Vacancy
7BH
Vacancy
7CH
(W)
ILR1
Interrupt level setting register 1
7DH
(W)
ILR2
Interrupt level setting register 2
7EH
(W)
ILR3
Interrupt level setting register 3
7FH
Vacancy
Note: Do not use vacancies.
25
MB89140 Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(AVSS = VSS = 0.0 V)
Parameter
Symbol
Value
Min.
Max.
VCC
AVCC
VIO1
VIO2
VSS – 0.3
VSS + 7.0
VSS – 0.3
VSS + 7.0
VSS – 0.3
VCC + 0.3
VSS – 0.3
7
V
V
V
V
“H” level total average output current
ΣIOH
—
–120
mA
—
–12
mA
“H” level maximum output current
IOH
—
—
–20
–36
mA
mA
—
–6
mA
—
–10
mA
—
–18
mA
Power supply voltage
I/O voltage
“H” level average output current
IOHAV
Remarks
Unit
“L” level total average output current
ΣIOLAV
—
150
mA
“L” level maximum output current
IOL
—
12
mA
“L” level average output current
IOLAV
—
6
mA
Power consumption
Operating temperature
Storage temperature
PD
TA
Tstg
—
–40
–55
500
+85
+150
mW
°C
°C
*2
Except P31
P31
Average value (operating current ×
operating rate)
P00 to P07, P10 to P17,
P20 to P23, P30, P32 to P37
P40 to P47, P50 to P57
P60 to P67, BZ
P00 to P07, P10 to P17,
P20 to P23, P30, P32 to P37
Average value (operating current ×
operating rate)*1
P40 to P47, P50 to P57
Average value (operating current ×
operating rate)*1
P60 to P67, BZ
Average value (operating current ×
operating rate)*1
Average value (operating current ×
operating rate)*1
P00 to P07, P10 to P17,
P20 to P23, P30 to P37
P00 to P07, P10 to P17,
P20 to P23, P30 to P37
Average value (operating current ×
operating rate)*1
*1: The total average output current is defined as the average current that flows through all of the relevant pins in
a 100 ms period. The output peak current is defined as the peak value of any one of the relevant pins. The
average output current is defined as the average current that flows through any one of the relevant pins in a
100 ms period.
*2: Use AVCC and VCC set at the same voltage.
Take care so that AVCC does not exceed VCC, such as when power is turned on.
Precautions: Permanent device damage may occur if the above “Absolute Maximum Ratings” are exceeded.
Functional operation should be restricted to the conditions as detailed in the operational sections of
this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
26
MB89140 Series
2. Recommended Operating Conditions
(AVSS = VSS = 0.0 V)
Value
Symbol
Parameter
Power supply voltage
VCC
AVCC
VFDP
Operating temperature
Unit
Max.
2.7*
6.0*
V
Normal operation assurance range*
2.2
6.0
V
In watch mode or subclock operation (Only for
the MB89P147, the minimum value is 2.7 V.)
1.5
6.0
V
Retains the RAM state in stop mode
VCC – 40 VCC + 0.3
–40
TA
Remarks
Min.
V
°C
+85
* : These values vary with the operating frequency and analog assurance range. See Figure 1 and “5. A/D Converter
Electrical Characteristics.”
Operating voltage (V)
6
5
Operation assurance range
4
3
2
1
2
3
4
5
6
7
8
Main clock operating frequency (at an instruction cycle of 4/FCH) (MHz)
2.0
0.8
0.5
Minimum execution time (instruction cycle) (µs)
Figure 1
Operating Voltage vs. Main Clock Operating Frequency
Figure 1 indicates the operating frequency of the external oscillator at an instruction cycle of 4/FCH.
Since the operating voltage range is dependent on the instruction cycle, see minimum execution time if the
operating speed is switched using a gear.
27
MB89140 Series
3. DC Characteristics
(AVCC = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Pin
Symbol
Condition
Value
Unit
Remarks
VCC + 0.3
V
Hysteresis input
—
0.2 VCC
V
Hysteresis input
Min.
Typ.
Max.
0.7 VCC
—
VSS – 0.3
P00 to P07,
“H” level input
voltage
P10 to P17,
VIHS
P30 to P37,
P70, P71,
X0, X1, RST, MODA
P00 to P07,
“L” level input
voltage
—
P10 to P17,
VILS
P30 to P37,
P70, P71,
X0, X1, RST, MODA
VOH1
P00 to P07,
P10 to P17,
P20 to P23,
P30, P32 to P37
IOH = –2.0 mA
2.4
—
—
V
VOH2
P40 to P47,
P50 to P57
IOH = –10 mA
3.0
—
—
V
VOH3
P60 to P67, BZ
IOH = –18 mA
3.0
—
—
V
VOL1
P00 to P07,
P10 to P17,
P20 to P23,
P30, P32 to P37
IOL = 1.8 mA
—
—
0.4
V
VOL2
RST
IOL = 4.0 mA
—
—
0.6
V
ILI1
P00 to P07,
P10 to P17,
P30 to P37,
P70, P71,
MODA
0.45 V < VI < VCC
ILI2
P14 to P17,
P32 to P37
VI = 0.0 V
ILO1
P40 to P47,
P50 to P57
ILO2
Pull-up
resistance
Pull-down
resistance
“H” level output
voltage
“L” level output
voltage
Input leakage
current
Output leakage
current
Without pull-up
—
—
±5
µA
resistor for P14
to P17 and P32
to P37
–200
–100
–50
µA
VI = VFDP
= VCC – 40 V
—
—
–10
µA
P60 to P67, BZ
VI = VFDP
= VCC – 40 V
—
—
–20
µA
RPULU
RST
P14 to P17,
P32 to P37
VI = 0.0 V
25
50
100
kΩ
RPULD
P40 to P47,
P50 to P57,
P60 to P67
VOH = 5.0 V
50
100
150
kΩ
With pull-up
resistor
With pull-up
resistor
With pull-down
resistor optional
(Continued)
28
MB89140 Series
(Continued)
(AVCC = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Pin
Symbol
—
9
15
mA
—
1.5
2
mA
—
2.5
5.0
FCH = 8 MHz
VCC = 5.0 V
tinst*2 = 0.5 µs
—
3
7
mA
FCH = 8 MHz
VCC = 3.2 V
tinst*2 = 8.0 µs
—
1
1.5
mA
—
50
150
µA
—
1
3
mA MB89P147
—
25
50
µA
ICC2
Subclock mode
FCL = 32.768 kHz
VCC = 3.0 V
ICCL
Remarks
Max.
FCH = 8 MHz
VCC = 3.2 V
tinst*2 = 8.0 µs
Output open
VCC
Unit
Typ.
ICC1
ICCS2
Value
Min.
FCH = 8 MHz
VCC = 5.0 V
tinst*2 = 0.5 µs
Output open
ICCS1
Power supply
current*1
Condition
Sleep mode
Parameter
mA MB89P147
Subclock sleep mode
ICCLS
FCL = 32.768 kHz
VCC = 3.0 V
ICCT
Watch mode
FCL = 32.768 kHz
VCC = 3.0 V
—
3
15
µA
ICCH
Stop mode
TA = +25°C
—
—
10
µA
—
1.5
4
mA
when A/D conversion
is stopped
—
1
5
µA
f = 1 MHz
—
10
—
pF
FCH = 8 MHz,
IA
AVCC
IAH
when A/D conversion
is activated
TA = +25°C,
Other than AVCC,
Input capacitance CIN
AVSS, VCC, and
VSS
*1: The power supply current is measured at the external clock.
*2: For information on tinst, see “(4) Instruction Cycle” in “4. AC Characteristics.”
Note: FCH indicates the main clock oscillation frequency. When FCH = 8 MHz, the 4/FCH execution time is 0.5 µs, and
the 64/FCH execution time is 8 µs.
29
MB89140 Series
4. AC Characteristics
(1) Reset Timing
(AVCC = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol
RST “L” pulse width
tZLZH
RST noise limit width
tZLNC
Condition
—
Value
Unit
Min.
Typ.
Max.
16 tXCYL
—
—
ns
30
50
80
ns
Remarks
Note: TXCYL is the oscillation cycle (1/FCH) to input to the X0 pin.
tZLZH
tZLNC
RST
0.2 VCC
0.2 VCC
(2) Power-on Reset
(AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol
Power supply rising time
tR
Power supply cut-off time
tOFF
Condition
—
Value
Unit
Remarks
Min.
Max.
—
50
ms
Power-on reset function only
1
—
ms
Due to repeated operations
Note: Make sure that power supply rises within the selected oscillation stabilization time.
If power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended.
tOFF
tR
2.0 V
VCC
30
0.2 V
0.2 V
0.2 V
MB89140 Series
(3) Clock Timing
(AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Symbol
Parameter
Clock frequency
Clock cycle time
Input clock pulse width
Input clock rising/falling
time
Pin
Condition
Value
Min.
Typ.
Max.
Unit
FCH
X0, X1
2
—
8
MHz
FCL
X0A, X1A
—
32.768
—
kHz
tXCYL
X0, X1
125
—
500
ns
tLXCYL
X0A, X1A
—
30.5
—
µs
PWH
PWL
X0
30
—
—
ns
PWHL
PWLL
X0A
—
15.2
—
µs
tCR
tCF
X0, X0A
—
—
10
ns
—
Remarks
External clock
External clock
X0 and X1 Timing and Conditions
tXCYL
PWH
PWL
tCF
tCR
0.8 VCC
0.8 VCC
X0
0.2 VCC
0.2 VCC
0.2 VCC
Main Clock Conditions
When a crystal or ceramic resonator is used
X0
X1
When an external clock is used
X0
X1
Open
C0
C1
31
MB89140 Series
X0A and X1A Timing and Conditions
tLXCYL
PWHL
PWLL
tCF
tCR
0.8 VCC
0.8 VCC
X0A
0.2 VCC
0.2 VCC
0.2 VCC
Subclock Conditions
MB89PV140
When a crystal or ceramic resonator is used
When an external clock is used
RF = approx. 2 MΩ
X0A
X0A
X1A
C0
C1
X1A
Open
RD
Mask ROM products and MB89P147
When a crystal or ceramic resonator is used
X0A
When an external clock is used
X0A
X1A
X1A
Open
RF
C0
RD
C1
Note: The subclock oscillator feedback resistor is connected externally in dual-clock mask ROM products and in the
MB89P147. (The subclock oscillator feedback resistor is connected internally in the MB89PV140-102.)
(4) Instruction Cycle
Parameter
Instruction cycle
(minimum execution time)
32
Symbol
Value (typical)
Unit
Remarks
4/FCH, 8/FCH, 16/FCH, 64/FCH
µs
(4/FCH) tinst = 0.5 µs when operating at
FCH = 8 MHz
2/FCL
µs
tinst = 61.036 µs when operating at
FCL = 32.768 kHz
tinst
MB89140 Series
(5) Serial I/O Timing
(AVCC = VCC = 5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol
Pin
Condition
Serial clock cycle time
tSCYC
SCK
SCK ↓ → SO time
tSLOV
SCK, SO
Valid SI → SCK ↑
tIVSH
SI, SCK
SCK ↑ → valid SI hold time
tSHIX
SCK, SI
Serial clock “H” pulse width
tSHSL
SCK
Serial clock “L” pulse width
tSLSH
SCK
Internal shift
clock mode
External shift
clock mode
Value
Unit
Min.
Max.
2 tinst*
—
µs
–200
200
ns
1/2 tinst*
—
µs
1/2 tinst*
—
µs
1 tinst*
—
µs
1 tinst*
—
µs
0
200
ns
SCK ↓ → SO time
tSLOV
SCK, SO
Valid SI → SCK ↑
tIVSH
SI, SCK
1/2 tinst*
—
µs
SCK ↑ → valid SI hold time
tSHIX
SCK, SI
1/2 tinst*
—
µs
Remarks
* : For information on tinst, see “(4) Instruction Cycle.”
Internal Shift Clock Mode
tSCYC
SCK
2.4 V
0.8 V
0.8 V
tSLOV
2.4 V
SO
0.8 V
tIVSH
SI
tSHIX
0.8 VCC
0.8 VCC
0.3 VCC
0.3 VCC
External Shift Clock Mode
tSLSH
SCK
SO
tSHSL
0.8 VCC
0.2 VCC
tSLOV
2.4 V
0.8 V
tIVSH
SI
0.8 VCC
0.2 VCC
tSHIX
0.8 VCC
0.8 VCC
0.3 VCC
0.3 VCC
33
MB89140 Series
(6) Peripheral Input Timing
(AVCC = VCC = 5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Symbol
Parameter
Pin
Condition
Value
Min.
Max.
Unit
Peripheral input “H” pulse width 1
tILIH1
TRG, DTTI
ADST, EC
INT0 to INT1
—
2 tinst*
—
µs
Peripheral input “L” pulse width 1
tIHIL1
TRG, DTTI
ADST, EC
INT0 to INT1
—
2 tinst*
—
µs
Remarks
* : For information on tinst, see “(4) Instruction Cycle.”
(7) Peripheral Input Noise Limit Width
(AVCC = VCC = 5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol
Peripheral input “H”
level noise limit width 1
tIHNC1
Peripheral input “L”
level noise limit width 1
tILNC1
Interrupt “H” level noise
limit width 2
tIHNC2
Interrupt “L” level noise
limit width 2
tILNC2
Value
Condition
All inputs except
INT1 and INT0
All inputs except
INT1 and INT0
INT1, INT0
INT1, INT0
Max.
7
15
30
ns
MB89P147/PV140
15
30
60
ns
Except MB89P147/PV140
7
15
30
ns
MB89P147/PV140
15
30
60
ns
Except MB89P147/PV140
30
50
100
ns
MB89P147/PV140
50
100
250
ns
Except MB89P147/PV140
30
50
100
ns
MB89P147/PV140
50
100
250
ns
Except MB89P147/PV140
tILIH1
0.8 VCC
0.2 VCC
34
tIHNC1
tIHNC2
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
tILNC1
tILNC2
P00 to P07, P01 to P17
P30 to P37, P70, P71
TRG, SCK, SI,
EC, DTTI, ADST
INT1, INT0
Remarks
Typ.
tIHIL1
TRG
DTTI
ADST
INT0 to INT1
EC
Unit
Min.
0.2 VCC
0.8 VCC
MB89140 Series
5. A/D Converter Electrical Characteristics
(AVCC = VCC = 5.0 V+10%, FCH = 8 MHz, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol
Pin
Resolution
Total error
Linearity error
Value
Min.
Typ.
Max.
—
—
10
bit
—
—
±3.0
LSB
—
—
±2.0
LSB
—
—
±1.5
LSB
—
AVSS – 1.5 LSB
AVSS + 0.5 LSB
AVSS + 2.5 LSB
mV
—
AVCC – 3.5 LSB AVCC – 1.5 LSB AVCC + 0.5 LSB
mV
—
—
—
AVCC = VCC
= 5.0 V
Differential linearity error
Zero transition voltage
VOT
Full-scale transition
voltage
VFST
AN0 to
ANB
AN0 to
ANB
Interchannel disparity
A/D mode conversion
time
—
—
At 8-MHz
oscillation
Analog port input current IAIN
Analog input voltage
—
—
AN0 to
AVCC = VCC
ANB
= 5.0 V
AN0 to
ANB
Unit
Condition
—
—
—
4
LSB
33
—
—
tinst*
—
—
10
µA
0.0
—
AVCC
V
Remarks
* : For information on tinst, see “(4) Instruction Cycle” in “4. AC Characteristics.”
Notes: • The smaller AVCC, the greater the error would become relatively.
• The output impedance of the external circuit connected to an analog input block should be no more than
several kΩ. If the output impedance is too high, the analog voltage sampling time might be insufficient.
Sample hold circuit
R ≤ 10 kΩ is
recommended.
AN
.
C =. 60 pF
Comparator
.
R =. 3 kΩ
Analog channel
selector
When R > 10 kΩ, it is
recommended to connect
an external capacitor of
approx. 0.1 µF.
Close for approx. 15 to 72 instruction cycles after
activating A/D conversion. (The close time
depends on the register settings.)
35
MB89140 Series
(1) A/D Glossary
• Resolution
Analog changes that are identifiable with the A/D converter
• Linearity error
The deviation of the straight line connecting the zero transition point (“00 0000 0000” ↔ “00 0000 0001”) with
the full-scale transition point (“11 1111 1110” ↔ “11 1111 1111”) from actual conversion characteristics
• Differential linearity error
The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value
• Total error
The difference between theoretical and actual values
This error is caused by the zero transition error, full-scale transition error, linearity error, quantization error and
noise.
Theoretical I/O characteristics
Total error
VFST
3FF
3FF
3FE
3FE
3FD
1.5 LSB
Digital output
Digital output
3FD
004
003
{1 LSB × N + 0.5 LSB}
004
VNT
003
VOT
002
Actual conversion
value
Actual conversion
value
002
1 LSB
Theoretical value
001
001
0.5 LSB
AVSS
AVR
Analog input
1 LSB =
VFST – VOT
1022
AVSS
AVR
Analog input
(V)
Total error for digital output N =
VNT – {1 LSB × N + 0.5 LSB}
1 LSB
(Continued)
36
MB89140 Series
(Continued)
Zero transition error
Full-scale transition error
004
Theoretical value
Actual conversion
value
3FF
Actual conversion
value
Digital output
Digital output
003
002
3FE
VFST
(measured value)
3FD
Actual conversion
value
Actual conversion
value
001
3FC
VOT (measured value)
AVSS
3FF
AVR
Analog input
Analog input
Linearity error
Differential linearity error
Theoretical value
Actual conversion
value
N+1
3FE
{1 LSB × N + VOT}
Actual conversion
value
VNT
VFST
(measured
value)
004
003
Actual conversion
value
Digital output
Digital output
3FD
V(N + 1) T
N
N–1
VNT
Actual conversion
value
002
Theoretical value
N–2
001
VOT (measured value)
AVSS
AVR
Analog input
Linearity error for digital output N =
AVSS
AVR
Analog input
VNT – {1 LSB × N + VOT}
1 LSB
V(N + 1) T – VNT
Differential linearity error for digital output N =
–1
1 LSB
37
MB89140 Series
■ EXAMPLE CHARACTERISTICS
(1) “L” Level Output Voltage
(2) “H” Level Output Voltage
VOL vs. IOL
VCC – VOH vs. IOH
VOL (V)
VCC = 2.5 V
TA = +25°C
VCC – VOH (V)
1.0
0.9
0.5
0.7
0.4
VCC = 4.0 V
VCC = 5.0 V
VCC = 6.0 V
0.6
VCC = 3.0 V
0.5
VCC = 4.0 V
VCC = 5.0 V
VCC = 6.0 V
0.4
0.2
0.3
0.2
0.1
0.0
VCC = 2.5 V
0.8
VCC = 3.0 V
0.3
TA = +25°C
0.1
0
1
2
3
4
5
6
7
8
9
0.0
0.0
10
IOL (mA)
–0.5
–1.0
–1.5
–2.0
–2.5
(3) “H” Level Input Voltage/“L” Level Input Voltage (Hysteresis Input)
CMOS hysteresis input
VIN (V)
5.0
4.5
TA = +25°C
4.0
3.5
VIHS
3.0
2.5
VILS
2.0
1.5
1.0
0.5
0.0
0
1
2
3
4
5
6
7
VCC (V)
VIHS: Threshold when input voltage in hysteresis characteristics is set to “H” level
VILS: Threshold when input voltage in hysteresis characteristics is set to “L” level
38
–3.0
IOH (mA)
MB89140 Series
(4) Power Supply Current (External Clock)
ICC1 vs. VCC, ICC2 vs. VCC
ICCS1 vs. VCC, ICCS2 vs. VCC
ICC (mA)
ICCS (mA)
FCH = 8 MHz
TA = +25°C
16
FCH = 8 MHz
TA = +25°C
4.0
Divide by 4 (ICCS1)
Divide by 4 (ICC1)
14
12
3.0
10
8
2.0
Divide by 64 (ICCS2)
6
4
1.0
Divide by 64 (ICC2)
2
0
0
2.0
3.0
4.0
5.0
6.0
7.0
2.0
3.0
4.0
5.0
6.0
VCC (V)
ICCL vs. VCC
ICCL (µA)
200
VCC (V)
ICCLS vs. VCC
ICCLS (µA)
TA = +25°C
7.0
50
TA = +25°C
180
40
160
140
30
120
100
80
20
60
40
10
20
0
0
2.0
3.0
4.0
5.0
6.0
7.0
VCC (V)
2.0
3.0
4.0
5.0
6.0
7.0
VCC (V)
(Continued)
39
MB89140 Series
(Continued)
ICCT vs. VCC
ICCT (µA)
ICCH vs. VCC
ICCH (µA)
18
1.8
TA = +25°C
16
TA = +25°C
1.6
14
1.4
12
1.2
10
1.0
8
0.8
6
0.6
4
0.4
2
0.2
0
0
2.0
3.0
4.0
5.0
6.0
7.0
2.0
3.0
4.0
VCC (V)
RPULL vs. VCC
RPULL (kΩ)
1,000
500
100
50
TA = +85°C
TA = +25°C
TA = –40°C
10
40
2
3
6.0
7.0
VCC (V)
(5) Pull-up Resistance
1
5.0
4
5
6
7
VCC (V)
MB89140 Series
■ INSTRUCTIONS
Execution instructions can be divided into the following four groups:
•
•
•
•
Transfer
Arithmetic operation
Branch
Others
Table 1 lists symbols used for notation of instructions.
Table 1
Instruction Symbols
Symbol
Meaning
dir
Direct address (8 bits)
off
Offset (8 bits)
ext
Extended address (16 bits)
#vct
Vector table number (3 bits)
#d8
Immediate data (8 bits)
#d16
Immediate data (16 bits)
dir: b
Bit direct address (8:3 bits)
rel
Branch relative address (8 bits)
@
Register indirect (Example: @A, @IX, @EP)
A
Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.)
AH
Upper 8 bits of accumulator A (8 bits)
AL
Lower 8 bits of accumulator A (8 bits)
T
Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the
instruction in use.)
TH
Upper 8 bits of temporary accumulator T (8 bits)
TL
Lower 8 bits of temporary accumulator T (8 bits)
IX
Index register IX (16 bits)
(Continued)
41
MB89140 Series
(Continued)
Symbol
Meaning
EP
Extra pointer EP (16 bits)
PC
Program counter PC (16 bits)
SP
Stack pointer SP (16 bits)
PS
Program status PS (16 bits)
dr
Accumulator A or index register IX (16 bits)
CCR
Condition code register CCR (8 bits)
RP
Register bank pointer RP (5 bits)
Ri
General-purpose register Ri (8 bits, i = 0 to 7)
×
Indicates that the very × is the immediate data.
(Whether its length is 8 or 16 bits is determined by the instruction in use.)
(×)
Indicates that the contents of × is the target of accessing.
(Whether its length is 8 or 16 bits is determined by the instruction in use.)
(( × ))
The address indicated by the contents of × is the target of accessing.
(Whether its length is 8 or 16 bits is determined by the instruction in use.)
Columns indicate the following:
Mnemonic:
Assembler notation of an instruction
~:
Number of instructions
#:
Number of bytes
Operation:
Operation of an instruction
TL, TH, AH:
A content change when each of the TL, TH, and AH instructions is executed. Symbols in
the column indicate the following:
• “–” indicates no change.
• dH is the 8 upper bits of operation description data.
• AL and AH must become the contents of AL and AH immediately before the instruction
is executed.
• 00 becomes 00.
N, Z, V, C:
An instruction of which the corresponding flag will change. If + is written in this column,
the relevant instruction will change its corresponding flag.
OP code:
Code of an instruction. If an instruction is more than one code, it is written according to
the following rule:
Example: 48 to 4F ← This indicates 48, 49, ... 4F.
42
MB89140 Series
Table 2
Transfer Instructions (48 instructions)
Mnemonic
~
#
Operation
TL
TH
AH
NZVC
OP code
MOV dir,A
MOV @IX +off,A
MOV ext,A
MOV @EP,A
MOV Ri,A
MOV A,#d8
MOV A,dir
MOV A,@IX +off
MOV A,ext
MOV A,@A
MOV A,@EP
MOV A,Ri
MOV dir,#d8
MOV @IX +off,#d8
MOV @EP,#d8
MOV Ri,#d8
MOVW dir,A
MOVW @IX +off,A
3
4
4
3
3
2
3
4
4
3
3
3
4
5
4
4
4
5
2
2
3
1
1
2
2
2
3
1
1
1
3
3
2
2
2
2
–
–
–
–
–
AL
AL
AL
AL
AL
AL
AL
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
––––
––––
––––
––––
––––
++––
++––
++––
++––
++––
++––
++––
––––
––––
––––
––––
––––
––––
45
46
61
47
48 to 4F
04
05
06
60
92
07
08 to 0F
85
86
87
88 to 8F
D5
D6
MOVW ext,A
MOVW @EP,A
MOVW EP,A
MOVW A,#d16
MOVW A,dir
MOVW A,@IX +off
5
4
2
3
4
5
3
1
1
3
2
2
–
–
–
AL
AL
AL
–
–
–
AH
AH
AH
–
–
–
dH
dH
dH
––––
––––
––––
++––
++––
++––
D4
D7
E3
E4
C5
C6
MOVW A,ext
MOVW A,@A
MOVW A,@EP
MOVW A,EP
MOVW EP,#d16
MOVW IX,A
MOVW A,IX
MOVW SP,A
MOVW A,SP
MOV @A,T
MOVW @A,T
MOVW IX,#d16
MOVW A,PS
MOVW PS,A
MOVW SP,#d16
SWAP
SETB dir: b
CLRB dir: b
XCH A,T
XCHW A,T
XCHW A,EP
XCHW A,IX
XCHW A,SP
MOVW A,PC
5
4
4
2
3
2
2
2
2
3
4
3
2
2
3
2
4
4
2
3
3
3
3
2
3
1
1
1
3
1
1
1
1
1
1
3
1
1
3
1
2
2
1
1
1
1
1
1
(dir) ← (A)
( (IX) +off ) ← (A)
(ext) ← (A)
( (EP) ) ← (A)
(Ri) ← (A)
(A) ← d8
(A) ← (dir)
(A) ← ( (IX) +off)
(A) ← (ext)
(A) ← ( (A) )
(A) ← ( (EP) )
(A) ← (Ri)
(dir) ← d8
( (IX) +off ) ← d8
( (EP) ) ← d8
(Ri) ← d8
(dir) ← (AH),(dir + 1) ← (AL)
( (IX) +off) ← (AH),
( (IX) +off + 1) ← (AL)
(ext) ← (AH), (ext + 1) ← (AL)
( (EP) ) ← (AH),( (EP) + 1) ← (AL)
(EP) ← (A)
(A) ← d16
(AH) ← (dir), (AL) ← (dir + 1)
(AH) ← ( (IX) +off),
(AL) ← ( (IX) +off + 1)
(AH) ← (ext), (AL) ← (ext + 1)
(AH) ← ( (A) ), (AL) ← ( (A) ) + 1)
(AH) ← ( (EP) ), (AL) ← ( (EP) + 1)
(A) ← (EP)
(EP) ← d16
(IX) ← (A)
(A) ← (IX)
(SP) ← (A)
(A) ← (SP)
( (A) ) ← (T)
( (A) ) ← (TH),( (A) + 1) ← (TL)
(IX) ← d16
(A) ← (PS)
(PS) ← (A)
(SP) ← d16
(AH) ↔ (AL)
(dir): b ← 1
(dir): b ← 0
(AL) ↔ (TL)
(A) ↔ (T)
(A) ↔ (EP)
(A) ↔ (IX)
(A) ↔ (SP)
(A) ← (PC)
AL
AL
AL
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
AL
AL
–
–
–
–
AH
AH
AH
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
AH
–
–
–
–
dH
dH
dH
dH
–
–
dH
–
dH
–
–
–
dH
–
–
AL
–
–
–
dH
dH
dH
dH
dH
++––
++––
++––
––––
––––
––––
––––
––––
––––
––––
––––
––––
––––
++++
––––
––––
––––
––––
––––
––––
––––
––––
––––
––––
C4
93
C7
F3
E7
E2
F2
E1
F1
82
83
E6
70
71
E5
10
A8 to AF
A0 to A7
42
43
F7
F6
F5
F0
Notes: • During byte transfer to A, T ← A is restricted to low bytes.
• Operands in more than one operand instruction must be stored in the order in which their mnemonics are
written. (Reverse arrangement of F2MC-8 family)
43
MB89140 Series
Table 3
44
Mnemonic
~
#
ADDC A,Ri
ADDC A,#d8
ADDC A,dir
ADDC A,@IX +off
ADDC A,@EP
ADDCW A
ADDC A
SUBC A,Ri
SUBC A,#d8
SUBC A,dir
SUBC A,@IX +off
SUBC A,@EP
SUBCW A
SUBC A
INC Ri
INCW EP
INCW IX
INCW A
DEC Ri
DECW EP
DECW IX
DECW A
MULU A
DIVU A
ANDW A
ORW A
XORW A
CMP A
CMPW A
RORC A
3
2
3
4
3
3
2
3
2
3
4
3
3
2
4
3
3
3
4
3
3
3
19
21
3
3
3
2
3
2
1
2
2
2
1
1
1
1
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
ROLC A
2
1
CMP A,#d8
CMP A,dir
CMP A,@EP
CMP A,@IX +off
CMP A,Ri
DAA
DAS
XOR A
XOR A,#d8
XOR A,dir
XOR A,@EP
XOR A,@IX +off
XOR A,Ri
AND A
AND A,#d8
AND A,dir
2
3
3
4
3
2
2
2
2
3
3
4
3
2
2
3
2
2
1
2
1
1
1
1
2
2
1
2
1
1
2
2
Arithmetic Operation Instructions (62 instructions)
Operation
TL
TH
AH
NZVC
OP code
(A) ← (A) + (Ri) + C
(A) ← (A) + d8 + C
(A) ← (A) + (dir) + C
(A) ← (A) + ( (IX) +off) + C
(A) ← (A) + ( (EP) ) + C
(A) ← (A) + (T) + C
(AL) ← (AL) + (TL) + C
(A) ← (A) − (Ri) − C
(A) ← (A) − d8 − C
(A) ← (A) − (dir) − C
(A) ← (A) − ( (IX) +off) − C
(A) ← (A) − ( (EP) ) − C
(A) ← (T) − (A) − C
(AL) ← (TL) − (AL) − C
(Ri) ← (Ri) + 1
(EP) ← (EP) + 1
(IX) ← (IX) + 1
(A) ← (A) + 1
(Ri) ← (Ri) − 1
(EP) ← (EP) − 1
(IX) ← (IX) − 1
(A) ← (A) − 1
(A) ← (AL) × (TL)
(A) ← (T) / (AL),MOD → (T)
(A) ← (A) ∧ (T)
(A) ← (A) ∨ (T)
(A) ← (A) ∀ (T)
(TL) − (AL)
(T) − (A)
→ C→A
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dL
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
00
–
–
–
–
–
–
–
–
–
–
–
dH
–
–
–
–
–
–
dH
–
–
–
–
dH
–
–
–
dH
dH
00
dH
dH
dH
–
–
–
++++
++++
++++
++++
++++
++++
++++
++++
++++
++++
++++
++++
++++
++++
+++–
––––
––––
++––
+++–
––––
––––
++––
––––
––––
++R–
++R–
++R–
++++
++++
++–+
28 to 2F
24
25
26
27
23
22
38 to 3F
34
35
36
37
33
32
C8 to CF
C3
C2
C0
D8 to DF
D3
D2
D0
01
11
63
73
53
12
13
03
C ← A←
–
–
–
++–+
02
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
++++
++++
++++
++++
++++
++++
++++
++R–
++R–
++R–
++R–
++R–
++R–
++R–
++R–
++R–
14
15
17
16
18 to 1F
84
94
52
54
55
57
56
58 to 5F
62
64
65
(A) − d8
(A) − (dir)
(A) − ( (EP) )
(A) − ( (IX) +off)
(A) − (Ri)
Decimal adjust for addition
Decimal adjust for subtraction
(A) ← (AL) ∀ (TL)
(A) ← (AL) ∀ d8
(A) ← (AL) ∀ (dir)
(A) ← (AL) ∀ ( (EP) )
(A) ← (AL) ∀ ( (IX) +off)
(A) ← (AL) ∀ (Ri)
(A) ← (AL) ∧ (TL)
(A) ← (AL) ∧ d8
(A) ← (AL) ∧ (dir)
MB89140 Series
(Continued)
Mnemonic
~
#
AND A,@EP
AND A,@IX +off
AND A,Ri
OR A
OR A,#d8
OR A,dir
OR A,@EP
OR A,@IX +off
OR A,Ri
CMP dir,#d8
CMP @EP,#d8
CMP @IX +off,#d8
CMP Ri,#d8
INCW SP
DECW SP
3
4
3
2
2
3
3
4
3
5
4
5
4
3
3
1
2
1
1
2
2
1
2
1
3
2
3
2
1
1
Operation
(A) ← (AL) ∧ ( (EP) )
(A) ← (AL) ∧ ( (IX) +off)
(A) ← (AL) ∧ (Ri)
(A) ← (AL) ∨ (TL)
(A) ← (AL) ∨ d8
(A) ← (AL) ∨ (dir)
(A) ← (AL) ∨ ( (EP) )
(A) ← (AL) ∨ ( (IX) +off)
(A) ← (AL) ∨ (Ri)
(dir) – d8
( (EP) ) – d8
( (IX) + off) – d8
(Ri) – d8
(SP) ← (SP) + 1
(SP) ← (SP) – 1
Table 4
Mnemonic
BZ/BEQ rel
BNZ/BNE rel
BC/BLO rel
BNC/BHS rel
BN rel
BP rel
BLT rel
BGE rel
BBC dir: b,rel
BBS dir: b,rel
JMP @A
JMP ext
CALLV #vct
CALL ext
XCHW A,PC
RET
RETI
~
#
3
3
3
3
3
3
3
3
5
5
2
3
6
6
3
4
6
2
2
2
2
2
2
2
2
3
3
1
3
1
3
1
1
1
Mnemonic
PUSHW A
POPW A
PUSHW IX
POPW IX
NOP
CLRC
SETC
CLRI
SETI
~
#
4
4
4
4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
TH
AH
NZVC
OP code
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
++R–
++R–
++R–
++R–
++R–
++R–
++R–
++R–
++R–
++++
++++
++++
++++
––––
––––
67
66
68 to 6F
72
74
75
77
76
78 to 7F
95
97
96
98 to 9F
C1
D1
Branch Instructions (17 instructions)
Operation
If Z = 1 then PC ← PC + rel
If Z = 0 then PC ← PC + rel
If C = 1 then PC ← PC + rel
If C = 0 then PC ← PC + rel
If N = 1 then PC ← PC + rel
If N = 0 then PC ← PC + rel
If V ∀ N = 1 then PC ← PC + rel
If V ∀ N = 0 then PC ← PC + reI
If (dir: b) = 0 then PC ← PC + rel
If (dir: b) = 1 then PC ← PC + rel
(PC) ← (A)
(PC) ← ext
Vector call
Subroutine call
(PC) ← (A),(A) ← (PC) + 1
Return from subrountine
Return form interrupt
Table 5
TL
TL
TH
AH
NZVC
OP code
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dH
–
–
––––
––––
––––
––––
––––
––––
––––
––––
–+––
–+––
––––
––––
––––
––––
––––
––––
Restore
FD
FC
F9
F8
FB
FA
FF
FE
B0 to B7
B8 to BF
E0
21
E8 to EF
31
F4
20
30
Other Instructions (9 instructions)
Operation
TL
TH
AH
NZVC
OP code
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dH
–
–
–
–
–
–
–
––––
––––
––––
––––
––––
–––R
–––S
––––
––––
40
50
41
51
00
81
91
80
90
45
L
46
B
C
D
E
F
MOV
CMP
ADDC SUBC
A,#d8
A,#d8
A,#d8
A,#d8
MOV
CMP
ADDC SUBC
MOV
XOR
AND
OR
MOV
CMP
CLRB
BBC
MOVW MOVW MOVW XCHW
A,dir
A,dir
A,dir
A,dir
dir,A
A,dir
A,dir
A,dir dir,#d8 dir,#d8
dir: 5 dir: 5,rel
A,dir
dir,A SP,#d16
A,SP
5
ADDC
A
SUBC
A
XCH
XOR
AND
OR
A, T
A
A
A
MOV
MOV
CLRB
BBC
INCW
DECW MOVW MOVW
@A,T
A,@A
dir: 2 dir: 2,rel
IX
IX
IX,A
A,IX
CLRB
BBC
INCW
DECW MOVW MOVW
dir: 1 dir: 1,rel
SP
SP
SP,A
A,SP
MOV
CMP
ADDC SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
DEC
CALLV BN
A,R3
A,R3
A,R3
A,R3
R3,A
A,R3
A,R3
A,R3 R3,#d8 R3,#d8
dir: 3 dir: 3,rel
R3
R3
#3
MOV
CMP
ADDC SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
DEC
CALLV BNZ
A,R4
A,R4
A,R4
A,R4
R4,A
A,R4
A,R4
A,R4 R4,#d8 R4,#d8
dir: 4 dir: 4,rel
R4
R4
#4
rel
MOV
CMP
ADDC SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
DEC
CALLV BZ
A,R5
A,R5
A,R5
A,R5
R5,A
A,R5
A,R5
A,R5 R5,#d8 R5,#d8
dir: 5 dir: 5,rel
R5
R5
#5
MOV
CMP
ADDC SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
DEC
CALLV BGE
A,R6
A,R6
A,R6
A,R6
R6,A
A,R6
A,R6
A,R6 R6,#d8 R6,#d8
dir: 6 dir: 6,rel
R6
R6
#6
rel
MOV
CMP
ADDC SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
DEC
CALLV BLT
A,R7
A,R7
A,R7
A,R7
R7,A
A,R7
A,R7
A,R7 R7,#d8 R7,#d8
dir: 7 dir: 7,rel
R7
R7
#7
rel
C
D
E
F
rel
rel
rel
rel
B
MOVW XCHW
IX,#d16
A,IX
MOV
CMP
ADDC SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
DEC
CALLV BP
A,R2
A,R2
A,R2
A,R2
R2,A
A,R2
A,R2
A,R2 R2,#d8 R2,#d8
dir: 2 dir: 2,rel
R2
R2
#2
MOVW
MOVW
A,@IX +d @IX +d,A
A
CLRB
BBC
dir: 6 dir: 6,rel
MOV
CMP
ADDC SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
DEC
CALLV BC
A,R1
A,R1
A,R1
A,R1
R1,A
A,R1
A,R1
A,R1 R1,#d8 R1,#d8
dir: 1 dir: 1,rel
R1
R1
#1
CMP
@IX +d,#d8 @IX +d,#d8
9
MOV
MOV
CMP
ADDC SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
DEC
CALLV BNC
A,R0
A,R0
A,R0
A,R0
R0,A
A,R0
A,R0
A,R0 R0,#d8 R0,#d8
dir: 0 dir: 0,rel
R0
R0
#0
rel
OR
A,@IX +d
8
XOR
AND
A,@IX +d A,@IX +d
MOV
CMP
MOV
CMP
ADDC SUBC
MOV
XOR
AND
OR
CLRB
BBC
MOVW MOVW MOVW XCHW
A,@EP A,@EP A,@EP A,@EP @EP,A A,@EP A,@EP A,@EP @EP,#d8 @EP,#d8
dir: 7 dir: 7,rel A,@EP @EP,A EP,#d16
A,EP
MOV @IX
+d,A
7
SUBC
A,@IX +d
CLRB
BBC
MOVW MOVW MOVW XCHW
dir: 4 dir: 4,rel
A,ext
ext,A A,#d16
A,PC
MOV
A,@IX +d
ADDC
A,@IX +d
DAS
6
CMP
A,@IX +d
XOR
AND
OR
DAA
A,#d8
A,#d8
A,#d8
MOVW MOVW CLRB
BBC
INCW
DECW MOVW MOVW
CMPW ADDCW SUBCW XCHW XORW ANDW ORW
A
A
A, T
A
A
A
@A,T
A,@A
dir: 3 dir: 3,rel
EP
EP
EP,A
A,EP
A
A
SETC
4
A
CMP
PUSHW POPW MOV
JMP
CALL
MOVW CLRC
IX
addr16 addr16
IX
ext,A
PS,A
RORC
A
DIVU
3
CLRB
BBC
INCW
DECW JMP
MOVW
dir: 0 dir: 0,rel
A
A
@A
A,PC
A
ROLC
A
SETI
7
PUSHW POPW MOV
MOVW CLRI
A
A
A,ext
A,PS
6
9
5
8
4
2
A
RETI
3
MULU
RET
2
1
SWAP
1
NOP
0
0
H
MB89140 Series
■ INSTRUCTION MAP
MB89140 Series
■ MASK OPTIONS
No.
Part number
Parameter
MB89PV140 MB89PV140
-101
-102
MB89145V1
MB89146V1
MB89145V2
MB89146V2
MB89P147V1
MB89P147V2
Power-on reset
1
With power-on reset
Fixed to with power-on reset
Specify when ordering masking
Set with EPROM programmer
Fixed to with power-on reset
Specify when ordering masking
Set with EPROM programmer
Single clock
Specify when ordering masking
Set with EPROM programmer
Specify when ordering masking
Set with EPROM programmer
(specify by pin)
(specify by pin)
Without power-on reset
Reset pin output
2
With reset output
Without reset output
Clock mode selection
3
Single-clock mode
Dual clock
Dual-clock mode
Pull-up resistors
4
P14 to P17
Fixed to without pull-up resistor
P32 to P37
Pull-down resistors
5
P47 to P40
P57 to P50
Fixed to without pull-up resistor
Without pulldown resistor
All pins with
pull-down
resistor
Without pulldown resistor
All pins with
pull-down
resistor
P67 to P60
■ ORDERING INFORMATION
Part number
MB89145V1P-SH
MB89145V2P-SH
MB89146V1P-SH
MB89146V2P-SH
MB89P147V1P-SH
MB89P147V2P-SH
MB89145V1PF
MB89145V2PF
MB89146V1PF
MB89146V2PF
MB89P147V1PF
MB89P147V2PF
Package
Remarks
64-pin Plastic SH-DIP
(DIP-64P-M01)
64-pin Plastic QFP
(FPT-64P-M06)
MB89PV140C-101-ES-SH
MB89PV140C-102-ES-SH
64-pin Ceramic MDIP
(MDP-64C-P02)
MB89PV140CF-101-ES
MB89PV140CF-102-ES
64-pin Ceramic MQFP
(MQP-64C-P01)
47
MB89140 Series
■ PACKAGE DIMENSIONS
64-pin Plastic SH-DIP
(DIP-64P-M01)
+0.22
58.00 –0.55
+.008
2.283 –.022
INDEX-1
17.00±0.25
(.669±.010)
INDEX-2
5.65(.222)MAX
0.25±0.05
(.010±.002)
3.00(.118)MIN
+0.50
0.45±0.10
(.018±.004)
1.00 –0
+.020
.039 –0
0.51(.020)MIN
15°MAX
19.05(.750)
TYP
1.778±0.18
(.070±.007)
1.778(.070)
MAX
C
55.118(2.170)REF
1994 FUJITSU LIMITED D64001S-3C-4
Dimensions in mm (inches)
64-pin Plastic QFP
(FPT-64P-M06)
24.70±0.40(.972±.016)
3.35(.132)MAX
20.00±0.20(.787±.008)
51
0.05(.002)MIN
(STAND OFF)
33
52
32
14.00±0.20
(.551±.008)
18.70±0.40
(.736±.016)
12.00(.472)
REF
16.30±0.40
(.642±.016)
INDEX
64
20
"A"
LEAD No.
1
19
0.40±0.10
(.016±.004)
1.00(.0394)
TYP
0.15±0.05(.006±.002)
0.20(.008)
M
Details of "A" part
0.25(.010)
Details of "B" part
"B"
0.10(.004)
18.00(.709)REF
22.30±0.40(.878±.016)
C
48
1994 FUJITSU LIMITED F64013S-3C-2
0.30(.012)
0.18(.007)MAX
0.63(.025)MAX
0 10°
1.20±0.20
(.047±.008)
Dimensions in mm (inches)
MB89140 Series
64-pin Ceramic MDIP
(MDP-64C-P02)
0°~9°
56.90±0.64
(2.240±.025)
15.24(.600)
TYP
18.75±0.30
(.738±.012)
INDEX AREA
2.54±0.25
(.100±.010)
33.02(1.300)REF
0.25±0.05
(.010±.002)
1.27±0.25
(.050±.010)
10.16(.400)MAX
+0.13
0.46 –0.08
+.005
.018 –.003
55.12(2.170)REF
1.778±0.25
(.070±.010)
C
19.05±0.30
(.750±.012)
3.43±0.38
(.135±.015)
0.90±0.13
(.035±.005)
1994 FUJITSU LIMITED M64002SC-1-4
Dimensions in mm (inches)
64-pin Ceramic MQFP
(MQP-64C-P01)
18.70(.736)TYP
INDEX AREA
16.30±0.33
(.642±.013)
15.58±0.20
(.613±.008)
12.00(.472)TYP
+0.40
1.20 –0.20
+.016
.047 –.008
1.00±0.25
(.039±.010)
1.00±0.25
(.039±.010)
1.27±0.13
(.050±.005)
22.30±0.33
(.878±.013)
24.70(.972)
TYP
0.30(.012)
TYP
1.27±0.13
(.050±.005)
18.12±0.20
12.02(.473)
(.713±.008)
TYP
10.16(.400)
14.22(.560)
TYP
TYP
0.30(.012)TYP
7.62(.300)TYP
0.40±0.10
(.016±.004)
18.00(.709)
TYP
0.40±0.10
(.016±.004)
+0.40
1.20 –0.20
+.016
.047 –.008
9.48(.373)TYP
11.68(.460)TYP
0.50(.020)TYP
C
1994 FUJITSU LIMITED M64004SC-1-3
10.82(.426)
0.15±0.05 MAX
(.006±.002)
Dimensions in mm (inches)
49
MB89140 Series
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka
Nakahara-ku, Kawasaki-shi
Kanagawa 211-88, Japan
Tel: (044) 754-3753
Fax: (044) 754-3329
North and South America
FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804, U.S.A.
Tel: (408) 922-9000
Fax: (408) 432-9044/9045
Europe
FUJITSU MIKROELEKTRONIK GmbH
Am Siebenstein 6-10
63303 Dreieich-Buchschlag
Germany
Tel: (06103) 690-0
Fax: (06103) 690-122
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE. LIMITED
No. 51 Bras Basah Road,
Plaza By The Park,
#06-04 to #06-07
Singapore 189554
Tel: 336-1600
Fax: 336-1609
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F9603
 FUJITSU LIMITED Printed in Japan
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