NGD15N41CL, NGD15N41ACL, NGB15N41CL, NGB15N41ACL, NGP15N41CL, NGP15N41ACL Ignition IGBT 15 A, 410 V http://onsemi.com 15 AMPS 410 VOLTS VCE(on) 3 2.1 V @ IC = 10 A, VGE . 4.5 V N−Channel DPAK, D2PAK and TO−220 This Logic Level Insulated Gate Bipolar Transistor (IGBT) features monolithic circuitry integrating ESD and Over−Voltage clamped protection for use in inductive coil drivers applications. Primary uses include Ignition, Direct Fuel Injection, or wherever high voltage and high current switching is required. C Features • • • • • • • • • • • Ideal for Coil−on−Plug Applications DPAK Package Offers Smaller Footprint and Increased Board Space Gate−Emitter ESD Protection Temperature Compensated Gate−Collector Voltage Clamp Limits Stress Applied to Load Integrated ESD Diode Protection New Design Increases Unclamped Inductive Switching (UIS) Energy Per Area Low Threshold Voltage to Interface Power Loads to Logic or Microprocessor Devices Low Saturation Voltage High Pulsed Current Capability Optional Gate Resistor (RG) and Gate−Emitter Resistor (RGE) These are Pb−Free Devices RG G RGE E 4 1 2 1 2 Symbol Value Unit VCES 440 VDC Collector−Gate Voltage VCER 440 VDC Gate−Emitter Voltage VGE 15 VDC IC 15 50 ADC AAC ESD (Human Body Model) R = 1500 Ω, C = 100 pF ESD ESD (Machine Model) R = 0 Ω, C = 200 pF ESD 800 V PD 107 0.71 Watts W/°C −55 to +175 °C Total Power Dissipation @ TC = 25°C Derate above 25°C Operating and Storage Temperature Range December, 2011 − Rev. 8 TO−220AB CASE 221A STYLE 9 1 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. © Semiconductor Components Industries, LLC, 2011 4 kV 8.0 TJ, Tstg D2PAK CASE 418B STYLE 4 3 Collector−Emitter Voltage Collector Current−Continuous @ TC = 25°C − Pulsed 3 4 MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Rating DPAK CASE 369C STYLE 2 1 2 3 ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet. DEVICE MARKING INFORMATION See general marking information in the device marking section on page 8 of this data sheet. Publication Order Number: NGD15N41CL/D NGD15N41CL, NGD15N41ACL, NGB15N41CL, NGB15N41ACL, NGP15N41CL, NGP15N41ACL UNCLAMPED COLLECTOR−TO−EMITTER AVALANCHE CHARACTERISTICS (−55° ≤ TJ ≤ 175°C) Symbol Characteristic Single Pulse Collector−to−Emitter Avalanche Energy VCC = 50 V, VGE = 5.0 V, Pk IL = 16.6 A, L = 1.8 mH, Starting TJ = 25°C VCC = 50 V, VGE = 5.0 V, Pk IL = 15 A, L = 1.8 mH, Starting TJ = 125°C Value EAS Unit mJ 250 200 THERMAL CHARACTERISTICS Characteristic Symbol Value Unit RθJC 1.4 °C/W DPAK (Note 1) RθJA 100 D2PAK RθJA 50 RθJA 62.5 TL 275 Thermal Resistance, Junction to Case Thermal Resistance, Junction to Ambient (Note 1) TO−220 Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 5 seconds °C ELECTRICAL CHARACTERISTICS Characteristic Symbol Test Conditions Temperature Min Typ Max Unit BVCES IC = 2.0 mA TJ = −40°C to 150°C 380 410 440 VDC IC = 10 mA TJ = −40°C to 150°C 380 410 440 TJ = 25°C − 2.0 20 TJ = 150°C − 10 40* TJ = −40°C − 1.0 10 TJ = 25°C − 0.7 2.0 TJ = 150°C − 12 25* TJ = −40°C − 0.1 1.0 TJ = 25°C 27 33 37 TJ = 150°C 30 36 40 TJ = −40°C 25 31 35 OFF CHARACTERISTICS Collector−Emitter Clamp Voltage Zero Gate Voltage Collector Current Reverse Collector−Emitter Leakage Current Reverse Collector−Emitter Clamp Voltage Gate−Emitter Clamp Voltage ICES VCE = 350 V, VGE = 0 V IECS VCE = −24 V BVCES(R) IC = −75 mA μADC mA VDC BVGES IG = 5.0 mA TJ = −40°C to 150°C 11 13 15 VDC IGES VGE = 10 V TJ = −40°C to 150°C 384 640 1000 μADC Gate Resistor RG − TJ = −40°C to 150°C − 70 − Ω Gate Emitter Resistor RGE − TJ = −40°C to 150°C 10 16 26 kΩ VDC Gate−Emitter Leakage Current ON CHARACTERISTICS (Note 2) Gate Threshold Voltage Threshold Temperature Coefficient (Negative) VGE(th) TJ = 25°C 1.1 1.4 1.9 IC = 1.0 mA, VGE = VCE TJ = 150°C 0.75 1.0 1.4 TJ = −40°C 1.2 1.6 2.1* − − − 3.4 − − 1. When surface mounted to an FR4 board using the minimum recommended pad size. 2. Pulse Test: Pulse Width v 300 μS, Duty Cycle v 2%. *Maximum Value of Characteristic across Temperature Range. http://onsemi.com 2 mV/°C NGD15N41CL, NGD15N41ACL, NGB15N41CL, NGB15N41ACL, NGP15N41CL, NGP15N41ACL ELECTRICAL CHARACTERISTICS (continued) Characteristic Symbol Test Conditions Temperature Min Typ Max Unit TJ = 25°C 1.0 1.6 1.8 VDC TJ = 150°C 0.9 1.5 1.8 TJ = −40°C 1.1 1.65 1.9* TJ = 25°C 1.3 1.8 2.0* TJ = 150°C 1.2 1.7 1.9 TJ = −40°C 1.4 1.8 2.0* TJ = 25°C 1.4 2.0 2.2 TJ = 150°C 1.5 2.0 2.3* TJ = −40°C 1.4 2.0 2.2 TJ = 25°C 1.3 1.9 2.1 TJ = 150°C 1.3 1.9 2.1 TJ = −40°C 1.4 1.95 2.1* VCE = 5.0 V, IC = 6.0 A TJ = −40°C to 150°C 8.0 15 25 Mhos 400 650 1000 pF VCC = 25 V, VGE = 0 V f = 1.0 MHz TJ = −40°C to 150°C 30 55 100 3.0 4.5 8.0 TJ = 25°C − 4.0 10 TJ = 150°C − 4.5 10 TJ = 25°C − 6.0 12 TJ = 150°C − 10 12 TJ = 25°C − 3.0 10 TJ = 150°C − 3.5 10 TJ = 25°C − 8.0 15 TJ = 150°C − 12 15 TJ = 25°C − 0.7 4.0 TJ = 150°C − 0.7 4.0 TJ = 25°C − 4.0 7.0 TJ = 150°C − 5.0 7.0 ON CHARACTERISTICS (continued) (Note 3) Collector−to−Emitter On−Voltage VCE(on) IC = 6.0 A, VGE = 4.0 V IC = 8.0 A, VGE = 4.0 V IC = 10 A, VGE = 4.0 V IC = 10 A, VGE = 4.5 V Forward Transconductance gfs DYNAMIC CHARACTERISTICS Input Capacitance CISS Output Capacitance COSS Transfer Capacitance CRSS SWITCHING CHARACTERISTICS Turn−Off Delay Time (Inductive) Fall Time (Inductive) Turn−Off Delay Time (Resistive) Fall Time (Resistive) Turn−On Delay Time Rise Time td(off) VCC = 300 V, IC = 6.5 A RG = 1.0 kΩ, L = 300 μH tf VCC = 300 V, IC = 6.5 A RG = 1.0 kΩ, L = 300 μH td(off) VCC = 300 V, IC = 6.5 A RG = 1.0 kΩ, RL = 46 Ω, tf VCC = 300 V, IC = 6.5 A RG = 1.0 kΩ, RL = 46 Ω, td(on) VCC = 10 V, IC = 6.5 A RG = 1.0 kΩ, RL = 1.5 Ω tr VCC = 10 V, IC = 6.5 A RG = 1.0 kΩ, RL = 1.5 Ω 3. Pulse Test: Pulse Width v 300 μS, Duty Cycle v 2%. *Maximum Value of Characteristic across Temperature Range. http://onsemi.com 3 μSec μSec μSec NGD15N41CL, NGD15N41ACL, NGB15N41CL, NGB15N41ACL, NGP15N41CL, NGP15N41ACL TYPICAL ELECTRICAL CHARACTERISTICS (unless otherwise noted) 60 VGE = 10 V IC, COLLECTOR CURRENT (AMPS) IC, COLLECTOR CURRENT (AMPS) 60 5V 50 4.5 V 40 4V 30 TJ = 25°C 3.5 V 20 3V 10 0 2.5 V 0 1 2 3 4 5 6 7 4V 30 3.5 V TJ = −40°C 20 3V 10 2.5 V 0 2 1 4 3 6 5 7 8 VCE, COLLECTOR TO EMITTER VOLTAGE (VOLTS) VCE, COLLECTOR TO EMITTER VOLTAGE (VOLTS) Figure 1. Output Characteristics Figure 2. Output Characteristics 30 IC, COLLECTOR CURRENT (AMPS) IC, COLLECTOR CURRENT (AMPS) 5V 40 VGE = 10 V 50 5V 4.5 V TJ = 150°C 40 4V 3.5 V 30 3V 20 2.5 V 10 0 1 2 3 4 5 6 7 VCE = 10 V 25 20 15 10 5 0 8 TJ = 25°C TJ = 150°C 0 VCE, COLLECTOR TO EMITTER VOLTAGE (VOLTS) COLLECTOR TO EMITTER VOLTAGE (VOLTS) 3.5 IC = 25 A 3.0 IC = 20 A 2.5 IC = 15 A 2.0 IC = 10 A 1.5 IC = 5 A 1.0 0.5 0.0 −50 −25 0 25 50 75 100 1 1.5 2 2.5 3 3.5 4 4.5 5 Figure 4. Transfer Characteristics 4.0 VGE = 5 V 0.5 TJ = −40°C VGE, GATE TO EMITTER VOLTAGE (VOLTS) Figure 3. Output Characteristics VCE, COLLECTOR TO EMITTER VOLTAGE (VOLTS) 4.5 V 50 0 8 60 0 VGE = 10 V 125 150 3 TJ = 25°C 2.5 IC = 15 A IC = 10 A 2 IC = 5 A 1.5 1 0.5 0 3 4 TJ, JUNCTION TEMPERATURE (°C) 5 6 7 8 9 GATE TO EMITTER VOLTAGE (VOLTS) Figure 5. Collector−to−Emitter Saturation Voltage versus Junction Temperature Figure 6. Collector−to−Emitter Voltage versus Gate−to−Emitter Voltage http://onsemi.com 4 10 10000 3 TJ = 150°C IC = 15 A 2.5 IC = 10 A 2 IC = 5 A 1.5 1 0.5 0 3 4 5 6 7 8 9 Coss 10 Crss 1 0 20 40 60 80 100 120 140 160 180 200 GATE TO EMITTER VOLTAGE (VOLTS) VCE, COLLECTOR TO EMITTER VOLTAGE (VOLTS) Figure 7. Collector−to−Emitter Voltage versus Gate−to−Emitter Voltage Figure 8. Capacitance Variation 30 1.8 Mean Mean + 4 σ IL, LATCH CURRENT (AMPS) THRESHOLD VOLTAGE (VOLTS) 100 0 10 2 1.6 1.4 Mean − 4 σ 1.2 1 0.8 0.6 0.4 0.2 0 −50 −30 −10 10 30 50 70 90 VCC = 50 V VGE = 5 V RG = 1000 Ω 25 20 L = 2 mH L = 3 mH 15 10 L = 6 mH 5 0 −50 −25 110 130 150 0 25 50 75 100 125 150 TEMPERATURE (°C) TEMPERATURE (°C) Figure 9. Gate Threshold Voltage versus Temperature Figure 10. Minimum Open Secondary Latch Current versus Temperature 175 12 30 VCC = 50 V VGE = 5 V RG = 1000 Ω 20 10 SWITCHING TIME (μs) 25 IL, LATCH CURRENT (AMPS) Ciss 1000 C, CAPACITANCE (pF) COLLECTOR TO EMITTER VOLTAGE (VOLTS) NGD15N41CL, NGD15N41ACL, NGB15N41CL, NGB15N41ACL, NGP15N41CL, NGP15N41ACL L = 2 mH 15 L = 3 mH 10 L = 6 mH 8 VCC = 300 V VGE = 5 V RG = 1000 Ω IC = 10 A L = 300 μH tf 6 td(off) 4 2 5 0 −50 −25 0 25 50 75 100 125 150 0 −50 −30 −10 175 10 30 50 70 90 110 130 150 TEMPERATURE (°C) TEMPERATURE (°C) Figure 11. Typical Open Secondary Latch Current versus Temperature Figure 12. Inductive Switching Fall Time versus Temperature http://onsemi.com 5 NGD15N41CL, NGD15N41ACL, NGB15N41CL, NGB15N41ACL, NGP15N41CL, NGP15N41ACL R(t), TRANSIENT THERMAL RESISTANCE (°C/Watt) 10 Duty Cycle = 0.5 0.2 1 0.1 0.05 0.02 0.1 0.01 D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT T1 P(pk) t1 Single Pulse t2 TJ(pk) − TA = P(pk) RθJA(t) RθJC ≅ R(t) for t ≤ 0.2 s DUTY CYCLE, D = t1/t2 0.01 0.00001 0.0001 0.001 0.1 0.01 1 10 t,TIME (S) Figure 13. Transient Thermal Resistance (Non−normalized Junction−to−Ambient mounted on fixture in Figure 14) 1.5″ 4″ 4″ 0.125″ 4″ Figure 14. Test Fixture for Transient Thermal Curve (48 square inches of 1/8, thick aluminum) http://onsemi.com 6 100 1000 NGD15N41CL, NGD15N41ACL, NGB15N41CL, NGB15N41ACL, NGP15N41CL, NGP15N41ACL 100 COLLECTOR CURRENT (AMPS) COLLECTOR CURRENT (AMPS) 100 DC 10 100 μs 1 ms 1 10 ms 100 ms 0.1 0.01 1 10 100 100 μs 0.1 1 ms 10 ms 100 ms 10 100 1000 COLLECTOR−EMITTER VOLTAGE (VOLTS) Figure 15. Single Pulse Safe Operating Area (Mounted on an Infinite Heatsink at TA = 255C) Figure 16. Single Pulse Safe Operating Area (Mounted on an Infinite Heatsink at TA = 1255C) 100 COLLECTOR CURRENT (AMPS) COLLECTOR CURRENT (AMPS) 1 COLLECTOR−EMITTER VOLTAGE (VOLTS) t1 = 1 ms, D = 0.05 t1 = 2 ms, D = 0.10 10 t1 = 3 ms, D = 0.30 1 I(pk) t1 t2 DUTY CYCLE, D = t1/t2 0.01 1 DC 0.01 1 1000 100 0.1 10 10 100 t1 = 1 ms, D = 0.05 t1 = 3 ms, D = 0.30 1 I(pk) t1 0.1 0.01 1 1000 t1 = 2 ms, D = 0.10 10 t2 DUTY CYCLE, D = t1/t2 10 100 1000 COLLECTOR−EMITTER VOLTAGE (VOLTS) COLLECTOR−EMITTER VOLTAGE (VOLTS) Figure 17. Pulse Train Safe Operating Area (Mounted on an Infinite Heatsink at TC = 255C) Figure 18. Pulse Train Safe Operating Area (Mounted on an Infinite Heatsink at TC = 1255C) http://onsemi.com 7 NGD15N41CL, NGD15N41ACL, NGB15N41CL, NGB15N41ACL, NGP15N41CL, NGP15N41ACL ORDERING INFORMATION Device Package Type Shipping† DPAK (Pb−Free) 2500/Tape & Reel D2PAK (Pb−Free) 800/Tape & Reel TO−220 (Pb−Free) 50 Units/Rail NGD15N41CLT4G NGD15N41ACLT4G NGB15N41CLT4G NGB15N41ACLT4G NGP15N41CLG NGP15N41ACLG †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. MARKING DIAGRAMS D2PAK CASE 418B STYLE 4 DPAK CASE 369C STYLE 7 3 Emitter 4 Collector 4 Collector 1 Gate 2 Collector TO−220AB CASE 221A STYLE 9 YWW GD 15N41G NGB 15N41CLG AYWW 4 Collector 1 Gate A Y WW G 2 Collector NGP 15N41CLG AYWW 3 Emitter = Assembly Location = Year = Work Week = Pb−Free Device http://onsemi.com 8 1 Gate 3 Emitter 2 Collector NGD15N41CL, NGD15N41ACL, NGB15N41CL, NGB15N41ACL, NGP15N41CL, NGP15N41ACL PACKAGE DIMENSIONS DPAK (SINGLE GAUGE) CASE 369C−01 ISSUE D A E b3 c2 B Z D 1 L4 A 4 L3 b2 e 2 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCHES. 3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.006 INCHES PER SIDE. 5. DIMENSIONS D AND E ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY. 6. DATUMS A AND B ARE DETERMINED AT DATUM PLANE H. C H DETAIL A 3 c b 0.005 (0.13) M H C L2 GAUGE PLANE C L SEATING PLANE A1 L1 DETAIL A ROTATED 905 CW 2.58 0.102 5.80 0.228 3.00 0.118 1.60 0.063 INCHES MIN MAX 0.086 0.094 0.000 0.005 0.025 0.035 0.030 0.045 0.180 0.215 0.018 0.024 0.018 0.024 0.235 0.245 0.250 0.265 0.090 BSC 0.370 0.410 0.055 0.070 0.108 REF 0.020 BSC 0.035 0.050 −−− 0.040 0.155 −−− STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN SOLDERING FOOTPRINT* 6.20 0.244 DIM A A1 b b2 b3 c c2 D E e H L L1 L2 L3 L4 Z 6.17 0.243 SCALE 3:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 9 MILLIMETERS MIN MAX 2.18 2.38 0.00 0.13 0.63 0.89 0.76 1.14 4.57 5.46 0.46 0.61 0.46 0.61 5.97 6.22 6.35 6.73 2.29 BSC 9.40 10.41 1.40 1.78 2.74 REF 0.51 BSC 0.89 1.27 −−− 1.01 3.93 −−− NGD15N41CL, NGD15N41ACL, NGB15N41CL, NGB15N41ACL, NGP15N41CL, NGP15N41ACL PACKAGE DIMENSIONS D2PAK CASE 418B−04 ISSUE K NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. 418B−01 THRU 418B−03 OBSOLETE, NEW STANDARD 418B−04. C E V W −B− 4 1 2 A S 3 −T− SEATING PLANE K J G D 3 PL 0.13 (0.005) VARIABLE CONFIGURATION ZONE W H M T B M N R P L M L M F F F VIEW W−W 1 VIEW W−W 2 VIEW W−W 3 SOLDERING FOOTPRINT* 10.49 8.38 16.155 2X 3.504 2X 1.016 5.080 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 10 INCHES MIN MAX 0.340 0.380 0.380 0.405 0.160 0.190 0.020 0.035 0.045 0.055 0.310 0.350 0.100 BSC 0.080 0.110 0.018 0.025 0.090 0.110 0.052 0.072 0.280 0.320 0.197 REF 0.079 REF 0.039 REF 0.575 0.625 0.045 0.055 STYLE 4: PIN 1. 2. 3. 4. U L M DIM A B C D E F G H J K L M N P R S V GATE COLLECTOR EMITTER COLLECTOR MILLIMETERS MIN MAX 8.64 9.65 9.65 10.29 4.06 4.83 0.51 0.89 1.14 1.40 7.87 8.89 2.54 BSC 2.03 2.79 0.46 0.64 2.29 2.79 1.32 1.83 7.11 8.13 5.00 REF 2.00 REF 0.99 REF 14.60 15.88 1.14 1.40 NGD15N41CL, NGD15N41ACL, NGB15N41CL, NGB15N41ACL, NGP15N41CL, NGP15N41ACL PACKAGE DIMENSIONS TO−220 CASE 221A−09 ISSUE AF −T− B F T SEATING PLANE C S 4 DIM A B C D F G H J K L N Q R S T U V Z A Q U 1 2 3 H K Z L R V NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION Z DEFINES A ZONE WHERE ALL BODY AND LEAD IRREGULARITIES ARE ALLOWED. J G D N INCHES MIN MAX 0.570 0.620 0.380 0.405 0.160 0.190 0.025 0.035 0.142 0.161 0.095 0.105 0.110 0.155 0.014 0.025 0.500 0.562 0.045 0.060 0.190 0.210 0.100 0.120 0.080 0.110 0.045 0.055 0.235 0.255 0.000 0.050 0.045 ----0.080 STYLE 9: PIN 1. 2. 3. 4. MILLIMETERS MIN MAX 14.48 15.75 9.66 10.28 4.07 4.82 0.64 0.88 3.61 4.09 2.42 2.66 2.80 3.93 0.36 0.64 12.70 14.27 1.15 1.52 4.83 5.33 2.54 3.04 2.04 2.79 1.15 1.39 5.97 6.47 0.00 1.27 1.15 ----2.04 GATE COLLECTOR EMITTER COLLECTOR ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. 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