AD OP497FS Precision picoampere input current quad operational amplifier Datasheet

Precision Picoampere Input Current
Quad Operational Amplifier
OP497
FEATURES
PIN CONNECTIONS
OUT A
1
16
OUT D
–IN A
2
15
–IN D
+IN A
3
14
+IN D
V+
4
13
V–
+IN B
5
12
+IN C
–IN B
6
11
–IN C
OUT B
7
10
OUT C
NC
8
9
NC
OP497
00309-001
Low offset voltage: 75 μV maximum
Low offset voltage drift: 1.0 μV/°C maximum
Very low bias current
25°C: 150 pA maximum
−40°C to +85°C: 300 pA maximum
Very high open-loop gain: 2000 V/mV minimum
Low supply current (per amplifier): 625 μA maximum
Operates from ±2 V to ±20 V supplies
High common-mode rejection: 114 dB minimum
NC = NO CONNECT
Strain gage and bridge amplifiers
High stability thermocouple amplifiers
Instrumentation amplifiers
Photocurrent monitors
High gain linearity amplifiers
Long-term integrators/filters
Sample-and-hold amplifiers
Peak detectors
Logarithmic amplifiers
Battery-powered systems
Precision performance of the OP497 includes very low offset
(<50 μV) and low drift (<0.5 μV/°C). Open-loop gain exceeds
2000 V/mV ensuring high linearity in every application. Errors
due to common-mode signals are eliminated by its commonmode rejection of >120 dB. The OP497 has a power supply
rejection of >120 dB which minimizes offset voltage changes
experienced in battery-powered systems. The supply current
of the OP497 is <625 μA per amplifier, and it can operate with
supply voltages as low as ±2 V.
The OP497 uses a superbeta input stage with bias current
cancellation to maintain picoamp bias currents at all temperatures.
This is in contrast to FET input op amps whose bias currents
start in the picoamp range at 25°C but double for every 10°C
rise in temperature to reach the nanoamp range above 85°C.
The input bias current of the OP497 is <100 pA at 25°C.
14
OUT D
2
13
–IN D
+IN A
3
12
+IN D
V+
4
11
V–
+IN B
5
10
+IN C
–IN B
6
9
–IN C
OUT B
7
8
OUT C
OP497
Figure 2. 14-Lead PDIP (N-14)
VS = ±15V
VCM = 0V
100
–IB
+IB
IOS
10
–75
–50
–25
0
25
50
75
100
TEMPERATURE (°C)
125
00309-003
The OP497 is a quad op amp with precision performance in
the space-saving, industry standard 16-lead SOlC package.
Its combination of exceptional precision with low power and
extremely low input bias current makes the quad OP497 useful
in a wide variety of applications.
1
–IN A
1k
INPUT CURRENT (pA)
GENERAL DESCRIPTION
OUT A
00309-002
Figure 1. 16-Lead Wide Body SOIC (RW-16)
APPLICATIONS
Figure 3. Input Bias, Offset Current vs. Temperature
Combining precision, low power, and low bias current, the OP497
is ideal for a number of applications, including instrumentation
amplifiers, log amplifiers, photodiode preamplifiers, and longterm integrators. For a single device, see the OP97 data sheet,
and for a dual device, see the OP297 data sheet.
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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Tel: 781.329.4700
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Fax: 781.461.3113 ©1991–2009 Analog Devices, Inc. All rights reserved.
OP497* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
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• OP497 Material Declaration
• PCN-PDN Information
DOCUMENTATION
• Quality And Reliability
Application Notes
• Symbols and Footprints
• AN-649: Using the Analog Devices Active Filter Design
Tool
DISCUSSIONS
Data Sheet
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• OP497: Military Data Sheet
• OP497: Precision Picoampere Input Current Quad
Operational Amplifier Data Sheet
TOOLS AND SIMULATIONS
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number.
• OP497 SPICE Macro-Model
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OP497
TABLE OF CONTENTS
Features .............................................................................................. 1
AC Performance ......................................................................... 10
Applications ....................................................................................... 1
Guarding And Shielding ........................................................... 11
General Description ......................................................................... 1
Open-Loop Gain Linearity ....................................................... 11
Pin Connections ............................................................................... 1
Applications Circuit ....................................................................... 12
Revision History ............................................................................... 2
Precision Absolute Value Amplifier ......................................... 12
Specifications..................................................................................... 3
Precision Current Pump ............................................................ 12
Absolute Maximum Ratings............................................................ 4
Precision Positive Peak Detector .............................................. 12
Thermal Resistance ...................................................................... 4
Simple Bridge Conditioning Amplifier ................................... 12
ESD Caution .................................................................................. 4
Nonlinear Circuits ...................................................................... 13
Typical Performance Characteristics ............................................. 5
Outline Dimensions ....................................................................... 14
Applications Information .............................................................. 10
Ordering Guide .......................................................................... 15
REVISION HISTORY
2/09—Rev. D to Rev. E
Deleted 14-Lead CERDIP............................................. Throughout
Changes to Features Section and General Description
Section ................................................................................................ 1
Delete Military Processed Devices Text, SMD Part Number,
ADI Part Number Table, and Dice Characteristics Figure ......... 3
Changes to Table 1 ............................................................................ 3
Changes to Absolute Maximum Ratings Section ......................... 4
Changes to Figure 12 ........................................................................ 6
Changes to Figure 18 and Figure 19 ............................................... 7
Changes to Figure 26 and Figure 28 ............................................... 8
Deleted OP497 Spice Macro-Model Section............................... 10
Changes to Applications Information Section............................ 10
Moved Figure 33 ............................................................................. 10
Deleted Table I. OP497 SPICE Net-List....................................... 11
Changes to Open-Loop Gain Linearity Section and
Figure 35 .......................................................................................... 11
Changes to Figure 40 ...................................................................... 13
Updated Outline Dimensions ....................................................... 14
Changes to Ordering Guide .......................................................... 15
11/01—Rev. C to Rev. D
Edits to Pin Connection Headings ..................................................1
Deleted Wafer Test Limits ................................................................3
Edits to Absolute Maximum Ratings ..............................................5
Edits to Outline Dimensions......................................................... 16
Edits to Ordering Guide ................................................................ 17
Rev. E | Page 2 of 16
OP497
SPECIFICATIONS
TA = 25°C, VS = ±15 V, unless otherwise noted.
Table 1.
Parameter
INPUT CHARACTERISTICS
Offset Voltage
Symbol
TCVOS
Average Input Bias Current Drift
Input Offset Current
TCIB
IOS
Average Input Offset Current Drift
Input Voltage Range 1
TCIOS
IVR
IB
Common-Mode Rejection
CMR
Large Signal Voltage Gain
AVO
Input Resistance Differential Mode
Input Resistance Common Mode
Input Capacitance
OUTPUT CHARACTERISTICS
Output Voltage Swing
RIN
RINCM
CIN
Short Circuit
POWER SUPPLY
Power Supply Rejection Ratio
ISC
Supply Voltage Range
DYNAMIC PERFORMANCE
Slew Rate
Gain Bandwidth Product
Channel Separation
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Current Noise Density
1
Min
VOS
Average Input Offset Voltage Drift
Long-Term Input Offset Voltage
Stability
Input Bias Current
Supply Current (per Amplifier)
Condition
VO
PSRR
ISY
VS
SR
GBW
CS
en p-p
en
in
−40°C ≤ +85°C
TMIN − TMAX
VCM = 0 V
−40° ≤ TA ≤ +85°C
−40° ≤ TA ≤ +85°C
VCM = 0 V
−40° ≤ TA ≤ +85°C
F Grade
Typ
Max
Min
G Grade
Typ
Max
Unit
40
70
0.4
0.1
75
150
1.0
80
120
0.6
0.1
150
250
1.5
μV
μV
μV/°C
μV/Month
40
60
0.3
30
50
0.3
±14
±13.5
135
120
4000
2000
30
500
3
150
200
60
80
0.3
50
80
0.4
±14
±13.5
135
120
4000
2000
30
500
3
200
300
pA
pA
pA/°C
pA
pA
pA/°C
V
V
dB
dB
V/mV
V/mV
MΩ
GΩ
pF
150
200
TMIN − TMAX
VCM = ±13 V
TMIN − TMAX
VO = ±10 V, RL = 2 kΩ
−40° ≤ TA ≤ +85°C
±13
±13
114
108
1500
800
RL = 2 kΩ
RL = 10 kΩ, TMIN − TMAX
RL = 10 kΩ
±13
±13
±13
±13.7
±14
±13.5
±25
±13
±13
±13
±13.7
±14
±13.5
±25
V
V
V
mA
VS = ±2 V to ±20 V
VS = ±2.5 V to ±20 V, TMIN − TMAX
No load
TMIN − TMAX
Operating range
TMIN − TMAX
114
108
135
120
525
580
114
108
135
120
525
750
dB
dB
μA
μA
V
V
±2
±2.5
0.05
VO = 20 V p-p, fO = 10 Hz
0.15
500
150
0.1 Hz to 10 Hz
en = 10 Hz
en = 1 kHz
in = 10 Hz
0.3
17
15
20
Guaranteed by CMR test.
Rev. E | Page 3 of 16
±13
±13
114
108
1200
800
200
300
625
750
±20
±20
580
±2
±2.5
0.05
625
±20
±20
0.15
500
150
V/μs
kHz
dB
0.3
17
15
20
μV/p-p
nV/√Hz
nV/√Hz
fA/√Hz
OP497
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 2.
Parameter
Supply Voltage
Input Voltage1
Differential Input Voltage1
Output Short-Circuit Duration
Storage Temperature Range
Operating Temperature Range
Junction Temperature Range
Lead Temperature (Soldering, 60 sec)
1
Rating
±20 V
20 V
40 V
Indefinite
−65°C to +150°C
−40°C to +85°C
−65°C to +150°C
300°C
θJA is specified for the worst-case mounting conditions, that is,
θJA is specified for a device in socket for the PDIP package, and
θJA is specified for a device soldered to the printed circuit board
(PCB) for the SOIC package.
Table 3.
Package Type
14-Lead PDIP (N-14)
16-Lead SOIC (RW-16)
θJC
33
23
Unit
°C/W
°C/W
–
For supply voltages less than ±20 V, the absolute maximum input voltage is
equal to the supply voltage.
1/4
V1 20V p-p @ 10Hz
OP497
+
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
θJA
76
92
2kΩ
50kΩ
50Ω
–
1/4
OP497
V2
+
V
CHANNEL SEPARATION = 20 log
1
( V2/10,000
)
Figure 4. Channel Separation Test Circuit
ESD CAUTION
Rev. E | Page 4 of 16
00309-004
Absolute maximum ratings apply to packaged parts.
OP497
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VS = ±15 V, unless otherwise noted.
50
50
VS = ±15V
VCM = 0V
TA = 25°C
VS = ±15V
VCM = 0V
40
PERCENTAGE OF UNITS
30
20
10
30
20
10
–80
–60
–40
–20
0
20
40
60
80
100
INPUT OFFSET VOLTAGE (µV)
0
00309-006
0
–100
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
TCVOS (µV/°C)
Figure 5. Typical Distribution of Input Offset Voltage
00309-009
PERCENTAGE OF UNITS
40
Figure 8. Typical Distribution of TCVOS
1k
50
VS = ±15V
VCM = 0V
TA = 25°C
VS = ±15V
VCM = 0V
INPUT CURRENT (pA)
PERCENTAGE OF UNITS
40
30
20
100
–IB
+IB
10
–40
–20
0
20
40
60
80
100
INPUT BIAS CURRENT (pA)
70
25
50
75
100
125
15
TA = 25°C
VS = ±15V
INPUT BIAS CURRENT (pA)
60
40
30
20
10
–IB
50
40
+IB
30
20
10
0
0
10
20
30
40
50
INPUT OFFSET CURRENT (pA)
60
0
–15
00309-008
PERCENTAGE OF UNITS
0
Figure 9. Input Bias, Offset Current vs. Temperature
TA = 25°C
VS = ±15V
VCM = 0V
50
–25
TEMPERATURE (°C)
Figure 6. Typical Distribution of Input Bias Current
60
–50
00309-010
–60
00309-007
–80
10
–75
00309-011
IOS
0
–100
–10
–5
0
5
10
COMMON-MODE VOLTAGE (V)
Figure 7. Typical Distribution of Input Offset Current
Figure 10. Input Bias Current vs. Common-Mode Voltage
Rev. E | Page 5 of 16
OP497
1k
±2
±1
100
CURRENT NOISE
VOLTAGE NOISE
10
0
3
4
5
TIME AFTER POWER APPLIED (Minutes)
1
1
10
Figure 14. Voltage Noise Density vs. Frequency
10
TA = 25°C
VS = ±2V TO ±20V
TOTAL NOISE DENSITY (µV/ Hz)
BALANCED OR UNBALANCED
VS = ±15V
VCM = 0V
1k
TA = 25°C
100
1k
10k
100k
1M
10M
SOURCE RESISTANCE (Ω)
00309-013
EFFECTIVE OFFSET VOLTAGE (µV)
10k
10
10
1k
FREQUENCY (Hz)
Figure 11. Input Offset Voltage Warm-Up Drift
100
100
00309-015
2
1
10Hz
1kHz
0.1
0.01
100
1k
10k
100k
1M
10M
SOURCE RESISTANCE (Ω)
Figure 12. Effective Offset Voltage vs. Source Resistance
Figure 15. Total Noise Density vs. Source Resistance
BALANCED OR UNBALANCED
VS = ±15V
VCM = 0V
NOISE VOLTAGE (100mV/DIV)
5mV
10
1
1s
100
90
10
0%
0.1
100
1k
10k
100k
1M
10M
SOURCE RESISTANCE (Ω)
100M
Figure 13. Effective TCVOS vs. Source Resistance
0
2
4
6
TIME (Seconds)
8
Figure 16. 0.1 Hz to 10 Hz Noise Voltage
Rev. E | Page 6 of 16
10
00309-017
VS = ±15V
TA = 25°C
00309-014
EFFECTIVE OFFSET VOLTAGE (µV/°C)
100
00309-016
1
00309-012
0
TA = 25°C
VS = ±2V TO ±20V
CURRENT NOISE DENSITY (fA/ Hz)
TA = 25°C
VS = ±15V
VCM = 0V
VOLTAGE NOISE DENSITY (nV/ Hz)
DEVIATION FROM FINAL VALUE (µV)
±3
OP497
100
GAIN
PHASE
90
135
20
0
180
–20
225
PHASE (Degrees)
60
120
100
80
60
40
20
10k
100k
1M
10M
FREQUENCY (Hz)
1
1k
10k
160
TA = 25°C
VS = ±15V
TA = 25°C
POWER SUPPLY REJECTION (dB)
140
TA = 125°C
1k
120
–PSR
100
+PSR
80
60
40
10
20
LOAD RESISTANCE (kΩ)
0
00309-019
1
1
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 18. Open-Loop Gain vs. Load Resistance
00309-022
20
VS = ±15V
VO = ±10V
100
1M
100k
Figure 20. Common-Mode Rejection vs. Frequency
10k
Figure 21. Power Supply Rejection vs. Frequency
35
RL = 2kΩ
VS = ±15V
VCN = ±10V
VS = ±15V
TA = 25°C
AVCL = +1
1% THD
RL = 10kΩ
30
OUTPUT SWING (V p-p)
TA = 125°C
TA = 25°C
25
20
15
10
5
–15
–10
–5
0
5
10
OUTPUT VOLTAGE (V)
15
0
100
00309-020
DIFFERENTIAL INPUT VOLTAGE (10µV/DIV)
100
FREQUENCY (Hz)
Figure 17. Open-Loop Gain and Phase vs. Frequency
OPEN-LOOP GAIN (V/mV)
10
00309-021
1k
00309-018
0
–40
100
1k
10k
FREQUENCY (Hz)
Figure 19. Open-Loop Gain Linearity
Figure 22. Maximum Output Swing vs. Frequency
Rev. E | Page 7 of 16
100k
00309-023
40
VS = ±15V
TA = 25°C
140
COMMON-MODE REJECTION (dB)
80
OPEN-LOOP GAIN (dB)
160
VS = ±15V
CL = 30pF
RL = 1MΩ
TA = 25°C
OP497
700
TA = 25°C
–1.0
–1.5
1.5
1.0
0.5
–VS
0
±5
±10
±20
±15
SUPPLY VOLTAGE (V)
400
300
0
±5
±10
±15
±20
SUPPLY VOLTAGE (V)
Figure 26. Supply Current (per Amplifier) vs. Supply Voltage
35
1k
VS = ±15V
TA = 25°C
30 AVCL = +1
1% THD
fO = 1kHz
25
VS = ±15V
TA = 25°C
100
IMPEDANCE (Ω)
20
15
10
1
AV = +1
0.1
10
1k
100
10k
LOAD RESISTANCE (Ω)
00309-025
0.001
0
10
1
1k
10k
100k
FREQUENCY (Hz)
Figure 27. Closed-Loop Output Impedance vs. Frequency
Figure 24. Maximum Output Swing vs. Load Resistance
35
+VS
TA = 25°C
RL = 10kΩ
30
SHORT-CIRCUIT CURRENT (mA)
–0.5
–1.0
–1.5
1.5
1.0
25
TA = 25°C
20
TA = 125°C
15
VS = ±15V
OUTPUT SHORTED
TO GROUND
–15
–20
TA = 125°C
–25
TA = 25°C
0.5
–30
–35
0
±5
±10
±15
SUPPLY VOLTAGE (V)
±20
00309-026
–VS
100
10
00309-028
0.01
5
0
1
2
3
4
TIME FROM OUTPUT SHORT (Minutes)
Figure 28. Short-Circuit Current vs. Time at Various Temperatures
Figure 25. Output Voltage Swing vs. Supply Voltage
Rev. E | Page 8 of 16
00309-029
OUTPUT SWING (V p-p)
25°C
500
200
Figure 23. Input Common-Mode Voltage Range vs. Supply Voltage
OUTPUT VOLTAGE SWING (V)
(REFERRED TO SUPPLY VOLTAGES)
125°C
600
00309-027
SUPPLY CURRENT (PER AMPLIFIER) (µA)
NO LOAD
–0.5
00309-024
INPUT COMMON-MODE VOLTAGE (V)
(REFERRED TO SUPPLY VOLTAGES)
+VS
OP497
70
VS = ±15V
TA = 25°C
60 AVCL = +1
VOUT = 100mV p-p
40
30
20
10
0
10
100
1k
LOAD CAPACITANCE (pF)
10k
00309-030
OVERSHOOT (%)
50
Figure 29. Small-Signal Overshoot vs. Load Capacitance
Rev. E | Page 9 of 16
OP497
APPLICATIONS INFORMATION
Extremely low bias current makes the OP497 attractive for use
in sample-and-hold amplifiers, peak detectors, and log amplifiers
that must operate over a wide temperature range. Balancing
input resistances is not necessary with the OP497. High source
resistance, even when unbalanced, only minimally degrades the
offset voltage and TCVOS.
100
90
The input pins of the OP497 are protected against large differential
voltage by back-to-back diodes and current-limiting resistors.
Common-mode voltages at the inputs are not restricted and
may vary over the full range of the supply voltages used.
The OP497 requires very little operating headroom about the
supply rails and is specified for operation with supplies as low as
±2 V. Typically, the common-mode range extends to within 1 V
of either rail. When using a 10 kΩ load, the output typically
swings to within 1 V of the rails.
10
20mV
00309-033
0%
5µs
Figure 31. Small Signal Transient Response (CLOAD = 1000 pF, AVCL = +1)
100
AC PERFORMANCE
90
10
0%
2V
00309-034
The ac characteristics of the OP497 are highly stable over its full
operating temperature range. Figure 30 shows the unity-gain
small signal response. Extremely tolerant of capacitive loading
on the output, the OP497 displays excellent response even with
1000 pF loads (see Figure 31).
50µs
Figure 32. Large Signal Transient Response (AVCL = +1)
100
90
20mV
5µs
00309-032
10
0%
Figure 30. Small Signal Transient Response (CLOAD = 100 pF, AVCL = +1)
V+
VOUT
2.5kΩ
–IN
2.5kΩ
V–
Figure 33. Simplified Schematic Showing One Amplifier
Rev. E | Page 10 of 16
00309-031
+IN
OP497
OPEN-LOOP GAIN LINEARITY
To maintain the extremely high input impedances of the OP497,
care must be taken in circuit board layout and manufacturing.
Board surfaces must be kept scrupulously clean and free of
moisture. Conformal coating is recommended to provide a
humidity barrier. Even a clean PCB can have 100 pA of leakage
currents between adjacent traces; therefore, use guard rings
around the inputs. Guard traces are operated at a voltage close
to that on the inputs, as shown in Figure 34, so that leakage
currents become minimal. In noninverting applications, connect
the guard ring to the common-mode voltage at the inverting
input. In inverting applications, both inputs remain at ground;
therefore, the guard trace should be grounded. Place guard
traces on both sides of the circuit board.
The OP497 has both an extremely high gain of 2000 V/mV
typical and constant gain linearity. This enhances the precision
of the OP497 and provides for very high accuracy in high
closed-loop gain applications. Figure 35 illustrates the typical
open-loop gain linearity of the OP497.
NONINVERTING AMPLIFIER
–
–
1/4
1/4
OP497
OP497
+
+
RL = 10kΩ
VS = ±15V
VCM = 0V
TA = 125°C
TA = 25°C
–15
–10
–5
0
5
10
OUTPUT VOLTAGE (V)
INVERTING AMPLIFIER
8
1/4
OP497
+
1
A
B
00309-035
–
Figure 35. Open-Loop Gain Linearity
PDIP
BOTTOM VIEW
Figure 34. Guard Ring Layout and Connections
Rev. E | Page 11 of 16
15
00309-036
UNITY-GAIN FOLLOWER
DIFFERENTIAL INPUT VOLTAGE (10µV/DIV)
GUARDING AND SHIELDING
OP497
APPLICATIONS CIRCUIT
PRECISION ABSOLUTE VALUE AMPLIFIER
PRECISION POSITIVE PEAK DETECTOR
The circuit in Figure 36 is a precision absolute value amplifier
with an input impedance of 30 MΩ. The high gain and low
TCVOS of the OP497 ensure accurate operation with microvolt
input signals. In this circuit, the input always appears as a commonmode signal to the op amps. The CMR of the OP497 exceeds
120 dB, yielding an error of less than 2 ppm.
In Figure 38, the CH must be of polystyrene, Teflon®, or
polyethylene to minimize dielectric absorption and leakage.
The droop rate is determined by the size of CH and the bias
current of the OP497.
1kΩ
2
6
1/4
R1
1kΩ
1/4
1
5
OP497
D2
1N4148
C3
0.1µF
R2
2kΩ
Maximum output current of the precision current pump shown
in Figure 37 is ±10 mA. Voltage compliance is ±10 V with ±15 V
supplies. Output impedance of the current transmitter exceeds
3 MΩ with linearity better than 16 bits.
R3
10kΩ
R2
10kΩ
+
SIMPLE BRIDGE CONDITIONING AMPLIFIER
Figure 39 shows a simple bridge conditioning amplifier using
the OP497. The transfer function is
⎛ ΔR ⎞ RF
⎟
VOUT = VREF ⎜
⎜ R + ΔR ⎟ R
⎝
⎠
The REF43 provides an accurate and stable reference voltage for
the bridge. To maintain the highest circuit accuracy, RF should
be 0.1% or better with a low temperature coefficient.
1/4
3
R5
10kΩ
1
OP497
2
IOUT
±10mA
REF43
8
R5
=
VIN
100Ω
= 10mA/V
RF
R
4
2
1/4
1/4
OP497
2.5V VREF
5
R + ΔR
R
3
OP497
1
VOUT
6
4
–15V
+5V
00309-038
7
6
R
+15V
VIN
–15V
+5V
2
R4
10kΩ
IOUT =
0.1µF
Figure 38. Precision Positive Peak Detector
PRECISION CURRENT PUMP
–
VOUT
RESET
0V < VOUT < 10V
Figure 36. Precision Absolute Value Amplifier
VIN
4
1kΩ
7
OP497
–15V
R1
10kΩ
+
6
8
1/4
Figure 37. Precision Current Pump
5
OP497
4
–5V
VOUT = VREF
7
( R ΔR
+ ΔR )
RF
R
00309-040
4
7
6
00309-037
VIN
3
8
1/4
OP497
1kΩ 5
CH
D1
1N4148
8
1/4
VIN
1kΩ 3
2N930
+
C1
30pF
R3
1kΩ
1
OP497
00309-039
C2
0.1µF
+
+15V
2
+15V
0.1µF
1N4148
Figure 39. Simple Bridge Conditioning Amplifier Using the OP497
Rev. E | Page 12 of 16
OP497
A similar analysis made for the square root amplifier circuit in
Figure 41 leads to its transfer function
NONLINEAR CIRCUITS
Due to its low input bias currents, the OP497 is an ideal log
amplifier in nonlinear circuits, such as the squaring amplifier
and square root amplifier circuits shown in Figure 40 and
Figure 41. Using the squaring amplifier circuit in Figure 40
as an example, the analysis begins by writing a voltage loop
equation across Transistors Q1, Q2, Q3, and Q4.
(V IN )(I REF )
VOUT = R2
R1
In these circuits, IREF is a function of the negative power supply. To
maintain accuracy, the negative supply should be well regulated.
For applications where very high accuracy is required, a voltage
reference can be used to set IREF. An important consideration for
the squaring circuit is that a sufficiently large input voltage can
force the output beyond the operating range of the output op
amp. Resistor R4 can be changed to scale IREF, or R1 and R2 can
be varied to keep the output voltage within the usable range.
⎛I ⎞
⎛ I ⎞
⎛I ⎞
⎛I ⎞
VT1In⎜⎜ IN ⎟⎟ + VT2In⎜⎜ IN ⎟⎟ = VT3In⎜⎜ I O ⎟⎟ + VT4In⎜⎜ REF ⎟⎟
⎝ IS4 ⎠
⎝ IS3 ⎠
⎝ IS2 ⎠
⎝ IS1 ⎠
All the transistors in the MAT04 are precisely matched and at
the same temperature; therefore, the IS and VT terms cancel,
giving
R2
33kΩ
2InIIN = InIO + InIREF = In (IO × IREF)
Exponentiating both sides of the thick equation lead to
(I IN )
IO
I REF
Op amp A2 forms a current-to-voltage converter which results
in VOUT = R2 × IO. Substituting (VIN/R1) for IIN and the previous
equation for IO yields
⎛ R2
VOUT = ⎜⎜
⎝ I REF
Q1 1
IIN
2
VIN
2
OP497
4
C2
100pF
14
8
Q2
Q3
9
R5
2kΩ
R3
50kΩ
1/4
IO
1
2
Q1
5
OP497
7
R1
133kΩ
IIN
A1
2
9
13
12
10
8
1/4
3
C1
100pF
Q3
IREF Q4
1
OP497
4
V–
R3
50kΩ
R4
50kΩ
–15V
00309-041
VIN
14
MAT04
8
–15V
Unadjusted accuracy of the square root circuit is better than
0.1% over an input voltage range of 100 mV to 10 V. For a similar
input voltage range, the accuracy of the squaring circuit is better
than 0.5%.
VOUT
Q2
5
V+
7
6
3
R4
50kΩ
Figure 41. Square Root Amplifier
R2
33kΩ
A2
12
1
V–
6
Q4
5 10
8
1/4
3
6
VOUT
IREF
MAT04
13
V+
R1
33kΩ
7
OP497
3
C1
100pF
7
⎞ ⎛ V IN ⎞ 2
⎟⎜
⎟ ⎝ R1 ⎟⎠
⎠
1/4
5
00309-042
IO =
C2
100pF
6
2
Figure 40. Squaring Amplifier
Rev. E | Page 13 of 16
OP497
OUTLINE DIMENSIONS
0.775 (19.69)
0.750 (19.05)
0.735 (18.67)
14
8
1
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
7
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.100 (2.54)
BSC
0.060 (1.52)
MAX
0.210 (5.33)
MAX
0.015
(0.38)
MIN
0.150 (3.81)
0.130 (3.30)
0.110 (2.79)
SEATING
PLANE
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
PLANE
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
0.430 (10.92)
MAX
0.005 (0.13)
MIN
0.070 (1.78)
0.050 (1.27)
0.045 (1.14)
070606-A
COMPLIANT TO JEDEC STANDARDS MS-001
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 42. 14-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body
(N-14)
Dimensions shown in inches and (millimeters)
10.50 (0.4134)
10.10 (0.3976)
9
16
7.60 (0.2992)
7.40 (0.2913)
8
1.27 (0.0500)
BSC
0.30 (0.0118)
0.10 (0.0039)
COPLANARITY
0.10
0.51 (0.0201)
0.31 (0.0122)
10.65 (0.4193)
10.00 (0.3937)
0.75 (0.0295)
0.25 (0.0098)
2.65 (0.1043)
2.35 (0.0925)
SEATING
PLANE
45°
8°
0°
0.33 (0.0130)
0.20 (0.0079)
COMPLIANT TO JEDEC STANDARDS MS-013- AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 43. 16-Lead Standard Small Outline Package [SOIC_W]
Wide Body
(RW-16)
Dimensions shown in millimeters and (inches)
Rev. E | Page 14 of 16
1.27 (0.0500)
0.40 (0.0157)
032707-B
1
OP497
ORDERING GUIDE
Model
OP497FP
OP497FPZ 1
OP497GP
OP497GPZ1
OP497FS
OP497FS-REEL
OP497FSZ1
OP497FSZ-REEL
OP497GS
OP497GS-REEL
OP497GSZ1
OP497GSZ-REEL1
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
14-Lead Plastic Dual In-Line Package [PDIP]
14-Lead Plastic Dual In-Line Package [PDIP]
14-Lead Plastic Dual In-Line Package [PDIP]
14-Lead Plastic Dual In-Line Package [PDIP]
16-Lead Standard Small Outline Package [SOIC_W]
16-Lead Standard Small Outline Package [SOIC_W]
16-Lead Standard Small Outline Package [SOIC_W]
16-Lead Standard Small Outline Package [SOIC_W]
16-Lead Standard Small Outline Package [SOIC_W
16-Lead Standard Small Outline Package [SOIC_W]
16-Lead Standard Small Outline Package [SOIC_W]
16-Lead Standard Small Outline Package [SOIC_W]
Z = RoHS Compliant Part.
Rev. E | Page 15 of 16
Package Option
N-14
N-14
N-14
N-14
RW-16
RW-16
RW-16
RW-16
RW-16
RW-16
RW-16
RW-16
OP497
NOTES
©1991–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00309-0-2/09(E)
Rev. E | Page 16 of 16