TI1 M430FR5989SRGCREP Mixed-signal microcontroller Datasheet

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MSP430FR5989-EP
SLASEC9 – APRIL 2017
MSP430FR5989-EP Mixed-Signal Microcontroller
1 Device Overview
1.1
Features
1
• Embedded Microcontroller
– 16-Bit RISC Architecture up to 16-MHz Clock
– Wide Supply Voltage Range (1.8 V to 3.6 V)
– 1.99-V Minimum Supply Voltage Required for
Power Up per SVSH Power-Up Level
• Optimized Ultra-Low-Power Modes
– Active Mode: Approximately 100 µA/MHz
– Standby (LPM3 With VLO): 0.4 µA (Typical)
– Real-Time Clock (RTC) (LPM3.5): 0.35 µA
(Typical) (1)
– Shutdown (LPM4.5): 0.02 µA (Typical)
• Ultra-Low-Power Ferroelectric RAM (FRAM)
– Up to 128KB of Nonvolatile Memory
– Ultra-Low-Power Writes
– Fast Write at 125 ns per Word (64KB in 4 ms)
– Unified Memory = Program + Data + Storage in
One Single Space
– 1015 Write Cycle Endurance
– Radiation Resistant and Nonmagnetic
• Intelligent Digital Peripherals
– 32-Bit Hardware Multiplier (MPY)
– Three-Channel Internal Direct Memory Access
(DMA)
– RTC With Calendar and Alarm Functions
– Five 16-Bit Timers With up to 7
Capture/Compare Registers Each
– 16-Bit and 32-Bit Cyclic Redundancy Checker
(CRC16, CRC32)
• High-Performance Analog
– 16-Channel Analog Comparator
– 12-Bit Analog-to-Digital Converter (ADC) With
Internal Reference and Sample-and-Hold and
up to 16 External Input Channels
– Integrated LCD Driver With Contrast Control for
up to 320 Segments
(1)
RTC is clocked by a 3.7-pF crystal.
1.2
•
•
•
• Multifunction Input/Output Ports
– All P1 to P10 and PJ Pins Support Capacitive
Touch Capability Without Need for External
Components
– Accessible Bit-, Byte- and Word-Wise (in Pairs)
– Edge-Selectable Wakeup From LPM on Ports
P1, P2, P3, and P4
– Programmable Pullup and Pulldown on All Ports
• Code Security
– True Random Number Seed for Random
Number Generation Algorithm
• Enhanced Serial Communication
– eUSCI_A0 and eUSCI_A1 Support:
– UART With Automatic Baud-Rate Detection
– IrDA Encode and Decode
– SPI
– eUSCI_B0 and eUSCI_B1 Support:
– I2C With Multiple-Slave Addressing
– SPI
– Hardware UART and I2C Bootloader (BSL)
• Flexible Clock System
– Fixed-Frequency DCO With 10 Selectable
Factory-Trimmed Frequencies
– Low-Power Low-Frequency Internal Clock
Source (VLO)
– 32-kHz Crystals (LFXT)
– High-Frequency Crystals (HFXT)
• Development Tools and Software
– Free Professional Development Environments
With EnergyTrace++™ Technology
– Experimenter and Development Kits
• Controlled Baseline
– One Assembly/Test Site, One Fabrication Site
• Enhanced Diminishing Manufacturing Sources
(DMS) Support
• Enhanced Product-Change Notification
• Qualification Pedigree
Applications
Water Meters
Heat Meters
Heat Cost Allocators
•
•
Portable Medical Meters
Data Logging
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
MSP430FR5989-EP
SLASEC9 – APRIL 2017
1.3
www.ti.com
Description
The MSP430™ ultra-low-power (ULP) FRAM platform combines uniquely embedded FRAM and a holistic
ultra-low-power system architecture, allowing innovators to increase performance at lowered energy
budgets. FRAM technology combines the speed, flexibility, and endurance of SRAM with the stability and
reliability of flash at much lower power.
The MSP430 ULP FRAM portfolio consists of a diverse set of devices that feature FRAM, the ULP 16-bit
MSP430 CPU, and intelligent peripherals targeted for various applications. The ULP architecture
showcases seven low-power modes, which are optimized to achieve extended battery life in energychallenged applications.
As a high reliability enhanced product, with controlled baseline, extended temperature range (–55°C to
95°C) and gold bond wires in the package, this device is uniquely suited to mission critical applications.
Device Information (1)
PART NUMBER
MSP430FR5989-EP
(1)
(2)
PACKAGE
BODY SIZE (2)
VQFN (64)
9.00 mm × 9.00 mm
For more information, see Section 8, Mechanical, Packaging, and Orderable Information.
The sizes shown here are approximations. For the package dimensions with tolerances, see the Mechanical Data in Section 8.
1.4
Functional Block Diagram
Figure 1-1 shows the functional block diagram.
P1.x/P2.x P3.x/P4.x P5.x/P6.x P7.x/P8.x
LFXIN,
HFXIN
2x8
LFXOUT,
HFXOUT
2x8
2x8
P9.x/P10.x
2x8
2x8
PJ.x
1x8
Capacitive Touch I/O 0, Capacitive Touch I/O 1
MCLK
Clock
System
Comp_E
ADC12_B
(up to 16
inputs)
(up to 16
std. inputs,
up to 8
diff. inputs)
SMCLK
DMA
Controller
3 Channel
Bus
Control
Logic
I/O Ports
P3, P4
2x8 I/Os
I/O Ports
P1, P2
2x8 I/Os
REF_A
ACLK
Voltage
Reference
I/O Port
P5, P6
2x8 I/Os
I/O Port
P7, P8
2x8 I/Os
I/O Port
P9, P10
1x8 I/Os
I/O Port
PJ
1x8 I/Os
PC
PD
PE
PB
PA
1x16 I/Os 1x16 I/Os 1x16 I/Os 1x16 I/Os 1x16 I/Os
MAB
MDB
CPUXV2
incl. 16
Registers
MPU
IP Encap
EEM
(S: 3 + 1)
EnergyTrace++
Technology
CRC16
FRAM
RAM
Up to
128KB
2KB
Power
Mgmt
LDO
SVS
Brownout
TA2
TA3
Timer_A
Timer_A
2 CC
Registers
(int. only)
5 CC
Registers
(int. only)
AES256
CRC-16CCITT
CRC32
CRC-32ISO-3309
MPY32
Security
Encryption,
Decryption
(128, 256)
Watchdog
MDB
JTAG
Interface
MAB
Spy-BiWire
TB0
TA0
TA1
Timer_B
Timer_A
Timer_A
7 CC
Registers
(int./ext.)
3 CC
Registers
(int./ext.)
3 CC
Registers
(int./ext.)
RTC_C
Calendar
and
Counter
Mode
eUSCI_A0
eUSCI_A1
eUSCI_B0
eUSCI_B1
(UART,
IrDA,
SPI)
(I C,
SPI)
2
Extended
Scan
Interface
LPM3.5 Domain
Copyright © 2016, Texas Instruments Incorporated
Figure 1-1. Functional Block Diagram – MSP430FR5989-EP
2
Device Overview
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SLASEC9 – APRIL 2017
Table of Contents
1
2
3
Device Overview ......................................... 1
Timing and Switching Characteristics ............... 22
Features .............................................. 1
1.2
Applications ........................................... 1
5.1
Overview
1.3
Description ............................................ 2
5.2
CPU
1.4
Functional Block Diagram ............................ 2
5.3
Revision History ......................................... 4
Terminal Configuration and Functions .............. 5
5.4
.......................................... 5
3.2
Signal Descriptions ................................... 6
3.3
Pin Multiplexing ..................................... 12
3.4
Connection of Unused Pins ......................... 12
Specifications ........................................... 13
4.1
Absolute Maximum Ratings ......................... 13
4.2
ESD Ratings ........................................ 13
4.3
Recommended Operating Conditions ............... 13
5.6
4.4
3.1
4
4.13
1.1
4.5
4.6
4.7
4.8
4.9
4.10
4.11
4.12
5
Thermal Resistance Characteristics
................
14
Memory Protection Unit Including IP Encapsulation 65
5.11
Peripherals
5.12
Device Descriptors (TLV) .......................... 113
5.13
Memory
5.14
Identification........................................ 134
5.8
6
7
18
19
20
21
8
..........................................
............................................
57
57
58
61
64
64
65
65
65
66
116
Applications, Implementation, and Layout ...... 135
6.1
6.2
16
22
5.10
5.7
15
15
5.9
............................................
.................................................
Operating Modes ....................................
Interrupt Vector Table and Signatures ..............
Bootloader (BSL) ....................................
JTAG Operation .....................................
FRAM................................................
RAM .................................................
Tiny RAM ............................................
5.5
Pin Diagram
Active Mode Supply Current Into VCC Excluding
External Current .....................................
Typical Characteristics, Active Mode Supply
Currents .............................................
Low-Power Mode (LPM0, LPM1) Supply Currents
Into VCC Excluding External Current ................
Low-Power Mode (LPM2, LPM3, LPM4) Supply
Currents (Into VCC) Excluding External Current ....
Low-Power Mode With LCD Supply Currents (Into
VCC) Excluding External Current ....................
Low-Power Mode LPMx.5 Supply Currents (Into
VCC) Excluding External Current ....................
Typical Characteristics, Low-Power Mode Supply
Currents .............................................
Typical Characteristics, Current Consumption per
Module ..............................................
Detailed Description ................................... 57
Device Connection and Layout Fundamentals .... 135
Peripheral- and Interface-Specific Design
Information ......................................... 139
Device and Documentation Support .............. 143
7.1
Device and Development Tool Nomenclature ..... 143
7.2
Tools and Software ................................ 145
7.3
Documentation Support ............................ 147
7.4
Community Resources............................. 148
7.5
Trademarks ........................................ 148
7.6
Electrostatic Discharge Caution
7.7
Export Control Notice .............................. 148
7.8
Glossary............................................ 149
...................
148
Mechanical, Packaging, and Orderable
Information ............................................. 149
Table of Contents
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SLASEC9 – APRIL 2017
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2 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
4
DATE
REVISION
NOTES
April 2017
*
Initial release.
Revision History
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3 Terminal Configuration and Functions
3.1
Pin Diagram
ESIDVSS
ESICI
ESICOM
AVCC1
AVSS3
PJ.7/HFXOUT
PJ.6/HFXIN
AVSS1
PJ.4/LFXIN
PJ.5/LFXOUT
AVSS2
P4.0/UCB1SIMO/UCB1SDA/MCLK
P4.1/UCB1SOMI/UCB1SCL/ACLK
DVSS3
DVCC3
P4.2/UCA0SIMO/UCA0TXD/UCB1CLK
Figure 3-1 shows the pinout of the 64-pin RGC package.
6
43
P9.3/ESICH3/ESITEST3/A11/C11
P2.5/TB0.4
7
42
P9.2/ESICH2/ESITEST2/A10/C10
P2.6/TB0.5/ESIC1OUT
8
41
P9.1/ESICH1/ESITEST1/A9/C9
P2.7/TB0.6/ESIC2OUT
9
40
P9.0/ESICH0/ESITEST0/A8/C8
P5.0/TA1.1/MCLK
10
39
P1.0/TA0.1/DMAE0/RTCCLK/A0/C0/VREF-/VeREF-
P5.1/TA1.2
11
38
P1.1/TA0.2/TA1CLK/COUT/A1/C1/VREF+/VeREF+
P5.2/TA1.0/TA1CLK/ACLK
12
37
P1.2/TA1.1/TA0CLK/COUT/A2/C2
P5.3/UCB1STE
13
36
P1.3/TA1.2/ESITEST4/A3/C3
P3.0/UCB1CLK
14
35
DVCC2
P3.1/UCB1SIMO/UCB1SDA
15
34
DVSS2
P3.2/UCB1SOMI/UCB1SCL
16
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
P2.0/UCA0SIMO/UCA0TXD/TB0.6/TB0CLK
P2.1/UCA0SOMI/UCA0RXD/TB0.5/DMAE0
DVSS1
P2.2/UCA0CLK/TB0.4/RTCCLK
P9.4/ESICI0/A12/C12
P2.4/TB0.3
P2.3/UCA0STE/TB0OUTH
44
P3.7/UCA1STE/TB0.3
5
P3.6/UCA1CLK/TB0.2
P9.5/ESICI1/A13/C13
P1.7/UCB0SOMI/UCB0SCL/TA0.2
P3.5/UCA1SOMI/UCA1RXD/TB0.1
45
P3.4/UCA1SIMO/UCA1TXD/TB0.0
4
P3.3/TA1.1/TB0CLK
P9.6/ESICI2/A14/C14
P1.6/UCB0SIMO/UCB0SDA/TA0.1
PJ.3/TCK/COUT/SRCPUOFF
46
PJ.2/TMS/ACLK/SROSCOFF
3
PJ.1/TDI/TCLK/MCLK/SRSCG0
P9.7/ESICI3/A15/C15
P1.5/UCB0STE/UCA0CLK/TA0.0
PJ.0/TDO/TB0OUTH/SMCLK/SRSCG1
47
RST/NMI/SBWTDIO
2
TEST/SBWTCK
ESIDVCC
P1.4/UCB0CLK/UCA0STE/TA1.0
DVCC1
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
48
P4.3/UCA0SOMI/UCA0RXD/UCB1STE
NOTE: TI recommends connecting the RGC package pad to VSS.
NOTE: On devices with UART BSL: P2.0: BSLTX; P2.1: BSLRX
NOTE: On devices with I2C BSL: P1.6: BSLSDA; P1.7: BSLSCL
Figure 3-1. 64-Pin RGC Package (Top View) – MSP430FR5989-EP
Terminal Configuration and Functions
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Signal Descriptions
Table 3-1. Signal Descriptions – MSP430FR5989-EP
TERMINAL
NAME
RGC
DESCRIPTION
NO.
General-purpose digital I/O
P4.3/UCA0SOMI/
UCA0RXD/UCB1STE
1
USCI_A0: Slave out, master in (SPI mode), Receive data (UART mode)
USCI_B1: Slave transmit enable (SPI mode)
General-purpose digital I/O
USCI_B0: Clock signal input (SPI slave mode), Clock signal output (SPI master mode)
P1.4/UCB0CLK/ UCA0STE/TA1.0
2
USCI_A0: Slave transmit enable (SPI mode)
Timer_A TA1 CCR0 capture: CCI0A input, compare: Out0 output
General-purpose digital I/O
USCI_B0: Slave transmit enable (SPI mode)
P1.5/UCB0STE/ UCA0CLK/TA0.0
3
USCI_A0: Clock signal input (SPI slave mode), Clock signal output (SPI master mode)
Timer_A TA0 CCR0 capture: CCI0A input, compare: Out0 output
General-purpose digital I/O
USCI_B0: Slave in, master out (SPI mode), I2C data (I2C mode)
P1.6/UCB0SIMO/ UCB0SDA/TA0.1
4
BSL Data (I2C BSL)
Timer_A TA0 CCR1 capture: CCI1A input, compare: Out1 output
General-purpose digital I/O
USCI_B0: Slave out, master in (SPI mode), I2C clock (I2C mode)
P1.7/UCB0SOMI/ UCB0SCL/TA0.2
5
BSL Clock (I2C BSL)
Timer_A TA0 CCR2 capture: CCI2A input, compare: Out2 output
General-purpose digital I/O
P2.4/TB0.3
6
Timer_B TB0 CCR3 capture: CCI3A input, compare: Out3 output
General-purpose digital I/O
P2.5/TB0.4
7
Timer_B TB0 CCR4 capture: CCI4A input, compare: Out4 output
General-purpose digital I/O
P2.6/TB0.5/ESIC1OUT
8
Timer_B TB0 CCR5 capture: CCI5A input, compare: Out5 output
ESI Comparator 1 output
General-purpose digital I/O
P2.7/TB0.6/ESIC2OUT
9
Timer_B TB0 CCR6 capture: CCI6A input, compare: Out6 output
ESI Comparator 2 output
General-purpose digital I/O
P5.0/TA1.1/MCLK
10
Timer_A TA1 CCR1 capture: CCI1A input, compare: Out1 output
MCLK output
General-purpose digital I/O
P5.1/TA1.2
11
Timer_A TA1 CCR2 capture: CCI2A input, compare: Out2 output
General-purpose digital I/O
Timer_A TA1 CCR0 capture: CCI0B input, compare: Out0 output
P5.2/TA1.0/TA1CLK/ACLK
12
Timer_A TA1 clock signal TA0CLK input
ACLK output
6
Terminal Configuration and Functions
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Table 3-1. Signal Descriptions – MSP430FR5989-EP (continued)
TERMINAL
NAME
RGC
DESCRIPTION
NO.
General-purpose digital I/O
P5.3/UCB1STE
13
USCI_B1: Slave transmit enable (SPI mode)
General-purpose digital I/O
P3.0/UCB1CLK
14
USCI_B1: Clock signal input (SPI slave mode), Clock signal output (SPI master mode)
General-purpose digital I/O
P3.1/UCB1SIMO/UCB1SDA
15
USCI_B1: Slave in, master out (SPI mode)
USCI_B1: I2C data (I2C mode)
General-purpose digital I/O
P3.2/UCB1SOMI/UCB1SCL
16
USCI_B1: Slave out, master in (SPI mode)
USCI_B1: I2C clock (I2C mode)
DVSS1
17
Digital ground supply
DVCC1
18
Digital power supply
TEST/SBWTCK
19
Test mode pin - select digital I/O on JTAG pins
Spy-Bi-Wire input clock
Reset input, active low
RST/NMI/SBWTDIO
20
Nonmaskable interrupt input
Spy-Bi-Wire data input/output
General-purpose digital I/O
Test data output port
PJ.0/TDO/TB0OUTH/
SMCLK/SRSCG1
21
Switch all PWM outputs high impedance input - Timer_B TB0
SMCLK output
Low-power debug: CPU Status register SCG1
General-purpose digital I/O
Test data input or test clock input
PJ.1/TDI/TCLK/MCLK/SRSCG0
22
MCLK output
Low-power debug: CPU Status register SCG0
General-purpose digital I/O
Test mode select
PJ.2/TMS/ACLK/SROSCOFF
23
ACLK output
Low-power debug: CPU Status register OSCOFF
General-purpose digital I/O
Test clock
PJ.3/TCK/COUT/SRCPUOFF
24
Comparator output
Low-power debug: CPU Status register CPUOFF
General-purpose digital I/O
P3.3/TA1.1/TB0CLK
25
Timer_A TA1 CCR1 capture: CCI1A input, compare: Out1 output
Timer_B TB0 clock signal TB0CLK input
General-purpose digital I/O
USCI_A1: Slave in, master out (SPI mode)
P3.4/UCA1SIMO/UCA1TXD/TB0.0
26
USCI_A1: Transmit data (UART mode)
Timer_B TB0 CCR0 capture: CCI0A input, compare: Out0 output
Terminal Configuration and Functions
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Table 3-1. Signal Descriptions – MSP430FR5989-EP (continued)
TERMINAL
NAME
RGC
DESCRIPTION
NO.
General-purpose digital I/O
USCI_A1: Slave out, master in (SPI mode)
P3.5/UCA1SOMI/UCA1RXD/TB0.1
27
USCI_A1: Receive data (UART mode)
Timer_B TB0 CCR1 capture: CCI1A input, compare: Out1 output
General-purpose digital I/O
P3.6/UCA1CLK/TB0.2
28
USCI_A1: Clock signal input (SPI slave mode), Clock signal output (SPI master mode)
Timer_B TB0 CCR2 capture: CCI2A input, compare: Out2 output
General-purpose digital I/O
P3.7/UCA1STE/TB0.3
29
USCI_A1: Slave transmit enable (SPI mode)
Timer_B TB0 CCR3 capture: CCI3B input, compare: Out3 output
General-purpose digital I/O
P2.3/UCA0STE/TB0OUTH
30
USCI_A0: Slave transmit enable (SPI mode)
Switch all PWM outputs high impedance input - Timer_B TB0
General-purpose digital I/O
USCI_A0: Clock signal input (SPI slave mode), Clock signal output (SPI master mode)
P2.2/UCA0CLK/TB0.4/RTCCLK
31
Timer_B TB0 CCR4 capture: CCI4B input, compare: Out4 output
RTC clock output for calibration
General-purpose digital I/O
USCI_A0: Slave out, master in (SPI mode)
P2.1/UCA0SOMI/UCA0RXD/TB0.5/
DMAE0
USCI_A0: Receive data (UART mode)
32
BSL receive (UART BSL)
Timer_B TB0 CCR5 capture: CCI5B input, compare: Out5 output
DMA external trigger input
General-purpose digital I/O
USCI_A0: Slave in, master out (SPI mode)
P2.0/UCA0SIMO/UCA0TXD/TB0.6/
TB0CLK
USCI_A0: Transmit data (UART mode)
33
BSL transmit (UART BSL)
Timer_B TB0 CCR6 capture: CCI6B input, compare: Out6 output
Timer_B TB0 clock signal TB0CLK input
DVSS2
34
Digital ground supply
DVCC2
35
Digital power supply
General-purpose digital I/O
ESI test signal 4
P1.3/ESITEST4/TA1.2/A3/C3
36
Timer_A TA1 CCR2 capture: CCI2A input, compare: Out2 output
Analog input A3
Comparator input C3
8
Terminal Configuration and Functions
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Table 3-1. Signal Descriptions – MSP430FR5989-EP (continued)
TERMINAL
NAME
RGC
DESCRIPTION
NO.
General-purpose digital I/O
Timer_A TA1 CCR1 capture: CCI1A input, compare: Out1 output
Timer_A TA0 clock signal TA0CLK input
P1.2/TA1.1/TA0CLK/COUT/A2/C2
37
Comparator output
Analog input A2
Comparator input C2
General-purpose digital I/O
Timer_A TA0 CCR2 capture: CCI2A input, compare: Out2 output
Timer_A TA1 clock signal TA1CLK input
P1.1/TA0.2/TA1CLK/
COUT/A1/C1/VREF+/ VeREF+
Comparator output
38
Analog input A1
Comparator input C1
Output of positive reference voltage
Input for an external positive reference voltage to the ADC
General-purpose digital I/O
Timer_A TA0 CCR1 capture: CCI1A input, compare: Out1 output
DMA external trigger input
P1.0/TA0.1/DMAE0/ RTCCLK/A0/C0/
VREF-/VeREF-
RTC clock output for calibration
39
Analog input A0
Comparator input C0
Output of negative reference voltage
Input for an external negative reference voltage to the ADC
General-purpose digital I/O
P9.0/ESICH0/ESITEST0/A8/C8
40
ESI channel 0 sensor excitation output and signal input
ESI test signal 0
Analog input A8; comparator input C8
General-purpose digital I/O
ESI channel 1 sensor excitation output and signal input
P9.1/ESICH1/ESITEST1/ A9/C9
41
ESI test signal 1
Analog input A9
Comparator input C9
General-purpose digital I/O
ESI channel 2 sensor excitation output and signal input
P9.2/ESICH2/ESITEST2/A10/C10
42
ESI test signal 2
Analog input A10
Comparator input C10
General-purpose digital I/O
ESI channel 3 sensor excitation output and signal input
P9.3/ESICH3/ESITEST3/A11/C11
43
ESI test signal 3
Analog input A11
Comparator input C11
Terminal Configuration and Functions
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Table 3-1. Signal Descriptions – MSP430FR5989-EP (continued)
TERMINAL
NAME
RGC
DESCRIPTION
NO.
General-purpose digital I/O
ESI channel 0 signal input to comparator
P9.4/ESICI0/A12/C12
44
Analog input A12
Comparator input C12
General-purpose digital I/O
ESI channel 1 signal input to comparator
P9.5/ESICI1/A13/C13
45
Analog input A13
Comparator input C13
General-purpose digital I/O
ESI channel 2 signal input to comparator
P9.6/ESICI2/A14/C14
46
Analog input A14
Comparator input C14
General-purpose digital I/O
ESI channel 3 signal input to comparator
P9.7/ESICI3/A15/C15
47
Analog input A15
Comparator input C15
ESIDVCC
48
ESI Power supply
ESIDVSS
49
ESI Ground supply
ESICI
50
ESI Scan IF input to Comparator
ESICOM
51
ESI Common termination for Scan IF sensors
AVCC1
52
Analog power supply
AVSS3
53
Analog ground supply
PJ.7/HFXOUT
54
General-purpose digital I/O
Output terminal of crystal oscillator XT2
General-purpose digital I/O
PJ.6/HFXIN
55
AVSS1
56
PJ.4/LFXIN
57
Input terminal for crystal oscillator XT2
Analog ground supply
General-purpose digital I/O
Input terminal for crystal oscillator XT1
General-purpose digital I/O
PJ.5/LFXOUT
58
Output terminal of crystal oscillator XT1
AVSS2
59
Analog ground supply
General-purpose digital I/O
USCI_B1: Slave in, master out (SPI mode)
P4.0/UCB1SIMO/UCB1SDA/MCLK
60
USCI_B1: I2C data (I2C mode)
MCLK output
General-purpose digital I/O
USCI_B1: Slave out, master in (SPI mode)
P4.1/UCB1SOMI/UCB1SCL/ACLK
61
DVSS3
62
Digital ground supply
DVCC3
63
Digital power supply
USCI_B1: I2C clock (I2C mode)
ACLK output
10
Terminal Configuration and Functions
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Table 3-1. Signal Descriptions – MSP430FR5989-EP (continued)
TERMINAL
NAME
RGC
DESCRIPTION
NO.
General-purpose digital I/O
P4.2/UCA0SIMO/UCA0TXD/
UCB1CLK
USCI_A0: Slave in, master out (SPI mode)
64
USCI_A0: Transmit data (UART mode)
USCI_B1: Clock signal input (SPI slave mode), Clock signal output (SPI master mode)
Thermal pad
Pad
RGC package only. QFN package exposed thermal pad. TI recommends connection to
VSS.
Terminal Configuration and Functions
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Pin Multiplexing
Pin multiplexing for these devices is controlled by both register settings and operating modes (for example, if the device is in test mode). For
details of the settings for each pin and schematics of the multiplexed ports, see Section 5.11.24.
3.4
Connection of Unused Pins
Table 3-2 lists the correct termination of all unused pins.
Table 3-2. Connection of Unused Pins (1)
PIN
POTENTIAL
AVCC
DVCC
AVSS
DVSS
Px.0 to Px.7
Open
Switched to port function, output direction (PxDIR.n = 1)
R33/LCDCAP
DVSS or DVCC
If not used the pin can be tied to either supplies.
ESIDVCC
DVCC
ESIDVSS
DVSS
ESICOM
Open
ESICI
Open
RST/NMI
DVCC or VCC
47-kΩ pullup or internal pullup selected with 2.2-nF (10-nF (2)) pulldown.
PJ.0/TDO
PJ.1/TDI
PJ.2/TMS
PJ.3/TCK
Open
The JTAG pins are shared with general-purpose I/O function (PJ.x). If not being used, these should be switched to port function, output
direction. When used as JTAG pins, these pins should remain open.
TEST
Open
This pin always has an internal pulldown enabled.
(1)
(2)
12
COMMENT
Any unused pin with a secondary function that is shared with general-purpose I/O should follow the Px.0 to Px.7 unused pin connection guidelines.
The pulldown capacitor should not exceed 2.2 nF when using devices with Spy-Bi-Wire interface in Spy-Bi-Wire mode or in 4-wire JTAG mode with TI tools like FET interfaces or GANG
programmers. If JTAG or Spy-Bi-Wire access is not needed, up to a 10-nF pulldown capacitor may be used.
Terminal Configuration and Functions
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4 Specifications
Absolute Maximum Ratings (1)
4.1
over operating junction temperature range (unless otherwise noted)
Voltage applied at DVCC and AVCC pins to VSS
Voltage difference between DVCC and AVCC pins
Voltage applied to any pin
MIN
MAX
–0.3
4.1
V
±0.3
V
–0.3
VCC + 0.3 V
(4.1 max)
V
(2)
(3)
Diode current at any device pin
Storage temperature, Tstg
(1)
(2)
(3)
(4)
(4)
–55
±2
mA
125
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Voltage differences between DVCC and AVCC exceeding the specified limits may cause malfunction of the device including erroneous
writes to RAM and FRAM.
All voltage values are with respect to VSS, unless otherwise noted.
Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
4.2
ESD Ratings
VALUE
V(ESD)
(1)
(2)
UNIT
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±1000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±250
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as
±1000 V may actually have higher performance.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±250 V
may actually have higher performance.
4.3
Recommended Operating Conditions
Typical data are based on VCC = 3 V, TJ = 25°C unless otherwise noted.
MIN
VCC
Supply voltage range applied at all DVCC, AVCC, and ESIDVCC pins
VSS
Supply voltage applied at all DVSS, AVSS, and ESIDVSS pins
TJ
Operating junction temperature
CDVCC
Capacitor value at DVCC and ESIDVCC (5)
fSYSTEM
Processor frequency (maximum MCLK
frequency) (6)
fACLK
Maximum ACLK frequency
fSMCLK
Maximum SMCLK frequency
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(1) (2) (3)
1.8
NOM
(4)
MAX
3.6
V
95
°C
0
–55
UNIT
V
1–20%
µF
No FRAM wait states (NWAITSx = 0)
0
8 (7)
With FRAM wait states (NWAITSx = 1) (8)
0
16 (9)
MHz
50
kHz
16 (9)
MHz
TI recommends powering the DVCC, AVCC, and ESIDVCC pins from the same source. At a minimum, during power up, power down,
and device operation, the voltage difference between DVCC, AVCC, and ESIDVCC must not exceed the limits specified in Absolute
Maximum Ratings. Exceeding the specified limits may cause malfunction of the device including erroneous writes to RAM and FRAM.
See Table 4-1 for additional important information.
Modules may have a different supply voltage range specification. See the specification of each module in this data sheet.
The minimum supply voltage is defined by the supervisor SVS levels. See Table 4-2 for the exact values.
Connect a low-ESR capacitor with at least the value specified and a maximum tolerance of 20% as close as possible to the DVCC and
ESIDVCC pins.
Modules may have a different maximum input clock specification. See the specification of each module in this data sheet.
DCO settings and HF crystals with a typical value less than or equal to the specified MAX value are permitted.
Wait states only occur on actual FRAM accesses; that is, on FRAM cache misses. RAM and peripheral accesses are always executed
without wait states.
DCO settings and HF crystals with a typical value less than or equal to the specified MAX value are permitted. If a clock sources with a
larger typical value is used, the clock must be divided in the clock system.
Specifications
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Active Mode Supply Current Into VCC Excluding External Current
over recommended operating junction temperature (unless otherwise noted) (1)
(2)
FREQUENCY (fMCLK = fSMCLK)
PARAMETER
EXECUTION
MEMORY
VCC
1 MHz
0 WAIT
STATES
(NWAITSx = 0)
TYP
IAM, FRAM_UNI
(Unified memory) (3)
(4) (5)
MAX
4 MHz
0 WAIT
STATES
(NWAITSx = 0)
TYP
MAX
8 MHz
0 WAIT
STATES
(NWAITSx = 0)
TYP
MAX
12 MHz
1 WAIT STATE
(NWAITSx = 1)
TYP
MAX
16 MHz
1 WAIT STATE
(NWAITSx = 1)
TYP
UNIT
MAX
FRAM
3.0 V
210
640
1220
1475
1845
µA
FRAM
0% cache hit
ratio
3.0 V
375
1290
2525
2100
2675
µA
IAM,
FRAM(0%)
IAM,
FRAM(50%)
(4) (5)
FRAM
50% cache hit
ratio
3.0 V
240
745
1440
1575
1990
µA
IAM,
FRAM(66%)
(4) (5)
FRAM
66% cache hit
ratio
3.0 V
200
560
1070
1300
1620
µA
IAM,
FRAM(75%)
(4) (5)
FRAM
75% cache hit
ratio
3.0 V
170
480
890
IAM,
FRAM(100%
FRAM
100% cache hit
ratio
3.0 V
110
235
420
640
730
IAM,
RAM
RAM
3.0 V
130
320
585
890
1070
RAM
3.0 V
100
290
555
860
1040
(6) (5)
IAM, RAM only
(1)
(2)
(3)
(4)
(5)
(6)
(7)
14
(4) (5)
(7) (5)
255
180
1085
1155
1310
1420
1620
µA
µA
µA
1300
µA
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
Characterized with program executing typical data processing.
fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO at specified frequency, except for 12 MHz. For 12 MHz, fDCO = 24 MHz and
fMCLK = fSMCLK = fDCO / 2.
At MCLK frequencies above 8 MHz, the FRAM requires wait states. When wait states are required, the effective MCLK frequency
(fMCLK,eff) decreases. The effective MCLK frequency also depends on the cache hit ratio. SMCLK is not affected by the number of wait
states or the cache hit ratio.
The following equation can be used to compute fMCLK,eff:
fMCLK,eff = fMCLK / [wait states × (1 – cache hit ratio) + 1]
For example, with 1 wait state and 75% cache hit ratio fMCKL,eff = fMCLK / [1 × (1 – 0.75) + 1] = fMCLK / 1.25.
Represents typical program execution. Program and data reside entirely in FRAM. All execution is from FRAM.
Program resides in FRAM. Data resides in SRAM. Average current dissipation varies with cache hit-to-miss ratio as specified. Cache hit
ratio represents number cache accesses divided by the total number of FRAM accesses. For example, a 75% ratio implies three of
every four accesses is from cache, and the remaining are FRAM accesses.
See Figure 4-1 for typical curves. Each characteristic equation shown in the graph is computed using the least squares method for best
linear fit using the typical data shown in Section 4.4.
Program and data reside entirely in RAM. All execution is from RAM.
Program and data reside entirely in RAM. All execution is from RAM. FRAM is off.
Specifications
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Typical Characteristics, Active Mode Supply Currents
3000
I(AM,0%)
I(AM,50%)
2500
I(AM,66%)
Active Mode Current (µA)
I(AM,75%)
2000
I(AM,100%)
I(AM,75%)[µA] = 103 × f[MHz] + 68
I(AM,RAMonly)
1500
1000
500
0
0
1
2
3
4
5
6
7
8
9
MCLK Frequency (MHz)
I(AM, cache hit ratio): Program resides in FRAM. Data resides in SRAM. Average current dissipation varies with
cache hit-to-miss ratio as specified. Cache hit ratio represents number cache accesses divided by the total number of
FRAM accesses. For example, a 75% ratio implies three of every four accesses is from cache, and the remaining are
FRAM accesses.
I(AM, RAMonly): Program and data reside entirely in RAM. All execution is from RAM. FRAM is off.
Figure 4-1. Typical Active Mode Supply Currents, No Wait States
4.6
Low-Power Mode (LPM0, LPM1) Supply Currents Into VCC Excluding External Current
over recommended operating junction temperature (unless otherwise noted) (1)
(2)
FREQUENCY (fSMCLK)
PARAMETER
VCC
1 MHz
TYP
ILPM0
ILPM1
(1)
(2)
2.2 V
75
3.0 V
85
2.2 V
40
3.0 V
40
4 MHz
MAX
120
65
TYP
8 MHz
MAX
TYP
12 MHz
MAX
TYP
16 MHz
MAX
TYP
105
165
250
230
115
175
260
240
65
130
215
195
65
130
215
195
UNIT
MAX
275
220
µA
µA
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
Current for watchdog timer clocked by SMCLK included.
fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO at specified frequency, except for 12 MHz: here fDCO = 24 MHz and fSMCLK = fDCO / 2.
Specifications
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Low-Power Mode (LPM2, LPM3, LPM4) Supply Currents (Into VCC) Excluding External
Current
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
(1)
TEMPERATURE (TJ)
PARAMETER
VCC
–55°C
TYP
25°C
MAX
TYP
ILPM2,XT12
Low-power mode 2, 12-pF
crystal (2) (3) (4)
2.2 V
0.6
1.2
3.0 V
0.6
1.2
ILPM2,XT3.7
Low-power mode 2, 3.7-pF
crystal (2) (5) (4)
2.2 V
0.5
3.0 V
0.5
ILPM2,VLO
Low-power mode 2, VLO,
includes SVS (6)
2.2 V
0.3
0.9
3.0 V
0.3
0.9
ILPM3,XT12
Low-power mode 3, 12-pF
crystal, excludes SVS (2) (3)
2.2 V
0.5
0.7
3.0 V
0.5
0.7
Low-power mode 3, 3.7-pF
crystal, excludes SVS (2) (5) (8)
(also see Figure 4-2)
2.2 V
0.4
ILPM3,XT3.7
3.0 V
ILPM3,VLO
Low-power mode 3,
VLO, excludes SVS
ILPM3,VLO,
RAMoff
(7)
(9)
Low-power mode 3,
VLO, excludes SVS, RAM
powered-down completely (10)
60°C
MAX
TYP
95°C
MAX
TYP
3.1
8.8
3.1
8.8
1.1
3.0
8.7
1.1
3.0
8.7
2.8
8.5
2.8
8.5
1.2
2.5
1.2
2.5
0.6
1.1
2.4
0.4
0.6
1.1
2.4
2.2 V
0.3
0.4
0.9
2.2
3.0 V
0.3
0.4
0.9
2.2
2.2 V
0.3
0.4
0.8
2.1
3.0 V
0.3
0.4
0.8
2.1
2.2
2.0
1.0
0.8
0.7
UNIT
MAX
20.8
μA
μA
20.5
6.4
μA
μA
μA
6.1
5.2
μA
μA
(1)
(2)
(3)
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
Not applicable for devices with HF crystal oscillator only.
Characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load capacitance are
chosen to closely match the required 12.5 pF load.
(4) Low-power mode 2, crystal oscillator test conditions:
Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. Current for brownout and SVS included.
CPUOFF = 1, SCG0 = 0 SCG1 = 1, OSCOFF = 0 (LPM2),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
(5) Characterized with a Seiko SSP-T7-FL (SMD) crystal with a load capacitance of 3.7 pF. The internal and external load capacitance are
chosen to closely match the required 3.7-pF load.
(6) Low-power mode 2, VLO test conditions:
Current for watchdog timer clocked by ACLK included. RTC disabled (RTCHOLD = 1). Current for brownout and SVS included.
CPUOFF = 1, SCG0 = 0 SCG1 = 1, OSCOFF = 0 (LPM2),
fXT1 = 0 Hz, fACLK = fVLO, fMCLK = fSMCLK = 0 MHz
(7) Low-power mode 3, 12-pF crystal excluding SVS test conditions:
Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. Current for brownout included. SVS disabled (SVSHE =
0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
Activating additional peripherals increases the current consumption due to active supply current contribution as well as due to additional
idle current. See the idle currents specified for the respective peripheral groups.
(8) Low-power mode 3, 3.7-pF crystal excluding SVS test conditions:
Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. Current for brownout included. SVS disabled (SVSHE =
0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
Activating additional peripherals increases the current consumption due to active supply current contribution as well as due to additional
idle current. See the idle currents specified for the respective peripheral groups.
(9) Low-power mode 3, VLO excluding SVS test conditions:
Current for watchdog timer clocked by ACLK included. RTC disabled (RTCHOLD = 1). Current for brownout included. SVS disabled
(SVSHE = 0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),
fXT1 = 0 Hz, fACLK = fVLO, fMCLK = fSMCLK = 0 MHz
Activating additional peripherals increases the current consumption due to active supply current contribution as well as due to additional
idle current. See the idle currents specified for the respective peripheral groups.
(10) Low-power mode 3, VLO excluding SVS test conditions:
Current for watchdog timer clocked by ACLK included. RTC disabled (RTCHOLD = 1). RAM disabled (RCCTL0 = 5A55h). Current for
brownout included. SVS disabled (SVSHE = 0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),
fXT1 = 0 Hz, fACLK = fVLO, fMCLK = fSMCLK = 0 MHz
Activating additional peripherals increases the current consumption due to active supply current contribution as well as due to additional
idle current. See the idle currents specified for the respective peripheral groups.
16
Specifications
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Low-Power Mode (LPM2, LPM3, LPM4) Supply Currents (Into VCC) Excluding External
Current (continued)
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
(1)
TEMPERATURE (TJ)
PARAMETER
VCC
–55°C
TYP
25°C
MAX
TYP
ILPM4,SVS
Low-power mode 4, includes
SVS (11)
2.2 V
0.4
0.5
3.0 V
0.4
0.5
ILPM4
Low-power mode 4, excludes
SVS (12)
2.2 V
0.2
0.3
3.0 V
0.2
0.3
Low-power mode 4, excludes
SVS, RAM powered-down
completely (13)
2.2 V
0.2
0.3
ILPM4,RAMoff
3.0 V
0.2
0.3
IIDLE,GroupA
Additional idle current if one or
more modules from Group A
(see Table 5-3) are activated in
LPM3 or LPM4
3.0V
IIDLE,GroupB
Additional idle current if one or
more modules from Group B
(see Table 5-3) are activated in
LPM3 or LPM4
IIDLE,GroupC
IIDLE,GroupD
60°C
MAX
TYP
95°C
MAX
TYP
UNIT
MAX
0.9
2.3
0.9
2.3
0.7
2.0
0.7
2.0
0.7
1.9
0.7
1.9
5.1
0.02
1.18
2.6
μA
3.0V
0.02
1.15
2.6
μA
Additional idle current if one or
more modules from Group C
(see Table 5-3) are activated in
LPM3 or LPM4
3.0V
0.02
1.5
2.8
μA
Additional idle current if one or
more modules from Group D
(see Table 5-3) are activated in
LPM3 or LPM4
3.0V
0.015
1.4
2.4
μA
0.8
0.6
0.6
6.2
6.0
μA
μA
μA
(11) Low-power mode 4 including SVS test conditions:
Current for brownout and SVS included (SVSHE = 1).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPM4),
fXT1 = 0 Hz, fACLK = 0 Hz, fMCLK = fSMCLK = 0 MHz
Activating additional peripherals increases the current consumption due to active supply current contribution as well as due to additional
idle current. See the idle currents specified for the respective peripheral groups.
(12) Low-power mode 4 excluding SVS test conditions:
Current for brownout included. SVS disabled (SVSHE = 0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPM4),
fXT1 = 0 Hz, fACLK = 0 Hz, fMCLK = fSMCLK = 0 MHz
Activating additional peripherals increases the current consumption due to active supply current contribution as well as due to additional
idle current. See the idle currents specified for the respective peripheral groups.
(13) Low-power mode 4 excluding SVS test conditions:
Current for brownout included. SVS disabled (SVSHE = 0). RAM disabled (RCCTL0 = 5A55h).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPM4),
fXT1 = 0 Hz, fACLK = 0 Hz, fMCLK = fSMCLK = 0 MHz
Activating additional peripherals increases the current consumption due to active supply current contribution as well as due to additional
idle current. See the idle currents specified for the respective peripheral groups.
Specifications
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Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
TEMPERATURE (TJ)
PARAMETER
VCC
–55°C
TYP
25°C
MAX
TYP
ILPM3,XT12
LCD,
ext. bias
Low-power mode 3 (LPM3)
current,12-pF crystal, LCD 4mux mode, external biasing,
excludes SVS (1) (2)
3.0 V
0.7
0.9
ILPM3,XT12
LCD,
int. bias
Low-power mode 3 (LPM3)
current, 12-pF crystal, LCD 4mux mode, internal biasing,
charge pump disabled,
excludes SVS (1) (3)
3.0 V
2.0
2.2
Low-power mode 3 (LPM3)
current,12-pF crystal, LCD 4mux mode, internal biasing,
charge pump enabled, 1/3 bias,
excludes SVS (1) (4)
2.2 V
5.0
ILPM3,XT12
LCD,CP
3.0 V
4.5
(1)
(2)
(3)
(4)
18
60°C
MAX
TYP
95°C
MAX
TYP
1.5
3.1
2.8
4.4
5.2
5.8
7.4
4.7
5.3
6.9
2.9
UNIT
MAX
µA
9.3
µA
µA
Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. Current for brownout included. SVS disabled (SVSHE =
0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
Activating additional peripherals increases the current consumption due to active supply current contribution as well as due to additional
idle current - idle current of Group containing LCD module already included. See the idle currents specified for the respective peripheral
groups.
LCDMx = 11 (4-mux mode), LCDREXT = 1, LCDEXTBIAS = 1 (external biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 0 (charge pump
disabled), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (fLCD = 32768 Hz / 32 / 4 = 256 Hz)
Current through external resistors not included (voltage levels are supplied by test equipment).
Even segments S0, S2, ... = 0, odd segments S1, S3, ... = 1. No LCD panel load.
LCDMx = 11 (4-mux mode), LCDREXT = 0, LCDEXTBIAS = 0 (internal biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 0 (charge pump
disabled), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (fLCD = 32768 Hz / 32 / 4 = 256 Hz)
Even segments S0, S2, ...=0, odd segments S1, S3, ... = 1. No LCD panel load.
LCDMx = 11 (4-mux mode), LCDREXT = 0, LCDEXTBIAS = 0 (internal biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 1 (charge pump
enabled), VLCDx = 1000 (VLCD= 3 V typical), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (fLCD = 32768 Hz / 32 / 4 = 256 Hz)
Even segments S0, S2, ...=0, odd segments S1, S3, ... = 1. No LCD panel load. CLCDCAP = 10 µF
Specifications
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4.9
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Low-Power Mode LPMx.5 Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted) (1)
PARAMETER
VCC
–55°C
TYP
25°C
MAX
TYP
ILPM3.5,XT12
Low-power mode 3.5, 12-pF
crystal including SVS (2) (3) (4)
2.2 V
0.4
0.45
3.0 V
0.4
0.45
ILPM3.5,XT3.7
Low-power mode 3.5, 3.7-pF
crystal excluding SVS (2) (5) (6)
2.2 V
0.3
3.0 V
0.3
ILPM4.5,SVS
Low-power mode 4.5, including
SVS (7)
2.2 V
0.2
0.2
3.0 V
0.2
0.2
ILPM4.5
Low-power mode 4.5,
excluding SVS (8)
2.2 V
0.02
3.0 V
0.02
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
60°C
MAX
TYP
95°C
MAX
TYP
0.55
0.75
0.55
0.75
0.35
0.4
0.65
0.35
0.4
0.65
0.25
0.35
0.25
0.35
0.02
0.03
0.14
0.02
0.03
0.13
0.7
0.4
MAX
1.6
UNIT
μA
μA
0.7
0.5
μA
μA
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
Not applicable for devices with HF crystal oscillator only.
Characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load capacitance are
chosen to closely match the required 12.5 pF load.
Low-power mode 3.5, 1-pF crystal including SVS test conditions:
Current for RTC clocked by XT1 included. Current for brownout and SVS included (SVSHE = 1). Core regulator disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
Characterized with a Seiko SSP-T7-FL (SMD) crystal with a load capacitance of 3.7 pF. The internal and external load capacitance are
chosen to closely match the required 3.7-pF load.
Low-power mode 3.5, 3.7-pF crystal excluding SVS test conditions:
Current for RTC clocked by XT1 included.Current for brownout included. SVS disabled (SVSHE = 0). Core regulator disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
Low-power mode 4.5 including SVS test conditions:
Current for brownout and SVS included (SVSHE = 1). Core regulator disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 0 Hz, fACLK = 0 Hz, fMCLK = fSMCLK = 0 MHz
Low-power mode 4.5 excluding SVS test conditions:
Current for brownout included. SVS disabled (SVSHE = 0). Core regulator disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 0 Hz, fACLK = 0 Hz, fMCLK = fSMCLK = 0 MHz
Specifications
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4.10 Typical Characteristics, Low-Power Mode Supply Currents
3
3
3.0 V, SVS off
3.0 V, SVS off
2.2 V, SVS off
2.2 V, SVS off
3.0 V, SVS on
2.5
3.0 V, SVS on
2.5
2.2 V, SVS on
LPM4 Supply Current (µA)
LPM3 Supply Current (µA)
2.2 V, SVS on
2
1.5
1
0.5
2
1.5
1
0.5
0
0
-50
-25
0
25
50
75
100
-50
-25
0
25
Temperature (°C)
50
75
100
Temperature (°C)
Figure 4-2. LPM3 Supply Current vs Temperature (LPM3, XT3.7)
Figure 4-3. LPM4 Supply Current vs Temperature (LPM4, SVS)
0.7
0.7
3.0 V, SVS off
3.0 V, SVS off
2.2 V, SVS off
0.6
2.2 V, SVS off
0.6
LPM4.5 Supply Current (µA)
LPM3.5 Supply Current (µA)
3.0 V, SVS on
0.5
0.4
0.3
0.2
0.1
2.2 V, SVS on
0.5
0.4
0.3
0.2
0.1
0
0
-50
-25
0
25
50
75
100
-50
-25
Temperature (°C)
25
50
75
100
Temperature (°C)
Figure 4-4. LPM3.5 Supply Current vs Temperature (LPM3.5,
XT3.7)
20
0
Figure 4-5. LPM4.5 Supply Current vs Temperature (LPM4.5)
Specifications
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4.11 Typical Characteristics, Current Consumption per Module (1)
MODULE
TEST CONDITIONS
REFERENCE CLOCK
Timer_A
MIN
TYP
Module input clock
Timer_B
MAX
UNIT
3
μA/MHz
Module input clock
5
μA/MHz
eUSCI_A
UART mode
Module input clock
5.5
μA/MHz
eUSCI_A
SPI mode
Module input clock
3.5
μA/MHz
eUSCI_B
SPI mode
Module input clock
3.5
μA/MHz
eUSCI_B
I2C mode, 100 kbaud
Module input clock
3.5
μA/MHz
32 kHz
100
nA
RTC_C
MPY
Only from start to end of operation
MCLK
25
μA/MHz
AES
Only from start to end of operation
MCLK
21
μA/MHz
CRC16
Only from start to end of operation
MCLK
2.5
μA/MHz
CRC32
Only from start to end of operation
MCLK
2.5
μA/MHz
(1)
LCD_C: See Section 4.8. For other module currents not listed here, see the module-specific parameter sections.
Specifications
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4.12 Thermal Resistance Characteristics
MSP430FR5989-EP
THERMAL METRIC (1)
RGC (VQFN)
UNIT
64 Pins
RθJA
Junction-to-ambient thermal resistance, still air (2)
29.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance (3)
13.9
°C/W
(4)
RθJB
Junction-to-board thermal resistance
8.1
°C/W
ΨJT
Junction-to-top thermal characterization parameter
8.0
°C/W
ΨJB
Junction-to-board thermal characterization parameter
0.2
°C/W
1.0
°C/W
RθJC(bot)
(1)
(2)
(3)
(4)
(5)
Junction-to-case (bottom) thermal resistance
(5)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
4.13 Timing and Switching Characteristics
4.13.1 Power Supply Sequencing
TI recommends powering the AVCC, DVCC, and ESIDVCC pins from the same source. At a minimum,
during power up, power down, and device operation, the voltage difference between AVCC, DVCC, and
ESIDVCC must not exceed the limits specified in Absolute Maximum Ratings. Exceeding the specified
limits may cause malfunction of the device including erroneous writes to RAM and FRAM.
At power up, the device does not start executing code before the supply voltage reached VSVSH+ if the
supply rises monotonically to this level.
Table 4-1 lists the power ramp requirements.
Table 4-1. Brownout and Device Reset Power Ramp Requirements
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER
VVCC_BOR–
Brownout power-down level (1) (2)
VVCC_BOR+
Brownout power-up level (2)
(1)
(2)
(3)
(4)
22
TEST CONDITIONS
| dDVCC/dt | < 3 V/s (3)
| dDVCC/dt | > 300 V/s (3)
| dDVCC/dt | < 3 V/s (4)
MIN
MAX
0.7
1.66
0
0.79
1.68
UNIT
V
V
In case of a supply voltage brownout, the device supply voltages must ramp down to the specified brownout power-down level
(VVCC_BOR-) before the voltage is ramped up again to ensure a reliable device start-up and performance according to the data sheet
including the correct operation of the on-chip SVS module.
Fast supply voltage changes can trigger a BOR reset even within the recommended supply voltage range. To avoid unwanted BOR
resets, the supply voltage must change by less than 0.05 V per microsecond (±0.05 V/µs). Following the data sheet recommendation for
capacitor CDVCC should limit the slopes accordingly.
The brownout levels are measured with a slowly changing supply. With faster slopes, the MIN level required to reset the device properly
can decrease to 0 V. Use the graph in Figure 4-6 to estimate the VVCC_BOR- level based on the down slope of the supply voltage. After
removing VCC, the down slope can be estimated based on the current consumption and the capacitance on DVCC: dV/dt = I/C where
dV/dt = slope, I = current, C = capacitance.
The brownout levels are measured with a slowly changing supply.
Specifications
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2
Brownout Power-Down Level (V)
Process-Temperature Corner Case 1
1.5
Typical
1
Process-Temperature Corner Case 2
MIN Limit
0.5
V VCC_BOR- for reliable
device start-up
0
1
10
100
1000
10000
100000
Supply Voltage Power-Down Slope (V/s)
Figure 4-6. Brownout Power-Down Level vs Supply Voltage Down Slope
Specifications
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Table 4-2 lists the characteristics of the SVS.
Table 4-2. SVS
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
ISVSH,LPM
SVSH current consumption, low-power modes
VSVSH-
SVSH power-down level
VSVSH+
SVSH power-up level
VSVSH_hys
SVSH hysteresis
tPD,SVSH, AM
SVSH propagation delay, active mode
MIN
TYP
MAX
UNIT
170
300
nA
1.74
1.81
1.86
V
1.76
1.88
1.99
V
120
mV
40
dVVcc/dt = –10 mV/µs
10
µs
4.13.2 Reset Timing
Table 4-3 lists the input requirements for the RST signal.
Table 4-3. Reset Input
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER
(1)
VCC
External reset pulse duration on RST (1)
t(RST)
MIN
2.2 V, 3.0 V
MAX
2
UNIT
µs
Not applicable if the RST/NMI pin is configured as NMI.
4.13.3 Clock Specifications
Table 4-4 lists the characteristics of the LFXT.
Table 4-4. Low-Frequency Crystal Oscillator, LFXT (1)
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER
IVCC.LFXT
fLFXT
Current consumption
TEST CONDITIONS
fOSC = 32768 Hz,
LFXTBYPASS = 0, LFXTDRIVE = {1},
TJ = 25°C, CL,eff = 6 pF, ESR ≈ 40 kΩ
3.0 V
185
fOSC = 32768 Hz,
LFXTBYPASS = 0, LFXTDRIVE = {2},
TJ = 25°C, CL,eff = 9 pF, ESR ≈ 40 kΩ
3.0 V
225
fOSC = 32768 Hz,
LFXTBYPASS = 0, LFXTDRIVE = {3},
TJ = 25°C, CL,eff = 12.5 pF, ESR ≈ 40 kΩ
3.0 V
330
DCLFXT
LFXT oscillator duty cycle
Measured at ACLK,
fLFXT = 32768 Hz
fLFXT,SW
LFXT oscillator logic-level
square-wave input frequency
LFXTBYPASS = 1 (2)
DCLFXT, SW
LFXT oscillator logic-level
square-wave input duty cycle
LFXTBYPASS = 1
(3)
24
TYP
180
LFXTBYPASS = 0
(2)
MIN
3.0 V
LFXT oscillator crystal frequency
(1)
VCC
fOSC = 32768 Hz,
LFXTBYPASS = 0, LFXTDRIVE = {0},
TJ = 25°C, CL,eff = 3.7 pF, ESR ≈ 44 kΩ
MAX
nA
32768
30%
(3)
UNIT
10.5
30%
Hz
70%
32.768
50
kHz
70%
To improve EMI on the LFXT oscillator, observe the following guidelines.
• Keep the trace between the device and the crystal as short as possible.
• Design a good ground plane around the oscillator pins.
• Prevent crosstalk from other clock or data lines into oscillator pins LFXIN and LFXOUT.
• Avoid running PCB traces underneath or adjacent to the LFXIN and LFXOUT pins.
• Use assembly materials and processes that avoid any parasitic load on the oscillator LFXIN and LFXOUT pins.
• If conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins.
When LFXTBYPASS is set, LFXT circuits are automatically powered down. Input signal is a digital square wave with parametrics
defined in the Schmitt-trigger Inputs section of this data sheet. Duty cycle requirements are defined by DCLFXT, SW.
Maximum frequency of operation of the entire device cannot be exceeded.
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Table 4-4. Low-Frequency Crystal Oscillator, LFXT(1) (continued)
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Oscillation allowance for
LF crystals (4)
OALFXT
VCC
MIN
TYP
LFXTBYPASS = 0, LFXTDRIVE = {1},
fLFXT = 32768 Hz, CL,eff = 6 pF
210
LFXTBYPASS = 0, LFXTDRIVE = {3},
fLFXT = 32768 Hz, CL,eff = 12.5 pF
300
MAX
UNIT
kΩ
CLFXIN
Integrated load capacitance at
LFXIN terminal (5) (6)
2
pF
CLFXOUT
Integrated load capacitance at
LFXOUT terminal (5) (6)
2
pF
tSTART,LFXT
fFault,LFXT
(4)
(5)
(6)
(7)
(8)
(9)
Start-up time (7)
Oscillator fault frequency (8)
fOSC = 32768 Hz,
LFXTBYPASS = 0, LFXTDRIVE = {0},
TJ = 25°C, CL,eff = 3.7 pF
3.0 V
fOSC = 32768 Hz,
LFXTBYPASS = 0, LFXTDRIVE = {3},
TJ = 25°C, CL,eff = 12.5 pF
3.0 V
800
ms
(9)
1000
0
3500
Hz
Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the
LFXTDRIVE settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following
guidelines, but should be evaluated based on the actual crystal selected for the application:
• For LFXTDRIVE = {0}, CL,eff = 3.7 pF.
• For LFXTDRIVE = {1}, CL,eff = 6 pF
• For LFXTDRIVE = {2}, 6 pF ≤ CL,eff ≤ 9 pF
• For LFXTDRIVE = {3}, 9 pF ≤ CL,eff ≤ 12.5 pF
This represents all the parasitic capacitance present at the LFXIN and LFXOUT terminals, respectively, including parasitic bond and
package capacitance. The effective load capacitance, CL,eff can be computed as CIN x COUT / (CIN + COUT), where CIN and COUT are the
total capacitance at the LFXIN and LFXOUT terminals, respectively.
Requires external capacitors at both terminals to meet the effective load capacitance specified by crystal manufacturers. Recommended
effective load capacitance values supported are 3.7 pF, 6 pF, 9 pF, and 12.5 pF. Maximum shunt capacitance of 1.6 pF. The PCB adds
additional capacitance, so it must also be considered in the overall capacitance. Verify that the recommended effective load capacitance
of the selected crystal is met.
Includes start-up counter of 1024 clock cycles.
Frequencies above the MAX specification do not set the fault flag. Frequencies between the MIN and MAX specification may set the
flag. A static condition or stuck at fault condition sets the flag.
Measured with logic-level input frequency but also applies to operation with crystals.
Table 4-5 lists the characteristics of the HFXT.
Table 4-5. High-Frequency Crystal Oscillator, HFXT (1)
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
fOSC = 4 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 0, HFFREQ =
1 (2)
TJ = 25°C, CL,eff = 18 pF, Typical ESR, Cshunt
IDVCC.HFXT
(1)
(2)
HFXT oscillator crystal
current HF mode at
typical ESR
fOSC = 8 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 1, HFFREQ = 1,
TJ = 25°C, CL,eff = 18 pF, Typical ESR, Cshunt
MIN
TYP
MAX
UNIT
75
120
3.0 V
μA
fOSC = 16 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 2, HFFREQ = 2,
TJ = 25°C, CL,eff = 18 pF, Typical ESR, Cshunt
190
fOSC = 24 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 3, HFFREQ = 3,
TJ = 25°C, CL,eff = 18 pF, Typical ESR, Cshunt
250
To improve EMI on the HFXT oscillator, observe the following guidelines.
• Keep the traces between the device and the crystal as short as possible.
• Design a good ground plane around the oscillator pins.
• Prevent crosstalk from other clock or data lines into oscillator pins HFXIN and HFXOUT.
• Avoid running PCB traces underneath or adjacent to the HFXIN and HFXOUT pins.
• Use assembly materials and processes that avoid any parasitic load on the oscillator HFXIN and HFXOUT pins.
• If conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins.
HFFREQ = {0} is not supported for HFXT crystal mode of operation.
Specifications
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Table 4-5. High-Frequency Crystal Oscillator, HFXT(1) (continued)
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
HFXTBYPASS = 0, HFFREQ = 1 (2) (3)
HFXT oscillator crystal
frequency, crystal mode
fHFXT
DCHFXT
fHFXT,SW
HFXT oscillator logiclevel square-wave input
frequency, bypass mode
DCHFXT,
SW
tSTART,HFXT
HFXT oscillator logiclevel square-wave input
duty cycle
Start-up time
(5)
TYP
MAX
4
8
HFXTBYPASS = 0, HFFREQ = 2 (3)
8.01
16
(3)
16.01
24
HFXTBYPASS = 0, HFFREQ = 3
HFXT oscillator duty
cycle
MIN
Measured at SMCLK, fHFXT = 16 MHz
40%
50%
0.9
HFXTBYPASS = 1, HFFREQ = 1 (4) (3)
4.01
8
HFXTBYPASS = 1, HFFREQ = 2 (4) (3)
8.01
16
HFXTBYPASS = 1, HFFREQ = 3 (4) (3)
16.01
24
40%
60%
fOSC = 4 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 0, HFFREQ = 1,
TJ = 25°C, CL,eff = 16 pF
3.0 V
fOSC = 24 MHz ,
HFXTBYPASS = 0, HFXTDRIVE = 3, HFFREQ = 3,
TJ = 25°C, CL,eff = 16 pF
3.0 V
MHz
60%
HFXTBYPASS = 1, HFFREQ = 0 (4) (3)
HFXTBYPASS = 1
UNIT
4
MHz
1.6
ms
0.6
CHFXIN
Integrated load
capacitance at HFXIN
terminaI (6) (7)
2
pF
CHFXOUT
Integrated load
capacitance at HFXOUT
terminaI (6) (7)
2
pF
fFault,HFXT
Oscillator fault
frequency (8) (9)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
26
0
800
kHz
Maximum frequency of operation of the entire device cannot be exceeded.
When HFXTBYPASS is set, HFXT circuits are automatically powered down. Input signal is a digital square wave with parametrics
defined in the Schmitt-trigger Inputs section of this data sheet. Duty cycle requirements are defined by DCHFXT, SW.
Includes start-up counter of 1024 clock cycles.
This represents all the parasitic capacitance present at the HFXIN and HFXOUT terminals, respectively, including parasitic bond and
package capacitance. The effective load capacitance, CL,eff can be computed as CIN x COUT / (CIN + COUT), where CIN and COUT is the
total capacitance at the HFXIN and HFXOUT terminals, respectively.
Requires external capacitors at both terminals to meet the effective load capacitance specified by crystal manufacturers. Recommended
effective load capacitance values supported are 14 pF, 16 pF, and 18 pF. Maximum shunt capacitance of 7 pF. The PCB adds
additional capacitance, so it must also be considered in the overall capacitance. Verify that the recommended effective load capacitance
of the selected crystal is met.
Frequencies above the MAX specification do not set the fault flag. Frequencies between the MIN and MAX might set the flag. A static
condition or stuck at fault condition set the flag.
Measured with logic-level input frequency but also applies to operation with crystals.
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Table 4-6 lists the characteristics of the DCO.
Table 4-6. DCO
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
1
±3.5%
MHz
fDCO1
DCO frequency range 1 MHz,
trimmed
Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 0,
DCORSEL = 1, DCOFSEL = 0
fDCO2.7
DCO frequency range 2.7 MHz,
trimmed
Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 1
2.667
±3.5%
MHz
fDCO3.5
DCO frequency range 3.5 MHz,
trimmed
Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 2
3.5
±3.5%
MHz
fDCO4
DCO frequency range 4 MHz,
trimmed
Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 3
4
±3.5%
MHz
fDCO5.3
DCO frequency range 5.3 MHz,
trimmed
Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 4,
DCORSEL = 1, DCOFSEL = 1
5.333
±3.5%
MHz
fDCO7
DCO frequency range 7 MHz,
trimmed
Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 5,
DCORSEL = 1, DCOFSEL = 2
7
±3.5%
MHz
fDCO8
DCO frequency range 8 MHz,
trimmed
Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 6,
DCORSEL = 1, DCOFSEL = 3
8
±3.5%
MHz
fDCO16
DCO frequency range 16 MHz,
trimmed
Measured at SMCLK, divide by 1,
DCORSEL = 1, DCOFSEL = 4
16
±3.5% (1)
MHz
fDCO21
DCO frequency range 21 MHz,
trimmed
Measured at SMCLK, divide by 2,
DCORSEL = 1, DCOFSEL = 5
21
±3.5% (1)
MHz
fDCO24
DCO frequency range 24 MHz,
trimmed
Measured at SMCLK, divide by 2,
DCORSEL = 1, DCOFSEL = 6
24
±3.5% (1)
MHz
Duty cycle
Measured at SMCLK, divide by 1,
no external divide, all
DCORSEL/DCOFSEL settings except
DCORSEL = 1, DCOFSEL = 5 and
DCORSEL = 1, DCOFSEL = 6
50%
52%
DCO jitter
Based on fsignal = 10 kHz and DCO
used for 12-bit SAR ADC sampling
source. This achieves >74 dB SNR due
to jitter (that is, it is limited by ADC
performance).
2
3
fDCO,DC
tDCO,
JITTER
dfDCO/dT
(1)
(2)
DCO temperature drift (2)
48%
3.0 V
0.01
ns
%/°C
After a wakeup from LPM1, LPM2, LPM3, or LPM4, the DCO frequency fDCO might exceed the specified frequency range for a few clock
cycles by up to 5% before settling into the specified steady-state frequency range.
Calculated using the box method: (MAX(–55°C to 95°C) – MIN(–55°C to 95°C)) / MIN(–55°C to 95°C) / (95°C – (–55°C))
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Table 4-7 lists the characteristics of the VLO.
Table 4-7. Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IVLO
Current consumption
fVLO
VLO frequency
Measured at ACLK
dfVLO/dT
VLO frequency temperature drift
Measured at ACLK (1)
dfVLO/dVCC
VLO frequency supply voltage drift
Measured at ACLK (2)
fVLO,DC
Duty cycle
Measured at ACLK
(1)
(2)
VCC
MIN
TYP
MAX
100
5
9.9
nA
15
0.2
50%
kHz
%/°C
0.7
40%
UNIT
%/V
60%
Calculated using the box method: (MAX(–55°C to 95°C) – MIN(–55°C to 95°C)) / MIN(–55°C to 95°C) / (95°C – (–55°C))
Calculated using the box method: (MAX(1.8 to 3.6 V) – MIN(1.8 to 3.6 V)) / MIN(1.8 to 3.6 V) / (3.6 V – 1.8 V)
Table 4-8 lists the characteristics of the MODOSC.
Table 4-8. Module Oscillator (MODOSC)
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IMODOSC
Current consumption
fMODOSC
MODOSC frequency
fMODOSC/dT
MODOSC frequency temperature drift (1)
fMODOSC/dVCC
MODOSC frequency supply voltage
drift (2)
DCMODOSC
Duty cycle
(1)
(2)
28
MIN
TYP
4.0
4.8
Enabled
Measured at SMCLK, divide by 1
MAX
UNIT
5.4
MHz
25
40%
μA
0.08
%/℃
1.4
%/V
50%
60%
Calculated using the box method: (MAX(–55°C to 95°C) – MIN(–55°C to 95°C)) / MIN(–55°C to 95°C) / (95°C – (–55°C))
Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)
Specifications
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4.13.4 Wake-up Characteristics
Table 4-9 lists the wake-up times.
Table 4-9. Wake-up Times From Low-Power Modes and Reset
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
TEST
CONDITIONS
PARAMETER
VCC
MIN
TYP
MAX
UNIT
6
10
μs
400 +
1.5 / fDCO
ns
tWAKE-UP FRAM
(Additional) wake-up time to activate the FRAM
in AM if previously disabled by the FRAM
controller or from an LPM if immediate
activation is selected for wakeup
tWAKE-UP LPM0
Wake-up time from LPM0 to active mode (1)
2.2 V, 3.0 V
tWAKE-UP LPM1
Wake-up time from LPM1 to active mode (1)
2.2 V, 3.0 V
6
tWAKE-UP LPM2
Wake-up time from LPM2 to active mode
(1)
2.2 V, 3.0 V
6
tWAKE-UP LPM3
Wake-up time from LPM3 to active mode (1)
2.2 V, 3.0 V
7
10
μs
tWAKE-UP LPM4
Wake-up time from LPM4 to active mode (1)
2.2 V, 3.0 V
7
10
μs
μs
tWAKE-UP LPM3.5 Wake-up time from LPM3.5 to active mode
(2)
tWAKE-UP-BOR
(1)
(2)
μs
2.2 V, 3.0 V
250
375
SVSHE = 1
2.2 V, 3.0 V
250
375
μs
SVSHE = 0
2.2 V, 3.0 V
1
1.5
ms
Wake-up time from a RST pin triggered reset to
active mode (2)
2.2 V, 3.0 V
318
400
μs
(2)
2.2 V, 3.0 V
1
1.5
ms
tWAKE-UP LPM4.5 Wake-up time from LPM4.5 to active mode (2)
tWAKE-UP-RST
μs
Wake-up time from power-up to active mode
The wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) to the first
externally observable MCLK clock edge. MCLK is sourced by the DCO and the MCLK divider is set to divide-by-1 (DIVMx = 000b,
fMCLK = fDCO). This time includes the activation of the FRAM during wakeup.
The wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) until the first
instruction of the user program is executed.
Table 4-10 lists the typical charge consumed during wakeup from various low-power modes.
Table 4-10. Typical Wake-up Charge (1)
also see Figure 4-7 and Figure 4-8
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
QWAKE-UP FRAM
Charge used for activating the FRAM in AM or during wake-up
from LPM0 if previously disabled by the FRAM controller.
15.1
nAs
QWAKE-UP LPM0
Charge used for wake-up from LPM0 to active mode (with
FRAM active)
4.4
nAs
QWAKE-UP LPM1
Charge used for wake-up from LPM1 to active mode (with
FRAM active)
15.1
nAs
QWAKE-UP LPM2
Charge used for wake-up from LPM2 to active mode (with
FRAM active)
15.3
nAs
QWAKE-UP LPM3
Charge used for wake-up from LPM3 to active mode (with
FRAM active)
16.5
nAs
QWAKE-UP LPM4
Charge used for wake-up from LPM4 to active mode (with
FRAM active)
16.5
nAs
76
nAs
(2)
QWAKE-UP LPM3.5
Charge used for wake-up from LPM3.5 to active mode
QWAKE-UP LPM4.5
Charge used for wake-up from LPM4.5 to active mode (2)
QWAKE-UP-RESET
Charge used for reset from RST or BOR event to active mode (2)
(1)
(2)
SVSHE = 1
77
SVSHE = 0
77.5
75
nAs
nAs
Charge used during the wake-up time from a given low-power mode to active mode. This does not include the energy required in active
mode (for example, for an interrupt service routine).
Charge required until start of user code. This does not include the energy required to reconfigure the device.
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4.13.4.1 Typical Characteristics, Average LPM Currents vs Wake-up Frequency
10000.00
LPM0
LPM1
Average Wake-up Current (µA)
1000.00
LPM2,XT12
LPM3,XT12
LPM3.5,XT12
100.00
10.00
1.00
0.10
0.001
0.01
0.1
1
10
100
1000
10000
100000
Wake-up Frequency (Hz)
NOTE: The average wake-up current does not include the energy required in active mode; for example, for an interrupt
service routine or to reconfigure the device.
Figure 4-7. Average LPM Currents vs Wake-up Frequency at 25°C
10000.00
LPM0
LPM1
Average Wake-up Current (µA)
1000.00
LPM2,XT12
LPM3,XT12
LPM3.5,XT12
100.00
10.00
1.00
0.10
0.001
0.01
0.1
1
10
100
1000
10000
100000
Wake-up Frequency (Hz)
NOTE: The average wake-up current does not include the energy required in active mode; for example, for an interrupt
service routine or to reconfigure the device.
Figure 4-8. Average LPM Currents vs Wake-up Frequency at 95°C
4.13.5 Peripherals
4.13.5.1 Digital I/Os
Table 4-11 lists the characteristics of the digital inputs.
30
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Table 4-11. Digital Inputs
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
2.2 V
1.2
TYP
MAX
1.65
3.0 V
1.65
2.25
2.2 V
0.55
1.00
3.0 V
0.75
1.35
2.2 V
0.44
0.98
3.0 V
0.60
1.30
UNIT
VIT+
Positive-going input threshold voltage
VIT–
Negative-going input threshold voltage
Vhys
Input voltage hysteresis (VIT+ – VIT–)
RPull
Pullup or pulldown resistor
For pullup: VIN = VSS
For pulldown: VIN = VCC
CI,dig
Input capacitance, digital only port pins
VIN = VSS or VCC
3
pF
CI,ana
Input capacitance, port pins with shared analog
VIN = VSS or VCC
functions (1)
5
pF
Ilkg(Px.y)
High-impedance input leakage current
See
t(int)
External interrupt timing (external trigger pulse
duration to set interrupt flag) (4)
Ports with interrupt capability
(see and Section 3.2)
t(RST)
External reset pulse duration on RST (5)
(1)
(2)
(3)
(4)
(5)
(2) (3)
20
35
50
V
V
V
kΩ
2.2 V,
3.0 V
–20
2.2 V,
3.0 V
20
ns
2.2 V,
3.0 V
2
µs
+20
nA
If the port pins PJ.4/LFXIN and PJ.5/LFXOUT are used as digital I/Os, they are connected by a 4-pF capacitor and a 35-MΩ resistor in
series. At frequencies of approximately 1 kHz and lower, the 4-pF capacitor can add to the pin capacitance of PJ.4/LFXIN and/or
PJ.5/LFXOUT.
The input leakage current is measured with VSS or VCC applied to the corresponding pins, unless otherwise noted.
The input leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor is
disabled.
An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It may be set by trigger signals
shorter than t(int).
Not applicable if RST/NMI pin configured as NMI.
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Table 4-12 lists the characteristics of the digital outputs.
Table 4-12. Digital Outputs
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TYP
I(OHmax) = –3 mA (2)
VCC –
0.60
VCC
I(OHmax) = –2 mA (1)
VCC –
0.25
VCC
VCC –
0.60
VCC
VSS
VSS +
0.25
I(OLmax) = 3 mA (2)
VSS
VSS +
0.60
I(OLmax) = 2 mA (1)
VSS
VSS +
0.25
VSS
VSS +
0.60
2.2 V
High-level output voltage
3.0 V
I(OHmax) = –6 mA (2)
I(OLmax) = 1 mA (1)
Low-level output voltage
3.0 V
I(OLmax) = 6 mA (2)
fPx.y
Port output frequency (with load) (3)
CL = 20 pF, RL
fPort_CLK
Clock output frequency (3)
ACLK, MCLK, or SMCLK at
configured output port
CL = 20 pF (5)
trise,dig
Port output rise time, digital only port pins
CL = 20 pF
tfall,dig
Port output fall time, digital only port pins
CL = 20 pF
trise,ana
Port output rise time, port pins with shared
analog functions
CL = 20 pF
tfall,ana
Port output fall time, port pins with shared
analog functions
CL = 20 pF
(1)
(2)
(3)
(4)
(5)
32
(4) (5)
2.2 V
16
3.0 V
16
2.2 V
16
3.0 V
16
UNIT
V
2.2 V
VOL
MAX
VCC
I(OHmax) = –1 mA (1)
VOH
MIN
VCC –
0.25
V
MHz
MHz
2.2 V
4
15
3.0 V
3
15
2.2 V
4
15
3.0 V
3
15
2.2 V
6
15
3.0 V
4
15
2.2 V
6
15
3.0 V
4
15
ns
ns
ns
ns
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop
specified.
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±100 mA to hold the maximum voltage
drop specified.
The port can output frequencies at least up to the specified limit - it might support higher frequencies.
A resistive divider with 2 × R1 and R1 = 1.6 kΩ between VCC and VSS is used as load. The output is connected to the center tap of the
divider. CL = 20 pF is connected from the output to VSS.
The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
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4.13.5.1.1 Typical Characteristics, Digital Outputs at 3.0 V and 2.2 V
100
50
25qC
95qC
40
35
30
25
20
15
10
80
70
60
50
40
30
20
10
5
0
0
0
0.25
0.5
0.75
1
1.25 1.5 1.75
Low-Level Output Voltage (V)
2
0
2.25
0.25
0.5
D005
VCC = 2.2 V
0.75
1
1.25 1.5 1.75
Low-Level Output Voltage (V)
2
2.25
D006
VCC = 3.0 V
Figure 4-9. Typical Low-Level Output Current vs Low-Level
Output Voltage
Figure 4-10. Typical Low-Level Output Current vs Low-Level
Output Voltage
0
0
25qC
95qC
-2.5
High-Level Output Current (mA)
High-Level Output Current (mA)
25qC
95qC
90
Low-Level Output Current (mA)
Low-Level Output Current (mA)
45
-5
-7.5
-10
-12.5
25qC
95qC
-5
-10
-15
-20
-25
-30
-15
0
0.25
0.5
0.75
1
1.25 1.5 1.75
High-Level Output Voltage (V)
2
2.25
0
0.25
0.5
D007
VCC = 2.2 V
0.75
1
1.25 1.5 1.75
High-Level Output Voltage (V)
2
2.25
D008
VCC = 3.0 V
Figure 4-11. Typical High-Level Output Current vs High-Level
Output Voltage
Figure 4-12. Typical High-Level Output Current vs High-Level
Output Voltage
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Table 4-13 lists the frequencies of the pin oscillator.
Table 4-13. Pin-Oscillator Frequency, Ports Px
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted) (see
Section 4.13.5.1.2)
PARAMETER
foPx.y
(1)
TEST CONDITIONS
Pin-oscillator frequency
VCC
MIN
TYP
MAX
UNIT
Px.y, CL = 10 pF (1)
3.0 V
1200
kHz
Px.y, CL = 20 pF (1)
3.0 V
650
kHz
CL is the external load capacitance connected from the output to VSS and includes all parasitic effects such as PCB traces.
1000
fitted
fitted
25°C
25°C
85°C
Pin Oscillator Frequency (kHz)
Pin Oscillator Frequency (kHz)
4.13.5.1.2 Typical Characteristics, Pin-Oscillator Frequency
85°C
100
100
10
100
External Load Capacitance (pF) (Including Board)
VCC = 2.2 V
One output active at a time.
Figure 4-13. Typical Oscillation Frequency vs Load Capacitance
34
1000
10
100
External Load Capacitance (pF) (Including Board)
VCC = 3.0 V
One output active at a time.
Figure 4-14. Typical Oscillation Frequency vs Load Capacitance
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4.13.5.2 Timer_A and Timer_B
Table 4-14 lists the characteristics of the Timer_A.
Table 4-14. Timer_A
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fTA
Timer_A input clock frequency
Internal: SMCLK or ACLK,
External: TACLK,
Duty cycle = 50% ±10%
tTA,cap
Timer_A capture timing
All capture inputs, minimum pulse
duration required for capture
VCC
2.2 V,
3.0 V
2.2 V,
3.0 V
MIN
TYP
MAX
UNIT
16
MHz
20
ns
Table 4-15 lists the characteristics of the Timer_B.
Table 4-15. Timer_B
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fTB
Timer_B input clock frequency
Internal: SMCLK or ACLK,
External: TBCLK,
Duty cycle = 50% ±10%
tTB,cap
Timer_B capture timing
All capture inputs, minimum pulse
duration required for capture
VCC
2.2 V,
3.0 V
2.2 V,
3.0 V
MIN
TYP
MAX
UNIT
16
MHz
20
ns
Specifications
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4.13.5.3 eUSCI
Table 4-16 lists the supported clock frequencies of the eUSCI in UART mode.
Table 4-16. eUSCI (UART Mode) Clock Frequency
PARAMETER
feUSCI
eUSCI input clock frequency
fBITCLK
BITCLK clock frequency
(equals baud rate in MBaud)
TEST CONDITIONS
MIN
Internal: SMCLK or ACLK,
External: UCLK,
Duty cycle = 50% ±10%
MAX
UNIT
16
MHz
4
MHz
Table 4-17 lists the characteristics of the eUSCI in UART mode.
Table 4-17. eUSCI (UART Mode)
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
UCGLITx = 0
UART receive deglitch time (1)
tt
UCGLITx = 1
2.2 V, 3.0 V
UCGLITx = 2
UCGLITx = 3
(1)
TYP
5
MAX
UNIT
30
20
90
35
160
50
220
ns
Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. Thus the selected deglitch
time can limit the max. useable baud rate. To ensure that pulses are correctly recognized their width should exceed the maximum
specification of the deglitch time.
Table 4-18 lists the supported clock frequencies of the eUSCI in SPI master mode.
Table 4-18. eUSCI (SPI Master Mode) Clock Frequency
PARAMETER
feUSCI
36
eUSCI input clock frequency
TEST CONDITIONS
Internal: SMCLK or ACLK,
Duty cycle = 50% ±10%
Specifications
MIN
MAX
UNIT
16
MHz
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Table 4-19 lists the characteristics of the eUSCI in SPI master mode.
Table 4-19. eUSCI (SPI Master Mode)
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
tSTE,LEAD
STE lead time, STE active to clock
UCSTEM = 1,
UCMODEx = 01 or 10
tSTE,LAG
STE lag time, last clock to STE inactive
UCSTEM = 1,
UCMODEx = 01 or 10
tSTE,ACC
STE access time, STE active to SIMO data
out
UCSTEM = 0,
UCMODEx = 01 or 10
2.2 V, 3.0 V
60
ns
tSTE,DIS
STE disable time, STE inactive to SOMI high UCSTEM = 0,
impedance
UCMODEx = 01 or 10
2.2 V, 3.0 V
80
ns
tSU,MI
SOMI input data setup time
tHD,MI
SOMI input data hold time
tVALID,MO
SIMO output data valid time (2)
UCLK edge to SIMO valid,
CL = 20 pF
tHD,MO
SIMO output data hold time (3)
CL = 20 pF
(1)
(2)
(3)
1
UCxCLK
cycles
1
UCxCLK
cycles
2.2 V
40
3.0 V
40
2.2 V
0
3.0 V
0
ns
ns
2.2 V
10
3.0 V
10
2.2 V
0
3.0 V
0
ns
ns
fUCxCLK = 1/2tLO/HI with tLO/HI = max(tVALID,MO(eUSCI) + tSU,SI(Slave), tSU,MI(eUSCI) + tVALID,SO(Slave)).
For the slave parameters tSU,SI(Slave) and tVALID,SO(Slave), see the SPI parameters of the attached slave.
Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams
in Figure 4-15 and Figure 4-16.
Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure 415 and Figure 4-16.
Specifications
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UCMODEx = 01
tSTE,LEAD
STE
tSTE,LAG
UCMODEx = 10
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tSU,MI
tHD,MI
SOMI
tHD,MO
tSTE,ACC
tSTE,DIS
tVALID,MO
SIMO
Figure 4-15. SPI Master Mode, CKPH = 0
UCMODEx = 01
tSTE,LEAD
STE
tSTE,LAG
UCMODEx = 10
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tHD,MI
tSU,MI
SOMI
tHD,MO
tSTE,ACC
tSTE,DIS
tVALID,MO
SIMO
Figure 4-16. SPI Master Mode, CKPH = 1
38
Specifications
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Table 4-20 lists the characteristics of the eUSCI in SPI slave mode.
Table 4-20. eUSCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
tSTE,LEAD
STE lead time, STE active to clock
tSTE,LAG
STE lag time, Last clock to STE inactive
tSTE,ACC
STE access time, STE active to SOMI data out
tSTE,DIS
STE disable time, STE inactive to SOMI high
impedance
tSU,SI
SIMO input data setup time
tHD,SI
SIMO input data hold time
tVALID,SO
SOMI output data valid time (2)
UCLK edge to SOMI valid,
CL = 20 pF
tHD,SO
SOMI output data hold time (3)
CL = 20 pF
(1)
(2)
(3)
VCC
MIN
2.2 V
45
3.0 V
40
2.2 V
2
3.0 V
3
MAX
ns
ns
2.2 V
45
3.0 V
40
2.2 V
50
3.0 V
45
2.2 V
4
3.0 V
4
2.2 V
7
3.0 V
7
35
35
3.0 V
0
ns
ns
3.0 V
0
ns
ns
2.2 V
2.2 V
UNIT
ns
ns
fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(eUSCI), tSU,MI(Master) + tVALID,SO(eUSCI)).
For the master parameters tSU,MI(Master) and tVALID,MO(Master), see the SPI parameters of the attached master.
Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams
in Figure 4-17 and Figure 4-18.
Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams inFigure 4-17
and Figure 4-18.
Specifications
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UCMODEx = 01
tSTE,LEAD
STE
tSTE,LAG
UCMODEx = 10
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tSU,SI
tLOW/HIGH
tHD,SI
SIMO
tHD,SO
tSTE,ACC
tSTE,DIS
tVALID,SO
SOMI
Figure 4-17. SPI Slave Mode, CKPH = 0
UCMODEx = 01
tSTE,LEAD
STE
tSTE,LAG
UCMODEx = 10
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tHD,SI
tSU,SI
SIMO
tHD,SO
tSTE,ACC
tVALID,SO
tSTE,DIS
SOMI
Figure 4-18. SPI Slave Mode, CKPH = 1
40
Specifications
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Table 4-21 lists the characteristics of the eUSCI in I2C mode.
Table 4-21. eUSCI (I2C Mode)
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted) (see Figure 4-19)
PARAMETER
TEST CONDITIONS
feUSCI
eUSCI input clock frequency
fSCL
SCL clock frequency
VCC
MIN
TYP
Internal: SMCLK or ACLK,
External: UCLK,
Duty cycle = 50% ±10%
2.2 V, 3.0 V
fSCL = 100 kHz
UNIT
16
MHz
400
kHz
4.0
tHD,STA
Hold time (repeated) START
tSU,STA
Setup time for a repeated START
tHD,DAT
Data hold time
2.2 V, 3.0 V
0
ns
tSU,DAT
Data setup time
2.2 V, 3.0 V
100
ns
fSCL > 100 kHz
fSCL = 100 kHz
fSCL > 100 kHz
fSCL = 100 kHz
tSU,STO
Setup time for STOP
tBUF
Bus free time between STOP and START
conditions
fSCL > 100 kHz
Pulse duration of spikes suppressed by
input filter
tSP
2.2 V, 3.0 V
0
MAX
2.2 V, 3.0 V
2.2 V, 3.0 V
4.7
4.0
4.7
1.3
UCGLITx = 0
50
2.2 V, 3.0 V
UCGLITx = 3
µs
0.6
fSCL > 100 kHz
UCGLITx = 2
µs
0.6
fSCL = 100 kHz
UCGLITx = 1
µs
0.6
µs
250
25
125
12.5
62.5
6.3
31.5
UCCLTOx = 1
tTIMEOUT
Clock low time-out
UCCLTOx = 2
27
2.2 V, 3.0 V
30
UCCLTOx = 3
tSU,STA
tHD,STA
ns
ms
33
tHD,STA
tBUF
SDA
tLOW
tHIGH
tSP
SCL
tSU,DAT
tSU,STO
tHD,DAT
Figure 4-19. I2C Mode Timing
Specifications
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4.13.5.4 LCD Controller
Table 4-22 lists the operating conditions of the LCD_C.
Table 4-22. LCD_C, Recommended Operating Conditions
MIN
NOM
MAX
UNIT
VCC,LCD_C,CP en,3.6
Supply voltage range,
charge pump enabled,
VLCD ≤ 3.6 V
LCDCPEN = 1, 0000b < VLCDx ≤ 1111b
(charge pump enabled, VLCD ≤ 3.6 V)
2.2
3.6
V
VCC,LCD_C,CP en,3.3
Supply voltage range,
charge pump enabled,
VLCD ≤ 3.3 V
LCDCPEN = 1, 0000b < VLCDx ≤ 1100b
(charge pump enabled, VLCD ≤ 3.3 V)
2.0
3.6
V
VCC,LCD_C,int.
bias
Supply voltage range,
internal biasing, charge
pump disabled
LCDCPEN = 0, VLCDEXT = 0
2.4
3.6
V
VCC,LCD_C,ext.
bias
Supply voltage range,
external biasing, charge
pump disabled
LCDCPEN = 0, VLCDEXT = 0
2.4
3.6
V
VCC,LCD_C,VLCDEXT
Supply voltage range,
external LCD voltage,
internal or external
biasing, charge pump
disabled
LCDCPEN = 0, VLCDEXT = 1
2.0
3.6
V
VLCDCAP
External LCD voltage at
LCDCAP, internal or
external biasing, charge
pump disabled
LCDCPEN = 0, VLCDEXT = 1
2.4
3.6
V
CLCDCAP
Capacitor value on
LCDCAP when charge
pump enabled
LCDCPEN = 1, VLCDx > 0000b (charge
pump enabled)
fACLK,in
ACLK input frequency
range
fLCD
LCD frequency range
fFRAME = 1/(2 × mux) × fLCD with mux = 1
(static) to 8
fFRAME,4mux
LCD frame frequency
range
fFRAME,8mux
4.7-20%
4.7
10+20%
µF
30
32.768
40
kHz
1024
Hz
fFRAME,4mux(MAX) = 1/(2 × 4) × fLCD(MAX)
= 1/(2 × 4) × 1024 Hz
128
Hz
LCD frame frequency
range
fFRAME,8mux(MAX) = 1/(2 × 4) × fLCD(MAX)
= 1/(2 × 8) × 1024 Hz
64
Hz
CPanel
Panel capacitance
fLCD = 1024 Hz, all common lines equally
loaded
10000
pF
VR33
Analog input voltage at
R33
LCDCPEN = 0, VLCDEXT = 1
VCC+0.2
V
VR23,1/3bias
Analog input voltage at
R23
LCDREXT = 1, LCDEXTBIAS = 1,
LCD2B = 0
VR13
VR03 + 2/3
× (VR33VR03)
VR33
V
VR13,1/3bias
Analog input voltage at
R13 with 1/3 biasing
LCDREXT = 1, LCDEXTBIAS = 1,
LCD2B = 0
VR03
VR03 + 1/3
× (VR33 –
VR03)
VR23
V
VR13,1/2bias
Analog input voltage at
R13 with 1/2 biasing
LCDREXT = 1, LCDEXTBIAS = 1,
LCD2B = 1
VR03
VR03 + 1/2
× (VR33 –
VR03)
VR33
V
VR03
Analog input voltage at
R03
R0EXT = 1
VSS
VLCD-VR03
Voltage difference
between VLCD and R03
LCDCPEN = 0, R0EXT = 1
2.4
VLCDREF
External LCD reference
voltage applied at
LCDREF
VLCDREFx = 01
0.8
42
Specifications
0
2.4
V
1.0
VCC+0.2
V
1.2
V
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Table 4-23 lists the characteristics of the LCD_C.
Table 4-23. LCD_C Electrical Characteristics
over operating junction temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
MAX
UNIT
VLCDx = 0000, VLCDEXT = 0
VLCD,1
LCDCPEN = 1, VLCDx = 0001b
2 V to 3.6 V
VLCD,2
LCDCPEN = 1, VLCDx = 0010b
2 V to 3.6 V
2.66
VLCD,3
LCDCPEN = 1, VLCDx = 0011b
2 V to 3.6 V
2.72
VLCD,4
LCDCPEN = 1, VLCDx = 0100b
2 V to 3.6 V
2.78
VLCD,5
LCDCPEN = 1, VLCDx = 0101b
2 V to 3.6 V
2.84
VLCD,6
LCDCPEN = 1, VLCDx = 0110b
2 V to 3.6 V
2.90
VLCD,7
LCDCPEN = 1, VLCDx = 0111b
2 V to 3.6 V
2.96
LCDCPEN = 1, VLCDx = 1000b
2 V to 3.6 V
3.02
VLCD,9
LCDCPEN = 1, VLCDx = 1001b
2 V to 3.6 V
3.08
VLCD,10
LCDCPEN = 1, VLCDx = 1010b
2 V to 3.6 V
3.14
VLCD,11
LCDCPEN = 1, VLCDx = 1011b
2 V to 3.6 V
3.20
VLCD,12
LCDCPEN = 1, VLCDx = 1100b
2 V to 3.6 V
3.26
VLCD,13
LCDCPEN = 1, VLCDx = 1101b
2.2 V to 3.6 V
3.32
VLCD,14
LCDCPEN = 1, VLCDx = 1110b
2.2 V to 3.6 V
3.38
VLCD,15
LCDCPEN = 1, VLCDx = 1111b
2.2 V to 3.6 V
VLCD,7,0.8
LCD voltage with external
reference of 0.8 V
LCDCPEN = 1, VLCDx = 0111b,
VLCDREFx = 01b,
VLCDREF = 0.8 V
2 V to 3.6 V
2.96 ×
0.8 V
V
VLCD,7,1.0
LCD voltage with external
reference of 1.0 V
LCDCPEN = 1, VLCDx = 0111b,
VLCDREFx = 01b,
VLCDREF = 1.0 V
2 V to 3.6 V
2.96 ×
1.0 V
V
VLCD,7,1.2
LCD voltage with external
reference of 1.2 V
LCDCPEN = 1, VLCDx = 0111b,
VLCDREFx = 01b,
VLCDREF = 1.2 V
2.2 V to 3.6 V
2.96 ×
1.2 V
V
ΔVLCD
Voltage difference between
consecutive VLCDx settings
ΔVLCD = VLCD,x - VLCD,x-1
with x = 0010b to 1111b
ICC,Peak,CP
Peak supply currents due to
charge pump activities
LCDCPEN = 1, VLCDx = 1111b
external, with decoupling capacitor
on DVCC supply ≥ 1 µF
2.2 V
600
tLCD,CP,on
Time to charge CLCD when
discharged
CLCD = 4.7 µF, LCDCPEN = 0→1,
VLCDx = 1111b
2.2 V
100
ICP,Load
Maximum charge pump load
current
LCDCPEN = 1, VLCDx = 1111b
2.2 V
RLCD,Seg
LCD driver output impedance,
segment lines
LCDCPEN = 0, ILOAD = ±10 µA
2.2 V
10
kΩ
RLCD,COM
LCD driver output impedance,
common lines
LCDCPEN = 0, ILOAD = ±10 µA
2.2 V
10
kΩ
VLCD,8
LCD voltage
2.4 V to 3.6 V
TYP
VLCD,0
VCC
2.49
3.32
40
2.60
3.44
60
2.72
V
3.6
80
µA
500
50
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4.13.5.5 ADC
Table 4-24 lists the input requirements of the ADC.
Table 4-24. 12-Bit ADC, Power Supply and Input Range Conditions
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Analog input voltage range (1)
V(Ax)
I(ADC12_B)
single-ended
mode
I(ADC12_B)
differential
mode
NOM
0
MAX
UNIT
AVCC
V
fADC12CLK = MODCLK, ADC12ON = 1,
ADC12PWRMD = 0, ADC12DIF = 0,
REFON = 0, ADC12SHTx = 0,
ADC12DIV = 0
3.0 V
145
199
(3)
2.2 V
140
190
175
245
(3)
fADC12CLK = MODCLK, ADC12ON = 1,
ADC12PWRMD = 0, ADC12DIF = 1,
REFON = 0, ADC12SHTx= 0,
ADC12DIV = 0
3.0 V
Operating supply current into
AVCC and DVCC terminals (2)
2.2 V
170
230
2.2 V
10
15
>2 V
0.5
4
<2 V
1
10
Input capacitance
Only one terminal Ax can be selected
at one time
RI
Input MUX ON resistance
0 V ≤ V(Ax) ≤ AVCC
44
MIN
Operating supply current into
AVCC and DVCC terminals (2)
CI
(1)
(2)
(3)
VCC
All ADC12 analog input pins Ax
µA
µA
pF
kΩ
The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results.
The internal reference supply current is not included in current consumption parameter I(ADC12_B).
Approximately 60% (typical) of the total current into the AVCC and DVCC terminals is from AVCC.
Specifications
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Table 4-25 lists the timing parameters of the ADC.
Table 4-25. 12-Bit ADC, Timing Parameters
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fADC12CLK
For specified performance of ADC12 linearity parameters
Frequency for specified with ADC12PWRMD = 0.
performance
If ADC12PWRMD = 1, the maximum is 1/4 of the value
shown here.
fADC12CLK
Frequency for reduced
performance
Linearity parameters have reduced performance
fADC12OSC
Internal oscillator (1)
ADC12DIV = 0, fADC12CLK = fADC12OSC from MODCLK
tCONVERT
Conversion time
REFON = 0, Internal oscillator,
fADC12CLK = fADC12OSC from MODCLK, ADC12WINC = 0
Turnon settling time of
the ADC
See
tADC12OFF
Time ADC must be off
before it can be turned
on again
tADC12OFF must be met to make sure that tADC12ON time
holds.
Sampling time
(1)
(2)
(3)
(4)
(5)
4
4.8
2.6
UNIT
5.4
MHz
kHz
5.4
MHz
3.5
µs
See
All pulse sample mode
(ADC12SHP = 1) and
extended sample mode
(ADC12SHP = 0) with
buffered reference
(ADC12VRSEL = 0x1, 0x3,
0x5, 0x7, 0x9, 0xB, 0xD,
0xF)
Extended sample mode
(ADC12SHP = 0) with
unbuffered reference
(ADC12VRSEL= 0x0, 0x2,
0x4, 0x6, 0xC, 0xE)
MAX
32.768
(3)
RS = 400 Ω, RI = 4 kΩ,
CI = 15 pF, Cpext= 8 pF (4)
TYP
0.45
External fADC12CLK from ACLK, MCLK, or SMCLK,
ADC12SSEL ≠ 0
tADC12ON
tSample
MIN
See
(2)
100
ns
100
ns
1
µs
(5)
µs
The ADC12OSC is sourced directly from MODOSC inside the UCS.
14 × 1 / fADC12CLK. If ADC12WINC = 1, then 15 × 1 / fADC12CLK.
The condition is that the error in a conversion started after tADC12ON is less than ±0.5 LSB. The reference and input signal are already
settled.
Approximately 10 Tau (τ) are needed to get an error of less than ±0.5 LSB: tsample = ln(2n+2) × (RS + RI) × (CI + Cpext), RS < 10 kΩ,
where n = ADC resolution = 12, RS = external source resistance, Cpext = external parasitic capacitance.
6 × 1 / fADC12CLK.
Specifications
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Table 4-26 lists the linearity parameters of the ADC when using an external reference.
Table 4-26. 12-Bit ADC, Linearity Parameters With External Reference (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Resolution
Number of no missing code
output-code bits
EI
Integral linearity error (INL) for
differential input
1.2 V ≤ VR+ – VR– ≤ AVCC
±2.4
LSB
EI
Integral linearity error (INL) for
single ended inputs
1.2 V ≤ VR+ – VR– ≤ AVCC
±2.8
LSB
ED
Differential linearity error (DNL)
+1.0
LSB
mV
Offset error (2)
EO
EG,ext
(3)
Gain error
12
–0.99
ADC12VRSEL = 0x2 or 0x4 without TLV calibration,
TLV calibration data can be used to improve the
parameter (4)
±0.5
±1.5
With external voltage reference without internal
buffer (ADC12VRSEL = 0x2 or 0x4) without TLV
calibration,
TLV calibration data can be used to improve the
parameter (4),
VR+ = 2.5 V, VR– = AVSS
±0.8
±2.5
LSB
With external voltage reference with internal buffer
(ADC12VRSEL = 0x3),
VR+ = 2.5 V, VR– = AVSS
ET,ext
(1)
(2)
(3)
(4)
46
Total unadjusted error
bits
±1
With external voltage reference without internal
buffer (ADC12VRSEL = 0x2 or 0x4) without TLV
calibration,
TLV calibration data can be used to improve the
parameter (4),
VR+ = 2.5 V, VR– = AVSS
±1.4
With external voltage reference with internal buffer
(ADC12VRSEL = 0x3),
VR+ = 2.5 V, VR– = AVSS
±1.4
±4.7
LSB
See Table 4-28 and Table 4-34 for more information on internal reference performance, and see Designing With the MSP430FR59xx
and MSP430FR58xx ADC for details on optimizing ADC performance for your application with the choice of internal or external
reference.
Offset is measured as the input voltage (at which ADC output transitions from 0 to 1) minus 0.5 LSB.
Offset increases as IR drop increases when VR– is AVSS.
For details, see the device descriptor in the MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, and MSP430FR69xx Family User's
Guide.
Specifications
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Table 4-27 lists the dynamic performance characteristics of the ADC with differential inputs and an
external reference.
Table 4-27. 12-Bit ADC, Dynamic Performance for Differential Inputs With External Reference (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
SNR
ENOB
(1)
(2)
TEST CONDITIONS
Signal-to-noise
Effective number of bits
(2)
MIN
TYP
MAX
UNIT
VR+ = 2.5 V, VR– = AVSS
71
dB
VR+ = 2.5 V, VR– = AVSS
11.2
bits
See Table 4-28 and Table 4-34 for more information on internal reference performance, and see Designing With the MSP430FR59xx
and MSP430FR58xx ADC for details on optimizing ADC performance for your application with the choice of internal or external
reference.
ENOB = (SINAD – 1.76) / 6.02
Table 4-28 lists the dynamic performance characteristics of the ADC with differential inputs and an internal
reference.
Table 4-28. 12-Bit ADC, Dynamic Performance for Differential Inputs With Internal Reference (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
ENOB
(1)
(2)
TEST CONDITIONS
Effective number of bits (2)
MIN
VR+ = 2.5 V, VR– = AVSS
TYP
MAX
10.7
UNIT
Bits
See Table 4-34 for more information on internal reference performance, and see Designing With the MSP430FR59xx and
MSP430FR58xx ADC for details on optimizing ADC performance for your application with the choice of internal or external reference.
ENOB = (SINAD – 1.76) / 6.02
Table 4-29 lists the dynamic performance characteristics of the ADC with single-ended inputs and an
external reference.
Table 4-29. 12-Bit ADC, Dynamic Performance for Single-Ended Inputs With External Reference (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SNR
Signal-to-noise
VR+ = 2.5 V, VR– = AVSS
68
dB
ENOB
Effective number of bits (2)
VR+ = 2.5 V, VR– = AVSS
10.7
bits
(1)
(2)
See Table 4-30 and Table 4-34 for more information on internal reference performance, and see Designing With the MSP430FR59xx
and MSP430FR58xx ADC for details on optimizing ADC performance for your application with the choice of internal or external
reference.
ENOB = (SINAD – 1.76) / 6.02
Table 4-30 lists the dynamic performance characteristics of the ADC with single-ended inputs and an
internal reference.
Table 4-30. 12-Bit ADC, Dynamic Performance for Single-Ended Inputs With Internal Reference (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
ENOB
(1)
(2)
TEST CONDITIONS
Effective number of bits
(2)
MIN
VR+ = 2.5 V, VR– = AVSS
TYP
MAX
10.4
UNIT
bits
See Table 4-34 for more information on internal reference performance, and see Designing With the MSP430FR59xx and
MSP430FR58xx ADC for details on optimizing ADC performance for your application with the choice of internal or external reference.
ENOB = (SINAD – 1.76) / 6.02
Table 4-31 lists the dynamic performance characteristics of the ADC using a 32.678-kHz clock.
Table 4-31. 12-Bit ADC, Dynamic Performance With 32.768-kHz Clock
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
ENOB
(1)
Effective number of bits
TEST CONDITIONS
(1)
Reduced performance with fADC12CLK from ACLK LFXT 32.768 kHz,
VR+ = 2.5 V, VR– = AVSS
TYP
10
UNIT
bits
ENOB = (SINAD – 1.76) / 6.02
Specifications
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Table 4-32 lists the characteristics of the temperature sensor and built-in V1/2 of the ADC.
Table 4-32. 12-Bit ADC, Temperature Sensor and Built-In V1/2
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
ADC12ON = 1, ADC12TCMAP = 1
2.5
mV/°C
(1) (2)
TCSENSOR
See
(2)
tSENSOR(sample)
Sample time required if ADCTCMAP = 1 and
channel (MAX – 1) is selected (3)
ADC12ON = 1, ADC12TCMAP = 1,
Error of conversion result ≤ 1 LSB
V1/2
AVCC voltage divider for ADC12BATMAP = 1
on MAX input channel
ADC12ON = 1, ADC12BATMAP = 1
IV
Current for battery monitor during sample time
ADC12ON = 1, ADC12BATMAP = 1
Sample time required if ADC12BATMAP = 1
and channel MAX is selected (4)
ADC12ON = 1, ADC12BATMAP = 1
tV 1/2 (sample)
(1)
(2)
(3)
(4)
UNIT
mV
See
1/2
MAX
700
VSENSOR
(also see Figure 4-20)
TYP
ADC12ON = 1, ADC12TCMAP = 1,
TA = 0°C
30
47.5%
µs
50% 52.5%
38
1.7
63
µA
µs
The temperature sensor offset can be as much as ±30°C. TI recommends a single-point calibration to minimize the offset error of the
built-in temperature sensor.
The device descriptor structure contains calibration values for 30°C ±3°C and 85°C ±3°C for each available reference voltage level. The
sensor voltage can be computed as VSENSE = TCSENSOR × (Temperature, °C) + VSENSOR, where TCSENSOR and VSENSOR can be
computed from the calibration values for higher accuracy.
The typical equivalent impedance of the sensor is 250 kΩ. The sample time required includes the sensor-on time tSENSOR(on).
The on-time tV1/2(on) is included in the sampling time tV1/2(sample); no additional on time is needed.
Typical Temperature Sensor Voltage (mV)
950
900
850
800
750
700
650
600
550
500
–40
–20
0
20
40
60
80
Ambient Temperature (°C)
Figure 4-20. Typical Temperature Sensor Voltage
48
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Table 4-33 lists the external reference requirements for the ADC.
Table 4-33. 12-Bit ADC, External Reference (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MAX
UNIT
1.2
AVCC
V
VR+ > VR–
0
1.2
V
VR+ > VR–
1.2
AVCC
V
VR+
Positive external reference voltage input
VeREF+ or VeREF- based on ADC12VRSEL bit
VR+ > VR–
VR–
Negative external reference voltage input
VeREF+ or VeREF- based on ADC12VRSEL bit
VR+ – VR–
Differential external reference voltage input
IVeREF+,
IVeREF-
IVeREF+,
IVeREF-
Static input current, singled-ended input mode
Static input current, differential input mode
MIN
TYP
1.2 V ≤ VeREF+ ≤ VAVCC, VeREF– = 0 V
fADC12CLK = 5 MHz, ADC12SHTx = 1h,
ADC12DIF = 0, ADC12PWRMD = 0
±10
1.2 V ≤ VeREF+ ≤ VAVCC , VeREF– = 0 V
fADC12CLK = 5 MHz, ADC12SHTx = 8h,
ADC12DIF = 0, ADC12PWRMD = 01
±2.5
1.2 V ≤ VeREF+ ≤ VAVCC, VeREF– = 0 V
fADC12CLK = 5 MHz, ADC12SHTx = 1h,
ADC12DIF = 1, ADC12PWRMD = 0
±20
1.2 V ≤ VeREF+ ≤ VAVCC , VeREF– = 0 V
fADC12CLK = 5 MHz, ADC12SHTx = 8h,
ADC12DIF = 1, ADC12PWRMD = 1
±5
µA
µA
IVeREF+
Peak input current with single-ended input
0 V ≤ VeREF+ ≤ VAVCC, ADC12DIF = 0
1.5
mA
IVeREF+
Peak input current with differential input
0 V ≤ VeREF+ ≤ VAVCC, ADC12DIF = 1
3
mA
CVeREF+/-
Capacitance at VeREF+ or VeREF- terminal
See
(1)
(2)
(2)
10
µF
The external reference is used during ADC conversion to charge and discharge the capacitance array. The input capacitance, CI, is also
the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy.
Connect two decoupling capacitors, 10 µF and 470 nF, to VeREF to decouple the dynamic current required for an external reference
source if it is used for the ADC12_B. Also see the MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, and MSP430FR69xx Family
User's Guide.
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4.13.5.6 Reference
Table 4-34 lists the characteristics of the built-in voltage reference.
Table 4-34. REF, Built-In Reference
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER
Positive built-in reference
voltage output
VREF+
TEST CONDITIONS
VCC
MIN
TYP
MAX
REFVSEL = {2} for 2.5 V, REFON = 1
2.7 V
2.5 ±1.5%
REFVSEL = {1} for 2.0 V, REFON = 1
2.2 V
2.0 ±1.5%
REFVSEL = {0} for 1.2 V, REFON = 1
1.8 V
1.2 ±1.8%
UNIT
V
Noise
RMS noise at VREF (1)
VOS_BUF_INT
VREF ADC BUF_INT buffer TJ = 25°C , ADC ON, REFVSEL = {0}, REFON
offset (2)
= 1, REFOUT = 0
–12
+12
mV
VOS_BUF_EXT
VREF ADC BUF_EXT
buffer offset (2)
TJ = 25°C, REFVSEL = {0} , REFOUT = 1,
REFON = 1 or ADC ON
–12
+12
mV
AVCC minimum voltage,
Positive built-in reference
active
REFVSEL = {0} for 1.2 V
1.8
AVCC(min)
REFVSEL = {1} for 2.0 V
2.2
REFVSEL = {2} for 2.5 V
2.7
Operating supply current
into AVCC terminal (3)
IREF+
IREF+_ADC_BUF
Operating supply current
into AVCC terminal (3)
From 0.1 Hz to 10 Hz, REFVSEL = {0}
110
V
REFON = 1
3V
8
15
ADC ON, REFOUT = 0, REFVSEL = {0, 1, 2},
ADC12PWRMD = 0,
3V
225
355
ADC ON, REFOUT = 1, REFVSEL = {0, 1, 2},
ADC12PWRMD = 0
3V
1030
1660
ADC ON, REFOUT = 0, REFVSEL = {0, 1, 2},
ADC12PWRMD = 1
3V
120
185
ADC ON, REFOUT = 1, REFVSEL = {0, 1, 2},
ADC12PWRMD = 1
3V
545
895
ADC OFF, REFON = 1, REFOUT = 1,
REFVSEL = {0, 1, 2}
3V
1085
IO(VREF+)
VREF maximum load
current, VREF+ terminal
REFVSEL = {0, 1, 2}, AVCC = AVCC(min) for
each reference level,
REFON = REFOUT = 1
ΔVout/ΔIo
(VREF+)
Load-current regulation,
VREF+ terminal
REFVSEL = {0, 1, 2},
IO(VREF+) = +10 µA or –1000 µA,
AVCC = AVCC(min) for each reference level,
REFON = REFOUT = 1
CVREF+/-
Capacitance at VREF+ and
VREF- terminals
REFON = REFOUT = 1
TCREF+
Temperature coefficient of
built-in reference
REFVSEL = {0, 1, 2}, REFON = REFOUT = 1,
TA = –55°C to 95°C (4)
18
PSRR_DC
Power supply rejection ratio
(DC)
AVCC = AVCC(min) to AVCC(max), TJ = 25°C,
REFVSEL = {0, 1, 2}, REFON = REFOUT = 1
120
PSRR_AC
Power supply rejection ratio
(AC)
dAVCC= 0.1 V at 1 kHz
3.0
tSETTLE
Settling time of reference
voltage (5)
AVCC = AVCC (min) to AVCC(max),
REFVSEL = {0, 1, 2}, REFON = 0 → 1
75
(1)
(2)
(3)
(4)
(5)
50
µV
–1000
+10
µA
µA
µA
2500 µV/mA
0
100
pF
50 ppm/K
400
µV/V
mV/V
80
µs
Internal reference noise affects ADC performance when ADC uses internal reference. See Designing With the MSP430FR59xx and
MSP430FR58xx ADC for details on optimizing ADC performance for your application with the choice of internal versus external
reference.
Buffer offset affects ADC gain error and thus total unadjusted error.
The internal reference current is supplied through terminal AVCC.
Calculated using the box method: (MAX(–55°C to 95°C) – MIN(–55°C to 95°C)) / MIN(–55°C to 95°C)/(95°C – (–55°C)).
The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB.
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4.13.5.7 Comparator
Table 4-35 lists the characteristics of the comparator.
Table 4-35. Comparator_E
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
CEPWRMD = 00, CEON = 1,
CERSx = 00 (fast)
IAVCC_COMP
CEPWRMD = 01, CEON = 1,
Comparator operating supply CERSx = 00 (medium)
current into AVCC, excludes
CEPWRMD = 10, CEON = 1,
reference resistor ladder
CERSx = 00 (slow), TJ = 30°C
2.2 V,
3.0 V
TYP
MAX
11
20
9
17
µA
0.6
CEPWRMD = 10, CEON = 1,
CERSx = 00 (slow), TJ = 95°C
IAVCC_REF
VREF
VIC
VOFFSET
Quiescent current of resistor
ladder into AVCC, including
REF module current
Reference voltage level
CEREFLx = 01, CERSx = 10, REFON = 0,
CEON = 0, CEREFACC = 0
CEREFLx = 01, CERSx = 10, REFON = 0,
CEON = 0, CEREFACC = 1
Input offset voltage
CIN
Input capacitance
RSIN
Series input resistance
tPD
Propagation delay, response
time
1.3
2.2 V,
3.0 V
12
15
5
7
µA
CERSx = 11, CEREFLx = 01, CEREFACC = 0
1.8 V
1.17
1.2
1.23
CERSx = 11, CEREFLx = 10, CEREFACC = 0
2.2 V
1.92
2.0
2.08
CERSx = 11, CEREFLx = 11, CEREFACC = 0
2.7 V
2.40
2.5
2.60
CERSx = 11, CEREFLx = 01, CEREFACC = 1
1.8 V
1.10
1.2
1.245
CERSx = 11, CEREFLx = 10, CEREFACC = 1
2.2 V
1.90
2.0
2.08
CERSx = 11, CEREFLx = 11, CEREFACC = 1
2.7 V
2.35
2.5
Common-mode input range
VCC-1
CEPWRMD = 00
–32
32
CEPWRMD = 01
–32
32
CEPWRMD = 10
–30
9
CEPWRMD = 10
9
tEN_CMP
Propagation delay with filter
active
Comparator enable time
mV
1
pF
3
50
kΩ
MΩ
CEPWRMD = 00, CEF = 0, Overdrive ≥ 20 mV
260
330
CEPWRMD = 01, CEF = 0, Overdrive ≥ 20 mV
350
460
CEPWRMD = 10, CEF = 0, Overdrive ≥ 20 mV
tPD,filter
V
30
CEPWRMD = 00 or CEPWRMD = 01
On (switch closed)
V
2.60
0
Off (switch open)
UNIT
ns
15
µs
700
1000
ns
CEPWRMD = 00 or 01, CEF = 1,
Overdrive ≥ 20 mV, CEFDLY = 01
1.0
1.8
CEPWRMD = 00 or 01, CEF = 1,
Overdrive ≥ 20 mV, CEFDLY = 10
2.0
3.5
CEPWRMD = 00 or 01, CEF = 1,
Overdrive ≥ 20 mV, CEFDLY = 11
4.0
7.0
CEON = 0 → 1, VIN+, VIN- from pins,
Overdrive ≥ 20 mV, CEPWRMD = 00
0.9
1.5
CEON = 0 → 1, VIN+, VIN- from pins,
Overdrive ≥ 20 mV, CEPWRMD = 01
0.9
1.5
CEON = 0 → 1, VIN+, VIN- from pins,
Overdrive ≥ 20 mV, CEPWRMD = 10
15
100
350
1500
µs
VIN ×
(n + 1)
/ 32
VIN ×
(n + 1.5)
/ 32
V
CEPWRMD = 00 or 01, CEF = 1,
Overdrive ≥ 20 mV, CEFDLY = 00
tEN_CMP_VREF
Comparator and reference
ladder and reference voltage
enable time
CEON = 0 → 1, CEREFLX = 10, CERSx = 10 or 11,
CEREF0 = CEREF1 = 0x0F,
Overdrive ≥ 20 mV
VCE_REF
Reference voltage for a
given tap
VIN = reference into resistor ladder,
n = 0 to 31
VIN ×
(n + 0.5)
/ 32
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4.13.5.8 Scan Interface
Table 4-36 lists the port timing characteristics of the ESI.
Table 4-36. Extended Scan Interface, Port Drive, Port Timing
over recommended operating junction temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
VOL(ESICHx)
Voltage drop due to ON-resistance
of excitation transistor (see
Figure 4-21)
I(ESICHx) = 2 mA, ESITEN = 1
3V
0.3
V
VOH(ESICHx)
Voltage drop due to ON-resistance
of damping transistor (1) (see
Figure 4-21)
I(ESICHx) = –200 µA, ESITEN = 1
3V
0.1
V
0
0.1
V
–50
50
nA
VOL(ESICOM)
I(ESICOM) = 3 mA, ESISH = 1
2.2 V, 3 V
IESICHx(tri-state)
V(ESICHx) = 0 V to AVCC, port
function disabled,
ESISH = 1
3V
(1)
ESICOM = 1.5 V, supplied externally (see Figure 4-22).
tEx(ESICHx)
ESIEX(tsm)
ESICH.x
tESICH(x)
Figure 4-21. P6.x/ESICHx Timing, ESICHx Function Selected
ESICOM
VOH(ESICHx)
Damping
Transistor
I(ESICHx)
ESICH.x
VOL(ESICHx)
Excitation
Transistor
Figure 4-22. Voltage Drop Due to ON-Resistance
52
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Table 4-37 lists the sample timing of the ESI.
Table 4-37. Extended Scan Interface, Sample Capacitor/Ri Timing
(1)
over operating junction temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
CSHC(ESICHx)
Sample capacitance on selected
ESICHx pin
ESIEx(tsm) = 1, ESISH = 1
2.2 V, 3 V
7
pF
Ri(ESICHx)
Serial input resistance at the
ESICHx pin
ESIEx(tsm) = 1, ESISH = 1
2.2 V, 3 V
1.5
kΩ
tHold
Maximum hold time (2)
ESISHTSM (3) = 1, measurement
sequence uses at least two ESICHx
inputs, ΔVsample < 3 mV
62
µs
(1)
(2)
(3)
The minimum sampling time (7.6 tau for 1/2 LSB accuracy) with maximum CSHC(ESICHx) and Ri(ESICHx) and Ri(source) is tsample(min) ≈ 7.6 ×
CSHC(ESICHx) × (Ri(ESICHx) + Ri(source)) with Ri(source) estimated at 3 kΩ, tsample(min) = 319 ns.
The sampled voltage at the sample capacitance varies less than 3 mV (ΔVsample) during the hold time tHold. If the voltage is sampled
after tHold, the sampled voltage may be any other value.
The control bit ESIVSS was renamed to ESISHTSM to avoid confusion with supply pin naming.
Table 4-38 lists the characteristics of the ESI VCC/2 generator.
Table 4-38. Extended Scan Interface, VCC/2 Generator
over operating junction temperature range (unless otherwise noted)
PARAMETER
ESI VCC/2
generator supply
voltage
VCC
IVMID
ESI VCC/2
generator
quiescent current
TEST CONDITIONS
AVCC = DVCC = ESIDVCC (connected
together), AVSS = DVSS = ESIDVSS
(connected together)
CL at ESICOM pin = 470 nF ±20%,
frefresh(ESICOM) = 32768 Hz,
T = 0°C to 95°C,
Rext = 1k in series to CL
VCC/2 refresh
frequency
Source clock = ACLK
V(ESICOM)
Output voltage at
pin ESICOM
CL at ESICOM pin = 470 nF ±20%,
ILoad = 1 µA
ton(ESICOM)
Time to reach 98%
CL at ESICOM pin = 470 nF ±20%,
after VCC / 2 is
frefresh(ESICOM) = 32768 Hz
switched on
tVccSettle
Settling time to
±VCC / 2560
(2 LSB) after AVCC
voltage change
(1)
MIN
TYP
2.2
MAX
3.6
370
UNIT
V
500
2.2 V, 3 V
nA
CL at ESICOM pin = 470 nF ±20%,
frefresh(ESICOM) = 32768 Hz,
T = –55°C to 95°C
frefresh(ESICOM)
(ESICOM)
VCC
370
2.2 V, 3 V
1600
32.768
AVCC / 2
–0.07
kHz
AVCC / 2
AVCC / 2 +
0.07
2.2 V, 3 V
1.7
6
ESIEN = 1, ESIVMIDEN (1) = 1,
ESISH = 0, AVCC = AVCC –100 mV,
frefresh(ESICOM) = 32768 Hz
2.2 V, 3 V
3
AVCC = AVCC + 100 mV,
frefresh(ESICOM) = 32768 Hz
2.2 V, 3 V
V
ms
ms
3
The control bit ESIVCC2 was renamed to ESIVMIDEN to avoid confusion with supply pin naming.
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Table 4-39 lists the characteristics of the ESI DAC.
Table 4-39. Extended Scan Interface, 12-Bit DAC
over operating junction temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
ESIDVCC = AVCC = DVCC
(connected together),
ESIDVSS = AVSS = DVSS
(connected together)
VCC
ESI DAC supply voltage
ICC
ESI 12-bit DAC operating supply
current into AVCC terminal (1)
MIN
2.2
3.6
10
27
3V
14
35
12
Integral nonlinearity
DNL
Differential nonlinearity
RL = 1000 MΩ, CL = 20 pF
With autozeroing
2.2 V, 3 V
–10
RL = 1000 MΩ, CL = 20 pF,
Without autozeroing
2.2 V, 3 V
RL = 1000 MΩ, CL = 20 pF,
With autozeroing
2.2 V, 3 V
±2
UNIT
V
µA
bit
+10
LSB
–10
+10
LSB
–10
+10
LSB
EOS
Offset error
With autozeroing
2.2 V, 3 V
EG
Gain error
With autozeroing
2.2 V, 3 V
ton(ESIDAC)
On time after AVCC of ESIDAC is
switched on
V+ESICA – VESIDAC = ±6 mV
2.2 V, 3 V
2
tSettle(ESIDAC)
Settling time
ESIDAC code = 0h → A0h
2.2 V, 3 V
2
ESIDAC code = A0h → 0h
2.2 V, 3 V
2
(1)
MAX
2.2 V
Resolution
INL
TYP
0
V
0.6%
µs
µs
This parameter covers one ESI 12-bit DAC, either ESI AFE1 12-bit DAC or ESI AFE2 12-bit DAC.
Table 4-40 lists the characteristics of the ESI comparator.
Table 4-40. Extended Scan Interface, Comparator
over operating junction temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
ESIDVCC = AVCC = DVCC
(connected together),
ESIDVSS = AVSS = DVSS
(connected together)
VCC
ESI comparator supply voltage
ICC
ESI comparator operating supply
current into AVCC terminal (1)
2.2 V, 3 V
VIC
Common-mode input voltage
range (2)
2.2 V, 3 V
VOffset
Input offset voltage
After autozeroing
2.2 V, 3 V
Temperature coefficient of VOffset
Without autozeroing
dVOffset/dT
(3)
After autozeroing
MIN
TYP
2.2
2.2 V, 3 V
MAX
UNIT
3.6
V
42
µA
0
VCC –
1
V
–1.5
1.5
25
40
2
mV
µV/°C
dVOffset/dVCC
VOffset supply voltage (VCC)
sensitivity (4)
Without autozeroing
0.3
After autozeroing
0.2
Vhys
Input voltage hysteresis
V+ terminal = V- terminal = 0.5 × VCC
2.2 V, 3 V
0.5
LSB
ton(ESICA)
On time after ESICA is switched
on
V+ESICA – VESIDAC = +6 mV,
V+ESICA = 0.5 × AVCC
2.2 V, 3 V
2.0
µs
tSettle(ESICA)
Settle time
V+ESICA – VESIDAC = –12 mV → 6 mV,
V+ESICA = 0.5 × AVCC
2.2 V, 3 V
3.0
µs
tautozero
Autozeroing time of comparator
Vinput = VCC / 2,
|Voffset| < 1 mV
2.2 V, 3 V
3.0
µs
(1)
(2)
(3)
(4)
54
mV/V
This parameter covers one single ESI comparator; either ESI AFE1 comparator or ESI AFE2 comparator.
The comparator output is reliable when at least one of the input signals is within the common-mode input voltage range.
Calculated using the box method: (MAX(–55°C to 95°C) – MIN(–55°C to 95°C)) / MIN(–55°C to 95°C) / (95°C – (–55°C))
Calculated using the box method: ABS((Voffset_Vcc_max – Voffset_Vcc_min)/(Vcc_max – Vcc_min))
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Table 4-41 lists the characteristics of the ESI oscillator and clock.
Table 4-41. Extended Scan Interface, ESICLK Oscillator and TSM Clock Signals
over operating junction temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
VCC
ESI oscillator supply voltage
ESIDVCC = AVCC = DVCC
(connected together),
ESIDVSS = AVSS = DVSS (connected
together)
ICC
ESI oscillator operating supply
current
fESIOSC= 4.8 MHz, ESIDIV1x = 00b,
ESICLKGON = 1, ESIEN = 1, no TSM
sequence running
fESIOSC_min
ESI oscillator at minimum setting
TJ = 30°C, ESICLKFQ = 000000
2.3
MHz
fESIOSC_max
ESI oscillator at maximum setting TJ = 30°C, ESICLKFQ = 111111
7.9
MHz
ton(ESIOSC)
Start-up time including
synchronization cycles
fESIOSC = 4.8 MHz
2.2 V, 3 V
400
ns
fESIOSC/dT
ESIOSC frequency temperature
drift (1)
fESIOSC= 4.8 MHz
2.2 V, 3 V
0.15
%/°C
fESIOSC/dVCC
ESIOSC frequency supply
voltage drift (2)
fESIOSC= 4.8 MHz
2.2 V, 3 V
2
%/V
fESILFCLK
TSM low-frequency state clock
fESIHFCLK
TSM high-frequency state clock
(1)
(2)
2.2
3.6
2.2 V
45
3V
50
32.768
0.25
V
µA
50
kHz
8
MHz
Calculated using the box method: (MAX(–55°C to 95°C) – MIN(–55°C to 95°C)) / MIN(–55°C to 95°C) / (95°C – (–55°C))
Calculated using the box method: (MAX(2.2 V to 3.6 V) – MIN(2.2 V to 3.6 V)) / MIN(2.2 V to 3.6 V) / (3.6 V – 2.2 V)
Specifications
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4.13.5.9 FRAM Controller
Table 4-42 lists the characteristics of the FRAM.
Table 4-42. FRAM
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
tRetention
IWRITE
Data retention duration
Erase current
tWRITE
Write time
tREAD
(1)
(2)
(3)
(4)
TJ = 25°C
100
TJ = 70°C
40
TJ = 95°C
10
Current to write into FRAM
IERASE
TYP
MAX
UNIT
1015
Read and write endurance
cycles
years
IREAD (1)
nA
(2)
nA
tREAD (3)
ns
n/a
Read time
NWAITSx = 0
1 / fSYSTEM (4)
NWAITSx = 1
2 / fSYSTEM (4)
ns
Writing to FRAM does not require a setup sequence or additional power when compared to reading from FRAM. The FRAM read
current IREAD is included in the active mode current consumption numbers IAM,FRAM.
FRAM does not require a special erase sequence.
Writing into FRAM is as fast as reading.
The maximum read (and write) speed is specified by fSYSTEM using the appropriate wait state settings (NWAITSx).
4.13.6 Emulation and Debug
Table 4-43 lists the characteristics of the JTAG and Spy-Bi-Wire interface.
Table 4-43. JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER
TEST
CONDITIONS
MIN
TYP
MAX
40
UNIT
IJTAG
Supply current adder when JTAG active (but not clocked)
2.2 V, 3.0 V
100
μA
fSBW
Spy-Bi-Wire input frequency
2.2 V, 3.0 V
0
10
MHz
tSBW,Low
Spy-Bi-Wire low clock pulse duration
2.2 V, 3.0 V
0.04
15
μs
tSBW, En
Spy-Bi-Wire enable time (TEST high to acceptance of first clock
edge) (1)
2.2 V, 3.0 V
110
μs
tSBW,Rst
Spy-Bi-Wire return to normal operation time
2.2 V
15
100
μs
0
16
MHz
16
MHz
50
kΩ
fTCK
TCK input frequency, 4-wire JTAG (2)
Rinternal
Internal pulldown resistance on TEST
fTCLK
TCLK/MCLK frequency during JTAG access, no FRAM access
(limited by fSYSTEM)
16
MHz
tTCLK,Low/High
TCLK low or high clock pulse duration, no FRAM access
25
ns
fTCLK,FRAM
TCLK/MCLK frequency during JTAG access, including FRAM access
(limited by fSYSTEM with no FRAM wait states)
4
MHz
tTCLK,FRAM,Low/High
TCLK low or high clock pulse duration, including FRAM accesses
(1)
(2)
56
3.0 V
0
2.2 V, 3.0 V
20
35
100
ns
Tools that access the Spy-Bi-Wire and BSL interfaces must wait for the tSBW,En time after the first transition of the TEST/SBWTCK pin
(low to high), before the second transition of the pin (high to low) during the entry sequence.
fTCK may be restricted to meet the timing requirements of the module selected.
Specifications
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5 Detailed Description
5.1
Overview
The TI MSP430FR5989-EP families of ultra-low-power microcontrollers consists of several devices
featuring different sets of peripherals. The architecture, combined with seven low-power modes, is
optimized to achieve extended battery life for example in flow metering applications. The devices features
a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code
efficiency.
The MSP430FR5989-EP device is a microcontroller configuration with an extended scan interface (ESI)
for background water, heat and gas volume metering together with up to five 16-bit timers, a comparator,
eUSCIs that support UART, SPI, and I2C, a hardware multiplier, an AES accelerator, DMA, an RTC
module with alarm capabilities, up to 83 I/O pins, and a high-performance 12-bit ADC.
5.2
CPU
The MSP430FR5989-EP CPU has a 16-bit RISC architecture that is highly transparent to the application.
All operations, other than program-flow instructions, are performed as register operations in conjunction
with seven addressing modes for source operand and four addressing modes for destination operand.
The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-toregister operation execution time is one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and
constant generator, respectively. The remaining registers are general-purpose registers.
Peripherals are connected to the CPU using data, address, and control buses. Peripherals can be
managed with all instructions.
The instruction set consists of the original 51 instructions with three formats and seven address modes
and additional instructions for the expanded address range. Each instruction can operate on word and
byte data.
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Operating Modes
The MSP430FR5989-EP devices have one active mode and seven software selectable low-power modes of operation (see Table 5-1). An interrupt
event can wake up the device from a low-power mode (LPM0 to LPM4), service the request, and restore back to the low-power mode on return
from the interrupt program. Low-power modes LPM3.5 and LPM4.5 disable the core supply to minimize power consumption.
Table 5-1. Operating Modes
MODE
AM
LPM0
ACTIVE,
FRAM OFF
ACTIVE
LPM1
LPM2
LPM3
LPM4
LPM3.5
CPU OFF
STANDBY
STANDBY
OFF
RTC ONLY
16 MHz
16 MHz
50 kHz
50 kHz
75 µA at 1 MHz
40 µA at 1 MHz
0.9 µA
0.4 µA
0.3 µA
0.35 µA
0.2 µA
0.02 µA
instant.
6 µs
6 µs
7 µs
7 µs
250 µs
250 µs
1000 µs
all
LF
I/O
Comp
LF
I/O
Comp
_
I/O
Comp
RTC
I/O
_
I/O
off
off
off
off
reset
reset
off
off
off
off
off
off
off
off
reset
reset
CPU OFF
(2)
(1)
Maximum system clock
Typical current consumption,
TJ = 25°C
16 MHz
103 µA/MHz
Typical wake-up time
65 µA/MHz
N/A
Wake-up events
N/A
CPU
all
on
FRAM
off
off (1)
on
standby (or off
(1)
)
0
High-frequency peripherals (4)
available
available
available
off
Low-frequency peripherals (4)
available
available
available
available
available
(5)
Unclocked peripherals (4)
available
available
available
available
available
(5)
MCLK
on
(16MHzMAX)
off
off
off
off
SMCLK
opt. (6)
(16MHzMAX)
opt. (6)
(16MHzMAX)
opt. (6)
(16MHzMAX)
off
ACLK
on
(50 kHzMAX)
on
(50 kHzMAX)
on
(50 kHzMAX)
External clock
optional
(16MHzMAX)
optional
(16MHzMAX)
optional
(16MHzMAX)
Full retention
(3)
LPM4.5
SHUTDOWN
WITH SVS
50 kHz
0
(3)
RTC
reset
reset
reset
off
off
off
off
off
off
off
on
(50 kHzMAX)
on
(50 kHzMAX)
off
off
off
optional
(50 kHzMAX)
optional
(50 kHzMAX)
optional
(50 kHzMAX)
off
off
yes
yes
yes
SVS
always
always
always
opt.
yes
Brownout
always
always
always
always
(8)
off
SHUTDOWN
WITHOUT SVS
available
yes
(7)
yes
(7)
opt.
(8)
opt.
(8)
always
always
(5)
no
opt.
no
(8)
always
on
(9)
off
(10)
always
(1)
(2)
FRAM disabled in FRAM controller
Disabling the FRAM through the FRAM controller decreases the LPM current consumption, but the wake-up time can increase. If the wake-up is for FRAM access (for example, to fetch an
interrupt vector), wake-up time is increased. If the wake-up is for an operation other than FRAM access (for example, DMA transfer to RAM), wake-up time is not increased.
(3) All clocks disabled
(4) See Table 5-2 for a detailed description of peripherals in high-frequency, low-frequency, or unclocked state.
(5) See Section 5.3.1, which describes the use of peripherals in LPM3 and LPM4.
(6) Controlled by SMCLKOFF
(7) Using the RAM controller, the RAM can be completely powered down to save leakage; however, all data are lost.
(8) Activated SVS (SVSHE = 1) results in higher current consumption. SVS is not included in typical current consumption.
(9) SVSHE = 1
(10) SVSHE = 0
58
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SLASEC9 – APRIL 2017
Peripherals in Low-Power Modes
Peripherals can be in different states that impact the achievable power modes of the device. The states
depend on the operational modes of the peripherals. The states are:
• A peripheral is in a high-frequency state if it requires or uses a clock with a "high" frequency of more
than 50 kHz.
• A peripheral is in a low-frequency state if it requires or uses a clock with a "low" frequency of 50 kHz or
less.
• A peripheral is in an unclocked state if it does not require or use an internal clock.
If the CPU requests a power mode that does not support the current state of all active peripherals, the
device does not enter the requested power mode and instead enters a power mode that still supports the
current state of the peripherals, unless an external clock is used. If an external clock is used, the
application must ensure that the correct frequency range for the requested power mode is selected.
Table 5-2. Peripheral States
PERIPHERAL
WDT
IN HIGH-FREQUENCY STATE (1)
IN LOW-FREQUENCY STATE (2)
IN UNCLOCKED STATE (3)
Clocked by SMCLK
Clocked by ACLK
Not applicable
(4)
Not applicable
Not applicable
Waiting for a trigger
RTC_C
Not applicable
Clocked by LFXT
Not applicable
LCD_C
Not applicable
Clocked by ACLK or VLOCLK
Not applicable
Timer_A TAx
Clocked by SMCLK or
clocked by external clock >50 kHz
Clocked by ACLK or
clocked by external clock ≤50 kHz.
Clocked by external clock ≤50 kHz.
Timer_B TBx
Clocked by SMCLK or
clocked by external clock >50 kHz
Clocked by ACLK or
clocked by external clock ≤50 kHz
Clocked by external clock ≤50 kHz
eUSCI_Ax in
UART mode
Clocked by SMCLK
Clocked by ACLK
Waiting for first edge of START bit
eUSCI_Ax in SPI
master mode
Clocked by SMCLK
Clocked by ACLK
Not applicable
eUSCI_Ax in SPI
slave mode
Clocked by external clock >50 kHz
Clocked by external clock ≤50 kHz
Clocked by external clock ≤50 kHz
eUSCI_Bx in I2C
master mode
Clocked by SMCLK or
clocked by external clock >50 kHz
Clocked by ACLK or
clocked by external clock ≤50 kHz
Not applicable
eUSCI_Bx in I2C
slave mode
Clocked by external clock >50 kHz
Clocked by external clock ≤50 kHz
Waiting for START condition or
clocked by external clock ≤50 kHz
eUSCI_Bx in SPI
master mode
Clocked by SMCLK
Clocked by ACLK
Not applicable
eUSCI_Bx in SPI
slave mode
Clocked by external clock >50 kHz
Clocked by external clock ≤50 kHz
Clocked by external clock ≤50 kHz
ESI
Clocked by SMCLK
Clocked by ACLK or ESIOSC
Not applicable
ADC12_B
Clocked by SMCLK or by MODOSC
Clocked by ACLK
Waiting for a trigger
REF_A
Not applicable
Not applicable
Always
COMP_E
Not applicable
Not applicable
Always
(5)
Not applicable
Not applicable
Not applicable
MPY (5)
Not applicable
Not applicable
Not applicable
AES (5)
Not applicable
Not applicable
Not applicable
DMA
CRC
(1)
(2)
(3)
(4)
(5)
Peripherals are in a state that requires or uses a clock with a "high" frequency of more than 50 kHz.
Peripherals are in a state that requires or uses a clock with a "low" frequency of 50 kHz or less.
Peripherals are in a state that does not require or does not use an internal clock.
The DMA always transfers data in active mode but can wait for a trigger in any low-power mode. A DMA trigger during a low-power
mode will cause a temporary transition into active mode for the time of the transfer.
Operates only during active mode and will delay the transition into a low-power mode until its operation is completed.
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Idle Currents of Peripherals in LPM3 and LPM4
Most peripherals can be activated to be operational in LPM3 if clocked by ACLK. Some modules are even
operational in LPM4 because they do not require a clock to operate (for example, the comparator).
Activating a peripheral in LPM3 or LPM4 increases the current consumption due to its active supply
current contribution but also due to an additional idle current. To limit the idle current adder certain
peripherals are group together. To achieve optimal current consumption try to use modules within one
group and to limit the number of groups with active modules. Table 5-3 lists the group for each peripheral.
Modules not listed in this table are either already included in the standard LPM3 current consumption
specifications or cannot be used in LPM3 or LPM4.
The idle current adder is very small at room temperature (25°C) but increases at high temperatures
(95°C). See the IIDLE parameters in Section 4.7 for details.
Table 5-3. Peripheral Groups
GROUP A
GROUP B
GROUP C
GROUP D
Timer TA0
Timer TA1
Timer TA2
Timer TA3
Comparator
Extended Scan Interface
(ESI)
Timer B0
LCD_C
ADC12_B
eUSCI_A0
eUSCI_A1
REF_A
eUSCI_B0
eUSCI_B1
60
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Interrupt Vector Table and Signatures
The interrupt vectors, the power-up start address and signatures are in the address range 0FFFFh to
0FF80h. Figure 5-1 summarizes the content of this address range.
Reset Vector
0FFFFh
BSL Password
Interrupt
Vectors
0FFE0h
JTAG Password
Reserved
Signatures
0FF88h
0FF80h
Figure 5-1. Interrupt Vectors, Signatures, and Passwords
The power-up start address or reset vector is located at 0FFFFh to 0FFFEh. It contains the 16-bit address
pointing to the start address of the application program.
The interrupt vectors start at 0FFFDh and extend to lower addresses. Each vector contains the 16-bit
address of the appropriate interrupt-handler instruction sequence. Table 5-4 shows the device-specific
interrupt vector locations.
The vectors programmed into the address range from 0FFFFh to 0FFE0h are used as the BSL password
(if enabled by the corresponding signature).
The signatures are located at 0FF80h and extend to higher addresses. Signatures are evaluated during
device start-up. Table 5-5 shows the device-specific signature locations.
A JTAG password can be programmed starting at address 0FF88h and extending to higher addresses.
The password can extend into the interrupt vector locations using the interrupt vector addresses as
additional bits for the password. The length of the JTAG password depends on the JTAG signature.
See the System Resets, Interrupts, and Operating Modes, System Control Module (SYS) chapter in the
MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, MSP430FR69xx Family User's Guide for details.
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Table 5-4. Interrupt Sources, Flags, and Vectors
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM
INTERRUPT
WORD
ADDRESS
PRIORITY
System Reset
Power up, Brownout, Supply
Supervisor
External Reset RST
Watchdog time-out (watchdog
mode)
WDT, FRCTL MPU, CS, PMM
password violation
FRAM uncorrectable bit error
detection
MPU segment violation
FRAM access time error
Software POR, BOR
SVSHIFG
PMMRSTIFG
WDTIFG
WDTPW, FRCTLPW, MPUPW, CSPW, PMMPW
UBDIFG
MPUSEGIIFG, MPUSEG1IFG, MPUSEG2IFG,
MPUSEG3IFG
ACCTEIFG
PMMPORIFG, PMMBORIFG
(SYSRSTIV) (1) (2)
Reset
0FFFEh
Highest
(Non)maskable
0FFFCh
System NMI
Vacant memory access
JTAG mailbox
FRAM bit error detection
MPU segment violation
(1)
(2)
(3)
62
VMAIFG
JMBINIFG, JMBOUTIFG
CBDIFG, UBDIFG
MPUSEGIIFG, MPUSEG1IFG, MPUSEG2IFG,
MPUSEG3IFG
(SYSSNIV) (1) (3)
User NMI
External NMI
Oscillator fault
NMIIFG, OFIFG
(SYSUNIV) (1) (3)
(Non)maskable
0FFFAh
Comparator_E
Comparator_E interrupt flags
(CEIV) (1)
Maskable
0FFF8h
Timer_B TB0
TB0CCR0.CCIFG
Maskable
0FFF6h
Timer_B TB0
TB0CCR1.CCIFG to TB0CCR6.CCIFG,
TB0CTL.TBIFG
(TB0IV) (1)
Maskable
0FFF4h
Watchdog timer
(interval timer mode)
WDTIFG
Maskable
0FFF2h
Extended Scan IF
ESIIFG0 to ESIIFG8
(ESIIV) (1)
Maskable
0FFF0h
eUSCI_A0 receive or transmit
UCA0IFG: UCRXIFG, UCTXIFG (SPI mode)
UCA0IFG:UCSTTIFG, UCTXCPTIFG, UCRXIFG,
UCTXIFG (UART mode)
(UCA0IV) (1)
Maskable
0FFEEh
eUSCI_B0 receive or transmit
UCB0IFG: UCRXIFG, UCTXIFG (SPI mode)
UCB0IFG: UCALIFG, UCNACKIFG, UCSTTIFG,
UCSTPIFG, UCRXIFG0, UCTXIFG0, UCRXIFG1,
UCTXIFG1, UCRXIFG2, UCTXIFG2, UCRXIFG3,
UCTXIFG3, UCCNTIFG, UCBIT9IFG (I2C mode)
(UCB0IV) (1)
Maskable
0FFECh
ADC12_B
ADC12IFG0 to ADC12IFG31
ADC12LOIFG, ADC12INIFG, ADC12HIIFG,
ADC12RDYIFG, ADC12OVIFG, ADC12TOVIFG
(ADC12IV) (1)
Maskable
0FFEAh
Timer_A TA0
TA0CCR0.CCIFG
Maskable
0FFE8h
Timer_A TA0
TA0CCR1.CCIFG to TA0CCR2.CCIFG,
TA0CTL.TAIFG
(TA0IV) (1)
Maskable
0FFE6h
eUSCI_A1 receive or transmit
UCA1IFG:UCRXIFG, UCTXIFG (SPI mode)
UCA1IFG:UCSTTIFG, UCTXCPTIFG, UCRXIFG,
UCTXIFG (UART mode)
(UCA1IV) (1)
Maskable
0FFE4h
Multiple source flags
A reset is generated if the CPU tries to fetch instructions from within peripheral space
(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.
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Table 5-4. Interrupt Sources, Flags, and Vectors (continued)
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM
INTERRUPT
WORD
ADDRESS
eUSCI_B1 receive or transmit)
UCB1IFG: UCRXIFG, UCTXIFG (SPI mode)
UCB1IFG: UCALIFG, UCNACKIFG, UCSTTIFG,
UCSTPIFG, UCRXIFG0, UCTXIFG0, UCRXIFG1,
UCTXIFG1, UCRXIFG2, UCTXIFG2, UCRXIFG3,
UCTXIFG3, UCCNTIFG, UCBIT9IFG (I2C mode)
(UCB1IV) (1)
Maskable
0FFE2h
DMA
DMA0CTL.DMAIFG, DMA1CTL.DMAIFG,
DMA2CTL.DMAIFG
(DMAIV) (1)
Maskable
0FFE0h
Timer_A TA1
TA1CCR0.CCIFG
Maskable
0FFDEh
Timer_A TA1
TA1CCR1.CCIFG to TA1CCR2.CCIFG,
TA1CTL.TAIFG
(TA1IV) (1)
Maskable
0FFDCh
I/O Port P1
P1IFG.0 to P1IFG.7
(P1IV) (1)
Maskable
0FFDAh
Timer_A TA2
TA2CCR0.CCIFG
Maskable
0FFD8h
Timer_A TA2
TA2CCR1.CCIFG
TA2CTL.TAIFG
(TA2IV) (1)
Maskable
0FFD6h
I/O Port P2
P2IFG.0 to P2IFG.7
(P2IV) (1)
Maskable
0FFD4h
Timer_A TA3
TA3CCR0.CCIFG
Maskable
0FFD2h
Timer_A TA3
TA3CCR1.CCIFG
TA3CTL.TAIFG
(TA3IV) (1)
Maskable
0FFD0h
I/O Port P3
P3IFG.0 to P3IFG.7
(P3IV) (1)
Maskable
0FFCEh
I/O Port P4
P4IFG.0 to P4IFG.7
(P4IV) (1)
Maskable
0FFCCh
Maskable
0FFCAh
LCD_C
(Reserved on MSP430FR5xxx)
LCD_C interrupt flags (LCDCIV)
(1)
RTC_C
RTCRDYIFG, RTCTEVIFG, RTCAIFG,
RT0PSIFG, RT1PSIFG, RTCOFIFG
(RTCIV) (1)
Maskable
0FFC8h
AES
AESRDYIFG
Maskable
0FFC6h
PRIORITY
Lowest
Table 5-5. Signatures
SIGNATURE
WORD ADDRESS
IP Encapsulation Signature2
IP Encapsulation Signature1
(1)
(1)
0FF8Ah
0FF88h
BSL Signature2
0FF86h
BSL Signature1
0FF84h
JTAG Signature2
0FF82h
JTAG Signature1
0FF80h
Must not contain 0AAAAh if used as JTAG password and IP encapsulation functionality is not desired.
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Bootloader (BSL)
The BSL enables programming of the FRAM or RAM using a UART serial interface (FRxxxx devices) or
an I2C interface (FRxxxx1 devices). Access to the device memory through the BSL is protected by an
user-defined password. Table 5-6 lists the BSL pin requirements. BSL entry requires a specific entry
sequence on the RST/NMI/SBWTDIO and TEST/SBWTCK pins. For complete description of the features
of the BSL and its implementation, see MSP430 Programming With the Bootloader (BSL).
Table 5-6. BSL Pin Requirements and Functions
5.6
5.6.1
DEVICE SIGNAL
BSL FUNCTION
RST/NMI/SBWTDIO
Entry sequence signal
TEST/SBWTCK
Entry sequence signal
P2.0
Devices with UART BSL (FRxxxx): Data transmit
P2.1
Devices with UART BSL (FRxxxx): Data receive
P1.6
Devices with I2C BSL (FRxxxx1): Data
P1.7
Devices with I2C BSL (FRxxxx1): Clock
VCC
Power supply
VSS
Ground supply
JTAG Operation
JTAG Standard Interface
The MSP430 family supports the standard JTAG interface, which requires four signals for sending and
receiving data. The JTAG signals are shared with general-purpose I/Os. The TEST/SBWTCK pin is used
to enable the JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO signal is required to
interface with MSP430 development tools and device programmers. Table 5-7 lists the JTAG pin
requirements. For details on interfacing to development tools and device programmers, see the MSP430
Hardware Tools User's Guide. For details on the JTAG implementation in MSP MCUs, see MSP430
Programming With the JTAG Interface.
Table 5-7. JTAG Pin Requirements and Functions
5.6.2
DEVICE SIGNAL
DIRECTION
FUNCTION
PJ.3/TCK
IN
JTAG clock input
PJ.2/TMS
IN
JTAG state control
PJ.1/TDI/TCLK
IN
JTAG data input, TCLK input
PJ.0/TDO
OUT
JTAG data output
TEST/SBWTCK
IN
Enable JTAG pins
RST/NMI/SBWTDIO
IN
External reset
VCC
Power supply
VSS
Ground supply
Spy-Bi-Wire Interface
In addition to the standard JTAG interface, the MSP430 family supports the 2-wire Spy-Bi-Wire interface.
Spy-Bi-Wire can be used to interface with MSP430 development tools and device programmers. Table 5-8
lists the Spy-Bi-Wire interface pin requirements. For details on interfacing to development tools and device
programmers, see the MSP430 Hardware Tools User's Guide. For details on the SBW implementation in
MSP MCUs, see MSP430 Programming With the JTAG Interface.
64
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Table 5-8. Spy-Bi-Wire Pin Requirements and Functions
5.7
DEVICE SIGNAL
DIRECTION
FUNCTION
TEST/SBWTCK
IN
Spy-Bi-Wire clock input
RST/NMI/SBWTDIO
IN, OUT
Spy-Bi-Wire data input/output
VCC
Power supply
VSS
Ground supply
FRAM
The FRAM can be programmed through the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in system by the
CPU. Features of the FRAM include:
• Ultra-low-power ultra-fast-write nonvolatile memory
• Byte and word access capability
• Programmable wait state generation
• Error correction coding (ECC)
NOTE
Wait States
For MCLK frequencies > 8 MHz, wait states must be configured following the flow described
in the "FRAM Controller (FRCTRL)" chapter, section "Wait State Control" of the
MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, MSP430FR69xx Family User's Guide.
For important software design information regarding FRAM including but not limited to partitioning the
memory layout according to application-specific code, constant, and data space requirements, the use of
FRAM to optimize application energy consumption, and the use of the memory protection unit (MPU) to
maximize application robustness by protecting the program code against unintended write accesses, see
MSP430™ FRAM Technology – How To and Best Practices.
5.8
RAM
The RAM is made up of one sector. The sector can be completely powered down in LPM3 and LPM4 to
save leakage; however, all data is lost during shutdown.
5.9
Tiny RAM
The Tiny RAM can be used to hold data or a very small stack if the complete RAM is powered down in
LPM3 and LPM4.
5.10 Memory Protection Unit Including IP Encapsulation
The FRAM can be protected from inadvertent CPU execution, read or write access by the MPU. Features
of the MPU include:
• IP Encapsulation with programmable boundaries (prevents reads from "outside" like JTAG or non-IP
software) in steps of 1KB.
• Main memory partitioning programmable up to three segments in steps of 1KB.
• The access rights of each segment (main and information memory) can be individually selected.
• Access violation flags with interrupt capability for easy servicing of access violations.
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5.11 Peripherals
Peripherals are connected to the CPU through data, address, and control buses. Peripherals can be
managed using all instructions. For complete module descriptions, see the MSP430FR58xx,
MSP430FR59xx, MSP430FR68xx, MSP430FR69xx Family User's Guide.
5.11.1 Digital I/O
Up to eleven 8-bit I/O ports are implemented:
• All individual I/O bits are independently programmable.
• Any combination of input, output, and interrupt conditions is possible.
• Programmable pullup or pulldown on all ports.
• Edge-selectable interrupt and LPM3.5 and LPM4.5 wake-up input capability is available for all pins of
ports P1, P2, P3, and P4.
• Read and write access to port-control registers is supported by all instructions.
• Ports can be accessed byte-wise or word-wise in pairs.
• Capacitive touch functionality is supported on all pins of ports P1 to P10 and PJ.
• No cross-currents during start-up
NOTE
Configuration of Digital I/Os After BOR Reset
To prevent any cross-currents during start-up of the device all port pins are high-impedance
with Schmitt triggers and their module functions disabled. To enable the I/O functionality after
a BOR reset the ports must be configured first and then the LOCKLPM5 bit must be cleared.
For details, see the Configuration After Reset section of the Digital I/O chapter in the
MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, MSP430FR69xx Family User's Guide.
5.11.2 Oscillator and Clock System (CS)
The clock system includes support for a 32-kHz watch crystal oscillator XT1 (LF), an internal very-lowpower low-frequency oscillator (VLO), an integrated internal digitally controlled oscillator (DCO), and a
high-frequency crystal oscillator XT2 (HF). The clock system module is designed to meet the requirements
of both low system cost and low power consumption. A fail-safe mechanism exists for all crystal sources.
The clock system module provides the following clock signals:
• Auxiliary clock (ACLK), sourced from a 32-kHz watch crystal (LFXT1), the internal low-frequency
oscillator (VLO), or a digital external low frequency (<50 kHz) clock source.
• Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced from a high-frequency
crystal (HFXT2), the internal digitally controlled oscillator DCO, a 32-kHz watch crystal (LFXT1), the
internal low-frequency oscillator (VLO), or a digital external clock source.
• Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be
sourced by same sources made available to MCLK.
5.11.3 Power-Management Module (PMM)
The primary functions of the PMM are:
•
•
•
66
Supply regulated voltages to the core logic
Supervise voltages that are connected to the device (at DVCC pins)
Give reset signals to the device during power on and power off
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5.11.4 Hardware Multiplier (MPY)
The multiplication operation is supported by a dedicated peripheral module. The module performs
operations with 32-, 24-, 16-, and 8-bit operands. The module supports signed and unsigned multiplication
as well as signed and unsigned multiply-and-accumulate operations.
5.11.5 Real-Time Clock (RTC_C)
The RTC_C module contains an integrated real-time clock (RTC) with the following features implemented:
• Calendar mode with leap year correction
• General-purpose counter mode
The internal calendar compensates months with less than 31 days and includes leap year correction. The
RTC_C also supports flexible alarm functions and offset-calibration hardware. RTC operation is available
in LPM3.5 modes to minimize power consumption.
5.11.6 Watchdog Timer (WDT_A)
The primary function of the WDT_A module is to perform a controlled system restart after a software
problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function
is not needed in an application, the module can be configured as an interval timer and can generate
interrupts at selected time intervals. Table 5-9 lists the clocks that can be used by the WDT.
NOTE
In watchdog mode, the watchdog timer prevents entry into LPM3.5 or LPM4.5 because this
would deactivate the watchdog.
Table 5-9. WDT_A Clocks
WDTSSEL
NORMAL OPERATION
(WATCHDOG AND INTERVAL TIMER MODE)
00
SMCLK
01
ACLK
10
VLOCLK
11
LFMODCLK
5.11.7 System Module (SYS)
The SYS module handles many of the system functions within the device. These system functions include
power-on reset and power-up clear handling, NMI source selection and management, reset interrupt
vector generators, bootloader entry mechanisms, and configuration management (device descriptors). The
SYS module also includes a data exchange mechanism through JTAG called a JTAG mailbox that can be
used in the application. Table 5-10 lists the interrupt vector registers of the SYS module.
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Table 5-10. System Module Interrupt Vector Registers
INTERRUPT
VECTOR REGISTER
SYSRSTIV,
System Reset
SYSSNIV,
System NMI
SYSUNIV,
User NMI
(1)
68
ADDRESS
019Eh
INTERRUPT EVENT
VALUE
No interrupt pending
00h
Brownout (BOR)
02h
RSTIFG RST/NMI (BOR)
04h
PMMSWBOR software BOR (BOR)
06h
LPMx.5 wakeup (BOR)
08h
Security violation (BOR)
0Ah
Reserved
0Ch
SVSHIFG SVSH event (BOR)
0Eh
Reserved
10h
Reserved
12h
PMMSWPOR software POR (POR)
14h
WDTIFG watchdog time-out (PUC)
16h
WDTPW password violation (PUC)
18h
FRCTLPW password violation (PUC)
1Ah
Uncorrectable FRAM bit error detection (PUC)
1Ch
Peripheral area fetch (PUC)
1Eh
PMMPW PMM password violation (PUC)
20h
MPUPW MPU password violation (PUC)
22h
CSPW CS password violation (PUC)
24h
MPUSEGPIFG encapsulated IP memory segment violation (PUC)
26h
019Ch
019Ah
MPUSEGIIFG information memory segment violation (PUC)
28h
MPUSEG1IFG segment 1 memory violation (PUC)
2Ah
MPUSEG2IFG segment 2 memory violation (PUC)
2Ch
MPUSEG3IFG segment 3 memory violation (PUC)
2Eh
ACCTEIFG access time error (PUC) (1)
30h
Reserved
32h to 3Eh
No interrupt pending
00h
Reserved
02h
Uncorrectable FRAM bit error detection
04h
Reserved
06h
MPUSEGPIFG encapsulated IP memory segment violation
08h
MPUSEGIIFG information memory segment violation
0Ah
MPUSEG1IFG segment 1 memory violation
0Ch
MPUSEG2IFG segment 2 memory violation
0Eh
MPUSEG3IFG segment 3 memory violation
10h
VMAIFG Vacant memory access
12h
JMBINIFG JTAG mailbox input
14h
JMBOUTIFG JTAG mailbox output
16h
Correctable FRAM bit error detection
18h
Reserved
1Ah to 1Eh
No interrupt pending
00h
NMIIFG NMI pin
02h
OFIFG oscillator fault
04h
Reserved
06h
Reserved
08h
Reserved
0Ah to 1Eh
PRIORITY
Highest
Lowest
Highest
Lowest
Highest
Lowest
Indicates incorrect wait state settings.
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5.11.8 DMA Controller
The DMA controller allows movement of data from one memory address to another without CPU
intervention. For example, the DMA controller can be used to move data from the ADC10_B conversion
memory to RAM. Using the DMA controller can increase the throughput of peripheral modules. The DMA
controller reduces system power consumption by allowing the CPU to remain in sleep mode, without
having to awaken to move data to or from a peripheral. Table 5-11 lists the triggers that can be used to
start DMA operation.
Table 5-11. DMA Trigger Assignments (1)
TRIGGER
CHANNEL 0
CHANNEL 1
0
DMAREQ
DMAREQ
DMAREQ
1
TA0CCR0 CCIFG
TA0CCR0 CCIFG
TA0CCR0 CCIFG
2
TA0CCR2 CCIFG
TA0CCR2 CCIFG
TA0CCR2 CCIFG
3
TA1CCR0 CCIFG
TA1CCR0 CCIFG
TA1CCR0 CCIFG
4
TA1CCR2 CCIFG
TA1CCR2 CCIFG
TA1CCR2 CCIFG
5
TA2 CCR0 CCIFG
TA2 CCR0 CCIFG
TA2 CCR0 CCIFG
6
TA3 CCR0 CCIFG
TA3 CCR0 CCIFG
TA3 CCR0 CCIFG
7
TB0CCR0 CCIFG
TB0CCR0 CCIFG
TB0CCR0 CCIFG
8
TB0CCR2 CCIFG
TB0CCR2 CCIFG
TB0CCR2 CCIFG
Reserved
9
Reserved
Reserved
10
Reserved
Reserved
Reserved
11
AES Trigger 0
AES Trigger 0
AES Trigger 0
12
AES Trigger 1
AES Trigger 1
AES Trigger 1
13
AES Trigger 2
AES Trigger 2
AES Trigger 2
14
UCA0RXIFG
UCA0RXIFG
UCA0RXIFG
15
UCA0TXIFG
UCA0TXIFG
UCA0TXIFG
16
UCA1RXIFG
UCA1RXIFG
UCA1RXIFG
17
UCA1TXIFG
UCA1TXIFG
UCA1TXIFG
18
UCB0RXIFG (SPI)
UCB0RXIFG0 (I2C)
UCB0RXIFG (SPI)
UCB0RXIFG0 (I2C)
UCB0RXIFG (SPI)
UCB0RXIFG0 (I2C)
19
UCB0TXIFG (SPI)
UCB0TXIFG0 (I2C)
UCB0TXIFG (SPI)
UCB0TXIFG0 (I2C)
UCB0TXIFG (SPI)
UCB0TXIFG0 (I2C)
20
UCB0RXIFG1 (I2C)
UCB0RXIFG1 (I2C)
UCB0RXIFG1 (I2C)
21
(1)
CHANNEL 2
2
UCB0TXIFG1 (I C)
2
2
UCB0TXIFG1 (I2C)
2
UCB0TXIFG1 (I C)
22
UCB0RXIFG2 (I C)
UCB0RXIFG2 (I C)
UCB0RXIFG2 (I2C)
23
UCB0TXIFG2 (I2C)
UCB0TXIFG2 (I2C)
UCB0TXIFG2 (I2C)
24
UCB1RXIFG (SPI)
UCB1RXIFG0 (I2C)
UCB1RXIFG (SPI)
UCB1RXIFG0 (I2C)
UCB1RXIFG (SPI)
UCB1RXIFG0 (I2C)
25
UCB1TXIFG (SPI)
UCB1TXIFG0 (I2C)
UCB1TXIFG (SPI)
UCB1TXIFG0 (I2C)
UCB1TXIFG (SPI)
UCB1TXIFG0 (I2C)
26
ADC12 end of conversion
ADC12 end of conversion
ADC12 end of
conversion
27
Reserved
Reserved
Reserved
28
ESI
ESI
ESI
29
MPY ready
MPY ready
MPY ready
30
DMA2IFG
DMA0IFG
DMA1IFG
31
DMAE0
DMAE0
DMAE0
If a reserved trigger source is selected, no trigger is generated.
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5.11.9 Enhanced Universal Serial Communication Interface (eUSCI)
The eUSCI modules are used for serial data communication. The eUSCI module supports synchronous
communication protocols such as SPI (3 or 4 pin) and I2C, and asynchronous communication protocols
such as UART, enhanced UART with automatic baud-rate detection, and IrDA.
The eUSCI_An module provides support for SPI (3 pin or 4 pin), UART, enhanced UART, and IrDA.
The eUSCI_Bn module provides support for SPI (3 pin or 4 pin) and I2C.
Two eUSCI_A modules and one or two eUSCI_B module are implemented.
5.11.10 Extended Scan Interface (ESI)
The ESI peripheral automatically scans sensors and measures linear or rotational motion with the lowest
possible power consumption. The ESI incorporates a VCC/2 generator, a comparator, and a 12-bit DAC
and supports up to four sensors.
5.11.11 Timer_A TA0, Timer_A TA1
TA0 and TA1 are 16-bit timers/counters (Timer_A type) with three capture/compare registers each. TA0
and TA1 can support multiple capture/compares, PWM outputs, and interval timing (see Table 5-12 and
Table 5-13). TA0 and TA1 have extensive interrupt capabilities. Interrupts can be generated from the
counter on overflow conditions and from each of the capture/compare registers.
Table 5-12. Timer_A TA0 Signal Connections
INPUT PORT PIN
DEVICE INPUT
SIGNAL
MODULE INPUT
SIGNAL
P1.2 or P6.7 or
P7.0
TA0CLK
TACLK
ACLK (internal)
ACLK
SMCLK (internal)
SMCLK
P1.2 or P6.7 or
P7.0
TA0CLK
INCLK
P1.5
TA0.0
CCI0A
P7.1 or P10.1
TA0.0
CCI0B
P1.0 or P1.6 or
P7.2 or P7.6
P1.1 or P1.7 or
P7.3 or P7.5
70
DVSS
GND
DVCC
VCC
TA0.1
CCI1A
COUT (internal)
CCI1B
MODULE
BLOCK
MODULE
OUTPUT
SIGNAL
Timer
N/A
DEVICE OUTPUT
OUTPUT PORT PIN
SIGNAL
N/A
P1.5
CCR0
TA0
TA0.0
P7.1
P10.1
P1.0
P1.6
CCR1
TA1
TA0.1
P7.2
P7.6
DVSS
GND
DVCC
VCC
ADC12 (internal)
ADC12SHSx = {1}
TA0.2
CCI2A
P1.1
ACLK (internal)
CCI2B
DVSS
GND
P7.3
DVCC
VCC
P7.5
CCR2
TA2
Detailed Description
TA0.2
P1.7
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Table 5-13. Timer_A TA1 Signal Connections
INPUT PORT PIN
DEVICE INPUT
SIGNAL
MODULE INPUT
SIGNAL
P1.1 or P4.4 or
P5.2
TA1CLK
TACLK
ACLK (internal)
ACLK
SMCLK (internal)
SMCLK
P1.1 or P4.4 or
P5.2
TA1CLK
INCLK
P1.4 or P4.5
TA1.0
CCI0A
P5.2 or P10.2
TA1.0
CCI0B
MODULE
BLOCK
MODULE
OUTPUT
SIGNAL
Timer
N/A
DEVICE OUTPUT
OUTPUT PORT PIN
SIGNAL
N/A
P1.4
CCR0
TA0
TA1.0
P4.5
DVSS
GND
DVCC
VCC
TA1.1
CCI1A
COUT (internal)
CCI1B
DVSS
GND
DVCC
VCC
ADC12 (internal)
ADC12SHSx = {4}
TA1.2
CCI2A
P1.3
ACLK (internal)
CCI2B
DVSS
GND
P5.1
DVCC
VCC
P7.7
P1.2 or P3.3 or
P4.6 or P5.0
P1.3 or P4.7 or
P5.1 or P7.7
P5.2
P10.2
P1.2
P4.6
CCR1
CCR2
TA1
TA1.1
TA2
TA1.2
P3.3
P5.0
P4.7
5.11.12 Timer_A TA2
TA2 is a 16-bit timer/counter (Timer_A type) with two capture/compare registers each and with internal
connections only. TA2 can support multiple capture/compares, PWM outputs, and interval timing (see
Table 5-14). TA2 has extensive interrupt capabilities. Interrupts may be generated from the counter on
overflow conditions and from each of the capture/compare registers.
Table 5-14. Timer_A TA2 Signal Connections
DEVICE INPUT SIGNAL
MODULE INPUT NAME
COUT (internal)
TACLK
ACLK (internal)
ACLK
SMCLK (internal)
SMCLK
From Capacitive Touch
I/O 0 (internal)
INCLK
TA3 CCR0 output
(internal)
CCI0A
ACLK (internal)
CCI0B
DVSS
GND
DVCC
VCC
From Capacitive Touch
I/O 0 (internal)
CCI1A
COUT (internal)
CCI1B
DVSS
GND
DVCC
VCC
MODULE BLOCK
MODULE OUTPUT
SIGNAL
Timer
N/A
DEVICE OUTPUT SIGNAL
TA3 CCI0A input
CCR0
TA0
ADC12 (internal)
ADC12SHSx = {5}
CCR1
TA1
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5.11.13 Timer_A TA3
TA3 is a 16-bit timer/counter (Timer_A type) with five capture/compare registers each and with internal
connections only. TA3 can support multiple capture/compares, PWM outputs, and interval timing (see
Table 5-15). TA3 has extensive interrupt capabilities. Interrupts may be generated from the counter on
overflow conditions and from each of the capture/compare registers.
Table 5-15. Timer_A TA3 Signal Connections
DEVICE INPUT SIGNAL
MODULE INPUT NAME
COUT (internal)
TACLK
ACLK (internal)
ACLK
SMCLK (internal)
SMCLK
From Capacitive Touch
I/O 1 (internal)
INCLK
TA2 CCR0 output
(internal)
CCI0A
ACLK (internal)
CCI0B
DVSS
GND
DVCC
VCC
From Capacitive Touch
I/O 1 (internal)
CCI1A
COUT (internal)
CCI1B
DVSS
GND
DVCC
VCC
72
DVSS
CCI2A
ESIO0 (internal)
CCI2B
DVSS
GND
DVCC
VCC
DVSS
CCI3A
ESIO1 (internal)
CCI3B
DVSS
GND
DVCC
VCC
DVSS
CCI4A
ESIO2 (internal)
CCI4B
DVSS
GND
DVCC
VCC
MODULE BLOCK
MODULE OUTPUT
SIGNAL
Timer
N/A
DEVICE OUTPUT SIGNAL
TA2 CCI0A input
CCR0
TA0
ADC12 (internal)
ADC12SHSx = {6}
CCR1
TA1
CCR2
TA2
CCR3
TA3
CCR4
TA4
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5.11.14 Timer_B TB0
TB0 is a 16-bit timer/counter (Timer_B type) with seven capture/compare registers each. TB0 can support
multiple capture/compares, PWM outputs, and interval timing (see Table 5-16). TB0 has extensive
interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each
of the capture/compare registers.
Table 5-16. Timer_B TB0 Signal Connections
INPUT PORT PIN
DEVICE INPUT
SIGNAL
MODULE INPUT
SIGNAL
P2.0 or P3.3 or
P5.7
TB0CLK
TBCLK
ACLK (internal)
ACLK
SMCLK (internal)
SMCLK
P2.0 or P3.3 or
P5.7
TB0CLK
INCLK
P3.4
TB0.0
CCI0A
P6.4
TB0.0
CCI0B
P3.5 or P6.5
DVSS
GND
DVCC
VCC
TB0.1
CCI1A
COUT (internal)
CCI1B
DVSS
P3.6 or P6.6
GND
DVCC
VCC
TB0.2
CCI2A
ACLK (internal)
CCI2B
DVSS
GND
DVCC
VCC
P2.4
TB0.3
CCI3A
P3.7
TB0.3
CCI3B
DVSS
GND
DVCC
VCC
P2.5
TB0.4
CCI4A
P2.2
TB0.4
CCI4B
DVSS
GND
DVCC
VCC
P2.6
TB0.5
CCI5A
P2.1
TB0.5
CCI5B
DVSS
GND
DVCC
VCC
P2.7
TB0.6
CCI6A
P2.0
TB0.6
CCI6B
DVSS
GND
DVCC
VCC
MODULE
BLOCK
MODULE
OUTPUT
SIGNAL
Timer
N/A
DEVICE OUTPUT
OUTPUT PORT PIN
SIGNAL
N/A
P3.4
P6.4
CCR0
TB0
TB0.0
ADC12 (internal)
ADC12SHSx = {2}
P3.5
P6.5
CCR1
TB1
TB0.1
ADC12 (internal)
ADC12SHSx = {3}
P3.6
CCR2
TB2
TB0.2
P6.6
P2.4
CCR3
TB3
TB0.3
P3.7
P2.5
CCR4
TB4
TB0.4
P2.2
P2.6
CCR5
TB5
TB0.5
P2.1
P2.7
CCR6
TB6
TB0.6
P2.0
Detailed Description
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5.11.15 ADC12_B
The ADC12_B module supports fast 12-bit analog-to-digital conversions with differential and single-ended
inputs. The module implements a 12-bit SAR core, sample select control, a reference generator, and a
conversion result buffer. A window comparator with lower and upper limits allows CPU-independent result
monitoring with three window comparator interrupt flags.
Table 5-17 lists the external trigger sources. Table 5-18 lists the available multiplexing between internal
and external analog inputs.
Table 5-17. ADC12_B Trigger Signal Connections
ADC12SHSx
CONNECTED TRIGGER
SOURCE
BINARY
DECIMAL
000
0
Software (ADC12SC)
001
1
Timer_A TA0 CCR1 output
010
2
Timer_B TB0 CCR0 output
011
3
Timer_B TB0 CCR1 output
100
4
Timer_A TA1 CCR1 output
101
5
Timer_A TA2 CCR1 output
110
6
Timer_A TA3 CCR1 output
111
7
Reserved (DVSS)
Table 5-18. ADC12_B External and Internal Signal Mapping
(1)
CONTROL BIT
EXTERNAL
(CONTROL BIT = 0)
INTERNAL
(CONTROL BIT = 1)
ADC12BATMAP
A31
Battery Monitor
ADC12TCMAP
A30
Temperature Sensor
ADC12CH0MAP
A29
N/A (1)
ADC12CH1MAP
A28
N/A (1)
ADC12CH2MAP
A27
N/A (1)
ADC12CH3MAP
A26
N/A (1)
N/A = No internal signal available on this device.
5.11.16 Comparator_E
The primary function of the Comparator_E module is to support precision slope analog-to-digital
conversions, battery voltage supervision, and monitoring of external analog signals.
5.11.17 CRC16
The CRC16 module produces a signature based on a sequence of entered data values and can be used
for data checking purposes. The CRC16 signature is based on the CRC-CCITT standard.
5.11.18 CRC32
The CRC32 module produces a signature based on a sequence of entered data values and can be used
for data checking purposes. The CRC32 signature is based on the ISO 3309 standard.
5.11.19 AES256 Accelerator
The AES accelerator module performs encryption and decryption of 128-bit data with 128-, 192-, or 256bit keys according to the Advanced Encryption Standard (AES) (FIPS PUB 197) in hardware.
74
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5.11.20 True Random Seed
The Device Descriptor Information (TLV) section contains a 128-bit true random seed that can be used to
implement a deterministic random number generator.
5.11.21 Shared Reference (REF_A)
The reference module (REF_A) generates all critical reference voltages that can be used by the various
analog peripherals in the device.
5.11.22 LCD_C
The LCD_C driver generates the segment and common signals required to drive a liquid crystal display
(LCD). The LCD_C controller has dedicated data memories to hold segment drive information. Common
and segment signals are generated as defined by the mode. Static and 2-mux to 8-mux LCDs are
supported. The module can provide a LCD voltage independent of the supply voltage with its integrated
charge pump. It is possible to control the level of the LCD voltage and thus contrast by software. The
module also provides an automatic blinking capability for individual segments in static, 2-mux, 3-mux, and
4-mux modes.
To reduce system noise, the charge pump can be temporarily disabled. Table 5-19 lists the available
automatic charge pump disable options.
Table 5-19. LCD Automatic Charge Pump Disable Bits (LCDCPDISx)
CONTROL BIT
LCDCPDIS0
LCDCPDIS1 to
LCDCPDIS7
DESCRIPTION
LCD charge pump disable during ADC12 conversion
0b = LCD charge pump not automatically disabled during conversion
1b = LCD charge pump automatically disabled during conversion
No functionality
5.11.23 Embedded Emulation
5.11.23.1 Embedded Emulation Module (EEM)
The EEM supports real-time in-system debugging. The S version of the EEM has the following features:
• Three hardware triggers or breakpoints on memory access
• One hardware trigger or breakpoint on CPU register write access
• Up to four hardware triggers that can be combined to form complex triggers or breakpoints
• One cycle counter
• Clock control on module level
5.11.23.2 EnergyTrace++™ Technology
These MCUs implement circuitry to support EnergyTrace++ technology. The EnergyTrace++ technology
allows you to observe information about the internal states of the microcontroller. These states include the
CPU Program Counter (PC), the ON or OFF status of the peripherals and the system clocks (regardless of
the clock source), and the low-power mode currently in use. These states can always be read by a debug
tool, even when the microcontroller sleeps in LPMx.5 modes.
The activity of the following modules can be observed:
• MPY is calculating.
• WDT is counting.
• RTC is counting.
• ADC: a sequence, sample, or conversion is active.
• REF: REFBG or REFGEN active and BG in static mode.
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•
•
•
•
•
•
•
•
•
•
•
•
76
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COMP is on.
AES is encrypting or decrypting.
eUSCI_A0 is transferring (receiving or transmitting)
eUSCI_A1 is transferring (receiving or transmitting)
eUSCI_B0 is transferring (receiving or transmitting)
eUSCI_B1 is transferring (receiving or transmitting)
TB0 is counting.
TA0 is counting.
TA1 is counting.
TA2 is counting.
TA3 is counting.
LCD: timing generator is active.
ESI:
– ESI is active using LF clock source
– ESI is active using HF clock source
data.
data.
data.
data.
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5.11.24 Input/Output Diagrams
5.11.24.1 Digital I/O Functionality – Ports P1 to P10
The port pins provide the following features:
• Interrupt and wakeup from LPMx.5 capability for ports P1, P2, P3, and P4
• Capacitive touch functionality (see Section 5.11.24.2)
• Up to three digital module input or output functions
• LCD segment functionality (not all pins, package dependent)
Figure 5-2 shows the features and the corresponding control logic (not including the capacitive touch
logic). It is applicable for all port pins P1.0 to P10.2 unless a dedicated diagram is available in the
following sections. The module functions provided per pin and whether the direction is controlled by the
module or by the port direction register for the selected secondary function are described in the pin
function tables.
Pad Logic
Sz
LCDSz
PxREN.y
PxDIR.y
00
From module 1
(B)
From module 2
(B)
10
From module 3
(B)
11
01
PxOUT.y
00
From module 1
01
From module 2
10
From module 3
11
Direction
0: Input
1: Output
DVSS
0
DVCC
1
1
Px.y/Mod1/Mod2/Mod3/Sz
PxSEL1.y
PxSEL0.y
PxIN.y
To module 1
(A)
To module 2
To module 3
(A)
(A)
A.
B.
The inputs from several pins toward a module are ORed together.
The direction is controlled either by the connected module or by the corresponding PxDIR.y bit. See the pin function
tables.
NOTE: Functional representation only.
Figure 5-2. General Port Pin Diagram
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5.11.24.2 Capacitive Touch Functionality Ports P1 to P10 and PJ
Figure 5-3 shows the Capacitive Touch functionality that all port pins provide. The Capacitive Touch
functionality is controlled using the Capacitive Touch I/O control registers CAPTIO0CTL and CAPTIO1CTL
as described in the MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, and MSP430FR69xx Family
User's Guide. The Capacitive Touch functionality is not shown in the other pin diagrams.
Analog Enable
PxREN.y
Capacitive Touch Enable 0
Capacitive Touch Enable 1
DVSS
0
DVCC
1
1
Direction Control
PxOUT.y
0
1
Output Signal
Px.y
Input Signal
Q
D
EN
Capacitive Touch Signal 0
Capacitive Touch Signal 1
NOTE: Functional representation only.
Figure 5-3. Capacitive Touch I/O Diagram
78
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5.11.24.3 Port P1 (P1.0 to P1.3) Input/Output With Schmitt Trigger
Figure 5-4 shows the port diagram. summarizes the selection of the pin function.
Pad Logic
(ADC) Reference
(P1.0, P1.1)
To ADC
From ADC
To Comparator
From Comparator
CEPD.x
P1REN.x
P1DIR.x
00
01
10
Direction
0: Input
1: Output
11
P1OUT.x
DVSS
0
DVCC
1
00
From module 1
01
From module 2
10
DVSS
11
P1.0/TA0.1/DMAE0/RTCCLK/
A0/C0/VREF-/VeREFP1.1/TA0.2/TA1CLK/COUT/
A1/C1VREF+/VeREF+
P1.2/TA1.1/TA0CLK/COUT/A2/C2
P1.3/TA1.2/ESITEST4/A3/C3
P1SEL1.x
P1SEL0.x
P1IN.x
To module 1
Bus
Keeper
(A)
To module 2
1
(A)
A. The inputs from several pins toward a module are ORed together.
NOTE: Functional representation only.
Figure 5-4. Port P1 (P1.0 to P1.3) Diagram
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Port P1 (P1.0 to P1.3) Pin Functions
PIN NAME (P1.x)
x
FUNCTION
P1.0 (I/O)
P1.0/TA0.1/DMAE0/RTCCLK/A0/C0/
VREF-/VeREF-
0
80
1
0
(3) (4)
X
1
1
I: 0; O: 1
0
0
0
1
1
0
X
1
1
I: 0; O: 1
0
0
0
1
1
0
X
1
1
I: 0; O: 1
0
0
0
1
1
0
1
1
TA0.CCI2A
0
TA0.2
1
TA1CLK
0
(5)
1
(3) (4)
TA1.CCI1A
0
TA1.1
1
TA0CLK
0
(6)
1
(3) (4)
TA1.CCI2A
0
TA1.2
1
N/A
0
ESITEST4
1
A3, C3
(5)
(6)
1
1
P1.3 (I/O)
(4)
0
0
A2, C2
(1)
(2)
(3)
0
RTCCLK (2)
COUT
3
0
DMAE0
P1.2 (I/O)
P1.3/TA1.2/ESITEST4/A3/C3
I: 0; O: 1
1
A1, C1, VREF+, VeREF+
2
P1SEL0.x
TA0.1
COUT
P1.2/TA1.1/TA0CLK/COUT/A2/C2
P1SEL1.x
0
P1.1 (I/O)
1
P1DIR.x
TA0.CCI1A
A0, C0, VREF-, VeREF-
P1.1/TA0.2/TA1CLK/COUT/A1/C1/
VREF+/VeREF+
CONTROL BITS AND SIGNALS (1)
(3) (4)
X
X = Don't care.
Do not use this pin as RTCCLK output if the DMAE0 functionality is used on any other pin. Select an alternative RTCCLK output pin.
Setting P1SEL1.x and P1SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
Setting the CEPD.x bit of the comparator disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals. Selecting the Cx input pin to the comparator multiplexer with the input select bits in the comparator module
automatically disables output driver and input buffer for that pin, regardless of the state of the associated CEPD.x bit.
Do not use this pin as COUT output if the TA1CLK functionality is used on any other pin. Select an alternative COUT output pin.
Do not use this pin as COUT output if the TA0CLK functionality is used on any other pin. Select an alternative COUT output pin.
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5.11.24.4 Port P1 (P1.4 to P1.7) Input/Output With Schmitt Trigger
For the pin diagram, see Figure 5-2. summarizes the selection of the pin function.
Port P1 (P1.4 to P1.7) Pin Functions
PIN NAME (P1.x)
x
FUNCTION
P1.4 (I/O)
P1.4/UCB0CLK/UCA0STE/TA1.0/Sz
4
5
0
0
1
0
UCA0STE
X
(3)
1
0
0
1
1
0
TA1.CCI0A
0
TA1.0
1
(4)
X
X
X
1
P1.5 (I/O)
I: 0; O: 1
0
0
0
UCB0STE
X
(2)
0
1
0
UCA0CLK
X
(3)
1
0
0
1
1
0
TA0.CCI0A
0
TA0.0
1
(4)
X
X
X
1
P1.6 (I/O)
I: 0; O: 1
0
0
0
0
1
0
1
0
0
1
1
0
(2)
X
N/A
0
Internally tied to DVSS
1
TA0.CCI1A
0
TA0.1
1
(4)
X
X
X
1
P1.7 (I/O)
I: 0; O: 1
0
0
0
0
1
0
1
0
0
1
1
0
X
X
1
(2)
X
N/A
0
Internally tied to DVSS
1
TA0.CCI2A
0
TA0.2
1
(4)
X
Sz
(1)
(2)
(3)
(4)
I: 0; O: 1
0
UCB0SOMI/UCB0SCL
7
LCDSz
0
Sz
P1.7/UCB0SOMI/UCB0SCL/TA0.2/
Sz
P1SEL0.x
(2)
UCB0SIMO/UCB0SDA
6
P1SEL1.x
X
Sz
P1.6/UCB0SIMO/UCB0SDA/TA0.1/
Sz
P1DIR.x
UCB0CLK
Sz
P1.5/UCB0STE/UCA0CLK/TA0.0/Sz
CONTROL BITS AND SIGNALS (1)
X = Don't care.
Direction controlled by eUSCI_B0 module.
Direction controlled by eUSCI_A0 module.
The associated LCD segment is package dependent. See the Signal Descriptions tables and Pin Diagrams figures.
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5.11.24.5 Port P2 (P2.0 to P2.3) Input/Output With Schmitt Trigger
For the pin diagram, see Figure 5-2. summarizes the selection of the pin function.
Port P2 (P2.0 to P2.3) Pin Functions
PIN NAME (P2.x)
x
FUNCTION
P2.0 (I/O)
UCA0SIMO/UCA0TXD
P2.0/UCA0SIMO/UCA0TXD/TB0.6/
TB0CLK/Sz
0
82
0
0
0
1
0
1
0
0
1
1
0
0
1
(3)
X
X
X
1
P2.1 (I/O)
I: 0; O: 1
0
0
0
0
1
0
1
0
0
1
1
0
(2)
X
TB0.CCI5B
0
TB0.5
1
DMA0E
0
Internally tied to DVSS
1
(3)
X
X
X
1
P2.2 (I/O)
I: 0; O: 1
0
0
0
0
1
0
1
0
0
1
1
0
(2)
X
TB0.CCI4B
0
TB0.4
1
N/A
0
RTCCLK
1
(3)
X
X
X
1
P2.3 (I/O)
I: 0; O: 1
0
0
0
0
1
0
1
0
0
1
1
0
X
X
1
(2)
X
TB0OUTH
0
Internally tied to DVSS
1
N/A
0
Internally tied to DVSS
1
Sz
(1)
(2)
(3)
0
(2)
X
Internally tied to DVSS
UCA0STE
3
I: 0; O: 1
TB0CLK
Sz
P2.3/UCA0STE/TB0OUTH/Sz
LCDSz
1
UCA0CLK
2
P2SEL0.x
TB0.6
Sz
P2.2/UCA0CLK/TB0.4/RTCCLK/Sz
P2SEL1.x
0
UCA0SOMI/UCA0RXD
1
P2DIR.x
TB0.CCI6B
Sz
P2.1/UCA0SOMI/UCA0RXD/TB0.5/
DMAE0/Sz
CONTROL BITS AND SIGNALS (1)
(3)
X
X = Don't care.
Direction controlled by eUSCI_A0 module.
The associated LCD segment is package dependent. See the Signal Descriptions tables and Pin Diagrams figures.
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5.11.24.6 Port P2 (P2.4 to P2.7) Input/Output With Schmitt Trigger
Figure 5-5 shows the port diagram. summarizes the selection of the pin function.
Sz
LCDSz
COM4/5/6/7
Pad Logic
P2REN.x
P2DIR.x
00
01
10
Direction
0: Input
1: Output
11
P2OUT.x
00
From module 1
01
From module 2
10
DVSS
11
DVSS
0
DVCC
1
1
P2.4/TB0.3/COM4/Sz
P2.5/TB0.4/COM5/Sz
P2.6/TB0.5/COM6/Sz
P2.7/TB0.6/COM7/Sz
P2SEL1.x
P2SEL0.x
P2IN.x
To module 1
Bus
Keeper
(A)
To module 2
(A)
A. The inputs from several pins toward a module are ORed together.
NOTE: Functional representation only.
Figure 5-5. Port P2 (P2.4 to P2.7) Diagram
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Port P2 (P2.4 to P2.7) Pin Functions
PIN NAME (P2.x)
x
FUNCTION
P2.4 (I/O)
P2.4/TB0.3/COM4/Sz
4
5
6
7
84
LCDSz
I: 0; O: 1
0
0
0
0
1
0
1
0
0
1
N/A
0
Internally tied to DVSS
1
COM4
X
1
1
0
(2)
X
X
X
1
P2.5 (I/O)
I: 0; O: 1
0
0
0
0
1
0
1
0
0
TB0.CCI4A
0
TB0.4
1
N/A
0
Internally tied to DVSS
1
COM5
X
1
1
0
(2)
X
X
X
1
P2.6 (I/O)
I: 0; O: 1
0
0
0
0
1
0
1
0
0
TB0.CCI5A
0
TB0.5
1
N/A
0
ESIC1OUT
1
COM6
X
1
1
0
(2)
X
X
X
1
P2.7 (I/O)
I: 0; O: 1
0
0
0
0
1
0
1
0
0
TB0.CCI6A
0
TB0.6
1
N/A
0
ESIC2OUT
1
COM7
X
1
1
0
X
X
X
1
Sz
(1)
(2)
P2SEL0.x
TB0.3
Sz
P2.7/TB0.6/ESIC2OUT/COM7/Sx
P2SEL1.x
0
Sz
P2.6/TB0.5/ESIC1OUT/COM6/Sx
P2DIR.x
TB0.CCI3A
Sz
P2.5/TB0.4/COM5/Sz
CONTROL BITS AND SIGNALS (1)
(2)
X = Don't care.
The associated LCD segment is package dependent. See the Signal Descriptions tables and Pin Diagrams figures.
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5.11.24.7 Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger
For the pin diagram, see Figure 5-2. and summarize the selection of the pin function.
Port P3 (P3.0 to P3.3) Pin Functions
PIN NAME (P3.x)
x
FUNCTION
P3.0 (I/O)
UCB1CLK
P3.0/UCB1CLK/Sz
0
LCDSz
I: 0; O: 1
0
0
0
0
1
0
1
0
0
1
1
0
(2)
X
1
N/A
0
Internally tied to DVSS
1
(3)
X
X
X
1
P3.1 (I/O)
I: 0; O: 1
0
0
0
0
1
0
1
0
0
1
1
0
(2)
X
N/A
0
Internally tied to DVSS
1
N/A
0
Internally tied to DVSS
1
(3)
X
X
X
1
P3.2 (I/O)
I: 0; O: 1
0
0
0
0
1
0
1
0
0
1
1
0
UCB1SOMI/UCB1SCL
2
P3SEL0.x
Internally tied to DVSS
Sz
P3.2/UCB1SOMI/UCB1SCL/Sz
P3SEL1.x
0
UCB1SIMO/UCB1SDA
1
P3DIR.x
N/A
Sz
P3.1/UCB1SIMO/UCB1SDA/Sz
CONTROL BITS AND SIGNALS (1)
(2)
X
N/A
0
Internally tied to DVSS
1
0
1
(3)
X
X
X
1
P3.3 (I/O)
I: 0; O: 1
0
0
0
0
1
0
1
0
0
1
1
0
X
X
1
Sz
P3.3/TA1.1/TB0CLK/Sz
3
N/A
0
Internally tied to DVSS
1
TA1.CCI1A
0
TA1.1
1
TB0CLK
0
Internally tied to DVSS
1
Sz
(1)
(2)
(3)
(3)
X
X = Don't care.
Direction controlled by eUSCI_B1 module.
The associated LCD segment is package dependent. See the Signal Descriptions tables and Pin Diagrams figures.
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Port P3 (P3.4 to P3.7) Pin Functions
PIN NAME (P3.x)
x
FUNCTION
P3.4 (I/O)
UCA1SIMO/UCA1TXD
P3.4/UCA1SIMO/UCA1TXD/TB0.0/
Sz
4
86
0
0
0
1
0
1
0
0
1
1
0
0
1
(3)
X
X
X
1
P3.5 (I/O)
I: 0; O: 1
0
0
0
0
1
0
1
0
0
1
1
0
(2)
X
TB0CCI1A
0
TB0.1
1
N/A
0
Internally tied to DVSS
1
(3)
X
X
X
1
P3.6 (I/O)
I: 0; O: 1
0
0
0
0
1
0
1
0
0
1
1
0
(2)
X
TB0CCI2A
0
TB0.2
1
N/A
0
Internally tied to DVSS
1
(3)
X
X
X
1
P3.7 (I/O)
I: 0; O: 1
0
0
0
0
1
0
1
0
0
1
1
0
X
X
1
(2)
X
TB0CCI3B
0
TB0.3
1
N/A
0
Internally tied to DVSS
1
Sz
(1)
(2)
(3)
0
(2)
X
Internally tied to DVSS
UCA1STE
7
I: 0; O: 1
N/A
Sz
P3.7/UCA1STE/TB0.3/Sz
LCDSz
1
UCA1CLK
6
P3SEL0.x
TB0.0
Sz
P3.6/UCA1CLK/TB0.2/Sz
P3SEL1.x
0
UCA1SOMI/UCA1RXD
5
P3DIR.x
TB0CCI0A
Sz
P3.5/UCA1SOMI/UCA1RXD/TB0.1/
Sz
CONTROL BITS AND SIGNALS (1)
(3)
X
X = Don't care.
Direction controlled by eUSCI_A1 module.
The associated LCD segment is package dependent. See the Signal Descriptions tables and Pin Diagrams figures.
Detailed Description
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5.11.24.8 Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
For the pin diagram, see Figure 5-2. and summarize the selection of the pin function.
Port P4 (P4.0 to P4.3) Pin Functions
PIN NAME (P4.x)
x
FUNCTION
P4.0 (I/O)
P4.0/UCB1SIMO/UCB1SDA/MCLK/
Sz
0
1
3
UCB1SIMO/UCB1SDA
I: 0; O: 1
0
0
0
0
1
0
1
0
0
1
1
0
(2)
X
N/A
0
MCLK
1
(3)
X
X
X
1
P4.1 (I/O)
I: 0; O: 1
0
0
0
0
1
0
1
0
0
1
1
0
N/A
0
Internally tied to DVSS
1
UCB1SOMI/UCB1SCL
(2)
X
N/A
0
ACLK
1
(3)
X
X
X
1
P4.2 (I/O)
I: 0; O: 1
0
0
0
UCB1CLK
X
(4)
0
1
0
X
(2)
1
0
0
1
1
0
N/A
0
Internally tied to DVSS
1
(3)
X
X
X
1
P4.3 (I/O)
I: 0; O: 1
0
0
0
UCA0SOMI/UCA0RXD
X
(4)
0
1
0
UCB1STE
X
(2)
1
0
0
1
1
0
X
X
1
N/A
0
Internally tied to DVSS
1
Sz
(1)
(2)
(3)
(4)
LCDSz
1
Sz
P4.3/UCA0SOMI/UCA0RXD/
UCB1STE/Sz
P4SEL0.x
Internally tied to DVSS
UCA0SIMO/UCA0TXD
2
P4SEL1.x
0
Sz
P4.2/UCA0SIMO/UCA0TXD/
UCB1CLK/Sz
P4DIR.x
N/A
Sz
P4.1/UCB1SOMI/UCB1SCL/ACLK/
Sz
CONTROL BITS AND SIGNALS (1)
(3)
X
X = Don't care.
Direction controlled by eUSCI_B1 module.
The associated LCD segment is package dependent. See the Signal Descriptions tables and Pin Diagrams figures.
Direction controlled by eUSCI_A0 module.
Detailed Description
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Port P4 (P4.4 to P4.7) Pin Functions
PIN NAME (P4.x)
x
FUNCTION
P4.4 (I/O)
P4.4/UCB1STE/TA1CLK/Sz
4
5
6
7
88
LCDSz
I: 0; O: 1
0
0
0
0
1
0
1
0
0
1
1
0
1
UCB1STE
(2)
X
TA1CLK
0
Internally tied to DVSS
1
(3)
X
X
X
1
P4.5 (I/O)
I: 0; O: 1
0
0
0
0
1
0
1
0
0
1
1
0
N/A
0
Internally tied to DVSS
1
UCB1CLK
(2)
X
TA1CCI0A
0
TA1.0
1
(3)
X
X
X
1
P4.6 (I/O)
I: 0; O: 1
0
0
0
0
1
0
1
0
0
1
1
0
N/A
0
Internally tied to DVSS
1
UCB1SIMO/UCB1SDA
(2)
X
TA1CCI1A
0
TA1.1
1
(3)
X
X
X
1
P4.7 (I/O)
I: 0; O: 1
0
0
0
0
1
0
1
0
0
1
1
0
X
X
1
N/A
0
Internally tied to DVSS
1
UCB1SOMI/UCB1SCL
(2)
X
TA1CCI2A
0
TA1.2
1
(3)
X
Sz
(1)
(2)
(3)
P4SEL0.x
Internally tied to DVSS
Sz
P4.7/UCB1SOMI/UCB1SCL/TA1.2/
Sz
P4SEL1.x
0
Sz
P4.6/UCB1SIMO/UCB1SDA/TA1.1/
Sz
P4DIR.x
N/A
Sz
P4.5/UCB1CLK/TA1.0/Sz
CONTROL BITS AND SIGNALS (1)
X = Don't care.
Direction controlled by eUSCI_B1 module.
The associated LCD segment is package dependent. See the Signal Descriptions tables and Pin Diagrams figures.
Detailed Description
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5.11.24.9 Port P5 (P5.0 to P5.7) Input/Output With Schmitt Trigger
For the pin diagram, see Figure 5-2. and summarize the selection of the pin function.
Port P5 (P5.0 to P5.3) Pin Functions
PIN NAME (P5.x)
P5.0/TA1.1/MCLK/Sz
x
0
FUNCTION
P5DIR.x
P5SEL1.x
P5SEL0.x
LCDSz
P5.0 (I/O)
I: 0; O: 1
0
0
0
TA1CCI1A
0
TA1.1
1
0
1
0
N/A
0
Internally tied to DVSS
1
1
0
0
N/A
0
MCLK
1
1
1
0
(2)
X
X
X
1
P5.1 (I/O)
I: 0; O: 1
0
0
0
TA1CCI2A
0
TA1.2
1
0
1
0
N/A
0
Internally tied to DVSS
1
1
0
0
N/A
0
N/A
1
1
1
0
Sz
P5.1/TA1.2/Sz
1
(2)
X
X
X
1
P5.2 (I/O)
I: 0; O: 1
0
0
0
TA1CCI0B
0
TA1.0
1
0
1
0
TA1CLK
0
Internally tied to DVSS
1
1
0
0
N/A
0
ACLK
1
1
1
0
Sz
P5.2/TA1.0/TA1CLK/ACLK/Sz
2
(2)
X
X
X
1
P5.3 (I/O)
I: 0; O: 1
0
0
0
0
1
0
1
0
0
1
1
0
X
X
1
Sz
P5.3/UCB1STE/Sz
3
N/A
0
Internally tied to DVSS
1
UCB1STE
(3)
X
N/A
0
Internally tied to DVSS
1
Sz
(1)
(2)
(3)
CONTROL BITS AND SIGNALS (1)
(2)
X
X = Don't care.
The associated LCD segment is package dependent. See the Signal Descriptions tables and Pin Diagrams figures.
Direction controlled by eUSCI_B1 module.
Detailed Description
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Port P5 (P5.4 to P5.7) Pin Functions
PIN NAME (P5.x)
x
FUNCTION
P5.4 (I/O)
UCA1SIMO/UCA1TXD
P5.4/UCA1SIMO/UCA1TXD/Sz
4
90
0
0
0
1
0
1
0
0
1
1
0
0
1
(3)
X
X
X
1
P5.5 (I/O)
I: 0; O: 1
0
0
0
0
1
0
1
0
0
1
1
0
(2)
X
N/A
0
Internally tied to DVSS
1
N/A
0
Internally tied to DVSS
1
(3)
X
X
X
1
P5.6 (I/O)
I: 0; O: 1
0
0
0
0
1
0
1
0
0
1
1
0
(2)
X
N/A
0
Internally tied to DVSS
1
N/A
0
Internally tied to DVSS
1
(3)
X
X
X
1
P5.7 (I/O)
I: 0; O: 1
0
0
0
0
1
0
1
0
0
1
1
0
X
X
1
(2)
X
N/A
0
Internally tied to DVSS
1
TB0CLK
0
Internally tied to DVSS
1
Sz
(1)
(2)
(3)
0
(2)
X
Internally tied to DVSS
UCA1STE
7
I: 0; O: 1
N/A
Sz
P5.7/UCA1STE/TB0CLK/Sz
LCDSz
1
UCA1CLK
6
P5SEL0.x
Internally tied to DVSS
Sz
P5.6/UCA1CLK/Sz
P5SEL1.x
0
UCA1SOMI/UCA1RXD
5
P5DIR.x
N/A
Sz
P5.5/UCA1SOMI/UCA1RXD/Sz
CONTROL BITS AND SIGNALS (1)
(3)
X
X = Don't care.
Direction controlled by eUSCI_A1 module.
The associated LCD segment is package dependent. See the Signal Descriptions tables and Pin Diagrams figures.
Detailed Description
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SLASEC9 – APRIL 2017
5.11.24.10 Port P6 (P6.0 to P6.6) Input/Output With Schmitt Trigger
Figure 5-6 shows the port diagram. and summarize the selection of the pin function.
To/From
LCD module
Pad Logic
P6REN.x
P6DIR.x
00
01
10
Direction
0: Input
1: Output
11
P6OUT.x
DVSS
0
DVCC
1
00
From module 1
01
From module 2
10
DVSS
11
P6.0/R23
P6.1/R13/LCDREF
P6.2/COUT/R03
P6.3/COM0
P6.4/TB0.0/COM1
P6.5/TB0.1/COM2
P6.6/TB0.2/COM3
P6SEL1.x
P6SEL0.x
P6IN.x
To module 1
Bus
Keeper
(A)
To module 2
1
(A)
A. The inputs from several pins toward a module are ORed together.
NOTE: Functional representation only.
Figure 5-6. Port P6 (P6.0 to P6.6) Diagram
Detailed Description
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Port P6 (P6.0 to P6.2) Pin Functions
PIN NAME (P6.x)
x
FUNCTION
P6.0 (I/O)
P6.0/R23
0
92
I: 0; O: 1
0
0
–
0
1
–
1
0
–
X
1
1
–
I: 0; O: 1
0
0
–
0
1
–
1
0
–
X
1
1
–
I: 0; O: 1
0
0
–
0
1
–
1
0
–
1
1
–
N/A
0
Internally tied to DVSS
1
(2)
N/A
0
Internally tied to DVSS
1
N/A
0
Internally tied to DVSS
1
(2)
N/A
0
COUT
1
N/A
0
Internally tied to DVSS
1
R03
(1)
(2)
LCDSz
1
P6.2 (I/O)
2
P6SEL0.x
Internally tied to DVSS
R13/LCDREF
P6.2/COUT/R03
P6SEL1.x
0
P6.1 (I/O)
1
P6DIR.x
N/A
R23
P6.1/R13/LCDREF
CONTROL BITS AND SIGNALS (1)
(2)
X
X = Don't care.
Setting P6SEL1.x and P6SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
Detailed Description
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Port P6 (P6.3 to P6.6) Pin Functions
PIN NAME (P6.x)
x
FUNCTION
P6DIR.x
P6SEL1.x
P6SEL0.x
LCDSz
I: 0; O: 1
0
0
–
0
1
–
1
0
–
X
1
1
–
P6.4 (I/O)
I: 0; O: 1
0
0
–
TB0CCI0B
0
TB0.0
1
0
1
–
N/A
0
Internally tied to DVSS
1
1
0
–
P6.3 (I/O)
P6.3/COM0
3
N/A
0
Internally tied to DVSS
1
N/A
0
Internally tied to DVSS
1
COM0
P6.4/TB0.0/COM1
4
COM1
P6.5/TB0.1/COM2
5
6
(2)
X
1
1
–
I: 0; O: 1
0
0
–
TB0CCI1A
0
TB0.1
1
0
1
–
N/A
0
Internally tied to DVSS
1
1
0
–
(2)
X
1
1
–
P6.6 (I/O)
I: 0; O: 1
0
0
–
TB0CCI2A
0
TB0.2
1
0
1
–
N/A
0
Internally tied to DVSS
1
1
0
–
1
1
–
COM3
(1)
(2)
(2)
P6.5 (I/O)
COM2
P6.6/TB0.2/COM3
CONTROL BITS AND SIGNALS (1)
(2)
X
X = Don't care.
Setting P6SEL1.x and P6SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
Detailed Description
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5.11.24.11 Port P6 (P6.7) Input/Output With Schmitt Trigger
For the pin diagram, see Figure 5-2. summarizes the selection of the pin function.
Port P6 (P6.7) Pin Functions
PIN NAME (P6.x)
P6.7/TA0CLK/Sz
x
7
FUNCTION
P6DIR.x
P6SEL1.x
P6SEL0.x
LCDSz
P6.7 (I/O)
I: 0; O: 1
0
0
0
TA0CLK
0
Internally tied to DVSS
1
0
1
0
N/A
0
Internally tied to DVSS
1
1
0
0
N/A
0
Internally tied to DVSS
1
1
1
0
X
X
1
Sz
(1)
(2)
94
CONTROL BITS AND SIGNALS (1)
(2)
X
X = Don't care.
The associated LCD segment is package dependent. See the Signal Descriptions tables and Pin Diagrams figures.
Detailed Description
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SLASEC9 – APRIL 2017
5.11.24.12 Port P7 (P7.0 to P7.7) Input/Output With Schmitt Trigger
For the pin diagram, see Figure 5-2. and summarize the selection of the pin function.
Port P7 (P7.0 to P7.3) Pin Functions
PIN NAME (P7.x)
P7.0/TA0CLK/Sz
x
0
FUNCTION
P7DIR.x
P7SEL1.x
P7SEL0.x
LCDSz
P7.0 (I/O)
I: 0; O: 1
0
0
0
TA0CLK
0
Internally tied to DVSS
1
0
1
0
N/A
0
Internally tied to DVSS
1
1
0
0
N/A
0
Internally tied to DVSS
1
1
1
0
(2)
X
X
X
1
P7.1 (I/O)
I: 0; O: 1
0
0
0
TA0CCI0B
0
TA0.0
1
0
1
0
N/A
0
Internally tied to DVSS
1
1
0
0
N/A
0
ACLK
1
1
1
0
(2)
X
X
X
1
P7.2 (I/O)
I: 0; O: 1
0
0
0
TA0CCI1A
0
TA0.1
1
0
1
0
N/A
0
Internally tied to DVSS
1
1
0
0
N/A
0
N/A
1
1
1
0
Sz
P7.1/TA0.0/ACLK/Sz
1
Sz
P7.2/TA0.1/Sz
2
(2)
X
X
X
1
P7.3 (I/O)
I: 0; O: 1
0
0
0
TA0CCI2A
0
TA0.2
1
0
1
0
N/A
0
Internally tied to DVSS
1
1
0
0
N/A
0
Internally tied to DVSS
1
1
1
0
X
X
1
Sz
P7.3/TA0.2/Sz
3
Sz
(1)
(2)
CONTROL BITS AND SIGNALS (1)
(2)
X
X = Don't care.
The associated LCD segment is package dependent. See the Signal Descriptions tables and Pin Diagrams figures.
Detailed Description
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Port P7 (P7.4 to P7.7) Pin Functions
PIN NAME (P7.x)
x
FUNCTION
P7.4 (I/O)
P7.4/SMCLK/Sz
4
5
6
7
96
LCDSz
I: 0; O: 1
0
0
0
0
1
0
1
0
0
1
1
0
1
N/A
0
Internally tied to DVSS
1
N/A
0
SMCLK
1
(2)
X
X
X
1
P7.5 (I/O)
I: 0; O: 1
0
0
0
TA0CCI2A
0
TA0.2
1
0
1
0
N/A
0
Internally tied to DVSS
1
1
0
0
N/A
0
Internally tied to DVSS
1
1
1
0
(2)
X
X
X
1
P7.6 (I/O)
I: 0; O: 1
0
0
0
TA0CCI1A
0
TA0.1
1
0
1
0
N/A
0
Internally tied to DVSS
1
1
0
0
N/A
0
Internally tied to DVSS
1
1
1
0
(2)
X
X
X
1
P7.7 (I/O)
I: 0; O: 1
0
0
0
0
1
0
1
0
0
1
1
0
X
X
1
N/A
0
Internally tied to DVSS
1
TA1.CCI2A
0
TA1.2
1
TB0OUTH
0
Internally tied to DVSS
1
Sz
(1)
(2)
P7SEL0.x
Internally tied to DVSS
Sz
P7.7/TA1.2/TB0OUTH/Sz
P7SEL1.x
0
Sz
P7.6/TA0.1/Sz
P7DIR.x
N/A
Sz
P7.5/TA0.2/Sz
CONTROL BITS AND SIGNALS (1)
(2)
X
X = Don't care.
The associated LCD segment is package dependent. See the Signal Descriptions tables and Pin Diagrams figures.
Detailed Description
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5.11.24.13 Port P8 (P8.0 to P8.3) Input/Output With Schmitt Trigger
For the pin diagram, see Figure 5-2. summarizes the selection of the pin function.
Port P8 (P8.0 to P8.3) Pin Functions
PIN NAME (P8.x)
x
FUNCTION
P8.0 (I/O)
P8.0/RTCCLK/Sz
0
1
2
3
LCDSz
I: 0; O: 1
0
0
0
0
1
0
1
0
0
1
1
0
1
N/A
0
Internally tied to DVSS
1
N/A
0
RTCCLK
1
(2)
X
X
X
1
P8.1 (I/O)
I: 0; O: 1
0
0
0
N/A
0
0
1
0
Internally tied to DVSS
1
N/A
0
Internally tied to DVSS
1
1
0
0
DMA0E
0
Internally tied to DVSS
1
1
1
0
(2)
X
X
X
1
P8.2 (I/O)
I: 0; O: 1
0
0
0
0
1
0
1
0
0
1
1
0
N/A
0
Internally tied to DVSS
1
N/A
0
Internally tied to DVSS
1
N/A
0
Internally tied to DVSS
1
(2)
X
X
X
1
P8.3 (I/O)
I: 0; O: 1
0
0
0
0
1
0
1
0
0
1
1
0
X
X
1
N/A
0
Internally tied to DVSS
1
N/A
0
Internally tied to DVSS
1
N/A
0
MCLK
1
Sz
(1)
(2)
P8SEL0.x
Internally tied to DVSS
Sz
P8.3/MCLK/Sz
P8SEL1.x
0
Sz
P8.2/Sz
P8DIR.x
N/A
Sz
P8.1/DMAE0/Sz
CONTROL BITS AND SIGNALS (1)
(2)
X
X = Don't care.
The associated LCD segment is package dependent. See the Signal Descriptions tables and Pin Diagrams figures.
Detailed Description
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5.11.24.14 Port P8 (P8.4 to P8.7) Input/Output With Schmitt Trigger
Figure 5-7 shows the port diagram. summarizes the selection of the pin function.
To ADC
From ADC
To Comparator
From Comparator
CEPD.x
Pad Logic
P8REN.x
P8DIR.x
00
01
10
11
P8OUT.x
Direction
0: Input
1: Output
DVSS
0
DVCC
1
1
00
DVSS
01
DVSS
10
DVSS
11
P8.4/A7/C7
P8.5/A6/C6
P8.6/A5/C5
P8.7/A4/C4
P8SEL1.x
P8SEL0.x
P8IN.x
Bus
Keeper
NOTE: Functional representation only.
Figure 5-7. Port P8 (P8.4 to P8.7) Diagram
98
Detailed Description
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Port P8 (P8.4 to P8.7) Pin Functions
PIN NAME (P8.x)
x
FUNCTION
P8.4 (I/O)
P8.4/A7/C7
4
(3)
0
1
1
0
X
1
1
I: 0; O: 1
0
0
0
1
1
0
X
1
1
I: 0; O: 1
0
0
0
1
1
0
X
1
1
I: 0; O: 1
0
0
0
1
1
0
1
1
0
1
(2) (3)
N/A
0
Internally tied to DVSS
1
N/A
0
Internally tied to DVSS
1
(2) (3)
N/A
0
Internally tied to DVSS
1
N/A
0
Internally tied to DVSS
1
(2) (3)
N/A
0
Internally tied to DVSS
1
N/A
0
Internally tied to DVSS
1
A4/C4
(1)
(2)
0
Internally tied to DVSS
P8.7 (I/O)
7
0
N/A
A5/C5
P8.7/A4/C4
I: 0; O: 1
1
P8.6 (I/O)
6
P8SEL0.x
Internally tied to DVSS
A6/C6
P8.6/A5/C5
P8SEL1.x
0
P8.5 (I/O)
5
P8DIR.x
N/A
A7/C7
P8.5/A6/C6
CONTROL BITS AND SIGNALS (1)
(2) (3)
X
X = Don't care.
Setting P8SEL1.x and P8SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
Setting the CEPD.x bit of the comparator disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals. Selecting the Cx input pin to the comparator multiplexer with the input select bits in the comparator module
automatically disables output driver and input buffer for that pin, regardless of the state of the associated CEPD.x bit.
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5.11.24.15 Port P9 (P9.0 to P9.3) Input/Output With Schmitt Trigger
Figure 5-8 shows the port diagram. summarizes the selection of the pin function.
ESITESTx
To ESI
To ADC
From ADC
To Comparator
From Comparator
CEPD.x
Pad Logic
P9REN.x
P9DIR.x
00
01
10
11
P9OUT.x
Direction
0: Input
1: Output
DVSS
0
DVCC
1
1
00
DVSS
01
DVSS
10
DVSS
11
P9.0/ESICH0/ESITEST0/A8/C8
P9.1/ESICH1/ESITEST1/A9/C9
P9.2/ESICH2/ESITEST2/A10/C10
P9.3/ESICH3/ESITEST3/A11/C11
P9SEL1.x
P9SEL0.x
P9IN.x
Bus
Keeper
NOTE: Functional representation only.
Figure 5-8. Port P9 (P9.0 to P9.3) Diagram
100
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Port P9 (P9.0 to P9.3) Pin Functions
PIN NAME (P9.x)
x
FUNCTION
P9.0 (I/O)
P9.0/ESICH0/ESITEST0/A8/C8
0
(3)
(4)
0
1
1
0
X
1
1
I: 0; O: 1
0
0
0
1
N/A
0
Internally tied to DVSS
1
ESITEST1 (2)
X
1
0
X
1
1
I: 0; O: 1
0
0
0
1
(2) (3) (4)
N/A
0
Internally tied to DVSS
1
ESITEST2 (2)
X
1
0
X
1
1
I: 0; O: 1
0
0
0
1
(2) (3) (4)
N/A
0
Internally tied to DVSS
1
ESITEST3 (2)
X
1
0
X
1
1
ESICH3/A11/C11
(1)
(2)
0
X
(2) (3) (4)
P9.3 (I/O)
3
0
ESITEST0 (2)
ESICH2/A10/C10
P9.3/ESICH3/ESITEST3/A11/C11
I: 0; O: 1
1
P9.2 (I/O)
2
P9SEL0.x
Internally tied to DVSS
ESICH1/A9/C9
P9.2/ESICH2/ESITEST2/A10/C10
P9SEL1.x
0
P9.1 (I/O)
1
P9DIR.x
N/A
ESICH0/A8/C8
P9.1/ESICH1/ESITEST1/A9/C9
CONTROL BITS AND SIGNALS (1)
(2) (3) (4)
X = Don't care.
Setting P9SEL1.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog
signals.
Setting the CEPD.x bit of the comparator disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals. Selecting the Cx input pin to the comparator multiplexer with the input select bits in the comparator module
automatically disables output driver and input buffer for that pin, regardless of the state of the associated CEPD.x bit.
Depending on the configuration of the ESI module other ESICHx pins are stimulated as well and thus should have the input Schmitt
triggers disabled (with P9SEL1.x = 1) and cannot be used as digital I/O, ADC or comparator inputs.
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5.11.24.16 Port P9 (P9.4 to P9.7) Input/Output With Schmitt Trigger
Figure 5-9 shows the port diagram. summarizes the selection of the pin function.
To ESI
To ADC
From ADC
To Comparator
From Comparator
CEPD.x
Pad Logic
P9REN.x
P9DIR.x
00
01
10
11
P9OUT.x
Direction
0: Input
1: Output
DVSS
0
DVCC
1
1
00
DVSS
01
DVSS
10
DVSS
11
P9.4/ESICI0/A12/C12
P9.5/ESICI1/A13/C13
P9.6/ESICI2/A14/C14
P9.7/ESICI3/A15/C15
P9SEL1.x
P9SEL0.x
P9IN.x
Bus
Keeper
NOTE: Functional representation only.
Figure 5-9. Port P9 (P9.4 to P9.7) Diagram
102
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Port P9 (P9.4 to P9.7) Pin Functions
PIN NAME (P9.x)
x
FUNCTION
P9.4 (I/O)
P9.4/ESICI0/A12/C12
4
(3)
(4)
0
1
1
0
X
1
1
I: 0; O: 1
0
0
0
1
1
0
X
1
1
I: 0; O: 1
0
0
0
1
1
0
X
1
1
I: 0; O: 1
0
0
0
1
1
0
1
1
0
1
(2) (3) (4)
N/A
0
Internally tied to DVSS
1
N/A
0
Internally tied to DVSS
1
(2) (3) (4)
N/A
0
Internally tied to DVSS
1
N/A
0
Internally tied to DVSS
1
(2) (3) (4)
N/A
0
Internally tied to DVSS
1
N/A
0
Internally tied to DVSS
1
ESICI3/A15/C15
(1)
(2)
0
Internally tied to DVSS
P9.7 (I/O)
7
0
N/A
ESICI2/A14/C14
P9.7/ESICI3/A15/C15
I: 0; O: 1
1
P9.6 (I/O)
6
P9SEL0.x
Internally tied to DVSS
ESICI1/A13/C13
P9.6/ESICI2/A14/C14
P9SEL1.x
0
P9.5 (I/O)
5
P9DIR.x
N/A
ESICI0/A12/C12
P9.5/ESICI1/A13/C13
CONTROL BITS AND SIGNALS (1)
(2) (3) (4)
X
X = Don't care.
Setting P9SEL1.x and P9SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
Setting the CEPD.x bit of the comparator disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals. Selecting the Cx input pin to the comparator multiplexer with the input select bits in the comparator module
automatically disables output driver and input buffer for that pin, regardless of the state of the associated CEPD.x bit.
Depending on the configuration of the ESI module, other ESICI2/ pins are used, and thus should have the input Schmitt triggers
disabled (with P9SEL1.x = 1 and P9SEL0.x = 1) and cannot be used as digital I/O, ADC, or comparator inputs.
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5.11.24.17 Port P10 (P10.0 to P10.2) Input/Output With Schmitt Trigger
For the pin diagram, see Figure 5-2. summarizes the selection of the pin function.
Port P10 (P10.0 to P10.2) Pin Functions
PIN NAME (P10.x)
x
FUNCTION
P10.0 (I/O)
P10.0/SMCLK/Sz
0
1
2
104
P10SEL0.x
LCDSz
I: 0; O: 1
0
0
0
0
1
0
1
0
0
1
1
0
Internally tied to DVSS
1
N/A
0
Internally tied to DVSS
1
N/A
0
SMCLK
1
(2)
X
X
X
1
P10.1 (I/O)
I: 0; O: 1
0
0
0
TA0.CCI0B
0
TA0.0
1
0
1
0
N/A
0
Internally tied to DVSS
1
1
0
0
N/A
0
Internally tied to DVSS
1
1
1
0
X
X
X
1
P10.2 (I/O)
I: 0; O: 1
0
0
0
TA1.CCI0B
0
TA1.0
1
0
1
0
N/A
0
Internally tied to DVSS
1
1
0
0
N/A
0
SMCLK
1
1
1
0
X
X
1
Sz
(1)
(2)
P10SEL1.x
0
Sz
P10.2/TA1.0/SMCLK/Sz
P10DIR.x
N/A
Sz
P10.1/TA0.0/Sz
CONTROL BITS AND SIGNALS (1)
(2)
(2)
X
X = Don't care.
The associated LCD segment is package dependent. See the Signal Descriptions tables and Pin Diagrams figures.
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5.11.24.18 Port PJ (PJ.4 and PJ.5) Input/Output With Schmitt Trigger
Figure 5-10 and Figure 5-11 show the port diagrams. summarizes the selection of the pin function.
Pad Logic
To LFXT XIN
PJREN.4
PJDIR.4
00
01
10
Direction
0: Input
1: Output
11
PJOUT.4
DVSS
0
DVCC
1
1
00
DVSS
01
DVSS
10
DVSS
11
PJ.4/LFXIN
PJSEL1.4
PJSEL0.4
PJIN.4
EN
To modules
Bus
Keeper
D
NOTE: Functional representation only.
Figure 5-10. Port PJ (PJ.4) Diagram
Detailed Description
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Pad Logic
To LFXT XOUT
PJSEL0.4
PJSEL1.4
LFXTBYPASS
PJREN.5
PJDIR.5
00
01
10
Direction
0: Input
1: Output
11
PJOUT.5
DVSS
0
DVCC
1
1
00
DVSS
01
DVSS
10
DVSS
11
PJ.5/LFXOUT
PJSEL1.5
PJSEL0.5
PJIN.5
EN
To modules
Bus
Keeper
D
NOTE: Functional representation only.
Figure 5-11. Port PJ (PJ.5) Diagram
106
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Port PJ (PJ.4 and PJ.5) Pin Functions
CONTROL BITS AND SIGNALS (1)
PIN NAME (PJ.x)
x
FUNCTION
PJ.4 (I/O)
PJ.4/LFXIN
4
PJSEL0.4
LFXT
BYPASS
I: 0; O: 1
X
X
0
0
X
X
X
1
X
X
1
(2)
X
X
X
0
1
0
X
X
X
0
1
1
I: 0; O: 1
0
0
(2)
N/A
0
Internally tied to DVSS
LFXOUT crystal mode
(3)
(4)
PJSEL1.4
Internally tied to DVSS
PJ.5 (I/O)
(1)
(2)
PJSEL0.5
0
LFXIN bypass mode
5
PJSEL1.5
N/A
LFXIN crystal mode
PJ.5/LFXOUT
PJDIR.x
1
(2)
X
see
see
X
(4)
(4)
see
see
X
(4)
(4)
0
0
1
X
X
X
0
0
1
X
X
X
0
0
1
X
X
X
1 (3)
0
1
0
0
1 (3)
0
1 (3)
0
X = Don't care.
Setting PJSEL1.4 = 0 and PJSEL0.4 = 1 causes the general-purpose I/O to be disabled. When LFXTBYPASS = 0, PJ.4 and PJ.5 are
configured for crystal operation and PJSEL1.5 and PJSEL0.5 are don't care. When LFXTBYPASS = 1, PJ.4 is configured for bypass
operation and PJ.5 is configured as general-purpose I/O.
When PJ.4 is configured in bypass mode, PJ.5 is configured as general-purpose I/O.
With PJSEL0.5 = 1 or PJSEL1.5 =1 the general-purpose I/O functionality is disabled. No input function is available. When configured as
output, the pin is actively pulled to zero.
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5.11.24.19 Port PJ (PJ.6 and PJ.7) Input/Output With Schmitt Trigger
Figure 5-12 and Figure 5-13 show the port diagrams. summarizes the selection of the pin function.
Pad Logic
To HFXT XIN
PJREN.6
PJDIR.6
00
01
10
Direction
0: Input
1: Output
11
PJOUT.6
DVSS
0
DVCC
1
1
00
DVSS
01
DVSS
10
DVSS
11
PJ.6/HFXIN
PJSEL1.6
PJSEL0.6
PJIN.6
EN
To modules
Bus
Keeper
D
NOTE: Functional representation only.
Figure 5-12. Port PJ (PJ.6) Diagram
108
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Pad Logic
To HFXT XOUT
PJSEL0.6
PJSEL1.6
HFXTBYPASS
PJREN.7
PJDIR.7
00
01
10
Direction
0: Input
1: Output
11
PJOUT.7
DVSS
0
DVCC
1
1
00
DVSS
01
DVSS
10
DVSS
11
PJ.7/HFXOUT
PJSEL1.7
PJSEL0.7
PJIN.7
EN
To modules
Bus
Keeper
D
NOTE: Functional representation only.
Figure 5-13. Port PJ (PJ.7) Diagram
Detailed Description
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Port PJ (PJ.6 and PJ.7) Pin Functions
CONTROL BITS AND SIGNALS (1)
PIN NAME (PJ.x)
x
FUNCTION
PJ.6 (I/O)
PJ.6/HFXIN
6
HFXT
BYPASS
I: 0; O: 1
X
X
0
0
X
X
X
1
X
X
(2)
X
X
X
0
1
0
X
X
X
0
1
1
I: 0; O: 1
0
0
(2)
N/A
0
HFXOUT crystal mode
110
PJSEL0.6
1
Internally tied to DVSS
(3)
(4)
PJSEL1.6
Internally tied to DVSS
PJ.7 (I/O)
(1)
(2)
PJSEL0.7
0
HFXIN bypass mode
7
PJSEL1.7
N/A
HFXIN crystal mode
PJ.7/HFXOUT
PJDIR.x
1
(2)
X
see
see
X
(4)
(4)
see
see
X
(4)
(4)
0
0
1
X
X
X
0
0
1
X
X
X
0
0
1
X
X
X
1 (3)
0
1
0
0
1 (3)
0
1 (3)
0
X = Don't care.
Setting PJSEL1.6 = 0 and PJSEL0.6 = 1 causes the general-purpose I/O to be disabled. When HFXTBYPASS = 0, PJ.6 and PJ.7 are
configured for crystal operation and PJSEL1.6 and PJSEL0.7 are don't care. When HFXTBYPASS = 1, PJ.6 is configured for bypass
operation and PJ.7 is configured as general-purpose I/O.
When PJ.6 is configured in bypass mode, PJ.7 is configured as general-purpose I/O.
With PJSEL0.7 = 1 or PJSEL1.7 =1 the general-purpose I/O functionality is disabled. No input function is available. When configured as
output, the pin is actively pulled to zero.
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5.11.24.20 Port PJ (PJ.0 to PJ.3) JTAG Pins TDO, TMS, TCK, TDI/TCLK, Input/Output With Schmitt
Trigger
Figure 5-14 shows the port diagram. summarizes the selection of the pin function.
Pad Logic
DVSS
JTAG enable
From JTAG
From JTAG
PJREN.x
PJDIR.x
00
1
01
Direction
0: Input
1: Output
11
PJOUT.x
DVSS
0
DVCC
1
0
10
1
00
From module 1
01
1
From Status Register (SR)
10
0
DVSS
11
PJSEL1.x
PJSEL0.x
PJIN.x
EN
Bus
Keeper
PJ.0/TDO/TB0OUTH/
SMCLK SRSCG1
PJ.1/TDI/TCLK/MCLK/
SRSCG0
PJ.2/TMS/ACLK/
SROSCOFF
PJ.3/TCK/COUT/
SRCPUOFF
D
To modules
and JTAG
NOTE: Functional representation only.
Figure 5-14. Port PJ (PJ.0 to PJ.3) Diagram
Detailed Description
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Port PJ (PJ.0 to PJ.3) Pin Functions
PIN NAME (PJ.x)
x
FUNCTION
PJ.0 (I/O)
TDO
PJ.0/TDO/TB0OUTH/
SMCLK/SRSCG1
PJ.1/TDI/TCLK/
MCLK/SRSCG0
0
1
(3)
(1)
(2)
(3)
(4)
(5)
112
0
X
0
1
1
0
1
1
N/A
0
CPU Status Register Bit SCG1
1
N/A
0
Internally tied to DVSS
1
PJ.1 (I/O)
(2)
I: 0; O: 1
0
0
TDI/TCLK
(3) (5)
X
X
X
0
1
1
0
1
1
N/A
0
MCLK
1
N/A
0
CPU Status Register Bit SCG0
1
N/A
0
Internally tied to DVSS
1
(2)
I: 0; O: 1
0
0
X
X
X
0
1
1
0
1
1
(3) (5)
N/A
0
ACLK
1
N/A
0
CPU Status Register Bit OSCOFF
1
N/A
0
Internally tied to DVSS
1
(2)
I: 0; O: 1
0
0
X
X
X
0
1
1
0
1
1
TCK
3
0
X
1
PJ.3 (I/O)
PJ.3/TCK/COUT/
SRCPUOFF
PJSEL0.x
X
0
SMCLK
PJSEL1.x
I: 0; O: 1
(4)
TMS
2
PJDIR.x
TB0OUTH
PJ.2 (I/O)
PJ.2/TMS/ACLK/
SROSCOFF
(2)
CONTROL BITS OR SIGNALS (1)
(3) (5)
N/A
0
COUT
1
N/A
0
CPU Status Register Bit CPUOFF
1
N/A
0
Internally tied to DVSS
1
X = Don't care
Default condition
The pin direction is controlled by the JTAG module. JTAG mode selection is made through the SYS module or by the Spy-Bi-Wire 4-wire
entry sequence. Neither PJSEL1.x and PJSEL0.x nor CEPD.x bits have an effect in these cases.
Do not use this pin as SMCLK output if the TB0OUTH functionality is used on any other pin. Select an alternative SMCLK output pin.
In JTAG mode, pullups are activated automatically on TMS, TCK, and TDI/TCLK. PJREN.x are don't care.
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5.12 Device Descriptors (TLV)
Table 5-20 summarizes the Device IDs. Table 5-21 lists the contents of the device descriptor tag-lengthvalue (TLV) structure for each device type.
Table 5-20. Device ID
DEVICE ID
DEVICE
MSP430FR5989
01A05h
01A04h
081h
0ABh
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Table 5-21. Device Descriptor Table
MSP430FRxxxx (UART BSL)
DESCRIPTION
ADDRESS
VALUE
ADDRESS
VALUE
01A00h
06h
01A00h
06h
CRC length
01A01h
06h
01A01h
06h
01A02h
Per unit
01A02h
Per unit
01A03h
Per unit
01A03h
Per unit
Info Block
01A04h
Device ID
01A05h
See .
01A06h
Per unit
01A06h
Per unit
01A07h
Per unit
01A07h
Per unit
Die record tag
01A08h
08h
01A08h
08h
Die record length
01A09h
0Ah
01A09h
0Ah
01A0Ah
Per unit
01A0Ah
Per unit
01A0Bh
Per unit
01A0Bh
Per unit
01A0Ch
Per unit
01A0Ch
Per unit
01A0Dh
Per unit
01A0Dh
Per unit
01A0Eh
Per unit
01A0Eh
Per unit
01A0Fh
Per unit
01A0Fh
Per unit
01A10h
Per unit
01A10h
Per unit
01A11h
Per unit
01A11h
Per unit
01A12h
Per unit
01A12h
Per unit
01A13h
Per unit
01A13h
Per unit
ADC12B calibration tag
01A14h
11h
01A14h
11h
ADC12B calibration length
01A15h
10h
01A15h
10h
01A16h
Per unit
01A16h
Per unit
01A17h
Per unit
01A17h
Per unit
01A18h
Per unit
01A18h
Per unit
Die X position
Die Y position
Test results
ADC gain factor (2)
ADC offset (3)
114
01A05h
Firmware revision
Die Record
(3)
See .
01A04h
Hardware revision
Lot/wafer ID
(1)
(2)
MSP430FRxxxx1 (I2C BSL)
Info length
CRC value
ADC12B
Calibration
(1)
01A19h
Per unit
01A19h
Per unit
ADC 1.2-V reference
Temperature sensor 30°C
01A1Ah
Per unit
01A1Ah
Per unit
01A1Bh
Per unit
01A1Bh
Per unit
ADC 1.2-V reference
Temperature sensor 95°C
01A1Ch
Per unit
01A1Ch
Per unit
01A1Dh
Per unit
01A1Dh
Per unit
ADC 2.0-V reference
Temperature sensor 30°C
01A1Eh
Per unit
01A1Eh
Per unit
01A1Fh
Per unit
01A1Fh
Per unit
ADC 2.0-V reference
Temperature sensor 95°C
01A20h
Per unit
01A20h
Per unit
01A21h
Per unit
01A21h
Per unit
ADC 2.5-V reference
Temperature sensor 30°C
01A22h
Per unit
01A22h
Per unit
01A23h
Per unit
01A23h
Per unit
ADC 2.5-V reference
Temperature sensor 95°C
01A24h
Per unit
01A24h
Per unit
01A25h
Per unit
01A25h
Per unit
NA = Not applicable, Per unit = Content can differ from device to device
ADC gain: The gain correction factor is measured using the internal voltage reference with REFOUT = 0. Other settings (for example,
with REFOUT = 1) can result in different correction factors.
ADC offset: The offset correction factor is measured using the internal 2.5-V reference.
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Table 5-21. Device Descriptor Table (1) (continued)
MSP430FRxxxx (UART BSL)
DESCRIPTION
ADDRESS
VALUE
ADDRESS
VALUE
REF calibration tag
01A26h
12h
01A26h
12h
REF calibration length
01A27h
06h
01A27h
06h
01A28h
Per unit
01A28h
Per unit
REF 1.2-V reference
01A29h
Per unit
01A29h
Per unit
01A2Ah
Per unit
01A2Ah
Per unit
01A2Bh
Per unit
01A2Bh
Per unit
01A2Ch
Per unit
01A2Ch
Per unit
01A2Dh
Per unit
01A2Dh
Per unit
128-bit random number tag
01A2Eh
15h
01A2Eh
15h
Random number length
01A2Fh
10h
01A2Fh
10h
01A30h
Per unit
01A30h
Per unit
01A31h
Per unit
01A31h
Per unit
01A32h
Per unit
01A32h
Per unit
01A33h
Per unit
01A33h
Per unit
01A34h
Per unit
01A34h
Per unit
01A35h
Per unit
01A35h
Per unit
01A36h
Per unit
01A36h
Per unit
01A37h
Per unit
01A37h
Per unit
01A38h
Per unit
01A38h
Per unit
01A39h
Per unit
01A39h
Per unit
01A3Ah
Per unit
01A3Ah
Per unit
01A3Bh
Per unit
01A3Bh
Per unit
01A3Ch
Per unit
01A3Ch
Per unit
01A3Dh
Per unit
01A3Dh
Per unit
01A3Eh
Per unit
01A3Eh
Per unit
01A3Fh
Per unit
01A3Fh
Per unit
REF Calibration
REF 2.0-V reference
REF 2.5-V reference
Random Number
128-bit random number (4)
BSL Configuration
(4)
MSP430FRxxxx1 (I2C BSL)
BSL tag
01A40h
1Ch
01A40h
1Ch
BSL length
01A41h
02h
01A41h
02h
BSL interface
01A42h
00h
01A42h
01h
BSL interface configuration
01A43h
00h
01A43h
48h
128-bit random number: The random number is generated during production test using the CryptGenRandom() function from Microsoft®.
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5.13 Memory
Table 5-22 summarizes the memory map.
Table 5-22. Memory Organization (1)
MSP430FRxxx9(1)
Memory (FRAM)
Main: interrupt vectors
and signatures
Main: code memory
Total Size
127KB
00FFFFh–00FF80h
023FFFh–004400h
Sect 1
2KB
0023FFh–001C00h
RAM
Boot memory (ROM)
256 B
001BFFh–001B00h
Device Descriptor Info
(TLV)
256 B
001AFFh–001A00h
Info A
128 B
0019FFh–001980h
Info B
128 B
00197Fh–001900h
Info C
128 B
0018FFh–001880h
Info D
128 B
00187Fh–001800h
BSL 3
512 B
0017FFh–001600h
BSL 2
512 B
0015FFh–001400h
BSL 1
512 B
0013FFh–001200h
BSL 0
512 B
0011FFh–001000h
Peripherals
Size
4KB
000FFFh–000020h
Tiny RAM
Size
26 B
000001Fh–000006h
Reserved (ROM)
Size
6B
000005h–000000h
Information memory
(FRAM)
Bootloader (BSL)
memory (ROM)
(1)
116
All address space not listed is considered vacant memory.
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5.13.1 Peripheral File Map
Table 5-23 lists the base address for each available peripheral. Table 5-24 through Table 5-59 list the
registers and their offsets for each peripheral.
Table 5-23. Peripherals
MODULE NAME
BASE ADDRESS
OFFSET ADDRESS
RANGE
Special Functions (see Table 5-24)
0100h
000h–01Fh
PMM (see Table 5-25)
0120h
000h–01Fh
FRAM Control (see Table 5-26)
0140h
000h–00Fh
CRC16 (see Table 5-27)
0150h
000h–007h
000h–001h
RAM Controller (see Table 5-28)
0158h
Watchdog Timer (see Table 5-29)
015Ch
000h–001h
CS (see Table 5-30)
0160h
000h–00Fh
SYS (see Table 5-31)
0180h
000h–01Fh
Shared Reference (see Table 5-32)
01B0h
000h–001h
Port P1, P2 (see Table 5-33)
0200h
000h–01Fh
Port P3, P4 (see Table 5-34)
0220h
000h–01Fh
Port P5, P6 (see Table 5-35)
0240h
000h–01Fh
Port P7, P8 (see Table 5-36)
0260h
000h–01Fh
Port P9, P10 (see Table 5-37)
0280h
000h–01Fh
Port PJ (see Table 5-38)
0320h
000h–01Fh
Timer_A TA0 (see Table 5-39)
0340h
000h–02Fh
Timer_A TA1 (see Table 5-40)
0380h
000h–02Fh
Timer_B TB0 (see Table 5-41)
03C0h
000h–02Fh
Timer_A TA2 (see Table 5-42)
0400h
000h–02Fh
Capacitive Touch I/O 0 (see Table 5-43)
0430h
000h–00Fh
Timer_A TA3 (see Table 5-44)
0440h
000h–02Fh
Capacitive Touch I/O 1 (see Table 5-45)
0470h
000h–00Fh
Real-Time Clock (RTC_C) (see Table 5-46)
04A0h
000h–01Fh
32-Bit Hardware Multiplier (see Table 5-47)
04C0h
000h–02Fh
DMA General Control (see Table 5-48)
0500h
000h–00Fh
DMA Channel 0 (see Table 5-48)
0510h
000h–00Fh
DMA Channel 1 (see Table 5-48)
0520h
000h–00Fh
DMA Channel 2 (see Table 5-48)
0530h
000h–00Fh
MPU (see Table 5-49)
05A0h
000h–00Fh
eUSCI_A0 (see Table 5-50)
05C0h
000h–01Fh
eUSCI_A1 (see Table 5-51)
05E0h
000h–01Fh
eUSCI_B0 (see Table 5-52)
0640h
000h–02Fh
eUSCI_B1 (see Table 5-53)
0680h
000h–02Fh
ADC12_B (see Table 5-54)
0800h
000h–09Fh
Comparator_E (see Table 5-55)
08C0h
000h–00Fh
CRC32 (see Table 5-56)
0980h
000h–02Fh
AES (see Table 5-57)
09C0h
000h–00Fh
LCD_C (see Table 5-58)
0A00h
000h–05Fh
ESI (see Table 5-59)
0D00h
000h–09Fh
ESI RAM (128 bytes)
0E00h
00h–07Fh
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Table 5-24. Special Function Registers (Base Address: 0100h)
REGISTER DESCRIPTION
REGISTER
OFFSET
SFR interrupt enable
SFRIE1
00h
SFR interrupt flag
SFRIFG1
02h
SFR reset pin control
SFRRPCR
04h
Table 5-25. PMM Registers (Base Address: 0120h)
REGISTER DESCRIPTION
REGISTER
OFFSET
PMM control 0
PMMCTL0
00h
PMM interrupt flags
PMMIFG
0Ah
PM5 control 0
PM5CTL0
10h
Table 5-26. FRAM Control Registers (Base Address: 0140h)
REGISTER DESCRIPTION
REGISTER
OFFSET
FRAM control 0
FRCTL0
00h
General control 0
GCCTL0
04h
General control 1
GCCTL1
06h
Table 5-27. CRC16 Registers (Base Address: 0150h)
REGISTER DESCRIPTION
REGISTER
OFFSET
CRC data input
CRC16DI
00h
CRC data input reverse byte
CRCDIRB
02h
CRC initialization and result
CRCINIRES
04h
CRC result reverse byte
CRCRESR
06h
Table 5-28. RAM Controller Registers (Base Address: 0158h)
REGISTER DESCRIPTION
RAM controller control 0
REGISTER
RCCTL0
OFFSET
00h
Table 5-29. Watchdog Registers (Base Address: 015Ch)
REGISTER DESCRIPTION
Watchdog timer control
REGISTER
WDTCTL
OFFSET
00h
Table 5-30. CS Registers (Base Address: 0160h)
REGISTER DESCRIPTION
REGISTER
OFFSET
CS control 0
CSCTL0
00h
CS control 1
CSCTL1
02h
CS control 2
CSCTL2
04h
CS control 3
CSCTL3
06h
CS control 4
CSCTL4
08h
CS control 5
CSCTL5
0Ah
CS control 6
CSCTL6
0Ch
Table 5-31. SYS Registers (Base Address: 0180h)
REGISTER DESCRIPTION
REGISTER
OFFSET
System control
SYSCTL
00h
JTAG mailbox control
SYSJMBC
06h
118
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Table 5-31. SYS Registers (Base Address: 0180h) (continued)
REGISTER DESCRIPTION
REGISTER
OFFSET
JTAG mailbox input 0
SYSJMBI0
08h
JTAG mailbox input 1
SYSJMBI1
0Ah
JTAG mailbox output 0
SYSJMBO0
0Ch
JTAG mailbox output 1
SYSJMBO1
0Eh
User NMI vector generator
SYSUNIV
1Ah
System NMI vector generator
SYSSNIV
1Ch
Reset vector generator
SYSRSTIV
1Eh
Table 5-32. Shared Reference Registers (Base Address: 01B0h)
REGISTER DESCRIPTION
Shared reference control
REGISTER
REFCTL
OFFSET
00h
Table 5-33. Port P1, P2 Registers (Base Address: 0200h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P1 input
P1IN
00h
Port P1 output
P1OUT
02h
Port P1 direction
P1DIR
04h
Port P1 resistor enable
P1REN
06h
Port P1 selection 0
P1SEL0
0Ah
Port P1 selection 1
P1SEL1
0Ch
Port P1 interrupt vector word
P1IV
0Eh
Port P1 complement selection
P1SELC
16h
Port P1 interrupt edge select
P1IES
18h
Port P1 interrupt enable
P1IE
1Ah
Port P1 interrupt flag
P1IFG
1Ch
Port P2 input
P2IN
01h
Port P2 output
P2OUT
03h
Port P2 direction
P2DIR
05h
Port P2 resistor enable
P2REN
07h
Port P2 selection 0
P2SEL0
0Bh
Port P2 selection 1
P2SEL1
0Dh
Port P2 complement selection
P2SELC
17h
Port P2 interrupt vector word
P2IV
1Eh
Port P2 interrupt edge select
P2IES
19h
Port P2 interrupt enable
P2IE
1Bh
Port P2 interrupt flag
P2IFG
1Dh
Table 5-34. Port P3, P4 Registers (Base Address: 0220h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P3 input
P3IN
00h
Port P3 output
P3OUT
02h
Port P3 direction
P3DIR
04h
Port P3 resistor enable
P3REN
06h
Port P3 selection 0
P3SEL0
0Ah
Port P3 selection 1
P3SEL1
0Ch
Port P3 interrupt vector word
P3IV
0Eh
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Table 5-34. Port P3, P4 Registers (Base Address: 0220h) (continued)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P3 complement selection
P3SELC
16h
Port P3 interrupt edge select
P3IES
18h
Port P3 interrupt enable
P3IE
1Ah
Port P3 interrupt flag
P3IFG
1Ch
Port P4 input
P4IN
01h
Port P4 output
P4OUT
03h
Port P4 direction
P4DIR
05h
Port P4 resistor enable
P4REN
07h
Port P4 selection 0
P4SEL0
0Bh
Port P4 selection 1
P4SEL1
0Dh
Port P4 complement selection
P4SELC
17h
Port P4 interrupt vector word
P4IV
1Eh
Port P4 interrupt edge select
P4IES
19h
Port P4 interrupt enable
P4IE
1Bh
Port P4 interrupt flag
P4IFG
1Dh
Table 5-35. Port P5, P6 Registers (Base Address: 0240h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P5 input
P5IN
00h
Port P5 output
P5OUT
02h
Port P5 direction
P5DIR
04h
Port P5 resistor enable
P5REN
06h
Port P5 selection 0
P5SEL0
0Ah
Port P5 selection 1
P5SEL1
0Ch
Reserved
0Eh
Port P5 complement selection
P5SELC
16h
Reserved
18h
Reserved
1Ah
Reserved
1Ch
Port P6 input
P6IN
01h
Port P6 output
P6OUT
03h
Port P6 direction
P6DIR
05h
Port P6 resistor enable
P6REN
07h
Port P6 selection 0
P6SEL0
0Bh
Port P6 selection 1
P6SEL1
0Dh
Port P6 complement selection
P6SELC
17h
Reserved
1Eh
Reserved
19h
Reserved
1Bh
Reserved
1Dh
Table 5-36. Port P7, P8 Registers (Base Address: 0260h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P7 input
P7IN
00h
Port P7 output
P7OUT
02h
Port P7 direction
P7DIR
04h
Port P7 resistor enable
P7REN
06h
120
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Table 5-36. Port P7, P8 Registers (Base Address: 0260h) (continued)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P7 selection 0
P7SEL0
0Ah
Port P7 selection 1
P7SEL1
0Ch
Reserved
0Eh
Port P7 complement selection
P7SELC
16h
Reserved
18h
Reserved
1Ah
Reserved
1Ch
Port P8 input
P8IN
01h
Port P8 output
P8OUT
03h
Port P8 direction
P8DIR
05h
Port P8 resistor enable
P8REN
07h
Port P8 selection 0
P8SEL0
0Bh
Port P8 selection 1
P8SEL1
0Dh
Port P8 complement selection
P8SELC
17h
Reserved
1Eh
Reserved
19h
Reserved
1Bh
Reserved
1Dh
Table 5-37. Port P9, P10 Registers (Base Address: 0280h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P9 input
P9IN
00h
Port P9 output
P9OUT
02h
Port P9 direction
P9DIR
04h
Port P9 resistor enable
P9REN
06h
Port P9 selection 0
P9SEL0
0Ah
Port P9 selection 1
P9SEL1
0Ch
Reserved
Port P9 complement selection
0Eh
P9SELC
16h
Reserved
18h
Reserved
1Ah
Reserved
1Ch
Port P10 input
P10IN
01h
Port P10 output
P10OUT
03h
Port P10 direction
P10DIR
05h
Port P10 resistor enable
P10REN
07h
Port P10 selection 0
P10SEL0
0Bh
Port P10 selection 1
P10SEL1
0Dh
Port P10 complement selection
P10SELC
17h
Reserved
1Eh
Reserved
19h
Reserved
1Bh
Reserved
1Dh
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Table 5-38. Port J Registers (Base Address: 0320h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port PJ input
PJIN
00h
Port PJ output
PJOUT
02h
Port PJ direction
PJDIR
04h
Port PJ resistor enable
PJREN
06h
Port PJ selection 0
PJSEL0
0Ah
Port PJ selection 1
PJSEL1
0Ch
Port PJ complement selection
PJSELC
16h
Table 5-39. Timer_A TA0 Registers (Base Address: 0340h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TA0 control
TA0CTL
00h
Capture/compare control 0
TA0CCTL0
02h
Capture/compare control 1
TA0CCTL1
04h
Capture/compare control 2
TA0CCTL2
06h
Capture/compare control 3
TA0CCTL3
08h
Capture/compare control 4
TA0CCTL4
0Ah
TA0 counter
TA0R
10h
Capture/compare 0
TA0CCR0
12h
Capture/compare 1
TA0CCR1
14h
Capture/compare 2
TA0CCR2
16h
Capture/compare 3
TA0CCR3
18h
Capture/compare 4
TA0CCR4
1Ah
TA0 expansion 0
TA0EX0
20h
TA0 interrupt vector
TA0IV
2Eh
Table 5-40. Timer_A TA1 Registers (Base Address: 0380h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TA1 control
TA1CTL
00h
Capture/compare control 0
TA1CCTL0
02h
Capture/compare control 1
TA1CCTL1
04h
Capture/compare control 2
TA1CCTL2
06h
TA1 counter
TA1R
10h
Capture/compare 0
TA1CCR0
12h
Capture/compare 1
TA1CCR1
14h
Capture/compare 2
TA1CCR2
16h
TA1 expansion 0
TA1EX0
20h
TA1 interrupt vector
TA1IV
2Eh
Table 5-41. Timer_B TB0 Registers (Base Address: 03C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TB0 control
TB0CTL
00h
Capture/compare control 0
TB0CCTL0
02h
Capture/compare control 1
TB0CCTL1
04h
Capture/compare control 2
TB0CCTL2
06h
Capture/compare control 3
TB0CCTL3
08h
Capture/compare control 4
TB0CCTL4
0Ah
122
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Table 5-41. Timer_B TB0 Registers (Base Address: 03C0h) (continued)
REGISTER DESCRIPTION
REGISTER
OFFSET
Capture/compare control 5
TB0CCTL5
0Ch
Capture/compare control 6
TB0CCTL6
0Eh
TB0 counter
TB0R
10h
Capture/compare 0
TB0CCR0
12h
Capture/compare 1
TB0CCR1
14h
Capture/compare 2
TB0CCR2
16h
Capture/compare 3
TB0CCR3
18h
Capture/compare 4
TB0CCR4
1Ah
Capture/compare 5
TB0CCR5
1Ch
Capture/compare 6
TB0CCR6
1Eh
TB0 expansion 0
TB0EX0
20h
TB0 interrupt vector
TB0IV
2Eh
Table 5-42. Timer_A TA2 Registers (Base Address: 0400h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TA2 control
TA2CTL
00h
Capture/compare control 0
TA2CCTL0
02h
Capture/compare control 1
TA2CCTL1
04h
TA2 counter
TA2R
10h
Capture/compare 0
TA2CCR0
12h
Capture/compare 1
TA2CCR1
14h
TA2 expansion 0
TA2EX0
20h
TA2 interrupt vector
TA2IV
2Eh
Table 5-43. Capacitive Touch I/O 0 Registers (Base Address: 0430h)
REGISTER DESCRIPTION
Capacitive Touch I/O 0 control
REGISTER
CAPTIO0CTL
OFFSET
0Eh
Table 5-44. Timer_A TA3 Registers (Base Address: 0440h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TA3 control
TA3CTL
00h
Capture/compare control 0
TA3CCTL0
02h
Capture/compare control 1
TA3CCTL1
04h
Capture/compare control 2
TA3CCTL2
06h
Capture/compare control 3
TA3CCTL3
08h
Capture/compare control 4
TA3CCTL4
0Ah
TA3 counter
TA3R
10h
Capture/compare 0
TA3CCR0
12h
Capture/compare 1
TA3CCR1
14h
Capture/compare 2
TA3CCR2
16h
Capture/compare 3
TA3CCR3
18h
Capture/compare 4
TA3CCR4
1Ah
TA3 expansion 0
TA3EX0
20h
TA3 interrupt vector
TA3IV
2Eh
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Table 5-45. Capacitive Touch I/O 1 Registers (Base Address: 0470h)
REGISTER DESCRIPTION
Capacitive Touch I/O 1 control
REGISTER
CAPTIO1CTL
OFFSET
0Eh
Table 5-46. RTC_C Registers (Base Address: 04A0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
RTC control 0
RTCCTL0
00h
RTC password
RTCPWD
01h
RTC control 1
RTCCTL1
02h
RTC control 3
RTCCTL3
03h
RTC offset calibration
RTCOCAL
04h
RTC temperature compensation
RTCTCMP
06h
RTC prescaler 0 control
RTCPS0CTL
08h
RTC prescaler 1 control
RTCPS1CTL
0Ah
RTC prescaler 0
RTCPS0
0Ch
RTC prescaler 1
RTCPS1
0Dh
RTC interrupt vector word
RTCIV
0Eh
RTC seconds/counter 1
RTCSEC/RTCNT1
10h
RTC minutes/counter 2
RTCMIN/RTCNT2
11h
RTC hours/counter 3
RTCHOUR/RTCNT3
12h
RTC day of week/counter 4
RTCDOW/RTCNT4
13h
RTC days
RTCDAY
14h
RTC month
RTCMON
15h
RTC year
RTCYEAR
16h
RTC alarm minutes
RTCAMIN
18h
RTC alarm hours
RTCAHOUR
19h
RTC alarm day of week
RTCADOW
1Ah
RTC alarm days
RTCADAY
1Bh
Binary-to-BCD conversion
BIN2BCD
1Ch
BCD-to-Binary conversion
BCD2BIN
1Eh
Table 5-47. 32-Bit Hardware Multiplier Registers (Base Address: 04C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
16-bit operand 1 – multiply
MPY
00h
16-bit operand 1 – signed multiply
MPYS
02h
16-bit operand 1 – multiply accumulate
MAC
04h
16-bit operand 1 – signed multiply accumulate
MACS
06h
16-bit operand 2
OP2
08h
16 × 16 result low word
RESLO
0Ah
16 × 16 result high word
RESHI
0Ch
16 × 16 sum extension
SUMEXT
0Eh
32-bit operand 1 – multiply low word
MPY32L
10h
32-bit operand 1 – multiply high word
MPY32H
12h
32-bit operand 1 – signed multiply low word
MPYS32L
14h
32-bit operand 1 – signed multiply high word
MPYS32H
16h
32-bit operand 1 – multiply accumulate low word
MAC32L
18h
32-bit operand 1 – multiply accumulate high word
MAC32H
1Ah
32-bit operand 1 – signed multiply accumulate low word
MACS32L
1Ch
32-bit operand 1 – signed multiply accumulate high word
MACS32H
1Eh
124
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Table 5-47. 32-Bit Hardware Multiplier Registers (Base Address: 04C0h) (continued)
REGISTER DESCRIPTION
REGISTER
OFFSET
32-bit operand 2 – low word
OP2L
20h
32-bit operand 2 – high word
OP2H
22h
32 × 32 result 0 – least significant word
RES0
24h
32 × 32 result 1
RES1
26h
32 × 32 result 2
RES2
28h
32 × 32 result 3 – most significant word
RES3
2Ah
MPY32 control 0
MPY32CTL0
2Ch
Table 5-48. DMA Registers (Base Address DMA General Control: 0500h,
DMA Channel 0: 0510h, DMA Channel 1: 0520h, DMA Channel 2: 0530h)
REGISTER DESCRIPTION
REGISTER
OFFSET
DMA channel 0 control
DMA0CTL
00h
DMA channel 0 source address low
DMA0SAL
02h
DMA channel 0 source address high
DMA0SAH
04h
DMA channel 0 destination address low
DMA0DAL
06h
DMA channel 0 destination address high
DMA0DAH
08h
DMA channel 0 transfer size
DMA0SZ
0Ah
DMA channel 1 control
DMA1CTL
00h
DMA channel 1 source address low
DMA1SAL
02h
DMA channel 1 source address high
DMA1SAH
04h
DMA channel 1 destination address low
DMA1DAL
06h
DMA channel 1 destination address high
DMA1DAH
08h
DMA channel 1 transfer size
DMA1SZ
0Ah
DMA channel 2 control
DMA2CTL
00h
DMA channel 2 source address low
DMA2SAL
02h
DMA channel 2 source address high
DMA2SAH
04h
DMA channel 2 destination address low
DMA2DAL
06h
DMA channel 2 destination address high
DMA2DAH
08h
DMA channel 2 transfer size
DMA2SZ
0Ah
DMA module control 0
DMACTL0
00h
DMA module control 1
DMACTL1
02h
DMA module control 2
DMACTL2
04h
DMA module control 3
DMACTL3
06h
DMA module control 4
DMACTL4
08h
DMA interrupt vector
DMAIV
0Eh
Table 5-49. MPU Control Registers (Base Address: 05A0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
MPU control 0
MPUCTL0
00h
MPU control 1
MPUCTL1
02h
MPU segmentation border 2
MPUSEGB2
04h
MPU segmentation border 1
MPUSEGB1
06h
MPU access management
MPUSAM
08h
MPU IP control 0
MPUIPC0
0Ah
MPU IP encapsulation segment border 2
MPUIPSEGB2
0Ch
MPU IP encapsulation segment border 1
MPUIPSEGB1
0Eh
Detailed Description
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Table 5-50. eUSCI_A0 Registers (Base Address: 05C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
eUSCI_A control word 0
UCA0CTLW0
00h
eUSCI _A control word 1
UCA0CTLW1
02h
eUSCI_A baud rate 0
UCA0BR0
06h
eUSCI_A baud rate 1
UCA0BR1
07h
eUSCI_A modulation control
UCA0MCTLW
08h
eUSCI_A status word
UCA0STATW
0Ah
eUSCI_A receive buffer
UCA0RXBUF
0Ch
eUSCI_A transmit buffer
UCA0TXBUF
0Eh
eUSCI_A LIN control
UCA0ABCTL
10h
eUSCI_A IrDA transmit control
UCA0IRTCTL
12h
eUSCI_A IrDA receive control
UCA0IRRCTL
13h
eUSCI_A interrupt enable
UCA0IE
1Ah
eUSCI_A interrupt flags
UCA0IFG
1Ch
eUSCI_A interrupt vector word
UCA0IV
1Eh
Table 5-51. eUSCI_A1 Registers (Base Address:05E0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
eUSCI_A control word 0
UCA1CTLW0
00h
eUSCI _A control word 1
UCA1CTLW1
02h
eUSCI_A baud rate 0
UCA1BR0
06h
eUSCI_A baud rate 1
UCA1BR1
07h
eUSCI_A modulation control
UCA1MCTLW
08h
eUSCI_A status word
UCA1STATW
0Ah
eUSCI_A receive buffer
UCA1RXBUF
0Ch
eUSCI_A transmit buffer
UCA1TXBUF
0Eh
eUSCI_A LIN control
UCA1ABCTL
10h
eUSCI_A IrDA transmit control
UCA1IRTCTL
12h
eUSCI_A IrDA receive control
UCA1IRRCTL
13h
eUSCI_A interrupt enable
UCA1IE
1Ah
eUSCI_A interrupt flags
UCA1IFG
1Ch
eUSCI_A interrupt vector word
UCA1IV
1Eh
Table 5-52. eUSCI_B0 Registers (Base Address: 0640h)
REGISTER DESCRIPTION
REGISTER
OFFSET
eUSCI_B control word 0
UCB0CTLW0
00h
eUSCI_B control word 1
UCB0CTLW1
02h
eUSCI_B bit rate 0
UCB0BR0
06h
eUSCI_B bit rate 1
UCB0BR1
07h
eUSCI_B status word
UCB0STATW
08h
eUSCI_B byte counter threshold
UCB0TBCNT
0Ah
eUSCI_B receive buffer
UCB0RXBUF
0Ch
eUSCI_B transmit buffer
UCB0TXBUF
0Eh
eUSCI_B I2C own address 0
UCB0I2COA0
14h
eUSCI_B I2C own address 1
UCB0I2COA1
16h
eUSCI_B I2C own address 2
UCB0I2COA2
18h
eUSCI_B I2C own address 3
UCB0I2COA3
1Ah
eUSCI_B received address
UCB0ADDRX
1Ch
126
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Table 5-52. eUSCI_B0 Registers (Base Address: 0640h) (continued)
REGISTER DESCRIPTION
REGISTER
OFFSET
eUSCI_B address mask
UCB0ADDMASK
1Eh
eUSCI_B I2C slave address
UCB0I2CSA
20h
eUSCI_B interrupt enable
UCB0IE
2Ah
eUSCI_B interrupt flags
UCB0IFG
2Ch
eUSCI_B interrupt vector word
UCB0IV
2Eh
Table 5-53. eUSCI_B1 Registers (Base Address: 0680h)
REGISTER DESCRIPTION
REGISTER
OFFSET
eUSCI_B control word 0
UCB1CTLW0
00h
eUSCI_B control word 1
UCB1CTLW1
02h
eUSCI_B bit rate 0
UCB1BR0
06h
eUSCI_B bit rate 1
UCB1BR1
07h
eUSCI_B status word
UCB1STATW
08h
eUSCI_B byte counter threshold
UCB1TBCNT
0Ah
eUSCI_B receive buffer
UCB1RXBUF
0Ch
eUSCI_B transmit buffer
UCB1TXBUF
0Eh
eUSCI_B I2C own address 0
UCB1I2COA0
14h
eUSCI_B I2C own address 1
UCB1I2COA1
16h
eUSCI_B I2C own address 2
UCB1I2COA2
18h
eUSCI_B I2C own address 3
UCB1I2COA3
1Ah
eUSCI_B received address
UCB1ADDRX
1Ch
eUSCI_B address mask
UCB1ADDMASK
1Eh
eUSCI_B I2C slave address
UCB1I2CSA
20h
eUSCI_B interrupt enable
UCB1IE
2Ah
eUSCI_B interrupt flags
UCB1IFG
2Ch
eUSCI_B interrupt vector word
UCB1IV
2Eh
Table 5-54. ADC12_B Registers (Base Address: 0800h)
REGISTER DESCRIPTION
REGISTER
OFFSET
ADC12_B control 0
ADC12CTL0
00h
ADC12_B control 1
ADC12CTL1
02h
ADC12_B control 2
ADC12CTL2
04h
ADC12_B control 3
ADC12CTL3
06h
ADC12_B window comparator low threshold
ADC12LO
08h
ADC12_B window comparator high threshold
ADC12HI
0Ah
ADC12_B interrupt flag 0
ADC12IFGR0
0Ch
ADC12_B Interrupt flag 1
ADC12IFGR1
0Eh
ADC12_B interrupt flag 2
ADC12IFGR2
10h
ADC12_B interrupt enable 0
ADC12IER0
12h
ADC12_B interrupt enable 1
ADC12IER1
14h
ADC12_B interrupt enable 2
ADC12IER2
16h
ADC12_B interrupt vector
ADC12IV
18h
ADC12_B memory control 0
ADC12MCTL0
20h
ADC12_B memory control 1
ADC12MCTL1
22h
ADC12_B memory control 2
ADC12MCTL2
24h
ADC12_B memory control 3
ADC12MCTL3
26h
ADC12_B memory control 4
ADC12MCTL4
28h
Detailed Description
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Table 5-54. ADC12_B Registers (Base Address: 0800h) (continued)
REGISTER DESCRIPTION
REGISTER
OFFSET
ADC12_B memory control 5
ADC12MCTL5
2Ah
ADC12_B memory control 6
ADC12MCTL6
2Ch
ADC12_B memory control 7
ADC12MCTL7
2Eh
ADC12_B memory control 8
ADC12MCTL8
30h
ADC12_B memory control 9
ADC12MCTL9
32h
ADC12_B memory control 10
ADC12MCTL10
34h
ADC12_B memory control 11
ADC12MCTL11
36h
ADC12_B memory control 12
ADC12MCTL12
38h
ADC12_B memory control 13
ADC12MCTL13
3Ah
ADC12_B memory control 14
ADC12MCTL14
3Ch
ADC12_B memory control 15
ADC12MCTL15
3Eh
ADC12_B memory control 16
ADC12MCTL16
40h
ADC12_B memory control 17
ADC12MCTL17
42h
ADC12_B memory control 18
ADC12MCTL18
44h
ADC12_B memory control 19
ADC12MCTL19
46h
ADC12_B memory control 20
ADC12MCTL20
48h
ADC12_B memory control 21
ADC12MCTL21
4Ah
ADC12_B memory control 22
ADC12MCTL22
4Ch
ADC12_B memory control 23
ADC12MCTL23
4Eh
ADC12_B memory control 24
ADC12MCTL24
50h
ADC12_B memory control 25
ADC12MCTL25
52h
ADC12_B memory control 26
ADC12MCTL26
54h
ADC12_B memory control 27
ADC12MCTL27
56h
ADC12_B memory control 28
ADC12MCTL28
58h
ADC12_B memory control 29
ADC12MCTL29
5Ah
ADC12_B memory control 30
ADC12MCTL30
5Ch
ADC12_B memory control 31
ADC12MCTL31
5Eh
ADC12_B memory 0
ADC12MEM0
60h
ADC12_B memory 1
ADC12MEM1
62h
ADC12_B memory 2
ADC12MEM2
64h
ADC12_B memory 3
ADC12MEM3
66h
ADC12_B memory 4
ADC12MEM4
68h
ADC12_B memory 5
ADC12MEM5
6Ah
ADC12_B memory 6
ADC12MEM6
6Ch
ADC12_B memory 7
ADC12MEM7
6Eh
ADC12_B memory 8
ADC12MEM8
70h
ADC12_B memory 9
ADC12MEM9
72h
ADC12_B memory 10
ADC12MEM10
74h
ADC12_B memory 11
ADC12MEM11
76h
ADC12_B memory 12
ADC12MEM12
78h
ADC12_B memory 13
ADC12MEM13
7Ah
ADC12_B memory 14
ADC12MEM14
7Ch
ADC12_B memory 15
ADC12MEM15
7Eh
ADC12_B memory 16
ADC12MEM16
80h
ADC12_B memory 17
ADC12MEM17
82h
ADC12_B memory 18
ADC12MEM18
84h
ADC12_B memory 19
ADC12MEM19
86h
128
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Table 5-54. ADC12_B Registers (Base Address: 0800h) (continued)
REGISTER DESCRIPTION
REGISTER
OFFSET
ADC12_B memory 20
ADC12MEM20
88h
ADC12_B memory 21
ADC12MEM21
8Ah
ADC12_B memory 22
ADC12MEM22
8Ch
ADC12_B memory 23
ADC12MEM23
8Eh
ADC12_B memory 24
ADC12MEM24
90h
ADC12_B memory 25
ADC12MEM25
92h
ADC12_B memory 26
ADC12MEM26
94h
ADC12_B memory 27
ADC12MEM27
96h
ADC12_B memory 28
ADC12MEM28
98h
ADC12_B memory 29
ADC12MEM29
9Ah
ADC12_B memory 30
ADC12MEM30
9Ch
ADC12_B memory 31
ADC12MEM31
9Eh
Table 5-55. Comparator_E Registers (Base Address: 08C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Comparator control 0
CECTL0
00h
Comparator control 1
CECTL1
02h
Comparator control 2
CECTL2
04h
Comparator control 3
CECTL3
06h
Comparator interrupt
CEINT
0Ch
Comparator interrupt vector word
CEIV
0Eh
Table 5-56. CRC32 Registers (Base Address: 0980h)
REGISTER DESCRIPTION
CRC32 data input
REGISTER
CRC32DIW0
OFFSET
00h
Reserved
02h
Reserved
04h
CRC32 data input reverse
CRC32DIRBW0
06h
CRC32 initialization and result word 0
CRC32INIRESW0
08h
CRC32 initialization and result word 1
CRC32INIRESW1
0Ah
CRC32 result reverse word 1
CRC32RESRW1
0Ch
CRC32 result reverse word 0
CRC32RESRW1
0Eh
CRC16 data input
CRC16DIW0
10h
Reserved
12h
Reserved
14h
CRC16 data input reverse
CRC16DIRBW0
16h
CRC16 initialization and result word 0
CRC16INIRESW0
18h
Reserved
1Ah
Reserved
CRC16 result reverse word 0
1Ch
CRC16RESRW1
1Eh
Reserved
20h
Reserved
22h
Reserved
24h
Reserved
26h
Reserved
28h
Reserved
2Ah
Reserved
2Ch
Detailed Description
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Table 5-56. CRC32 Registers (Base Address: 0980h) (continued)
REGISTER DESCRIPTION
REGISTER
Reserved
OFFSET
2Eh
Table 5-57. AES Accelerator Registers (Base Address: 09C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
AES accelerator control 0
AESACTL0
00h
AES accelerator control 1
AESACTL1
02h
AES accelerator status
AESASTAT
04h
AES accelerator key
AESAKEY
06h
AES accelerator data in
AESADIN
008h
AES accelerator data out
AESADOUT
00Ah
AES accelerator XORed data in
AESAXDIN
00Ch
AES accelerator XORed data in (no trigger)
AESAXIN
00Eh
Table 5-58. LCD_C Registers (Base Address: 0A00h)
REGISTER DESCRIPTION
REGISTER
OFFSET
LCD_C control 0
LCDCCTL0
000h
LCD_C control 1
LCDCCTL1
002h
LCD_C blinking control
LCDCBLKCTL
004h
LCD_C memory control
LCDCMEMCTL
006h
LCD_C voltage control
LCDCVCTL
008h
LCD_C port control 0
LCDCPCTL0
00Ah
LCD_C port control 1
LCDCPCTL1
00Ch
LCD_C port control 2
LCDCPCTL2
00Eh
LCD_C charge pump control
LCDCCPCTL
012h
LCD_C interrupt vector
LCDCIV
01Eh
LCD_C memory 1
LCDM1
020h
LCD_C memory 2
LCDM2
021h
LCD_C memory 3
LCDM3
022h
LCD_C memory 4
LCDM4
023h
LCD_C memory 5
LCDM5
024h
LCD_C memory 6
LCDM6
025h
LCD_C memory 7
LCDM7
026h
LCD_C memory 8
LCDM8
027h
LCD_C memory 9
LCDM9
028h
LCD_C memory 10
LCDM10
029h
LCD_C memory 11
LCDM11
02Ah
LCD_C memory 12
LCDM12
02Bh
LCD_C memory 13
LCDM13
02Ch
LCD_C memory 14
LCDM14
02Dh
LCD_C memory 15
LCDM15
02Eh
LCD_C memory 16
LCDM16
02Fh
LCD_C memory 17
LCDM17
030h
LCD_C memory 18
LCDM18
031h
LCD_C memory 19
LCDM19
032h
LCD_C memory 20
LCDM20
033h
LCD_C memory 21
LCDM21
034h
Static and 2 to 4 mux modes
130
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Table 5-58. LCD_C Registers (Base Address: 0A00h) (continued)
REGISTER DESCRIPTION
LCD_C memory 22
REGISTER
LCDM22
Reserved
OFFSET
035h
036h
Reserved
037h
LCD_C blinking memory 1
LCDBM1
040h
LCD_C blinking memory 2
LCDBM2
041h
LCD_C blinking memory 3
LCDBM3
042h
LCD_C blinking memory 4
LCDBM4
043h
LCD_C blinking memory 5
LCDBM5
044h
LCD_C blinking memory 6
LCDBM6
045h
LCD_C blinking memory 7
LCDBM7
046h
LCD_C blinking memory 8
LCDBM8
047h
LCD_C blinking memory 9
LCDBM9
048h
LCD_C blinking memory 10
LCDBM10
049h
LCD_C blinking memory 11
LCDBM11
04Ah
LCD_C blinking memory 12
LCDBM12
04Bh
LCD_C blinking memory 13
LCDBM13
04Ch
LCD_C blinking memory 14
LCDBM14
04Dh
LCD_C blinking memory 15
LCDBM15
04Eh
LCD_C blinking memory 16
LCDBM16
04Fh
LCD_C blinking memory 17
LCDBM17
050h
LCD_C blinking memory 18
LCDBM18
051h
LCD_C blinking memory 19
LCDBM19
052h
LCD_C blinking memory 20
LCDBM20
053h
LCD_C blinking memory 21
LCDBM21
054h
LCD_C blinking memory 22
LCDBM22
055h
Reserved
056h
Reserved
057h
5 to 8 mux modes
LCD_C memory 1
LCDM1
020h
LCD_C memory 2
LCDM2
021h
LCD_C memory 3
LCDM3
022h
LCD_C memory 4
LCDM4
023h
LCD_C memory 5
LCDM5
024h
LCD_C memory 6
LCDM6
025h
LCD_C memory 7
LCDM7
026h
LCD_C memory 8
LCDM8
027h
LCD_C memory 9
LCDM9
028h
LCD_C memory 10
LCDM10
029h
LCD_C memory 11
LCDM11
02Ah
LCD_C memory 12
LCDM12
02Bh
LCD_C memory 13
LCDM13
02Ch
LCD_C memory 14
LCDM14
02Dh
LCD_C memory 15
LCDM15
02Eh
LCD_C memory 16
LCDM16
02Fh
LCD_C memory 17
LCDM17
030h
LCD_C memory 18
LCDM18
031h
LCD_C memory 19
LCDM19
032h
Detailed Description
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Table 5-58. LCD_C Registers (Base Address: 0A00h) (continued)
REGISTER DESCRIPTION
REGISTER
OFFSET
LCD_C memory 20
LCDM20
033h
LCD_C memory 21
LCDM21
034h
LCD_C memory 22
LCDM22
035h
LCD_C memory 23
LCDM23
036h
LCD_C memory 24
LCDM24
037h
LCD_C memory 25
LCDM25
038h
LCD_C memory 26
LCDM26
039h
LCD_C memory 27
LCDM27
03Ah
LCD_C memory 28
LCDM28
03Bh
LCD_C memory 29
LCDM29
03Ch
LCD_C memory 30
LCDM30
03Dh
LCD_C memory 31
LCDM31
03Eh
LCD_C memory 32
LCDM32
03Fh
LCD_C memory 33
LCDM33
040h
LCD_C memory 34
LCDM34
041h
LCD_C memory 35
LCDM35
042h
LCD_C memory 36
LCDM36
043h
LCD_C memory 37
LCDM37
044h
LCD_C memory 38
LCDM38
045h
LCD_C memory 39
LCDM39
046h
LCD_C memory 40
LCDM40
047h
LCD_C memory 41
LCDM41
048h
LCD_C memory 42
LCDM42
049h
LCD_C memory 43
LCDM43
04Ah
Table 5-59. Extended Scan Interface (ESI) Registers (Base Address: 0D00h)
REGISTER DESCRIPTION
REGISTER
OFFSET
ESI debug 1
ESIDEBUG1
000h
ESI debug 2
ESIDEBUG2
002h
ESI debug 3
ESIDEBUG3
004h
ESI debug 4
ESIDEBUG4
006h
ESI debug 5
ESIDEBUG5
008h
Reserved
00Ah
Reserved
00Ch
Reserved
00Eh
ESI PSM counter 0
ESICNT0
010h
ESI PSM counter 1
ESICNT1
012h
ESI PSM counter 2
ESICNT2
014h
ESI oscillator counter
ESICNT3
016h
Reserved
018h
ESI interrupt vector
ESIIV
01Ah
ESI interrupt 1
ESIINT1
01Ch
ESI interrupt 2
ESIINT2
01Eh
ESI AFE control
ESIAFE
020h
ESI PPU control
ESIPPU
022h
ESI TSM control
ESITSM
024h
ESI PSM control
ESIPSM
026h
132
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Table 5-59. Extended Scan Interface (ESI) Registers (Base Address: 0D00h) (continued)
REGISTER DESCRIPTION
REGISTER
OFFSET
ESI oscillator control
ESIOSC
028h
ESI control
ESICTL
02Ah
ESI PSM counter threshold 1
ESITHR1
02Ch
ESI PSM counter threshold 2
ESITHR2
02Eh
ESI A/D conversion memory 1
ESIADMEM1
030h
ESI A/D conversion memory 2
ESIADMEM2
032h
ESI A/D conversion memory 3
ESIADMEM3
034h
ESI A/D conversion memory 4
ESIADMEM4
036h
Reserved
038h
Reserved
03Ah
Reserved
03Ch
Reserved
03Eh
ESI DAC1 0
ESIDAC1R0
040h
ESI DAC1 1
ESIDAC1R1
042h
ESI DAC1 2
ESIDAC1R2
044h
ESI DAC1 3
ESIDAC1R3
046h
ESI DAC1 4
ESIDAC1R4
048h
ESI DAC1 5
ESIDAC1R5
04Ah
ESI DAC1 6
ESIDAC1R6
04Ch
ESI DAC1 7
ESIDAC1R7
04Eh
ESI DAC2 0
ESIDAC2R0
050h
ESI DAC2 1
ESIDAC2R1
052h
ESI DAC2 2
ESIDAC2R2
054h
ESI DAC2 3
ESIDAC2R3
056h
ESI DAC2 4
ESIDAC2R4
058h
ESI DAC2 5
ESIDAC2R5
05Ah
ESI DAC2 6
ESIDAC2R6
05Ch
ESI DAC2 7
ESIDAC2R7
05Eh
ESI TSM 0
ESITSM0
060h
ESI TSM 1
ESITSM1
062h
ESI TSM 2
ESITSM2
064h
ESI TSM 3
ESITSM3
066h
ESI TSM 4
ESITSM4
068h
ESI TSM 5
ESITSM5
06Ah
ESI TSM 6
ESITSM6
06Ch
ESI TSM 7
ESITSM7
06Eh
ESI TSM 8
ESITSM8
070h
ESI TSM 9
ESITSM9
072h
ESI TSM 10
ESITSM10
074h
ESI TSM 11
ESITSM11
076h
ESI TSM 12
ESITSM12
078h
ESI TSM 13
ESITSM13
07Ah
ESI TSM 14
ESITSM14
07Ch
ESI TSM 15
ESITSM15
07Eh
ESI TSM 16
ESITSM16
080h
ESI TSM 17
ESITSM17
082h
ESI TSM 18
ESITSM18
084h
Detailed Description
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Table 5-59. Extended Scan Interface (ESI) Registers (Base Address: 0D00h) (continued)
REGISTER DESCRIPTION
REGISTER
OFFSET
ESI TSM 19
ESITSM19
086h
ESI TSM 20
ESITSM20
088h
ESI TSM 21
ESITSM21
08Ah
ESI TSM 22
ESITSM22
08Ch
ESI TSM 23
ESITSM23
08Eh
ESI TSM 24
ESITSM24
090h
ESI TSM 25
ESITSM25
092h
ESI TSM 26
ESITSM26
094h
ESI TSM 27
ESITSM27
096h
ESI TSM 28
ESITSM28
098h
ESI TSM 29
ESITSM29
09Ah
ESI TSM 30
ESITSM30
09Ch
ESI TSM 31
ESITSM31
09Eh
5.14 Identification
5.14.1 Revision Identification
The device revision information is shown as part of the top-side marking on the device package. The
device-specific errata sheet describes these markings. For links to all of the errata sheets for the devices
in this data sheet, see Section 7.3.
The hardware revision is also stored in the Device Descriptor structure in the Info Block section. For
details on this value, see the "Hardware Revision" entries in Section 5.12.
5.14.2 Device Identification
The device type can be identified from the top-side marking on the device package. The device-specific
errata sheet describes these markings. For links to all of the errata sheets for the devices in this data
sheet, see Section 7.3.
A device identification value is also stored in the Device Descriptor structure in the Info Block section. For
details on this value, see the "Device ID" entries in Section 5.12.
5.14.3 JTAG Identification
Programming through the JTAG interface, including reading and identifying the JTAG ID, is described in
detail in MSP430 Programming With the JTAG Interface.
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6 Applications, Implementation, and Layout
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
6.1
Device Connection and Layout Fundamentals
This section discusses the recommended guidelines when designing with the MSP430. These guidelines
are to make sure that the device has proper connections for powering, programming, debugging, and
optimum analog performance.
6.1.1
Power Supply Decoupling and Bulk Capacitors
TI recommends connecting a combination of a 1-µF plus a 100-nF low-ESR ceramic decoupling capacitor
to each AVCC, DVCC, and ESIDVCC pin. Higher-value capacitors may be used but can impact supply rail
ramp-up time. Decoupling capacitors must be placed as close as possible to the pins that they decouple
(within a few millimeters). Additionally, TI recommends separated grounds with a single-point connection
for better noise isolation from digital to analog circuits on the board and to achieve high analog accuracy.
DVCC, ESIDVCC
Digital
Power Supply
Decoupling
+
1 µF
100 nF
DVSS, ESIDVSS
AVCC
Analog
Power Supply
Decoupling
+
1 µF
100 nF
AVSS
Figure 6-1. Power Supply Decoupling
6.1.2
External Oscillator
Depending on the device variant, the device can support a low-frequency crystal (32 kHz) on the LFXT
pins, a high-frequency crystal on the HFXT pins, or both. External bypass capacitors for the crystal
oscillator pins are required.
It is also possible to apply digital clock signals to the LFXIN and HFXIN input pins that meet the
specifications of the respective oscillator if the appropriate LFXTBYPASS or HFXTBYPASS mode is
selected. In this case, the associated LFXOUT and HFXOUT pins can be used for other purposes. If they
are left unused, terminate them according to Section 3.4.
Figure 6-2 shows a typical connection diagram.
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LFXIN
or
HFXIN
CL1
LFXOUT
or
HFXOUT
CL2
Figure 6-2. Typical Crystal Connection
See MSP430 32-kHz Crystal Oscillators for more information on selecting, testing, and designing a crystal
oscillator with the MSP430 devices.
6.1.3
JTAG
With the proper connections, the debugger and a hardware JTAG interface (such as the MSP-FET or
MSP-FET430UIF) can be used to program and debug code on the target board. In addition, the
connections also support the MSP-GANG production programmers, thus providing an easy way to
program prototype boards, if desired. Figure 6-3 shows the connections between the 14-pin JTAG
connector and the target device required to support in-system programming and debugging for 4-wire
JTAG communication. Figure 6-4 shows the connections for 2-wire JTAG mode (Spy-Bi-Wire).
The connections for the MSP-FET and MSP-FET430UIF interface modules and the MSP-GANG are
identical. Both can supply VCC to the target board (through pin 2). In addition, the MSP-FET and MSPFET430UIF interface modules and MSP-GANG have a VCC sense feature that, if used, requires an
alternate connection (pin 4 instead of pin 2). The VCC-sense feature senses the local VCC present on the
target board (that is, a battery or other local power supply) and adjusts the output signals accordingly.
Figure 6-3 and Figure 6-4 show a jumper block that supports both scenarios of supplying VCC to the
target board. If this flexibility is not required, the desired VCC connections may be hard-wired to eliminate
the jumper block. Pins 2 and 4 must not be connected at the same time.
For additional design information regarding the JTAG interface, see the MSP430 Hardware Tools User's
Guide.
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VCC
Important to connect
MSP430FRxxx
J1 (see Note A)
AVCC/DVCC
J2 (see Note A)
R1
47 kW
JTAG
VCC TOOL
VCC TARGET
TEST
2
RST/NMI/SBWTDIO
1
4
3
6
5
8
7
10
9
12
11
14
13
TDO/TDI
TDO/TDI
TDI
TDI
TMS
TCK
TMS
TCK
GND
RST
TEST/SBWTCK
C1
2.2 nF
(see Note B)
AVSS/DVSS
Copyright © 2016, Texas Instruments Incorporated
A.
B.
If a local target power supply is used, make connection J1. If power from the debug or programming adapter is used,
make connection J2.
The upper limit for C1 is 2.2 nF when using current TI tools.
Figure 6-3. Signal Connections for 4-Wire JTAG Communication
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VCC
Important to connect
MSP430FRxxx
J1 (see Note A)
AVCC/DVCC
J2 (see Note A)
R1
47 kΩ
(See Note B)
JTAG
VCC TOOL
VCC TARGET
2
1
4
3
6
5
8
7
10
9
12
11
14
13
TDO/TDI
RST/NMI/SBWTDIO
TCK
GND
TEST/SBWTCK
C1
2.2 nF
(See Note B)
AVSS/DVSS
Copyright © 2016, Texas Instruments Incorporated
A.
B.
Make connection J1 if a local target power supply is used, or make connection J2 if the target is powered from the
debug or programming adapter.
The device RST/NMI/SBWTDIO pin is used in 2-wire mode for bidirectional communication with the device during
JTAG access, and any capacitance that is attached to this signal may affect the ability to establish a connection with
the device. The upper limit for C1 is 2.2 nF when using current TI tools.
Figure 6-4. Signal Connections for 2-Wire JTAG Communication (Spy-Bi-Wire)
6.1.4
Reset
The reset pin can be configured as a reset function (default) or as an NMI function in the Special Function
Register (SFR), SFRRPCR.
In reset mode, the RST/NMI pin is active low, and a pulse applied to this pin that meets the reset timing
specifications generates a BOR-type device reset.
Setting SYSNMI causes the RST/NMI pin to be configured as an external NMI source. The external NMI is
edge sensitive, and its edge is selectable by SYSNMIIES. Setting the NMIIE enables the interrupt of the
external NMI. When an external NMI event occurs, the NMIIFG is set.
The RST/NMI pin can have either a pullup or pulldown that is enabled or not. SYSRSTUP selects either
pullup or pulldown, and SYSRSTRE causes the pullup (default) or pulldown to be enabled (default) or not.
If the RST/NMI pin is unused, it is required either to select and enable the internal pullup or to connect an
external 47-kΩ pullup resistor to the RST/NMI pin with a 2.2-nF pulldown capacitor.
The pulldown capacitor should not exceed 2.2 nF when using devices with Spy-Bi-Wire mode or in 4-wire
JTAG mode with TI tools like FET interfaces or GANG programmers. If JTAG or Spy-Bi-Wire access is not
needed, up to a 10-nF pulldown capacitor may be used.
See the MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, and MSP430FR69xx Family User's Guide for
more information on the referenced control registers and bits.
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6.1.5
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Unused Pins
For details on the connection of unused pins, see Section 3.4.
6.1.6
General Layout Recommendations
•
•
•
•
•
6.1.7
Proper grounding and short traces for external crystal to reduce parasitic capacitance. See MSP430
32-kHz Crystal Oscillators for recommended layout guidelines.
Proper bypass capacitors on DVCC, AVCC, and reference pins if used.
Avoid routing any high-frequency signal close to an analog signal line. For example, keep digital
switching signals such as PWM or JTAG signals away from the oscillator circuit.
See Circuit Board Layout Techniques for a detailed discussion of PCB layout considerations. This
document is written primarily about op amps, but the guidelines are generally applicable for all mixedsignal applications.
Proper ESD level protection should be considered to protect the device from unintended high-voltage
electrostatic discharge. See MSP430 System-Level ESD Considerations for guidelines.
Do's and Don'ts
TI recommends powering the AVCC, DVCC, and ESIDVCC pins from the same source. At a minimum,
during power up, power down, and device operation, the voltage difference between AVCC and DVCC
must not exceed the limits specified in the Absolute Maximum Ratings section. Exceeding the specified
limits may cause malfunction of the device including erroneous writes to RAM and FRAM.
6.2
Peripheral- and Interface-Specific Design Information
6.2.1
ADC12_B Peripheral
6.2.1.1
Partial Schematic
Figure 6-5 shows the recommended decoupling circuit when an external voltage reference is used.
AVSS
Using an
External
Positive
Reference
Using an
External
Negative
Reference
VREF+/VEREF+
+
10 µF
4.7 µF
VEREF+
10 µF
4.7 µF
Figure 6-5. ADC12_B Grounding and Noise Considerations
6.2.1.2
Design Requirements
As with any high-resolution ADC, appropriate printed-circuit-board layout and grounding techniques should
be followed to eliminate ground loops, unwanted parasitic effects, and noise.
Ground loops are formed when return current from the ADC flows through paths that are common with
other analog or digital circuitry. If care is not taken, this current can generate small unwanted offset
voltages that can add to or subtract from the reference or input voltages of the ADC. The general
guidelines in Section 6.1.1 combined with the connections shown in Section 6.2.1.1 prevent this.
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In addition to grounding, ripple and noise spikes on the power-supply lines that are caused by digital
switching or switching power supplies can corrupt the conversion result. A noise-free design using
separate analog and digital ground planes with a single-point connection is recommend to achieve high
accuracy.
Figure 6-5 shows the recommended decoupling circuit when an external voltage reference is used. The
internal reference module has a maximum drive current as specified in the Reference module's IO(VREF+)
specification.
The reference voltage must be a stable voltage for accurate measurements. The capacitor values that are
selected in the general guidelines filter out the high- and low-frequency ripple before the reference voltage
enters the device. In this case, the 10-µF capacitor is used to buffer the reference pin and filter any lowfrequency ripple. A bypass capacitor of 4.7 µF is used to filter out any high-frequency noise.
6.2.1.3
Detailed Design Procedure
For additional design information, see Designing With the MSP430FR58xx, FR59xx, FR68xx, and FR69xx
ADC.
6.2.1.4
Layout Guidelines
Component that are shown in the partial schematic (see Figure 6-5) should be placed as close as possible
to the respective device pins. Avoid long traces, because they add additional parasitic capacitance,
inductance, and resistance on the signal.
Avoid routing analog input signals close to a high-frequency pin (for example, a high-frequency PWM),
because the high-frequency switching can be coupled into the analog signal.
If differential mode is used for the ADC12_B, the analog differential input signals must be routed closely
together to minimize the effect of noise on the resulting signal.
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6.2.2
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LCD_C Peripheral
6.2.2.1
Partial Schematic
Required LCD connections greatly vary by the type of display that is used (static or multiplexed), whether
external or internal biasing is used, and also whether the on-chip charge pump is employed. For any
display used, there is flexibility as to how the segment (Sx) and common (COMx) signals are connected to
the MCU, which (assuming that the correct choices are made) can be advantageous for the PCB layout
and for the design of the application software.
Because LCD connections are application specific, it is difficult to provide a single one-fits-all schematic.
However, for an example of connecting a 4-mux LCD with 40 segment lines that has a total of
4 × 40 = 160 individually addressable LCD segments to an MSP430FR6989, see the Water Meter
Reference Design for Two LC Sensors, Using Extended Scan Interface (ESI).
6.2.2.2
Design Requirements
Due to the flexibility of the LCD_C peripheral module to accommodate various segment-based LCDs,
selecting the correct display for the application in combination with determining specific design
requirements is often an iterative process. There can be well defined requirements in terms of how many
individually addressable LCD segments need to be controlled, what the requirements for LCD contrast
are, which device pins are available for LCD use, and which are required by other application functions,
and what the power budget is, to name just a few. TI recommends reviewing the LCD_C peripheral
module chapter in the MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, and MSP430FR69xx Family
User's Guide during the initial design requirements and decision process. Table 6-1 is a brief overview
over different choices that can be made and their effects.
Table 6-1. LCD Features and Use Cases
OPTION OR FEATURE
IMPACT OR USE CASE
Multiplexed LCD
•
•
•
•
•
Enable displays with more segments
Use fewer device pins
LCD contrast decreases as mux level increases
Power consumption increases with mux level
Requires multiple intermediate bias voltages
Static LCD
•
•
•
•
Limited number of segments that can be addressed
Use a relatively large number of device pins
Use the least amount of power
Use only VCC and GND to drive LCD signals
Internal bias generation
•
•
•
Simpler solution – no external circuitry
Independent of VLCD source
Somewhat higher power consumption
•
•
•
Requires external resistor ladder divider
Resistor size depends on display
Ability to adjust drive strength to optimize tradeoff between power consumption and good drive of large
segments (high capacitive load)
External resistor ladder divider can be stabilized through capacitors to reduce ripple
External bias generation
•
•
Internal charge pump
•
•
•
Helps ensure a constant level of contrast despite decaying supply voltage conditions (battery-powered
applications)
Programmable voltage levels allow software-driven contrast control
Requires an external capacitor on the LCDCAP pin
Higher current consumption than simply using VCC for the LCD driver
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6.2.2.3
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Detailed Design Procedure
A major component in designing the LCD solution is determining the exact connections between the
LCD_C peripheral module and the display itself. Two basic design processes can be employed for this
step, although in reality often a balanced co-design approach is recommended:
• PCB layout-driven design
• Software-driven design
In the PCB layout-driven design process, the segment Sx and common COMx signals are connected to
respective MSP430 device pins so that the routing of the PCB can be optimized to minimize signal
crossings and to keep signals on one side of the PCB only, typically the top layer. For example, using a
multiplexed LCD, it is possible to arbitrarily connect the Sx and COMx signals between the LCD and the
MSP430 device as long as segment lines are swapped with segment lines and common lines are
swapped with common lines. It is also possible to not contiguously connect all segment lines but rather
skip LCD_C module segment connections to optimize layout or to allow access to other functions that may
be multiplexed on a particular device port pin. Employing a purely layout-driven design approach,
however, can result in the LCD_C module control bits that are responsible for turning on and off segments
to appear scattered throughout the memory map of the LCD controller (LCDMx registers). This approach
potentially places a rather large burden on the software design that may also result in increased energy
consumption due to the computational overhead required to work with the LCD.
The other extreme is a purely software-driven approach that starts with the idea that control bits for LCD
segments that are frequently turned on and off together should be co-located in memory in the same
LCDMx register or in adjacent registers. For example, in case of a 4-mux display that contains several 7segment digits, from a software perspective it can be very desirable to control all 7 segments of each digit
though a single byte-wide access to an LCDMx register. And consecutive segments are mapped to
consecutive LCDMx registers. This allows use of simple look-up tables or software loops to output
numbers on an LCD, reducing computational overhead and optimizing the energy consumption of an
application. Establishing of the most convenient memory layout needs to be performed in conjunction with
the specific LCD that is being used to understand its design constraints in terms of which segment and
which common signals are connected to, for example, a digit.
For design information regarding the LCD controller input voltage selection including internal and external
options, contrast control, and bias generation, see the LCD_C Controller chapter in the MSP430FR58xx,
MSP430FR59xx, MSP430FR68xx, and MSP430FR69xx Family User's Guide.
For additional design information, see Designing With MSP430 and Segment LCDs.
6.2.2.4
Layout Guidelines
LCD segment (Sx) and common (COMx) signal traces are continuously switching while the LCD is
enabled and should, therefore, be kept away from sensitive analog signals such as ADC inputs to prevent
any noise coupling. TI recommends keeping the LCD signal traces on one side of the PCB grouped
together in a bus-like fashion. A ground plane underneath the LCD traces and guard traces employed
alongside the LCD traces can provide shielding.
If the internal charge pump of the LCD module is used, the externally provided capacitor on the LCDCAP
pin should be located as close as possible to the MCU. The capacitor should be connected to the device
using a short and direct trace and also have a solid connection to the ground plane that is supplying the
VSS pins of the MCU.
For an example layout of connecting a 4-mux LCD with 40 segments to an MSP430FR6989 and using the
charge pump feature, see Water Meter Reference Design for Two LC Sensors, Using Extended Scan
Interface (ESI).
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7 Device and Documentation Support
7.1
Device and Development Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
MSP430 MCU devices and support tools. Each MSP430 MCU commercial family member has one of
three prefixes: MSP, PMS, or XMS. TI recommends two of three possible prefix designators for its support
tools: MSP and MSPX. These prefixes represent evolutionary stages of product development from
engineering prototypes (with XMS for devices and MSPX for tools) through fully qualified production
devices and tools (with MSP for devices and MSP for tools).
Device development evolutionary flow:
XMS – Experimental device that is not necessarily representative of the final device's electrical
specifications
PMS – Final silicon die that conforms to the device's electrical specifications but has not completed quality
and reliability verification
MSP – Fully qualified production device
Support tool development evolutionary flow:
MSPX – Development-support product that has not yet completed TI internal qualification testing
MSP – Fully-qualified development-support product
XMS and PMS devices and MSPX development-support tools are shipped against the following
disclaimer:
"Developmental product is intended for internal evaluation purposes."
MSP devices and MSP development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (XMS and PMS) have a greater failure rate than the standard
production devices. TI recommends that these devices not be used in any production system because
their expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
package type (for example, PZ) and temperature range (for example, I). Figure 7-1 provides a legend for
reading the complete device name for any family member.
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MSP
430 FR 6 9891
I
PZ
T
Feature Set
Processor Family
MCU Platform
Optional: Distribution Format
Device Type
Packaging
Series
Optional: Temperature Range
AES
ESI
Optional: BSL
FRAM
Processor
Family
MSP = Mixed-Signal Processor
XMS = Experimental Silicon
MCU
Platform
430 = TI’s 16-bit MSP430 Low-Power Microcontroller Platform
Device
Type
Memory Type
FR = FRAM
Series
6 = FRAM 6 series up to 16 MHz with LCD
5 = FRAM 5 series up to 16 MHz without LCD
Feature
Set
First Digit: AES
9 = AES
8 = No AES
Optional:
Temperature
Range
S = 0°C to 50°C
I = –40°C to 85°C
T = –40°C to 105°C
Second Digit: Extended Scan Interface
8 = ESI
7 = No ESI
2 = No ESI, LCD, 64 pins
Packaging
www.ti.com/packaging
Optional:
Distribution
Format
T = Small reel
R = Large reel
No Markings = Tube or tray
Optional:
Additional
Features
-Q1 = Automotive Qualified
-EP = Enhanced Product (–40°C to 105°C)
-HT = Extreme Temperature Parts (–55°C to 150°C)
Third Digit: FRAM (KB)
9 = 128
8 = 96
7 = 64
6 = 48
Optional Fourth Digit: BSL
2
1=IC
No value = UART
NOTE: This figure does not represent a complete list of the available features and options, and does not indicate that all of
these features and options are available for a given device or family.
Figure 7-1. Device Nomenclature – Part Number Decoder
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7.2
SLASEC9 – APRIL 2017
Tools and Software
Table 7-1 lists the debug features supported by the MSP430FR698x(1) and MSP430FR598x(1)
microcontrollers. See the Code Composer Studio for MSP430 User's Guide for details on the available
features.
Table 7-1. Hardware Features
MSP430
ARCHITECTURE
4-WIRE
JTAG
2-WIRE
JTAG
BREAKPOINTS
(N)
RANGE
BREAKPOINTS
CLOCK
CONTROL
STATE
SEQUENCER
TRACE
BUFFER
LPMX.5
DEBUGGING
SUPPORT
EnergyTrace++
TECHNOLOGY
MSP430Xv2
Yes
Yes
3
Yes
Yes
No
No
Yes
Yes
EnergyTrace™ technology is supported with Code Composer Studio version 6.0 and newer. It requires
specialized debugger circuitry, which is supported with the second-generation on-board eZ-FET flash
emulation tool and second-generation stand-alone MSP-FET JTAG emulator. See Advanced Debugging
Using the Enhanced Emulation Module (EEM) With Code Composer Studio Version 6 and MSP430™
Advanced Power Optimizations: ULP Advisor™ and EnergyTrace™ Technology for additional information.
Design Kits and Evaluation Modules
100-pin Target Development Board and MSP-FET Programmer Bundle for MSP430FRxx FRAM
MCUs
The MSP-FET430U100D is a bundle featuring the MSP-FET programmer and debugger with
the MSP-TS430PZ100D, a stand-alone 100-pin ZIF socket target board. This bundle can be
used to program and debug the MSP430 MCU in system through the JTAG interface or the
Spy-Bi-Wire (2-wire JTAG) protocol.
MSP-TS430PZ100D- 100-pin Target Development Board for MSP430FRxx FRAM MCUs The MSPTS430PZ100D is a stand-alone 100-pin ZIF socket target board used to program and debug
the MSP430 MCU in-system through the JTAG interface or the Spy-Bi-Wire (2-wire JTAG)
protocol.
MSP430FR6989 LaunchPad™ Development Kit The MSP-EXP430FR6989 LaunchPad Development
Kit is an easy-to-use evaluation module (EVM) for the MSP40FR6989 microcontroller (MCU).
It contains everything needed to start developing on the ultra-low-power MSP430FRx FRAM
microcontroller platform, including onboard emulation for programming, debugging, and
energy measurements.
Software
MSP430FR5x8x, MSP430FR692x, MSP430FR6x7x, MSP430FR6x8x Code Examples
C
Code
examples are available for every MSP device that configures each of the integrated
peripherals for various application needs.
FRAM Embedded Software Utilities for MSP Ultra-Low-Power Microcontrollers The TI FRAM Utilities
software is designed to grow as a collection of embedded software utilities that leverage the
ultra-low-power and virtually unlimited write endurance of FRAM. The utilities are available
for MSP430FRxx FRAM microcontrollers and provide example code to help start application
development.
FlowESI GUI for Flow Meter Configuration Using the Extended Scan Interface (ESI)
Follow
the
simple graphical instructions and connect upto three LC sensors to the Extended Scan
Interface module. The tool provides fully functional CCS and IAR projects or source code
than can be incorporated into custom projects.
MSP430 Touch Pro GUI The MSP430 Touch Pro Tool is a PC-based tool that can be used to verify
capacitive touch button, slider,and wheel designs. The tool receives and visualizes captouch
sensor data to help the user quickly and easily evaluate, diagnose, and tune button, slider,
and wheel designs.
MSP430 Touch Power Designer GUI The MSP430 Capacitive Touch Power Designer enables the
calculation of the estimated average current draw for a given MSP430 capacitive touch
system. By entering system parameters such as operating voltage, frequency, number of
buttons, and button gate time, the user can have a power estimate for a given capacitive
touch configuration on a given device family in minutes.
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Digital Signal Processing (DSP) Library for MSP Microcontrollers The Digital Signal Processing
library is a set of highly optimized functions to perform many common signal processing
operations on fixed-point numbers for MSP430 and MSP432 microcontrollers. This function
set is typically used for applications where processing-intensive transforms are done in realtime for minimal energy and with very high accuracy. This optimal use of the MSP intrinsic
hardware for fixed-point math allows for significant performance gains.
MSP Driver Library The abstracted API of MSP Driver Library provides easy-to-use function calls that
free you from directly manipulating the bits and bytes of the MSP430 hardware. Thorough
documentation is delivered through a helpful API Guide, which includes details on each
function call and the recognized parameters. Developers can use Driver Library functions to
write complete projects with minimal overhead.
MSP EnergyTrace Technology EnergyTrace technology for MSP430 microcontrollers is an energybased code analysis tool that measures and displays the energy profile of the application
and helps to optimize it for ultra-low-power consumption.
ULP (Ultra-Low Power) Advisor ULP Advisor™ software is a tool for guiding developers to write more
efficient code to fully use the unique ultra-low-power features of MSP and MSP432
microcontrollers. Aimed at both experienced and new microcontroller developers, ULP
Advisor checks your code against a thorough ULP checklist to help minimize the energy
consumption of your application. At build time, ULP Advisor provides notifications and
remarks to highlight areas of your code that can be further optimized for lower power.
IEC60730 Software Package The IEC60730 MSP430 software package was developed to help
customers comply with IEC 60730-1:2010 (Automatic Electrical Controls for Household and
Similar Use – Part 1: General Requirements) for up to Class B products, which includes
home appliances, arc detectors, power converters, power tools, e-bikes, and many others.
The IEC60730 MSP430 software package can be embedded in customer applications
running on MSP430s to help simplify the customer’s certification efforts of functional safetycompliant consumer devices to IEC 60730-1:2010 Class B.
Fixed Point Math Library for MSP The MSP IQmath and Qmath Libraries are a collection of highly
optimized and high-precision mathematical functions for C programmers to seamlessly port a
floating-point algorithm into fixed-point code on MSP430 and MSP432 devices. These
routines are typically used in computationally intensive real-time applications where optimal
execution speed, high accuracy, and ultra-low energy are critical. By using the IQmath and
Qmath libraries, it is possible to achieve execution speeds considerably faster and energy
consumption considerably lower than equivalent code written using floating-point math.
Floating Point Math Library for MSP430 Continuing to innovate in the low-power and low-cost
microcontroller space, TI provides MSPMATHLIB. Leveraging the intelligent peripherals of
our devices, this floating-point math library of scalar functions is up to 26 times faster than
the standard MSP430 math functions. Mathlib is easy to integrate into your designs. This
library is free and is integrated in both Code Composer Studio IDE and IAR Embedded
Workbench IDE.
Development Tools
Code Composer Studio™ Integrated Development Environment for MSP Microcontrollers
Code
Composer Studio (CCS) integrated development environment (IDE) supports all MSP
microcontroller devices. CCS comprises a suite of embedded software utilities used to
develop and debug embedded applications. CCS includes an optimizing C/C++ compiler,
source code editor, project build environment, debugger, profiler, and many other features.
MSPWare Software MSPWare software is a collection of code examples, data sheets, and other design
resources for all MSP devices delivered in a convenient package. In addition to providing a
complete collection of existing MSP design resources, MSPWare software also includes a
high-level API called MSP Driver Library. This library makes it easy to program MSP
hardware. MSPWare software is available as a component of CCS or as a stand-alone
package.
Command-Line Programmer MSP Flasher is an open-source shell-based interface for programming
MSP microcontrollers through a FET programmer or eZ430 using JTAG or Spy-Bi-Wire
(SBW) communication. MSP Flasher can download binary files (.txt or .hex) directly to the
MSP microcontroller without an IDE.
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MSP MCU Programmer and Debugger The MSP-FET is a powerful emulation development tool – often
called a debug probe – which lets users quickly begin application development on MSP lowpower MCUs. Creating MCU software usually requires downloading the resulting binary
program to the MSP device for validation and debugging.
MSP-GANG Production Programmer The MSP Gang Programmer is an MSP430 or MSP432 device
programmer that can program up to eight identical MSP430 or MSP432 flash or FRAM
devices at the same time. The MSP Gang Programmer connects to a host PC using a
standard RS-232 or USB connection and provides flexible programming options that let the
user fully customize the process.
7.3
Documentation Support
The following documents describe the MSP430FR698x(1) and MSP430FR598x(1) MCUs. Copies of these
documents are available on the Internet at www.ti.com.
Receiving Notification of Document Updates
To receive notification of documentation updates—including silicon errata—go to the product folder for
your device on ti.com. In the upper right corner, click the "Alert me" button. This registers you to receive a
weekly digest of product information that has changed (if any). For change details, check the revision
history of any revised document.
Errata
MSP430FR5989 Device Erratasheet Describes the known exceptions to the functional specifications.
User's Guides
MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, and MSP430FR69xx Family User's Guide Detailed
description of all modules and peripherals available in this device family.
Code Composer Studio v6.1 for MSP430 User's Guide This manual describes the use of TI Code
Composer Studio IDE v6.1 (CCS v6.1) with the MSP430 ultra-low-power microcontrollers.
This document applies only for the Windows version of the Code Composer Studio IDE. The
Linux version is similar and, therefore, is not described separately.
IAR Embedded Workbench Version 3+ for MSP430 User's Guide This manual describes the use of
IAR Embedded Workbench (EW430) with the MSP430 ultra-low-power microcontrollers.
MSP430FR57xx, MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, and MSP430FR69xx Bootloader
(BSL)
The bootloader (BSL, formerly known as the bootstrap loader) provides a method to program
memory during MSP430 MCU project development and updates. It can be activated by a
utility that sends commands using a serial protocol. The BSL lets the user control the activity
of the MSP430 and to exchange data using a personal computer or other device.
MSP430 Programming With the JTAG Interface This document describes the functions that are
required to erase, program, and verify the memory module of the MSP430 flash-based and
FRAM-based microcontroller families using the JTAG communication port. In addition, it
describes how to program the JTAG access security fuse that is available on all MSP430
devices. This document describes device access using both the standard 4-wire JTAG
interface and the 2-wire JTAG interface, which is also referred to as Spy-Bi-Wire (SBW).
MSP430 Hardware Tools User's Guide This manual describes the hardware of the TI MSP-FET430
Flash Emulation Tool (FET). The FET is the program development tool for the MSP430 ultralow-power microcontroller. Both available interface types, the parallel port interface and the
USB interface, are described.
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Application Reports
MSP430 FRAM Technology – How To and Best Practices FRAM is a nonvolatile memory technology
that behaves similar to SRAM while enabling a whole host of new applications, but also
changing the way firmware should be designed. This application report outlines the how to
and best practices of using FRAM technology in MSP430 from an embedded software
development perspective. It discusses how to implement a memory layout according to
application-specific code, constant, data space requirements, and the use of FRAM to
optimize application energy consumption.
MSP430 32-kHz Crystal Oscillators Selection of the right crystal, correct load circuit, and proper board
layout are important for a stable crystal oscillator. This application report summarizes crystal
oscillator function and explains the parameters to select the correct crystal for MSP430 ultralow-power operation. In addition, hints and examples for correct board layout are given. The
document also contains detailed information on the possible oscillator tests to ensure stable
oscillator operation in mass production.
MSP430 System-Level ESD Considerations System-Level ESD has become increasingly demanding
with silicon technology scaling towards lower voltages and the need for designing costeffective and ultra-low-power components. This application report addresses three different
ESD topics to help board designers and OEMs understand and design robust system-level
designs.
7.4
Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E™ Community
TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At
e2e.ti.com, you can ask questions, share knowledge, explore ideas, and help solve problems with fellow
engineers.
TI Embedded Processors Wiki
Texas Instruments Embedded Processors Wiki. Established to help developers get started with embedded
processors from Texas Instruments and to foster innovation and growth of general knowledge about the
hardware and software surrounding these devices.
7.5
Trademarks
EnergyTrace++, MSP430, EnergyTrace, LaunchPad, ULP Advisor, Code Composer Studio, E2E are
trademarks of Texas Instruments.
Microsoft is a registered trademark of Microsoft Corporation.
All other trademarks are the property of their respective owners.
7.6
Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
7.7
Export Control Notice
Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data
(as defined by the U.S., EU, and other Export Administration Regulations) including software, or any
controlled product restricted by other applicable national regulations, received from disclosing party under
nondisclosure obligations (if any), or any direct product of such technology, to any destination to which
such export or re-export is restricted or prohibited by U.S. or other applicable laws, without obtaining prior
authorization from U.S. Department of Commerce and other competent Government authorities to the
extent required by those laws.
148
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7.8
SLASEC9 – APRIL 2017
Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms and definitions.
8 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the
most current data available for the designated devices. This data is subject to change without notice and
revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2017, Texas Instruments Incorporated
Mechanical, Packaging, and Orderable Information
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PACKAGING INFORMATION
Orderable Device
Status
(1)
M430FR5989SRGCREP
ACTIVE
Package Type Package Pins Package
Drawing
Qty
VQFN
RGC
64
2000
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
Op Temp (°C)
Device Marking
(4/5)
-55 to 95
FR5989EP
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
19-Apr-2017
OTHER QUALIFIED VERSIONS OF MSP430FR5989-EP :
• Catalog: MSP430FR5989
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
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